Three-dimensional integrated circuit package structure and assembly method

Abstract

The present invention provides a three-dimensional hybrid integrated circuit packaging structure and an assembly method, belonging to the technical field of semiconductor packaging. It includes a packaging shell, a lower substrate, and an upper substrate. The packaging shell is provided with pins penetrating through the bottom plate of the packaging shell; the upper substrate and the lower substrate are stacked and interconnected through the BGA ball mounting flip-chip soldering process; components are provided on the lower front pads of the lower substrate and the upper front pads of the upper substrate. The three-dimensional hybrid integrated circuit packaging structure provided by the present invention can improve the integration degree of the hybrid integrated circuit. At the same time, components with larger volume and requiring debugging can be placed on the upper substrate, which is convenient for separate debugging and separate assembly. Moreover, other devices are not damaged during debugging, improving the operability of the product and simplifying the assembly difficulty.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and more specifically, relates to a three-dimensional hybrid integrated circuit packaging structure and an assembly method thereof. Background Art

[0002] Hybrid integrated circuits are an important circuit design and integration method in the field of microelectronics technology. They have flexible design, short development cycles, are adjustable, have a wide operating frequency range, and are widely used in microwave circuit products.

[0003] Thin-film hybrid integrated circuits refer to passive networks made by thin-film processes such as evaporation, sputtering, and electroplating on a ceramic substrate. The ceramic substrate made by the thin-film process has high line accuracy, can design thin-film resistors, and is suitable for assembly methods such as pasting and bonding. Then, discrete micro-components and devices are assembled on the ceramic substrate. The discrete micro-components and devices assembled can be semiconductor chips or monolithic integrated circuits, etc. Finally, an external package is added for sealing to form a hybrid integrated circuit.

[0004] Hybrid integrated circuits, especially thin-film hybrid integrated circuits, are in their advantageous fields in the low-frequency band. For example, for microwave circuit products below 6 GHz, since discrete capacitors, resistors, inductors, etc. are often required in the circuit, and these components are relatively large in size, a hybrid integrated circuit method must be used for integration, while it is more difficult to implement MMIC circuits.

[0005] The main problems existing in the existing hybrid integrated circuit technology are as follows: Due to the adoption of two-dimensional planar integration technology, all components are mounted on the ceramic substrate in the direction of the largest surface. The wire bonding between semiconductor chips and other devices and the ceramic substrate requires a certain span from one solder joint to another. In addition, necessary thin-film resistors, thin-film capacitors, thin-film inductors, etc. also need to be assembled on the ceramic substrate according to the requirements of specific circuits. Therefore, the number of components mounted on the surface of the ceramic substrate is limited, especially the components with larger volumes occupy most of the area and space on the ceramic substrate.

[0006] At the same time, as the operating frequency of the product decreases, some components in the circuit must use components that match the frequency. As the frequency decreases, the capacitance value of the capacitor, the inductance value of the inductor, the resistance value of the resistor, etc. will all increase, and their Q value, that is, the quality factor, is also required to be higher. For example, tantalum capacitors for filtering, core-wound inductors and magnetic-core wound inductors for matching, feeding, and transformers, etc. are all much larger in volume than semiconductor chip devices.

[0007] The two-dimensional planar integration technology not only affects the product volume and reduces the integration degree, but also brings certain impacts and limitations in circuit design, component assembly, and circuit debugging.

[0008] With the development of three-dimensional integration technology, the introduction of three-dimensional integration technology into hybrid integrated circuits can effectively improve the assembly density of components in hybrid integrated circuits, reduce the product package size, and further improve the adaptability and technological development of hybrid integrated circuits.

[0009] However, in three-dimensional hybrid integrated circuits, it is also necessary to propose effective technical solutions to solve the layout and debugging problems of components with larger volumes. Summary of the Invention

[0010] The purpose of the present invention is to provide a three-dimensional hybrid integrated circuit package structure, aiming to solve the problems of inconvenient component debugging and inconvenient layout of components with larger volumes.

[0011] To achieve the above object, the technical solution adopted by the present invention is: providing a three-dimensional hybrid integrated circuit package structure, including: a package housing, a lower substrate, and an upper substrate. The package housing is provided with pins penetrating through the bottom plate of the package housing; the lower substrate is connected to the package housing through lower back pads provided on the back surface of the lower substrate. The front surface of the lower substrate is provided with lower front pads, and the lower front pads and the pins are interconnected by gold wire bonding; the upper substrate is provided with upper front pads on its front surface and upper back pads on its back surface. The upper substrate is provided with a plurality of metal filling holes for connecting the upper front pads and the upper back pads. Solder balls arranged in an array are provided between the upper substrate and the lower substrate, and the upper substrate and the lower substrate are stacked and interconnected through BGA ball mounting flip-chip soldering process; components are provided on both the lower front pads of the lower substrate and the upper front pads of the upper substrate.

[0012] As another embodiment of the present application, the components on the upper front pads are a magnetic core winding inductor to be debugged and a first chip component. The magnetic core winding inductor is connected to the upper front pads through enameled wire. The components provided on the lower front pads of the lower substrate are a semiconductor chip that does not need to be debugged and a second chip component. The volume of the first chip component is larger than that of the second chip component.

[0013] As another embodiment of the present application, the magnetic core winding inductor and the first chip component are fixed on the upper front pads by pasting or soldering.

[0014] As another embodiment of the present application, the semiconductor chip and the second chip component are fixed on the lower front pads by pasting or soldering.

[0015] As another embodiment of the present application, the solder balls in the BGA ball mounting flip-chip soldering are arranged directly below each of the metal filling holes in a one-to-one correspondence.

[0016] As another embodiment of the present application, both the upper substrate and the lower substrate are ceramic components.

[0017] As another embodiment of the present application, the lower back surface pads of the lower substrate are fixed to the bottom plate of the package housing through conductive adhesive.

[0018] As another embodiment of the present application, the lower back surface pads are laid flat on the back surface of the lower substrate, and the peripheral side surfaces of the lower back surface pads are flush with the peripheral side surfaces of the lower substrate.

[0019] The present invention also provides an assembly method for a three-dimensional hybrid integrated circuit package structure, including the following steps:

[0020] Arrange components on the lower front surface pads of the lower substrate;

[0021] Utilize the BGA ball mounting flip-chip soldering process to connect the lower back surface pads of the upper substrate and the lower front surface pads of the lower substrate, realizing the stacked interconnection of the upper substrate and the lower substrate;

[0022] Fix the lower back surface pads of the lower substrate after stacked interconnection to the bottom plate of the package housing;

[0023] Fix components on the upper front surface pads of the upper substrate;

[0024] Bond the lower front surface pads of the lower substrate to the pins of the package housing through gold wires, and the components fixed on the upper substrate realize signal connection through metal filling holes, solder balls, lower front surface pads, gold wires and pins.

[0025] The beneficial effects of the three-dimensional hybrid integrated circuit package structure and the assembly method provided by the present invention are as follows: Compared with the prior art, the three-dimensional hybrid integrated circuit package structure of the present invention utilizes the ball grid array BGA technology to realize the stacked application of two substrates within the product package. The thin-film assembly process is adopted to assemble the lower substrate and the upper substrate; first, semiconductor chips and surface-mounted components are assembled on the lower substrate, and then the BGA ball mounting flip-chip soldering process is used to interconnect the upper substrate and the lower substrate to realize the stacked substrate; then the stacked substrate is assembled onto the bottom plate of the package housing; then, components such as relatively large chip capacitors and core-wound inductors that need to be debugged are assembled on the upper substrate; finally, gold wire soldering is used to connect the ports of the lower substrate or the upper substrate to the package pins, and the main performance debugging points are all set on the upper substrate, where fine adjustment, local debugging, and even replacement of component specifications can be performed to meet the performance indicators.

[0026] The present invention uses a three-dimensional integrated circuit to improve the integration degree of a hybrid integrated circuit. At the same time, components that are relatively large in size and require debugging can be placed on the upper substrate, which facilitates separate debugging and separate assembly. Moreover, other devices are not damaged during debugging, improving the operability of the product and simplifying the assembly difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 It is a schematic structural diagram of a three-dimensional hybrid integrated circuit package structure provided by an embodiment of the present invention;

[0029] Figure 2 It is a schematic structural diagram of a package housing provided by an embodiment of the present invention;

[0030] Figure 3 It is a schematic structural diagram of a lower substrate provided by an embodiment of the present invention;

[0031] Figure 4 It is a schematic structural diagram of an upper substrate provided by an embodiment of the present invention;

[0032] Figure 5 It is a schematic structural diagram of component assembly on the lower substrate provided by an embodiment of the present invention;

[0033] Figure 6 It is a schematic structural diagram of the lamination process of the lower substrate and the upper substrate provided by an embodiment of the present invention;

[0034] Figure 7 It is a schematic structural diagram of the laminated assembly of the lower substrate and the upper substrate provided by an embodiment of the present invention;

[0035] Figure 8 It is a structural diagram of the upper substrate after assembling components provided by an embodiment of the present invention;

[0036] Figure 9 It is a schematic manufacturing process diagram of a three-dimensional hybrid integrated circuit package structure provided by an embodiment of the present invention.

[0037] In the figure: 1. Encapsulation housing; 2. Pin; 3. Lower substrate; 4. Upper substrate; 5. Lower front pad; 6. Lower back pad; 7. Upper front pad; 8. Upper back pad; 9. Metal filling hole; 10. Solder ball; 11. Gold wire; 12. Semiconductor chip; 13. First surface-mounted device; 14. Core winding inductor; 15. Enameled wire; 16. Second surface-mounted device. Detailed implementation manners

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] Please refer to Figures 1 to 8 simultaneously, and a three-dimensional hybrid integrated circuit packaging structure provided by the present invention will be described. The three-dimensional hybrid integrated circuit packaging structure includes an encapsulation housing 1, a lower substrate 3, and an upper substrate 4. The encapsulation housing 1 is provided with pins 2 penetrating through the bottom plate of the encapsulation housing 1; the lower substrate 3 is connected to the encapsulation housing 1 through a lower back pad 6 provided on the back of the lower substrate 3. The front of the lower substrate 3 is provided with a lower front pad 5, and the lower front pad 5 and the pin 2 are interconnected by wire bonding with a gold wire 11; the upper substrate 4 is provided with an upper front pad 7 on the front and an upper back pad 8 on the back. The upper substrate 4 is provided with a plurality of metal filling holes 9 for connecting the upper front pad 7 and the upper back pad 8. Solder balls 10 are arranged in an array between the upper substrate 4 and the lower substrate 3, and the upper substrate 4 and the lower substrate 3 are stacked and interconnected through a BGA ball mounting flip-chip soldering process; components are provided on both the lower front pad 5 of the lower substrate 3 and the upper front pad 7 of the upper substrate 4.

[0040] Compared with the prior art, the three-dimensional hybrid integrated circuit packaging structure provided by the present invention utilizes the ball grid array BGA technology to realize the stacked application of two substrates within the product package. The lower substrate 3 and the upper substrate 4 are assembled by a thin-film assembly process; first, a semiconductor chip 12 and surface-mounted components are assembled on the lower substrate 3, and then the upper substrate 4 and the lower substrate 3 are interconnected by a BGA ball mounting flip-chip soldering process to form a stacked substrate; then the stacked substrate is assembled onto the bottom plate of the encapsulation housing 1; then components such as a relatively large surface-mounted capacitor and a core winding inductor 14 that needs to be debugged are assembled on the upper substrate 4; finally, the ports of the lower substrate 3 or the upper substrate 4 are connected to the package pins 2 by soldering with a gold wire 11. Among them, the main performance debugging points are all set on the upper substrate 4, and micro-adjustment, local debugging, and even replacement of component specifications can be performed to meet the performance indicators.

[0041] The present invention utilizes a three-dimensional solid circuit to improve the integration degree of a hybrid integrated circuit. At the same time, components that are relatively large in size and require debugging can be placed on the upper substrate 4, which facilitates separate debugging and separate assembly. Moreover, other devices are not damaged during debugging, improving the operability of the product and simplifying the assembly difficulty.

[0042] When debugging the circuit performance, the tightness and routing mode of the enameled wire 15 can be adjusted, or the specifications of the surface-mounted devices can be changed, or the specifications of the core-wound inductor 14 can be changed to meet the required circuit performance indicators. When replacing the components on the upper substrate 4 or during debugging, other components such as the semiconductor chips 12 are not damaged.

[0043] In the present invention, the main function of the package housing 1 is to carry the ceramic substrate and perform sealing protection on the internal circuit after assembly and debugging; the main function of the pins 2 is to conduct signal connection with the substrate through wire bonding with gold wires 11 inside the package and at the same time lead to the outside of the package housing 1.

[0044] Ball Grid Array, abbreviated as BGA, is to make spherical contacts as pins on the back of the substrate in an array manner, and components are assembled on the front of the substrate (for some BGA chips, the lead-out ends are on the same side as the substrate). It is a surface-mount package used for multi-pin LSI (Large-scale integrated circuit). In this embodiment, there are two layers of substrates. The ball grid array solder balls 10 are led out from the back of the upper substrate 4, and components can be installed on the front of both the upper substrate 4 and the lower substrate 3, improving the integration degree of the hybrid integrated circuit. At the same time, components that are relatively large in size and require debugging are placed on the upper ceramic substrate, which facilitates separate debugging and separate assembly.

[0045] Among them, the metal filling holes 9 play a role in connecting signals and grounding.

[0046] As a specific implementation manner of the three-dimensional solid hybrid integrated circuit package structure provided by the present invention, please refer to Figure 1, the components on the upper front pad 7 are the core-wound inductor 14 to be debugged and the first surface-mount device 13. The core-wound inductor 14 is connected to the upper front pad 7 through an enameled wire 15. The components on the lower front pad 5 of the lower substrate 3 are the semiconductor chip 12 and the second surface-mount device 16 that do not need to be debugged. At the same time, the semiconductor chip 12 and the second surface-mount device 16 that do not need to be debugged are interconnected with the lower front pad 5 by gold wires 11. The volume of the first surface-mount device 13 is larger than that of the second surface-mount device 16. By fixing the components that need to be debugged and the components with larger volume on the upper substrate 4, it is convenient for separate debugging and separate assembly, and other devices are not damaged during debugging. Moreover, the overall height or volume of the packaged device can be reduced, improving the operability of the product and simplifying the assembly difficulty.

[0047] As a specific implementation manner of an embodiment of the present invention, please refer to Figure 1 , the core-wound inductor 14 and the first surface-mount device 13 are fixed on the upper front pad 7 by pasting or soldering.

[0048] As a specific implementation manner of an embodiment of the present invention, refer to Figure 1 , the semiconductor chip 12 and the second surface-mount device 16 are fixed on the lower front pad 5 by pasting or soldering.

[0049] As a specific implementation manner of an embodiment of the present invention, please refer to Figure 1 , the solder balls 10 in the BGA ball grid array flip chip solder joints are arranged one by one directly below each of the metal filling holes 9. The solder balls 10 are tin balls, or copper pillars, or gold bumps, or alloy bumps.

[0050] As a specific implementation manner of an embodiment of the present invention, please refer to Figure 1 , both the upper substrate 4 and the lower substrate 3 are ceramic parts. Using thin-film process technology, front and back circuit patterns are assembled on the front and back of the upper substrate 4 and the lower substrate 3.

[0051] As a specific implementation manner of an embodiment of the present invention, please refer to Figure 1 , the lower back pad 6 of the lower substrate 3 is fixed to the bottom plate of the package housing 1 through a conductive adhesive.

[0052] As a specific implementation manner of an embodiment of the present invention, please refer to Figure 1 , the lower back pad 6 is laid flat on the back of the lower substrate 3, and the peripheral sides of the lower back pad 6 are flush with the peripheral sides of the lower substrate 3.

[0053] See Figures 1 to 9, the present invention also provides an assembly method for a three-dimensional hybrid integrated circuit packaging structure, comprising the following steps:

[0054] S101: Set components on the lower front pads 5 of the lower substrate 3;

[0055] S102: Use the BGA ball-planting flip-chip soldering process to connect the lower back pads 6 of the upper substrate 4 and the lower front pads 5 of the lower substrate 3, realizing the stacked interconnection of the upper substrate 4 and the lower substrate 3;

[0056] S103: Fix the lower back pads 6 of the lower substrate 3 after stacked interconnection to the bottom plate of the packaging shell 1;

[0057] Fix components on the upper front pads 7 of the upper substrate 4;

[0058] S104: Bond the lower front pads 5 of the lower substrate 3 to the pins 2 of the packaging shell 1 through gold wires 11, and the components fixed on the upper substrate 4 achieve signal connection through metal filling holes 9, solder balls 10, lower front pads 5, gold wires 11 and pins 2.

[0059] In this embodiment, the BGA ball-planting flip-chip soldering process is an existing packaging technology for multi-pin 2 devices and circuits. The biggest feature of BGA is that it uses solder balls 10 as pins 2, which not only improves the packaging density but also improves the packaging performance.

[0060] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. 3D three-dimensional hybrid integrated circuit package structure, characterized in that, comprising: a package housing provided with pins penetrating the bottom plate of the package housing; a lower substrate connected to the package housing through lower back pads provided on the back surface of the lower substrate, the front surface of the lower substrate being provided with lower front pads, and the lower front pads and the pins being interconnected by wire bonding with gold wires; an upper substrate having upper front pads on its front surface and upper back pads on its back surface, the upper substrate being provided with a plurality of metal filling holes for connecting the upper front pads and the upper back pads, solder balls arranged in an array being provided between the upper substrate and the lower substrate, and the upper substrate and the lower substrate being stacked and interconnected by BGA ball mounting flip-chip soldering process; components are provided on both the lower front pads of the lower substrate and the upper front pads of the upper substrate; the components on the upper front pads are a core-wound inductor to be debugged and a first chip component, the core-wound inductor being connected to the upper front pads by enameled wires, the components provided on the lower front pads of the lower substrate being a semiconductor chip not requiring debugging and a second chip component, and the volume of the first chip component being larger than the volume of the second chip component; the core-wound inductor and the first chip component are fixed on the upper front pads by pasting or soldering; the semiconductor chip and the second chip component are fixed on the lower front pads by pasting or soldering.

2. The 3D three-dimensional hybrid integrated circuit package structure according to claim 1, characterized in that, the solder balls in the BGA ball mounting flip-chip soldering are arranged one by one directly below each of the metal filling holes.

3. The 3D three-dimensional hybrid integrated circuit package structure according to claim 1, characterized in that, both the upper substrate and the lower substrate are ceramic components.

4. The 3D three-dimensional hybrid integrated circuit package structure according to claim 1, characterized in that, the lower back pads of the lower substrate are fixed to the bottom plate of the package housing by conductive adhesive.

5. The 3D three-dimensional hybrid integrated circuit package structure according to claim 1, characterized in that, the lower back pads are laid flat on the back surface of the lower substrate, and the peripheral sides of the lower back pads are flush with the peripheral sides of the lower substrate.

6. The assembly method of the 3D three-dimensional hybrid integrated circuit package structure according to any one of claims 1-5, characterized in that, comprising the following steps: arranging components on the lower front pads of the lower substrate; using the BGA ball mounting flip-chip soldering process to connect the lower back pads of the upper substrate and the lower front pads of the lower substrate to achieve stacked interconnection of the upper substrate and the lower substrate; fixing the lower back pads of the stacked and interconnected lower substrate to the bottom plate of the package housing; fixing components on the upper front pads of the upper substrate; bonding the lower front pads of the lower substrate to the pins of the package housing by gold wires, and the components fixed on the upper substrate achieving signal connection through metal filling holes, solder balls, lower front pads, gold wires and pins.

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