Boron-doped GaAs crystals with low etch pit density

Abstract

Methods and systems for low etch pit density gallium arsenide crystals containing boron dopants may include a gallium arsenide single crystal wafer containing boron as a dopant and having an etch pit density of less than 500 cm ‑2 , and the light absorption at 940nm is 6cm ‑1 The chip's etch pit density can be less than 200cm ‑2 The diameter of the wafer can be 6 inches or larger. The boron concentration of the wafer can be between 1×10 19 cm ‑3 and 2×10 19 cm ‑3 The thickness of the wafer may be 300 μm or more. An optoelectronic device may be formed on the first surface of the wafer, the wafer may be cut into a plurality of dies, and an optical signal from an optoelectronic device on one side of one of the dies may be transmitted from a side of the die opposite to the first side.

Description

[0001] CROSS-REFERENCE / INCORPORATION TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 779,036, filed on December 13, 2018, which is hereby incorporated by reference in its entirety into this application. Technical Field

[0003] Certain embodiments of the present invention relate to semiconductor substrates. More specifically, certain embodiments of the present invention relate to low etch pit density gallium arsenide crystals containing boron dopants. Background Art

[0004] Semiconductor substrates, especially III-V semiconductor substrates, are used to manufacture electronic and optoelectronic devices such as heterojunction bipolar transistors (HBTs), pseudomorphic high electron mobility transistors (pHEMTs), and lasers, for example. Defects in the substrates can reduce productivity and increase costs.

[0005] Other limitations and disadvantages of conventional and traditional solutions will be apparent to those skilled in the art by comparing such systems with the present invention as described in the remainder of this application in conjunction with the accompanying drawings. Summary of the invention

[0006] A system and / or method for low etch pit density gallium arsenide crystals containing boron dopants is generally as shown in and / or described in conjunction with at least one of the accompanying drawings, as more fully recited in the claims.

[0007] Various advantages, aspects and novel features of the present invention, as well as specific details of illustrated embodiments thereof, will be more fully understood from the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram showing a vertical gradient solidification reactor according to an exemplary embodiment of the present invention.

[0009] Figure 2 Shown are etch pit density results for a 6-inch gallium arsenide wafer manufactured according to one embodiment of the present invention.

[0010] Figure 3 A flow chart of manufacturing a gallium arsenide wafer using a vertical gradient solidification method according to an exemplary embodiment of the present invention is shown.

[0011] Figure 4 Devices fabricated on a 6-inch semi-insulating gallium arsenide wafer with low etch pit density are shown according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0012] Certain aspects of the present invention may be based on methods and corresponding wafers for low etch pit density gallium arsenide crystals containing boron dopants.

[0013] Figure 1 is a schematic diagram showing a vertical gradient solidification reactor according to an exemplary embodiment of the present invention. Figure 1 , a vertical gradient solidification (VGF) system 100 is shown, which includes an ampoule 110, a support 107, a heating coil 120, and a crucible 130. Within the ampoule 110, growth can be performed using a seed crystal 101 and a liquid melt 105 in a vertical configuration, wherein a solid 103 is formed due to a very gradual cooling of the melt 105. The crucible 130 may include, for example, pyrolytic boron nitride (PBN), and may contain the melt and seed material during the manufacturing process.

[0014] The VGF system 100 includes an arrangement for a growth charge, heater, insulator, and support that includes: direct radiation from a heating coil 120 above the level of the cone in the crystal growth charge, a seed 101, and may also include a support structure 107 for supporting an ampoule 110 in the heating coil 120. In addition, an insulator 109 may be placed within the support 107 to facilitate inward radiative heat flow during growth and heat dissipation during post-growth and cooling. The support cylinder 107 for the growth ampoule 110 may include a hollow cone located below the seed capsule containing the seed crystal 101 to provide a conductive heat flow path downward through the center that is aided and made more stable by a larger diameter quartz rod leading down to the bottom of the heater.

[0015] In the VGF process, a polycrystalline charge, seed 101, in a crucible 130 in an ampoule 110 may be heated using a multi-zone furnace, represented by heating coils 120. Crystal growth is initiated by melting the charge to the seed 101, thereby forming a melt 105, and the temperature is slowly reduced to cool the melt 105 at the seed 101. The crystallization process to form a solid 103 can be precisely controlled by changing the temperature gradient of different furnace zones, such as applying different currents to different parts of the heating coils 120. Thus, the heating coils 120 can constitute a multi-zone heating system capable of achieving different temperatures, different heating / cooling rates, and different spatial temperature distributions.

[0016] The VGF method has many advantages over other methods such as the liquid enclosed Czochralski method (LEC) and the horizontal Bridgman method (HB). First, the thermal environment of the crystal and the melt is radially symmetric, enabling a radially uniform interface and precise temperature distribution control. Second, the growth with low axial and radial temperature gradients, combined with the diameter control applied by the crucible and the absence of large temperature gradients for rapid solidification of the crystal, can significantly reduce strain and thus dislocations in the crystal. Third, the liquid-solid interface develops upward through the melt and crystallization begins at the seed 101 at the bottom of the crucible. The system is cooler at the bottom and can be thermodynamically stabilized against convection. Even during the cooling process, the easily adjustable cooling allows the crystal to reach room temperature with the lowest possible defect rate.

[0017] Previously, non-n-type or p-type average dislocation densities of 1000 cm-1 have not been produced in wafers of 6 inches or larger diameter. -2 The following GaAs crystal. Conventional silicon-doped GaAs wafers can have low EPD due to the solid solution hardening effect when doped in sufficiently high amounts, but this can result in large infrared absorption. In an exemplary embodiment of the present invention, boron can be used as a dopant, added to pure GaAs crystals, to achieve a very low dislocation density effect when the VGF method is performed with special growth control. In an example case, in order to improve the infrared transmittance of the substrate, silicon doping is not used, however a small amount can still be present, co-doped with boron.

[0018] Before crystal growth, boron-containing GaAs polycrystals are pre-prepared by poly synthesis. The poly synthesis method can be carried out in a quartz reaction tube using a boat method, which can ensure that boron is uniformly introduced into the GaAs crystal, enabling the crystal growth process to accept dopants. Once polycrystalline GaAs is generated, the VGF crystal growth process can be carried out. In order to achieve low EPD, multiple VGF parameters are carefully controlled. The first parameter may include the shape of the melt / crystal interface 140, which can be controlled to be concave to the melt, for example, 10 mm concave, and the center of a 6-inch diameter crystal is about 10 mm lower than the edge. This can be controlled with different time-temperature distributions and / or spatial temperature distributions.

[0019] Secondly, the crystallization speed, which is controlled by the cooling rate, can be set to 0.2-0.5°C / hour. Different solidification rates can be set at different parts of the ingot. The temperature gradient along the growing crystal can produce stress in the boule, where the head cools earlier and in some cases it can happen that the head is about 100 degrees cooler than the tail, so precise control is required.

[0020] Finally, the temperature gradient at the melt / crystal interface can be set to between 4 and 8°C / cm. Similarly, multi-zone heating enables precise control of the temperature throughout the crucible 130. After all solidification is completed, the heating temperature can be reduced to room temperature in different heating zones at rates of approximately 0.5-5°C / hour, 1-20°C / hour, and 5-20°C / hour, respectively. This method can obtain a 6-inch diameter GaAs single crystal with a length of approximately 85 mm and a cylindrical portion and low dislocation. Although this method is targeted at 6-inch diameter ingots, the same method can also be used in other diameters using different furnace sizes. The dislocation density obtained by this method is less than 500cm -2 , less than 200cm -2 , even less than 100cm -2 ,like Figure 2 shown.

[0021] Figure 2 Figure 2 shows the etch pit density results for a 6-inch gallium arsenide wafer manufactured according to one embodiment of the present invention. Figure 2 EPD measurements were performed according to SEMI M36-0699 and ASTM test method F140-92. 2 An example of the EPD level measured at Figure 2 In , the results are for the seed end and the tail end of the crystal.

[0022] Wafers from different ingots were measured, showing average EPDs of 50 and 75 / cm2 for the wafers at the seed end of the two ingots. 2 , the maximum EPD is 875 and 1583 / cm 2 The average EPD of the wafers at the tail end of the two ingots is 156 and 164 / cm 2 , the maximum EPD is 3125 and 4958 / cm 2 This is a significant improvement over existing GaAs substrates.

[0023] Table 1 shows the absorption coefficient data of GaAs substrate.

[0024] Dopant Thickness(μm) Absorption coefficient (1 / cm) B 692 5.340 B 693 5.337 B 693 3.823 B 694 4.585 Si 577 10.219 Si 578 9.040 Si 580 7.057 Si 581 11.113

[0025] Table 1 shows the absorption data of wafers from the ingots prepared by the method of the present invention. For wafers from both ends of the ingot with a nominal thickness of about 600 μm, the absorption coefficient values ​​at a wavelength of 940 nm were measured. The wafers can be between 300 μm and 1000 μm, for example. For the boron-doped wafers, the absorption coefficients are all less than 6 cm -1This value is much lower than that of conventional Si-doped GaAs wafers, whose absorption coefficient can be between about 7.0-11.0 cm -1 As shown above for the silicon-doped wafer, using similar measurements at 940 nm. At 1000 nm and 1050 nm, the absorption coefficient of the boron-doped wafer is less than 2 cm -1 .

[0026] Growing low-absorption B-doped GaAs wafers with extremely low EPD by the VGF method can bring high device productivity and is very useful in the design and production of vertical light-emitting structures such as LEDs and VCSELs (vertical cavity surface emitting lasers) using flip-chip technology. The above VGF method can obtain wafers with extremely low EPD and low absorption of 6 inches or more in diameter.

[0027] Figure 3 Shows the use of Figure 1 The method for making GaAs wafers in the vertical gradient solidification furnace 100 shown in the figure. The method obtains an etch pit density of less than 500 cm -2 6-inch GaAs substrate, can obtain less than 100cm -2 The average corrosion pit density is less than 6cm -1 The absorption coefficient at 940nm. This method can also be used to make indium phosphide (InP), gallium phosphide (GaP) or other related III-V compound semiconductors.

[0028] In step 301, raw materials arsenic (As), gallium (Ga) and boron (B) may be obtained and tested on the raw materials before placing them in a boat in a quartz tube to prepare B-doped polycrystalline GaAs by polysynthesis. The method includes preparing the charge with a crucible containing boron-containing polycrystalline GaAs pre-made by polysynthesis, a seed crystal, an appropriate amount of B2O3 sealant, an appropriate amount of carbon dopant, emptying the crucible and sealing the crucible in a fused quartz ampoule.

[0029] Once polycrystalline GaAs is grown, vertical gradient freezing (VGF) crystal growth is performed in step 303, where an ampoule with a crucible is heated in a controlled manner in a multi-zone heating system to gradually melt the boron-containing polycrystalline charge from top to bottom until a portion of the seed crystals are melted. Growth can be initiated from the partially melted seeds by implementing controlled cooling of the multi-zone heater. The temporal and spatial temperature profiles are closely controlled to obtain temperatures below 500 cm -2 Crystals of 6 inches or larger in diameter.

[0030] To achieve low EPD, multiple VGF parameters are carefully controlled. The first parameter may include the shape of the melt / crystal interface, which can be controlled to be concave into the melt, for example 10 mm, with the center of a 6-inch diameter solidified crystal being about 10 mm lower than the edge. This can be controlled using different time-temperature profiles and / or spatial temperature profiles. Secondly, the crystallization rate, which is controlled by the cooling rate, can be set to 0.1-2°C / hour for different parts of the ingot, while applying a temperature gradient of 1 to 8°C / cm at the melt-crystal interface. By using an appropriate cooling rate in a multi-zone heating system, the interface shape can be controlled to be slightly concave into the melt. Different solidification rates can be set at different parts of the ingot. Finally, the temperature gradient at the melt / crystal interface can be set to between 4 and 8°C / cm. After the entire solidification of the charge material is completed, controlled cooling is applied at appropriate cooling rates of 0.5-5°C / hour, 1-10°C / hour and 5-20°C / hour for different heating zones for the initial 300°C, and then cooled to room temperature at a rate of 20-50°C / hour to obtain crystals with very low defect density.

[0031] Once the VGF crystal is grown (and optionally inspected), an ingot shaping process may be performed in step 305 to obtain, for example, a rounded ingot with a desired flatness, which may also be inspected. Once the crystal is shaped, the ingot may be cut into wafers in step 307, and the wafers may be optionally inspected.

[0032] Once the low EPD wafers are cut from the ingot, the wafers may proceed to wafer processing step 309. An optional wafer annealing process may be performed. In an exemplary annealing process, one or more annealing stages may be employed in which the wafers may be vertically loaded into a horizontal quartz boat and inserted into a horizontal quartz ampoule along with an arsenic block. The arsenic block may be configured to provide the required vapor pressure at the annealing temperature to avoid arsenic dissociation from the GaAs substrate. The ampoule is then pumped to a high vacuum level (less than 5E -3 The ampoule and its contents can then be inserted into, for example, a horizontal 3-zone furnace to begin heating the ampoule and its contents to the desired set (plateau) temperature.

[0033] To ensure structural and electrical quality, testing can be performed on the wafer. In one example, the boron concentration in the entire ingot can be greater than 1×10 19 cm -3 , in some embodiments between 1.0×10 19 cm -3 Up to 2×10 19 cm -3and the boron ratio is 1:1 to 1:3 from one end of the ingot to the other, or 1:1 to 1:1.5 in a more uniform ingot. The structural quality can be assessed by X-ray characterization and etch pit density measurement. The above method can produce less than 500 / cm 2 , less than 200cm -2 , even less than 100cm -2 The structural and electrical quality can also be assessed by optical absorption measurements, where the absorption coefficient at 940 nm can be measured at 6 cm -1 the following.

[0034] Once the low EPD wafers are annealed and optionally tested, a wafer polishing process for polishing the low EPD wafers can be performed, and the polished wafers can optionally be tested again. Once the wafers are polished, they can be cleaned and then proceed to step 311 where they can be packaged for shipping to customers. The above process can also be used to manufacture indium phosphide (InP) or other composite semiconductor wafers. As a result of this method, a low EPD 6-inch GaAs wafer is produced.

[0035] Figure 4 A device fabricated on a low etch pit density, low absorption 6-inch gallium arsenide wafer according to an exemplary embodiment of the present invention is shown. Figure 4 , which shows a 6-inch GaAs wafer 401 manufactured using the above method and further processed using electronic devices and / or optoelectronic devices on a die 403. It also shows a flat 405, which can be formed during wafer manufacturing to indicate a crystal plane. The number of dies 403 on the wafer 401 can be defined by the area of ​​each die, Figure 4 The dimensions shown are only an example.

[0036] In addition, die 403 may include optoelectronic devices such as edge-emitting lasers, vertical cavity surface emitting lasers (VCSELs), and optical detectors when it is necessary to transmit optical signals through wafer 401. For example, a row of detectors or surface emitting lasers may be formed on wafer 401, and a reader and control circuit may be placed on the device while receiving optical signals and / or transmitting optical signals through wafer 401. The low optical signal absorption described herein is, for example, less than 5 cm at 940 nm. -1 or less than 2cm at 1000nm -1 , allowing such infrared applications.

[0037] The above method can be used to prepare semi-insulating low-doped substrates, and / or doped substrates. Semi-insulating GaAs substrates enable the preparation of high-speed electronic devices due to the high resistivity of the substrate, where the conductive substrate can cause losses and parasitic capacitance. Example devices include pseudomorphic high electron mobility transistors (pHEMTs) and heterojunction bipolar transistors (HBTs). Dislocations in the substrate can reduce the reliability of the device because, for example, current flow can increase the defect size. In addition, the resulting wafers have a sufficiently low 6 cm at 940 nm. -1 The following absorption can form optical and optoelectronic devices on the chip with minimal loss of optical signals when passing through the chip.

[0038] In one embodiment of the present invention, the low etch pit density gallium arsenide crystal containing boron as a dopant may include a gallium arsenide single crystal wafer containing boron as a dopant, wherein the etch pit density is less than 500 cm -2 , the light absorption at 940nm is 6cm -1 The wafer may have a diameter of less than 200 cm -2 The diameter of the wafer can be 6 inches or larger. The boron concentration of the wafer can be greater than 1×10 19 cm -3 , or in some embodiments between 1×10 19 cm -3 Up to 3×10 19 cm -3 The thickness of the wafer may be above 300 μm. A plurality of optoelectronic devices may be formed on the first surface of the wafer, which is cut into a plurality of bare chips, and an optical signal from an optoelectronic device on one side of one of the bare chips may be transmitted from the side of the bare chip opposite to the first side.

[0039] In another embodiment of the present invention, a method for low etch pit density gallium arsenide crystals containing boron dopants may include: sealing a charge material in a crucible, the charge material including a polycrystalline gallium arsenide seed crystal, a B2O3 sealant and carbon; sealing the crucible in a quartz ampoule; heating the ampoule by using a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal is melted, thereby performing a vertical gradient solidification crystal growth process; initiating growth from the partially melted seed by controlled cooling of the multi-zone heating system; applying a temperature gradient of 1 to 8°C / cm at the melt-crystal interface; and controlling the shape of the interface using a cooling rate in the multi-zone heating system so that it is concave toward the melt to form a solidified gallium arsenide crystal.

[0040] The cooling of the multi-zone heating system can be configured at a rate of 0.1-2°C / hour. The crucible can be evacuated before it is sealed in the quartz ampoule. For the first 300°C, the solidified charge can be cooled at rates of 0.5-5°C / hour, 1-10°C / hour, and 5-20°C / hour in different heating zones, and then cooled to room temperature at a rate of 20-50°C / hour. The interface shape can be controlled to be concave toward the melt, with the center of the solidified crystal about 10mm lower than the edge. The diameter of the solidified crystal can be 6 inches or larger, and the etch pit density can be 500cm -2 The boron concentration of the solidified crystal can be greater than 1×10 19 cm -3 , in some embodiments between 1×10 19 cm -3 Up to 2×10 19 cm -3 The solidified crystal may include an ingot, and the boron concentration in the ingot may be greater than 1×10 19 cm -3 , in some embodiments between 1×10 19 cm -3 Up to 3×10 19 cm -3 and the boron ratio is 1:1 to 1:1.5 from one end of the ingot to the other.

[0041] Although the present invention has been described in conjunction with certain embodiments, it will be appreciated by those skilled in the art that various modifications and equivalent substitutions may be made without departing from the scope of the present invention. In addition, in order to conform a particular situation or material to the teachings of the present invention, a variety of modifications may be made without departing from the scope. Therefore, it is intended to point out that the present invention is not limited to the specific embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the claims.

Claims

1. Gallium arsenide single crystal wafers containing boron as a dopant and no silicon, with an etch pit density of less than 500 cm -2 , and the light absorption at 940nm is 6cm -1 the following; The boron concentration of the wafer is greater than 1×10 19 cm -3 ; The method for forming a gallium arsenide single crystal comprises: Sealing a charge material in a crucible, the charge material comprising a polycrystalline gallium arsenide seed crystal, a B2O3 sealant, and carbon; The crucible was sealed in a quartz ampoule; The ampoule is heated by adopting a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal is melted, thereby performing vertical gradient solidification crystal growth; Initiating growth from the partially melted seeds by controlled cooling of the multi-zone heating system, wherein the cooling of the multi-zone heating system is controlled at a rate of 0.1 to 2° C. / hour; applying a temperature gradient of 1 to 8°C / cm at the melt-crystal interface; and The shape of the interface is controlled to be concave toward the melt by using the cooling rate in the multi-zone cooling system to form a solidified gallium arsenide crystal; The boron concentration of the solidified crystal is greater than 1×10 19 cm -3 .

2. The wafer according to claim 1, wherein the etch pit density of the wafer is less than 200 cm -2 .

3. The wafer according to claim 1, wherein the etch pit density of the wafer is less than 100 cm -2 .

4. The wafer of claim 1, wherein the wafer has a diameter of 6 inches or greater. The wafer according to claim 1 , wherein the wafer has a thickness of 300 μm or more.

6. The wafer according to claim 1, wherein electronic devices and / or optoelectronic devices are formed on the first surface of the wafer.

7. The wafer according to claim 6, wherein the wafer is cut into a plurality of dies, and an optical signal from an optoelectronic device on one side of one of the dies is transmitted from a side of the die opposite to the side.

8. The wafer of claim 1, wherein the method comprises evacuating the crucible prior to sealing the crucible in the quartz ampoule.

9. The wafer of claim 1 , wherein the method comprises cooling the solidified charge material at rates of 0.5-5° C. / hour, 1-10° C. / hour and 5-20° C. / hour for different heating zones for the initial 300° C., and then cooling to room temperature at a rate of 20-50° C. / hour.

10. The wafer according to claim 1, wherein the method includes controlling the shape of the interface to be concave toward the melt, with the center of the solidified crystal being 10 mm lower than the edge.

11. The wafer of claim 1, wherein the diameter of the solidified crystal is greater than 6 inches.

12. The wafer according to claim 1, wherein the etch pit density of the solidified crystal is 500 cm -2 Below, and the light absorption at 940nm is 6cm -1 the following.

13. The wafer according to claim 1, wherein the solidified crystal comprises an ingot, the boron concentration in the ingot being greater than 1×10 19 cm -3 , and the ratio of boron is 1:1 to 1:3 from one end of the ingot to the other.

14. A semiconductor substrate, comprising: The gallium arsenide single crystal wafer according to any one of claims 1 to 13, wherein the wafer contains boron as a dopant and does not contain silicon, and the etching pit density is less than 500 cm -2 , boron concentration is greater than 1×10 19 cm -3 Up to 3×10 19 cm -3 and the light absorption at 940nm is 6cm -1 the following.

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