Apparatus for digitally controlled oscillators and related methods

Abstract

The present application discloses an apparatus for a digitally controlled oscillator and a related method. An apparatus includes a digitally controlled oscillator (DCO), the digitally controlled oscillator including an inductor coupled in series with a first capacitor. The DCO also includes: a second capacitor coupled in parallel with the series-coupled inductor and the first capacitor; a first inverter coupled in parallel with the second capacitor; and a second inverter coupled back-to-back to the first inverter. The DCO also includes a digital-to-analog converter (DAC) for changing the capacitance of the first capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to the following U.S. patent applications: U.S. patent application No. 16 / 221,426, filed on December 14, 2018, entitled “Apparatus for Digital Frequency Synthesizers and Associated Methods,” attorney docket No. SILA408; and U.S. patent application No. 16 / 221,430, filed on December 14, 2018, entitled “Apparatus for Time-to-Digital Converters and Associated Methods,” attorney docket No. SILA409. Technical Field

[0003] The present disclosure relates generally to signal generating apparatus and methods, and more particularly, to apparatus including a digitally controlled oscillator (DCO) and related methods. Background Art

[0004] With the increasing popularity of wireless technologies such as Wi-Fi, Bluetooth, and mobile or wireless Internet of Things (IoT) devices, more and more devices or systems integrate RF circuits, such as receivers and / or transmitters. In order to reduce cost, size, and bill of materials, and to improve the reliability of such devices or systems, various circuits or functions have been integrated into integrated circuits (ICs). For example, an IC typically includes a receiver and / or transmitter circuit. Typically, the receiver and / or transmitter circuit uses one or more signals to perform various functions, such as clock circuits (e.g., analog-to-digital converters (ADCs)), image rejection calibration, mixing radio frequency (RF) signals to baseband or intermediate frequencies (IFs), mixing baseband or IF signals to RF signals, etc.

[0005] The description in this section and any corresponding drawings are included as background information material. The inclusion of the materials in this section should not be construed as an admission that such materials constitute prior art to this patent application. Summary of the invention

[0006] Various apparatus and related methods are contemplated according to exemplary embodiments. According to one exemplary embodiment, an apparatus includes a digitally controlled oscillator (DCO) comprising an inductor coupled in series with a first capacitor. The DCO also includes: a second capacitor coupled in parallel with the series-coupled inductor and the first capacitor; a first inverter coupled in parallel with the second capacitor; and a second inverter coupled back-to-back to the first inverter. The DCO also includes a digital-to-analog converter (DAC) for varying the capacitance of the first capacitor. More specifically, the capacitance of the first capacitor is varied in order to perform relatively fine frequency control of the frequency of the output signal of the DCO. More specifically, the DAC varies the capacitance of the second capacitor to perform relatively coarse frequency control of the output signal of the DCO.

[0007] According to another exemplary embodiment, a device includes a DCO, the DCO including: a first capacitor having a first terminal and a second terminal; a first inductor having a first terminal and a second terminal, wherein the first terminal is dotted and coupled to the first terminal of the first capacitor; and a second inductor having a first terminal and a second terminal, wherein the first terminal is dotted and coupled to the second terminal of the first capacitor. The DCO also includes a group of capacitors coupled in a Π-configuration, wherein the first terminal of the Π-configuration is coupled to the second terminal of the first inductor, and the second terminal of the Π-configuration is coupled to the second terminal of the second inductor.

[0008] According to another exemplary embodiment, a device includes a DCO, the DCO including: a first capacitor having a first terminal and a second terminal; a first inductor having a first terminal and a second terminal, wherein the first terminal is dotted and coupled to the first terminal of the first capacitor; and a second inductor having a first terminal and a second terminal, wherein the first terminal is dotted and wherein the second terminal is coupled to the second terminal of the first capacitor. The DCO also includes a group of capacitors coupled in a Π-configuration, wherein the first terminal of the Π-configuration is coupled to the second terminal of the first inductor, and the second terminal of the Π-configuration is coupled to the first terminal of the second inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present application or claims. It will be understood by those skilled in the art that the disclosed concepts lend themselves to other equivalent embodiments. In the accompanying drawings, the same reference numerals used in more than one drawing represent the same, similar or equivalent functions, components or blocks.

[0010] Figure 1A and Figure 1B A circuit arrangement of a DFS according to an exemplary embodiment is shown.

[0011] Figure 2 A circuit arrangement of a TDC according to an exemplary embodiment is shown.

[0012] Figure 3 A timing diagram of a TDC according to an exemplary embodiment is shown.

[0013] Figure 4 A circuit arrangement of a coarse TDC (C-TDC or CTDC) according to an exemplary embodiment is shown.

[0014] Figure 5A The circuit arrangement of a conventional TDC is shown.

[0015] Figure 5B A circuit arrangement of a fine TDC (F-TDC or FTDC) according to an exemplary embodiment is shown.

[0016] Figure 6 A circuit arrangement of a digital loop filter according to an exemplary embodiment is shown.

[0017] Figure 7 A diagram showing transfer functions of various circuit blocks of a DFS according to an exemplary embodiment is shown.

[0018] Figure 8 A diagram showing transfer functions of various circuit blocks of a DFS according to another exemplary embodiment is shown.

[0019] Fig. 9 A diagram showing transfer functions of various circuit blocks of a DFS according to another exemplary embodiment is shown.

[0020] Fig.10 A diagram relating to a first operating mode of a sigma-delta modulator (SDM) according to an exemplary embodiment is shown.

[0021] Fig.11 A diagram relating to another mode of operation of the SDM is shown according to an exemplary embodiment.

[0022] Fig.12 A diagram relating to another mode of operation of the SDM is shown according to an exemplary embodiment.

[0023] Fig.13 A circuit arrangement for a first operating mode of an SDM according to an exemplary embodiment is shown.

[0024] Fig.14A circuit arrangement for another operating mode of the SDM according to an exemplary embodiment is shown.

[0025] Fig.15 A circuit arrangement for another operating mode of the SDM according to an exemplary embodiment is shown.

[0026] Fig.16 A circuit arrangement of a conventional inductor-capacitor (LC) oscillator is shown.

[0027] Fig.17 A circuit arrangement of a single-ended digitally controlled inductor-capacitor (LC) oscillator (DCO) according to an exemplary embodiment is shown.

[0028] Fig.18 A circuit arrangement for controlling a single-ended DCO according to an exemplary embodiment is shown.

[0029] Fig.19 A circuit arrangement of a differential mode DCO according to an exemplary embodiment is shown.

[0030] Fig. 20 A circuit arrangement of a differential mode DCO according to another exemplary embodiment is shown.

[0031] Fig.21 A circuit arrangement of an RF receiver including a DFS according to an exemplary embodiment is shown.

[0032] Fig. 22 A circuit arrangement of an RF receiver including a DFS according to an exemplary embodiment is shown.

[0033] Fig.23 A circuit arrangement of an RF receiver including a DFS according to an exemplary embodiment is shown.

[0034] Fig.24 A circuit arrangement of an RF transmitter including a DFS according to an exemplary embodiment is shown.

[0035] Fig.25 A circuit arrangement of an RF communication system according to an exemplary embodiment is shown.

[0036] Fig.26 A circuit arrangement of an IC including a receiver including one or more DFSs according to an exemplary embodiment is shown.

[0037] Fig. 27 A circuit arrangement of an IC including a transmitter including one or more DFSs according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0038] One aspect of the present disclosure relates to DFS. DFS according to various embodiments may be used in various devices, subsystems, systems, modules, ICs, etc. Without limitation, examples include RF receivers, RF transmitters, and RF transceivers.

[0039] From an area perspective, DFS is beneficial because the loop filter (charge pump, capacitors, and resistors in analog implementations) is implemented digitally. A smaller number of circuits include strictly analog or mixed-signal components in DFS, such as TDC and DCO. Compared to conventional analog approaches to frequency synthesizers, DFS provides lower area, higher immunity to semiconductor manufacturing process variations, easier programmability, and faster migration to new technology nodes.

[0040] A DFS according to an exemplary embodiment employs a fractional-N phase-locked loop (PLL) with residue cancellation. Fractional divider control is implemented by a sigma-delta modulator (SDM). Residue cancellation is performed by a digital subtractor at the output of the TDC. In contrast, an analog PLL typically uses a DAC to implement residue cancellation. In an analog system, the linearity and gain of the residue DAC, phase detector, and charge pump have a relatively high impact on the performance of the analog synthesizer. In a DFS according to various embodiments, fewer parameters (such as the gain and linearity of the TDC) have a relatively high impact on the DFS performance. In addition, the gain error of the TDC can be fully compensated in the digital domain. As described in more detail below, after the residue cancellation, the measurement of the RMS phase error is used to digitally adjust the gain of the residue path to increase or maximize the residue cancellation and minimize the RMS phase error of the DFS.

[0041] As mentioned above, another aspect of the present disclosure relates to a TDC. With respect to a digital loop filter, as used in an exemplary embodiment, the phase error between a reference input signal (refclk) and a feedback clock or signal is converted to a digital output and used to lock the DFS. In an exemplary embodiment, this conversion of the error signal to a digital signal is performed by a TDC.

[0042] A TDC according to an exemplary embodiment can be an arbitrarily long loop because the delay line is implemented as a loop. The signal propagates along the line, but can wrap around multiple times so that a longer total delay can be achieved. Each time the signal wraps around, another latch in a string of latches is set to count how many cycles are completed. Such a TDC can produce a relatively fine step size, for example, up to 22ps in a 40nm semiconductor manufacturing node, even with such fine resolution near the locked position. On the other hand, a larger phase error can tolerate a coarse TDC. Therefore, in an exemplary embodiment, a CTDC is used together with a fine TDC (FTDC or F-TDC) so that the entire 2π range can be spanned. As needed, a vernier technique known to those of ordinary skill in the art can be used as an enhancement of such a TDC.

[0043] TDCs according to various embodiments provide many benefits. First, they use all-digital circuits, thereby reducing size / circuit area and improving simplicity. Second, the use of a wraparound structure described in detail below saves area and clock signal power. In addition, the coarse TDC (CTDC or C-TDC) in the exemplary embodiments saves size / circuit area, reduces power consumption, and reduces or minimizes jitter accumulation (compared to designs that use all fine steps to cover the entire 2π range).

[0044] As described above, another aspect of the present disclosure relates to a DCO. With respect to a digital loop filter, as used in a DFS according to an exemplary embodiment, the digital output of the loop filter (or a signal derived from the output signal of the digital loop filter) controls an oscillator (typically an LC oscillator). In an exemplary embodiment, a digital-to-analog converter (DAC) is included in the LC voltage-controlled oscillator (VCO) circuit. Controlling the frequency of the VCO can be achieved by using the output signal of the DAC to change the capacitance of the LC tank. In other words, the digital output signal of the digital loop filter is used to digitally program the capacitance value of the LC tank and therefore the output frequency of the VCO.

[0045] Conventional techniques for digitally controlling the frequency of an LC oscillator cannot achieve fine frequency resolution through capacitor selection because the capacitors will be relatively small and difficult to implement, as described above. In conventional implementations, the capacitors that are switched (to change the capacitance of the LC tank) will be on the order of aF (i.e., 10 -15 F) to obtain a relatively fine frequency resolution. As described in detail below, a DCO topology according to an exemplary embodiment uses two inductors and two sets of capacitors. This topology provides a relatively wide tuning range and relatively fine frequency steps, which together enable a reasonable size of the DCO frequency control word through feasible capacitor size selection.

[0046] An alternative to conventional methods utilizes a sigma-delta modulator to drive a switchable capacitor. A density of the modulator is then used to implement a fractional value of the capacitor that is 0 to 1 times the actual capacitance. The sigma-delta modulation used to implement the effective value of the fractional capacitor uses digital hardware that consumes power, uses additional circuit area, and may introduce switching spurs in the clock output. The DCO according to an exemplary embodiment does not employ a sigma-delta modulator, and in a locked condition, the effective relatively small capacitor (relatively low capacitance) is rarely triggered to maintain the phase lock of the DFS.

[0047] Figure 1A 1 shows a circuit arrangement of a DFS 10 according to an exemplary embodiment. The DFS 10 employs a negative feedback loop. More specifically, as described above, the TDC 1005 converts the phase difference between the reference clock refclk and the feedback clock fbclk provided by the multi-mode divider (MMD) 1045 into a digital value. The MMD 1045 divides the nominal (or desired) frequency (labeled "LO") of the output signal of the DFS 10 by a number that can be an integer or an integer plus a fraction. The negative feedback loop causes the average frequency of the MMD output signal to be the same as the frequency of the reference signal. The role of the negative feedback loop is to minimize the frequency and phase errors in the output signal of the DFS 10.

[0048] The output signal of TDC 1005 is provided to subtractor 1015. The output signal of scaling circuit 1055 (described below) is provided to another input of subtractor 1015. The difference between the two signals (i.e., the output signal of subtractor 1015) is provided to digital loop filter 1020, which digitally filters the output signal of subtractor 1015. In an exemplary embodiment, as understood by one of ordinary skill in the art, digital loop filter 1020 can have a desired order, such as a first order filter, a second order filter, etc. For a given implementation, the selection of the filter order and the resulting circuit depends on a variety of factors, such as design specifications, performance specifications, cost, IC or device area, available technology (e.g., semiconductor manufacturing technology), target market, target end user, etc., as will be understood by one of ordinary skill in the art. The filtered signal at the output of digital loop filter 1020 drives DCO 1025. DCO 1025 includes a DAC 1030 that converts the output of digital loop filter 1020 to program a capacitor array in a VCO circuit of DCO 1025 .

[0049] The output signal of DCO 1025 is provided to divider 1035. Divider 1035 divides the frequency of its input signal by a desired value, such as 2 in the example shown (hence labeled "Div 2"), although other values ​​may be used as desired. The output signal of divider 1035 constitutes the output signal of DFS 10 (labeled "LO"). As described above, the output signal of DFS 10 drives MMD 1045.

[0050] It should be noted that, as will be understood by one of ordinary skill in the art, the frequency divider 1035 may be omitted in some embodiments, depending on the desired frequency of the output signal of the DFS 10 and the available frequency of refclk. In addition, it should be noted that in some embodiments, the MMD 1045 may be optional. Specifically, if the desired output frequency of the DFS 10 is equal to (or nearly equal to in a practical implementation) the reference frequency, the MMD 1045 may be omitted, and the output signal of the DFS 10 is fed back to the input of the TDC 1005.

[0051] The integer value and fractional value of DFS 10 are provided to SDM 1060 (for example, if a total value of 64.3 is desired, the integer (N) value and fractional (n) value provided to SDM 1060 are N=64 and n=0.3, respectively). In response, SDM 1060 generates an output signal sdbits and a residual signal. The output signal sdbits is provided to delay circuit 1050, which delays sdbits by the desired delay value. The delayed signal is used to control MMD 1045, that is, to select the desired modulus for MMD 1045. In an exemplary embodiment, the delay provided by delay circuit 1050 is selected to match the delay of scaling circuit 1055.

[0052] The residual signal from SDM 1060 is provided to scaling circuit 1055. Scaling circuit 1055 multiplies the residual signal by a value selected from x1 to x4 representing a scaling value (or other values ​​and / or values ​​as desired). The scaling value scales the residual value to match the gain of TDC 1005. As described above, the output of scaling circuit 1055 is provided to subtractor 1015.

[0053] The output of the scaling circuit 1055 is also provided to a least mean square (LMS) adaptive circuit 1040. The output of the TDC 1005 is also provided to the LMS adaptive circuit 1040. The output of the LMS adaptive circuit 1040 is used to select a scaling value in the scaling circuit 1055, for example, one of x1 to x4 in the example shown. Thus, a feedback loop is formed around the LMS adaptive circuit 1040 and the scaling circuit 1055, wherein in response to the phase error level at the output of the TDC 1005 and the scaled residual from the scaling circuit 1055, the LMS adaptive circuit 1040 causes a change in the gain (scaling factor) of the scaling circuit 1055 to reduce or minimize the effect of the residual on the DFS 10 (i.e., perform residual cancellation). In other words, the phase error level at the output of the TDC 1005 is used to select the gain (scaling factor) of the scaling circuit 1055 to cause cancellation of the residual or residual effect. In other words, the gain or scaling factor of the scaling circuit 1055 is selected or set to reduce or eliminate the phase error due to the residual signal.

[0054] In an ideal locked condition, the phase error from the TDC 1005 will be exactly equal to the value predicted by the scaled residual (i.e., the output of the scaling circuit 1055), i.e., the output of the TDC 1005 is equal to the output of the scaling circuit 1055, which results in a zero output of the subtractor 1015. However, in a practical implementation, the gain error in the TDC 1005 causes the output of the subtractor 1015 to be finite, i.e., non-zero. The LMS adaptive circuit 1040 tracks the magnitude of the phase error from the TDC 1005 (the output signal of the TDC 1005) relative to the scaled residual (the output of the scaling circuit 1055), and increases or decreases the gain of the scaling circuit 1055 in a relatively slow manner (to allow variations to be resolved in various circuits) so as to drive the difference between the scaled residual and the TDC phase error to zero (or close to zero in a practical implementation). Therefore, the LMS adaptive circuit uses a least mean square technique in combination with feedback to drive the output of the subtractor 1015 to zero (or close to zero) by changing the gain of the scaling circuit 1055. In this manner, scaling circuit 1055 operates as an adaptive or self-adaptive scaling circuit.

[0055] In some embodiments, the incremental gain change occurs for each phase measurement (i.e., once for each cycle of the reference clock refclk), and the incremental gain change is selected to be relatively small, such as less than 1% of the nominal scaling factor or gain of the scaling circuit 1055. In some embodiments, the adaptation or adaptive function of the LMS adaptive circuit 1040 can be enabled or disabled during DFS operation. For example, in some embodiments, to prevent divergence of the LMS adaptation, the LMS adaptive circuit 1040 can be disabled if the TDC phase error (the output of the TDC 1005) is relatively large, indicating that the DFS has not achieved phase lock.

[0056] The output of the subtractor 1015 is provided to the residual error circuit 1010. When the feedback loop in the DFS 10 is locked, the input of the digital loop filter 1020 should have a value of zero. The residual error circuit 1010 produces an output signal that is approximately representative of the variance of the jitter (the absolute value sum of the outputs of the subtractors 1015, e.g., obtained by using an integrate / dump technique), i.e., a measure of the gain match between the residual signal from the SDM 1060 and the gain of the TDC 1005. The jitter represents the quantization jitter of the SDM 1060. The output signal of the residual error circuit 1010 is provided to the jitter monitor circuit 1017. By examining the jitter variance at the output of the subtractor 1015 (as measured by the residual circuit 1010 and monitored by the jitter monitor circuit 1017), as described above, a measure of the quality of the reference signal and / or the convergence of the LMS adaptation function can be obtained. The DFS 10 (or another module or circuit in a system or device including the DFS 10) can use the monitoring performed by the jitter monitor circuit 1017 to determine potential degradation of the LO phase noise without direct phase noise measurement. In addition, if the DFS 10 does not implement the LMS adaptive function, the monitored jitter can be used to calibrate the residual calibration circuit 1005, as described below in conjunction with Figure 1B described.

[0057] Figure 1B A circuit arrangement of a DFS 10 according to another exemplary embodiment is shown. Figure 1B DFS 10 and Figure 1A is similar to DFS 10 in , but uses a different residual elimination technique. More specifically, again referring to Figure 1B, the output of the residual error circuit 1010 is provided to the calibration circuit 1065. The calibration circuit 1065 uses the output of the residual error circuit 1010 (roughly the variance of the jitter) to select the scaling ratio or gain of the scaling circuit 1055 so as to cause residual cancellation (reduce or cancel or eliminate the effect of the residual on the DFS 10). In some embodiments, the calibration circuit 1065 can use information or data included or contained in the firmware, such as information determined during the design, manufacture, testing and / or operation of the DFS 10 or a device (e.g., IC) that includes the DFS 10. Such information or data is then used for residual cancellation during operation of the DFS 10.

[0058] Figure 2 The circuit arrangement of TDC 1005 according to an exemplary embodiment is shown. TDC 1005 includes C-TDC 1100 and F-TDC 1105, which together cover the entire 2π range of phase error values. C-TDC 1100 covers the range of the entire cycle of reference clock refclk. F-TDC 1105 implements a range centered on the lock position, within which quantization jitter such as SDM 1060 is maintained. Signal refclk drives the input of C-TDC 1100. Signal fbdel from delay circuit 1110 in F-TDC 1105 drives another input of C-TDC 1100. The delay generated by delay circuit 1110 is half the range of output values ​​of F-TDC 1105. The output of C-TDC 1100 includes signal ctdc (having 2 to 7 bits in the example shown, although other values ​​can be used as needed) and early / late signals. Both output signals of C-TDC 1100 are provided to control circuit 1115 .

[0059] The signal refclk also drives the input of the F-TDC 1105. The signal fbclk (see Figure 1A 1B) drives delay circuit 1110. As described above, a delayed version of signal fbclk is provided as signal fbdel. The output of F-TDC 1105 includes signal ftdc (having 0 to 5 bits in the example shown, although other values ​​may be used as desired), which is provided to control circuit 1115. Using signals ctdc and ftdc and the early / late signal, control circuit 1115 generates an output signal of TDC 1005, which includes a tdc signal and a sign bit signal (i.e., signbit). In the example shown, the tdc signal has 0 to 11 bits, but other values ​​may be used as desired.

[0060] Reference Figure 3, the operation of the control circuit 1115 can be better understood, which shows a timing diagram of the TDC according to an exemplary embodiment. More specifically, the figure shows the range of the C-TDC and F-TDC output signals, which are related to the refclk, fbdel and fbclk signals. The range of values ​​corresponding to the early and late periods is also indicated. The locked condition (or ideal state) is indicated at the boundary between the early and late ranges.

[0061] therefore, Figure 3 It is shown that the C-TDC causes a number of phase steps within a range indicated as the "C-TDC range" to bring the frequency of the fbclk signal closer to the frequency of the refclk signal. The F-TDC causes a number of additional phase steps within a range indicated as the "F-TDC range" to bring the frequency of the fbclk signal closer to the frequency of the refclk signal and eventually enter phase lock. It should be noted that the "C-TDC range" spans the "F-TDC range". In other words, the "C-TDC range" is divided into two ranges, one range below or before or in front of the "F-TDC range" and the other range above or after or behind the "F-TDC range". In addition, it should be noted that in various embodiments, one or more C-TDC phase steps (one or more phase steps taken by the C-TDC 1100) are larger than one or more F-TDC phase steps (one or more phase steps taken by the C-TDC 1105), so the labels are "coarse" TDC (C-TDC) and "fine" TDC (F-TDC), respectively. In some embodiments, the ratio of one or more C-TDC phase steps to one or more F-TDC phase steps is an integer. In some embodiments, the ratio of one or more C-TDC phase steps to one or more F-TDC phase steps is a non-integer.

[0062] Figure 4 1 shows a circuit arrangement of a C-TDC 1100 according to an exemplary embodiment. The refclk and fbdel signals drive the D input and the clock input of a D-type flip-flop 1210. As described above, the output of the flip-flop 1210 constitutes an early / late signal (a binary logic value of 0 indicates that the fbdel signal is early, while a binary logic value of 1 indicates that the fbdel signal is late). The refclk and fbdel signals also drive the input of the control circuit 1205. In response, the control circuit 1205 generates a reset signal that is used to reset the synchronous counter 1220 to an initial count value. The control circuit 1205 also generates an enable signal for the oscillator 1215. In response to the enable signal (i.e., when the enable signal is asserted), the oscillator 1215 provides a clock signal to the synchronous counter 1220.

[0063] More specifically, control circuit 1205 enables oscillator 1215 at the occurrence of a rising edge of refclk (or fbdel). Control circuit 1205 stops (deasserts the enable signal) oscillator 1215 at the rising edge of fbdel (or refclk). The output of synchronous counter 1220 together with the early / late signal constitutes the ctdc signal.

[0064] Figure 5A The circuit arrangement of a conventional TDC is shown. The TDC includes a chain of delay circuits fed by an input signal (e.g., fbclk), a chain of flip-flops fed by a clock signal (e.g., refclk), and a thermometer to binary encoder. The operation of the circuit is known to those of ordinary skill in the art. Figure 5A In the conventional method of TDC shown in the figure, the phase difference (or time difference) between the two clock signals can be measured and quantized into discrete values ​​by passing one clock signal (CLK1) through a delay line and using a second clock signal (CLK2) to control the sampling action of the trigger. In essence, the transition in the second clock signal takes a snapshot of the output of the delay element and locates the distance that the first clock signal has propagated into the delay line. This position can then be encoded as a binary output that represents the relative time delay between the two clock signals. If a relatively large delay range is desired, the direct approach is to simply cascade more delay stages and add more triggers. However, doing so will increase the chip area, require more triggers to be driven by the second clock signal, and the corresponding additional capacitive load will increase power consumption, and as the second clock signal is distributed to more triggers, there will be more complex clock skew management.

[0065] Instead of extending the length of the delay line and associated flip-flops, a recirculating delay line and associated flip-flops can be created. Conceptually, when the first clock transition occurs, it is emitted into the first delay element in a delay circuit or delay line containing multiple delay cells or elements. The first clock signal propagates through the delay line, and when it reaches the last delay element, an inverted version of the output signal of the last delay element is fed into the first delay element, and at the same time a wrap counter records that a round trip through the delay element has occurred. The first clock signal continues to propagate and wrap around the delay line until a second clock samples the wrap count value and all states of the delay element simultaneously. The encoder circuit then combines the flip-flop samples and generates a binary output. As described in detail below, Figure 5B One implementation of this concept is shown.

[0066] More specifically, in Figure 5BA single-ended embodiment of a recirculating F-TDC is shown in . Initially, the multiplexer (MUX) is set to one position, namely position “0”, and a first clock signal (e.g., fbclk) transitions into the first delay cell. When the first clock signal reaches the last delay cell, the output signal of the delay cell signal is inverted, and the MUX is automatically reconfigured to select the recirculating signal with another position (e.g., position “1”). The MUX remains in this position until a second clock signal (e.g., refclk) samples the output of the delay cell and the wrap-around counter. After sampling is completed, a reset signal clears the wrap-around counter, sets the MUX to position “0”, and sets all delay elements to their reset levels (e.g., “0”).

[0067] Reference Figure 5B The reference signal refclk drives the clock input of the D-type flip-flops 1275 coupled in a cascade or chain. The output of the flip-flops 1275 is provided to the encoder logic circuit 1270. The output of the encoder logic circuit 1270 constitutes the output of the F-TDC 1105, namely the ftdc signal (see Figure 2 ).

[0068] Reference again Figure 5B , the D input of the flip-flop 1275 is driven by the output signal of the MUX 1255 and a delayed version of the signal. More specifically, the output signal of the MUX 1255 is provided to the D input of the first flip-flop 1275. The outputs of a set of delay circuits coupled in a cascade or chain manner drive the corresponding D inputs of the remaining flip-flops 1275. The output of the last delay circuit 1110 drives the input of the inverter 1250. The output of the inverter 1250 drives one input of the MUX 1255, as well as the clock input of the wrap-around counter 1265. In response, the wrap-around counter 1265 counts the number of times the signal has propagated through the delay circuit 1110. The output of the wrap-around counter 1265 is provided to the encoder logic circuit 1270. The encoder logic circuit 1270 combines the wrap count value (the output of the wrap-around counter 1265) with the state of the flip-flop 1275 (the Q output) to form a signed binary output word. If the wrap count is even, the state of the flip-flop 1275 is thermometer-to-binary encoded by the encoder logic circuit 1270. However, if the wrap count is odd, the state of the flip-flop 1275 is inverted in the encoder logic circuit 1270 before the thermometer-to-binary conversion in the encoder logic circuit 1270.

[0069] Signal fbclk drives a second input of MUX 1255. A select signal for MUX 1255 is provided by MUX control circuit 1260. If the select signal for MUX 1255 has a binary logic 0 value, signal fbclk is provided as an output signal for MUX 1255. Conversely, if the select signal has a binary logic 1 value, the output signal of inverter 1250 is provided as an output signal for MUX 1255. MUX control circuit 1260 generates the select signal using the fbclk signal, the refclk signal, and the output signal of inverter 1250.

[0070] In an exemplary embodiment, such as Figure 5B In the illustrated embodiment, the F-TDC 1105 is of a recirculating type or operates in a recirculating manner. The recirculating operation of the F-TDC 1105 (including the operation of the MUX control circuit 1260) occurs as follows: Initially, the F-TDC 1105 is reset with the falling edge of refclk, and the MUX 1255 provides the fbclk signal as the output signal (i.e., the binary logic 0 value of the selection signal). Initially, the fbclk clock signal propagates through the delay blocks in the delay circuit 1110 (all delay line outputs change from 0 to 1 in sequence). When the signal reaches the last delay block, the following occurs: (a) the inverter 1250 provides a binary logic 0 to the MUX 1255; (b) the wrap counter 1265 increments to indicate that a trip through the delay circuit 1110 has occurred; (c) the MUX 1255 switches to position 1 (providing the output signal of the inverter 1250) and remains in that position until the F-TDC 1105 is reset. The output of MUX 1255 then propagates a binary logic zero through delay circuit 1110. If a second wrap condition occurs, wrap counter 1265 increments and MUX 1255 propagates a binary logic one value through delay circuit 1110. Further wrapping causes wrap counter 1265 to increment and binary logic values ​​of one and zero to propagate alternately through delay circuit 1110.

[0071] On the rising edge of refclk, the output values ​​of all flip-flops 1275 and wrap counter 1265 are sampled. Encoder logic circuit 1270 encodes the output value (or count) of wrap counter 1265 and the output signal of flip-flops 1275 and produces a binary word representing the time (or phase difference) between two clock edges (fbclk and refclk). On the falling edge of refclk, the entire circuit in F-TDC 1105 is reset and the process continues as described above.

[0072] Figure 61 shows a circuit arrangement of a digital loop filter 1020 according to an exemplary embodiment. The input signal of the loop filter 1020 consists of a signal "a" (which has 0 to 15 bits, i.e., a 16-bit signal, although other values ​​may be used as desired), and a signbit signal (i.e., a signal indicating the sign of the "a" signal) provided, for example, by the TDC 1005 (see Figure 2 ) composition. Again refer to Figure 6 , signal "a" and the "signbit" signal are provided to a one's complement circuit 1305. The output of the one's complement circuit 1305 drives a first input of an adder 1310, and the signbit signal constitutes the carry (ci) input of the adder 1310. The output of register 1325, signal yout (which has 0 to 15 bits in the example shown, although other sizes or values ​​may be used as desired) drives a second input of the adder 1310.

[0073] The sum of the inputs to adder 1310 is provided in the form of a signal xout, which has 0 to 15 bits in the example shown, but other sizes or values ​​may be used as desired. Signal xout drives the input of register 1325, and signal refclk clocks register 1325. The output of one's complement circuit 1305 is scaled by scaling circuit 1315, which scales the signal by 2 N The output signal of scaling circuit 1315 constitutes the proportional path signal and is provided to adder 1320. The signbit signal is provided as the carry (ci) to adder 1320. Signal xout (the output of adder 1310) constitutes the integral path signal and is also provided to adder 1320. The summed output of adder 1320 drives the input of register 1330, which is clocked by signal refclk. The output of register 1330 constitutes the digital control signal used to control DCO 1025 (see Figure 1A or Figure 1B ).

[0074] Reference again Figure 6, the control circuit (not shown) detects overflow and underflow conditions and sets the output of register 1330 appropriately as needed. More specifically, if the carry out signal of adder 1320 has a logic 1 signal and the carry in signal of adder 1320 has a binary logic 0 value, an overflow condition exists. Therefore, the output of register 1330 is set to all ones (0xFFFF for the example shown). Conversely, if the carry in of adder 1320 has a binary logic 1 value, the previous most significant bit (MSB) of the output of adder 1320 has a binary 0 logic value, and the new MSB of the output of adder 1320 has a binary 1 logic value, an underflow condition (negative number) is detected. Therefore, the output of register 1330 is set to all zeros (0x0000 for the example shown).

[0075] Figure 7 A graphical representation of the transfer functions of various circuit blocks of a DFS according to an exemplary embodiment is shown. The transfer functions can be used to derive the overall transfer function of the DFS 10. In the exemplary embodiment shown, block 1375 represents the transfer function of the TDC 1005, block 1378 represents the integral path of the loop filter (digital loop filter 1020 in FIG. 1), block 1380 represents the proportional path of the loop filter, block 1382 represents a summer or adder, block 1385 represents a VCO or DCO, and block 1388 represents a feedback path circuit. Using the transfer functions shown, the overall transfer function can be expressed as:

[0076]

[0077] Where K O =2πK vco T ref

[0078] as well as

[0079]

[0080] And K vco represents the DCO gain, K o represents the DCO phase change, k D represents the TDC gain, k P represents the proportional path gain, k I represents the integral path gain, T ref represents the period of the reference clock signal refclk (e.g., 26ns in the BLE example), and Δ TDC is the nominal phase step size of the F-TDC1105 (e.g., 22ps in the BLE example).

[0081] Figure 8 FIG. 4 shows a diagram of transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. More specifically, the diagram shows a transfer function including SDM and residual elimination (e.g., Figure 1A or 1B) in the DFS of each block. Figure 8 , some of which are related to Figure 7 The blocks in are the same as in , namely 1375, 1378, 1380, 1382 and 1385. Block 1400 represents the MMD, block 1405 represents the SDM, and blocks 1408 and 1410 represent the processing of the SDM error output to produce a residual. The residual is scaled by block 1412. It should be noted that the adaptation k DD The LMS adaptive technique for compensating TDC gain variations with process and temperature is not shown in this figure for ease of demonstration. Blocks 1405, 1408, and 1410 correspond to Figure 1A and Figure 1B The SDM 1060 and the delay circuit 1050 in FIG. Figure 8 The transfer function shown, the overall transfer function can be expressed as:

[0082]

[0083] Assume k I =1; k P = 32, 64, and 128; and a refclk frequency of 38.4 MHz (e.g., an implementation of DFS for Bluetooth Low Energy (BLE) applications), the VCO or DCO frequency range (2·N·refclk) ranges from 4200-5700 MHz, which means that N values ​​are 54-74. Using these values, and assuming that K VCO is about 5kHz / LSB, and according to k D According to the above formula, a TDC step size of 22.2ps should be used.

[0084] Fig. 9 FIG. 1 shows a diagram of the transfer functions of various circuit blocks of a DFS according to another exemplary embodiment. The DFS in this example uses a third order PLL, as indicated by the addition of block 1390 (compare Figure 7 and Fig. 9 ). Block 1390 is a first-order low-pass filter, which is used to reduce the high-frequency ripple from the output of the summing block 1382 to reduce the phase noise and spurious generated at the DCO output, that is, block 1385. The parameter β is changed to change the corner frequency of the low-pass filter, that is, block 1390. Fig. 9 In , block 1378 implements the integral path, block 1380 implements the proportional path, and the two are combined by summing block 1382. Blocks 1378, 1380, 1382 and 1390 are represented as a group as a loop filter, that is, Figure 1A and Figure 1B The digital loop filter 1020 in FIG. Using the transfer function shown, the overall transfer function can be expressed as:

[0085]

[0086] In an exemplary embodiment, a second-order or third-order SDM may be used, which may have 2, 3, 4, or other values ​​for the number of output levels. As will be appreciated by one of ordinary skill in the art, in selecting Figure 1A and Figure 1B Many tradeoffs need to be made when determining the design and performance parameters of the SDM 1060 in FIG. 1. As will be appreciated by those skilled in the art, for a given implementation, the selection of such parameters and the resulting circuit depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technology (such as semiconductor manufacturing technology), target market, target end user, etc.

[0087] For example, using a third order SDM results in lower quantization noise below 6.7 MHz (e.g., using the BLE example above), but the digital loop filter 1020 will use an extra pole in its transfer function to suppress quantization noise at higher frequency levels. On the other hand, using a second order SDM will allow for a simpler and wider bandwidth digital loop filter 1020. A higher number of output levels (e.g., 4) will accommodate relatively large jitter suppression from the SDM 1060 relative to the output level. On the other hand, using a lower number (e.g., 2) will reduce the range of the FTDC 1105 (see Figure 2 ), resulting in reduced power consumption, reduced circuit area / size, and reduced accumulated jitter.

[0088] As an illustration, and by way of example only, for an embodiment that accommodates BLE parameters and specifications, a second order SDM 1060 with a 1-bit output may be used. Such a choice would accommodate the relatively high bandwidth used for transmit modulation and would reduce or minimize the switching step size of the MMD 1045 (see Figure 1A or Figure 1B ), and will reduce or minimize the range of FTDC 1105 (as opposed to a multi-bit SDM). Such an SDM will have three modes depending on the value of n (the fractional division / divide parameter of the DFS). The three modes are as follows:

[0089] Mode 0: 0.25 <n<0.75

[0090] Mode 1: n≤0.25

[0091] Mode 2: n ≥ 0.75

[0092] Using the above pattern, the fractional portion (n) is kept relatively close to a level of 50% in order to reduce or minimize the output signal ( Figure 1A or Figure 1B The spurious and tone outputs in the sdbits (in sdbits). Fig.10 Operation is shown in Mode 0. In this mode, the output signal sdbits of SDM 1060 switches between values ​​N and N+1. Fig.11 Operation is shown in Mode 1. In this mode, the output signal sdbits of SDM 1060 switches between values ​​N-1 and N+1. Fig.12 Operation is shown in Mode 2. In this mode, the output signal sdbits of SDM 1060 switches between values ​​N and N+2.

[0093] To implement Modes 0, 1, and 2, some changes are made to the circuitry and / or operating parameters of SDM 1060. Fig.13 A circuit arrangement of an SDM 1060 operating in Mode 0 is shown according to an exemplary embodiment. As described above, the SDM 1060 receives values ​​of n and N as input signals. The fractional value (n) is provided to an adder 1060A, which receives a constant -0.5 at a second input. The sum at the output of adder 1060A drives the input of adder 1060B, and the second input of adder 1060B receives the output of a 1-bit digital-to-digital converter (DDC) 1060K, which is multiplied by -0.5 by a scaling circuit 1060M. The DDC 1060K generates a +1 or -1 value at its output, depending on the value of its input signal.

[0094] The sum at the output of adder 1060B drives the input of integrator 1060C. The output of integrator 1060C constitutes the residual output of SDM 1060 and is also provided to adder 1060D. The output of DDC 1060K, which is multiplied by -1.0 by scaling circuit 1060L, drives the other input of adder 1060D. The sum at the output of adder 1060D drives the input of integrator 1060F, the output of which drives one input of adder 1060G. As will be appreciated by one of ordinary skill in the art, the other input of adder 1060G is driven by the output of a pseudo-random binary sequence (PRBS) dither circuit 1060E (used to break up periodic cycles or limit cycles in SDM 1060 to eliminate or reduce spurs or make the input signal of quantizer 1060H look more like noise).

[0095] The sum at the output of adder 1060G drives the input of quantizer 1060H (e.g., by using a comparator, as will be understood by those skilled in the art). The output of quantizer 1060H is provided to DDC 1060K as an input signal. The sum at the output of adder 1060G is quantized into a single bit by quantizer 1060H and then provided to delay circuit 1060I. The delayed output of delay circuit 1060I drives one input of adder 1060J. The input value N drives the second input of adder 1060J. The sum at the output of adder 1060J is provided as the output of SDM 1060 and is used to drive MMD 1045. In the illustrated case (i.e., mode 0), as described above, the output switches between N and N+1.

[0096] Fig.14 1060I. The circuit arrangement of SDM 1060 operating in mode 1 according to an exemplary embodiment is shown. In this mode, a scaling circuit 1060N with a gain of 0.5 is driven by an input signal n, and its output drives the input of adder 1060A. A second input of adder 1060A is driven by a value of 0. In addition, scaling circuit 1060P scales the output of integrator 1060C by 2.0 and provides the resulting scaled value as a residual output. Scaling circuit 1060Q scales the output of delay circuit 1060I by 2.0 and provides the resulting value to adder 1060J. A third input to adder 1060J is provided with a value of -1.0.

[0097] Fig.15 A circuit arrangement of SDM 1060 operating in Mode 2 according to an exemplary embodiment is shown. In this mode, the gain of scaling circuit 1060N is 0.5, which is the same as in Mode 1. However, the second input of adder 1060A is driven by a value of -0.5. Similar to Mode 1, scaling circuit 1060P scales the output of integrator 1060C by 2.0 and provides the resulting scaled value as a residual output. In addition, similar to Mode 1, scaling circuit 1060Q scales the output of delay circuit 1060I by 2.0 and provides the resulting value to adder 1060J. The third input to adder 1060J is provided with a value of 0.

[0098] As described above, one aspect of the present disclosure relates to a DCO. In an exemplary embodiment, a DAC is included in the DCO (see Figure 1A or Figure 1B ) to program (or set or configure or adjust) the effective capacitance of the LC resonant tank used in the VCO. Fig.16A circuit arrangement of a conventional LC oscillator 1600 is shown, which includes an inductor L, a capacitor C, and back-to-back inverters 1605 and 1610. Considering this simple LC resonant tank oscillator in the context of the above BLE example, the BLE modulation uses a frequency deviation of ±250kHz or about ±102ppm. Assuming that 6 bits are used to control the value of capacitor C, a change in the value of the least significant bit (LSB) will cause a frequency change of about 7.8kHz, or about 3.2ppm. A frequency change of 3.2ppm means ±6.4ppm in capacitance. Assuming the nominal value of capacitor C is 1pF, ±6.4ppm in capacitance means a step size of ±6.4aF, which may not be feasible with current manufacturing technology.

[0099] The topology used by the DCO according to the exemplary embodiment is different from that of the conventional VCO (see Fig.16 ). Fig.17 1 shows a circuit arrangement of a single-ended DCO 1025 according to an exemplary embodiment (DAC 1030 is not shown). DCO 1025 includes a capacitor C. However, instead of a simple inductor, DCO 1025 uses a capacitor C. x The inductor L is coupled in series to achieve an effective inductance L eff In other words, the inductor L and capacitor C x The combination provides an effective inductance L eff , which forms an LC resonant circuit together with capacitor C. Inverter 1605 is coupled back-to-back to inverter 1610. Inverter 1605 and inverter 1610 are coupled in parallel with capacitor C and in series with inductor L and capacitor C. x Parallel coupling.

[0100] By changing the capacitors C and C x As mentioned above, the topology shown provides a relatively wide tuning range and relatively fine frequency steps, which together make the capacitor C x In DCO 1025, L eff The value of can be expressed as:

[0101]

[0102] or

[0103]

[0104] Capacitor C x The step size change can be expressed as:

[0105]

[0106] The step size change in output frequency is given by:

[0107]

[0108] Capacitor C x The step size change can be expressed as:

[0109]

[0110] Assume that the capacitance of capacitor C is 1pF and capacitor C x The capacitance is 20pF, ΔC x The value is about 1.52fF, which is Fig.17 The corresponding step size change in the circuit shown is about 380 times larger. Therefore, Fig.17 The DCO topology shown in will be easier to implement.

[0111] Fig.18 1 shows a circuit arrangement for controlling the frequency of a single-ended DCO 1025 according to an exemplary embodiment. More specifically, the figure shows that a DAC 1030 receives a set of control signals (from a digital loop filter 1020, such as Figure 1A or 1B), and use this group of control signals to change capacitors C and C x Assuming those capacitors are implemented as varactor diodes, DAC 1030 can drive an analog voltage to control or vary capacitors C and C x Alternatively, instead of using DAC1030, the control circuit includes logic circuits and switches to program capacitors C and C x Typically, as will be understood by one of ordinary skill in the art, capacitors C and C x This can be achieved in a variety of ways through a combination of programmable (discrete capacitance step changes) and varactor capacitors. As will be appreciated by one of ordinary skill in the art, the choice of implementation for a given embodiment depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technology (such as semiconductor manufacturing technology), target market, target end users, etc.

[0112] Using the BLE example discussed above, assuming a frequency tuning range of ±10% (±100,000ppm) and a frequency resolution (or step size) of about 3.2ppm for the DCO output signal, the DAC 1030 will have to use about 16 bits in the set of control signals. x that is, some bits are used to change the capacitance of capacitor C, and the remaining bits in the group of control bits are used to change the capacitance of capacitor C x of capacitance.

[0113] In an exemplary embodiment, capacitors C and C x There may be discontinuities in the total capacitance provided. Given this assumption, capacitors C and C x The capacitance values ​​are designed to overlap (for example, using non-radix 2 capacitors C and C x In addition, the capacitor C can be designed x , so that the fractional division of the fractional value (n) (by MMD 1045 (see Figure 1A or 1B) implementation) value does not cause a change in capacitor C. Therefore, taking BLE as an example, capacitor C x The variation should cover a frequency range of at least 38.4MHz from 2.45GHz, or 15,600ppm. Capacitor C x A 2ppm resolution in the capacitance of C represents 7,800 steps in the capacitance value. Therefore, 13 bits will be allocated to change the capacitor C x The additional four bits will be allocated to change the capacitance value of capacitor C. Fig.18 This configuration is shown.

[0114] However, it should be noted that the choice of the total number of bits in the set of control bits has a significant impact on the capacitors C and C x The bit allocation of, and other such parameters of a given implementation and the resulting circuit depend on various factors, as will be understood by one of ordinary skill in the art. Such factors include design specifications, performance specifications, cost, IC or device area, available technology (such as semiconductor manufacturing technology), target market, target end user, etc. Therefore, Fig.18 The examples shown in are illustrative only, and other DCO implementations may be used as desired.

[0115] In some applications, a differential-mode DCO may be used instead of a single-ended DCO as desired. Fig.19 FIG. 1 shows a circuit arrangement of a differential mode DCO 1025 according to an exemplary embodiment (DAC 1030 is not shown). In this topology, the inductor L is connected by using two inductors L coupled in series. a and L b In addition, capacitor C x This is achieved by using three capacitors coupled in a π-configuration (or pi configuration to represent the capital Greek letter pi), which includes capacitors C xa , C xb and C xc In the embodiment shown, capacitor C xb has a fixed value, and the capacitor C xa and C xcThe capacitance of is changed by DAC 1030 (not shown) as described above. It should be noted that the resistor represents the inductance L a and L b The parasitic series resistance and / or capacitor C x The effective series resistance of the capacitor of FIG. 102 is used to model the passive losses in the DCO 1025. In some cases, as will be appreciated by one of ordinary skill in the art, the resistor has a relatively small value and may be omitted from the circuit and / or design calculations.

[0116] For the BLE example discussed above, the values ​​for the components are Fig.19 Note the dotted lines for the two inductors, which conceptually represent the direction in which the turns of the conductor in the inductor are "wound" (or in some way implemented in an IC, etc.). Fig.19 In the topology, the dot indicates the inductor L a The inductor L along the turns of the conductor b The turns of the conductor in the circuit are "wound" in opposite directions (e.g., clockwise versus counterclockwise). Using this configuration, the inductor L a The effective inductance L a-effective can be expressed as:

[0117] L a-effective =(L a –M)=L a (1-k),

[0118] Where M represents the inductor L a and L b The mutual inductance between the two, and k represents the inductor L a and L b Similarly, for the inductor L b , inductor L b The effective inductance L b-valid can be expressed as

[0119] L b -effective=(L b –M)=L b (1-k).

[0120] The inductance L can be changed a and L b The points are provided to implement an alternative exemplary embodiment of a differential mode DCO. Fig. 20 A circuit arrangement for this topology is shown (DAC 1030 is not shown). Fig.19 The embodiment shown in FIG. 1 is similar to that shown in FIG. 1 , except that the inductor L a and L b The point specifies the inductance L a The turns of the conductor and the inductance Lb The turns of the conductor in the circuit are "wound" in the same direction. Using this configuration, the inductor L a and L b The effective inductance can be expressed as:

[0121] L a-effective =(L a +M)=L a (1+k),

[0122] as well as

[0123] L b-effective =(L b +M)=L b (1+k).

[0124] From the above description, it can be noted that Fig.19 The value of the inductor L in the DCO topology shown is Fig. 20 The value of the inductor L in the DCO topology shown is lower. On the other hand, Fig. 20 The DCO topology shown is less susceptible to interference from interfering signals that would appear in the VCO as common-mode signals in the circuit. Fig.19 The topology and Fig. 20 The above factors may be considered when selecting a topology in the embodiment. However, in addition or alternatively, as will be appreciated by one of ordinary skill in the art, the selection of topology may be based on other parameters or factors. For a given implementation or situation, such factors include design specifications, performance specifications, cost, IC or device area, available technology (such as semiconductor manufacturing technology), target market, target end users, etc.

[0125] As described above, but not limited to, a DFS (including a TDC and / or a DCO) according to an exemplary embodiment may be used in a variety of applications. Examples include RF receivers, RF transmitters, and RF transceivers. Fig.21 A circuit arrangement of an RF receiver 100 including a DFS 10 according to an exemplary embodiment is shown. The receiver 100 receives an RF signal via an antenna 105. The RF signal feeds the input of a low noise amplifier (LNA) 120. The LNA 120 provides low noise amplification of the RF signal and provides the amplified RF signal to a mixer 130.

[0126] The mixer 130 performs a frequency translation or shifting of the RF signal using a reference or local oscillator (LO) frequency provided by the LO 125. For example, in some embodiments, the mixer 30 frequency translates the RF signal to a baseband frequency. As another example, in some embodiments, the mixer 30 frequency translates the RF signal to an intermediate frequency (IF).

[0127] The mixer 130 provides the transformed output signal as a set of two signals, namely an in-phase (I) signal and a quadrature (Q) signal. The I and Q signals are analog time domain signals. The analog-to-digital converter (ADC) 135 converts the I and Q signals into digital I and Q signals. In an exemplary embodiment, the ADC 135 can use various signal conversion techniques. For example, in some embodiments, the ADC 135 can use delta-sigma (or sometimes referred to as sigma-delta) analog-to-digital conversion.

[0128] ADC 135 provides the digital I and Q signals to signal processing circuitry 140. Generally speaking, signal processing circuitry 140 processes the digital I and Q signals, for example, digital signal processing (DSP). Signal processing circuitry 140 provides information, such as demodulated data, to data processing circuitry 155 via link 150. Data processing circuitry 155 may perform various functions (e.g., logic, arithmetic, etc.). For example, data processing circuitry 155 may use the demodulated data in a program, routine, or algorithm (whether in software, firmware, hardware, or a combination) to perform a desired control or data processing task.

[0129] In some embodiments, data processing circuit 155 may perform control of other circuits, subsystems, or systems (not shown). In some embodiments, data processing circuit 155 may provide data (after processing, as needed, such as filtering) to another circuit (not shown), such as a transducer, a display, etc.

[0130] In exemplary embodiments, link 150 may take a variety of forms. For example, in some embodiments, link 150 may constitute a number of conductors or coupling mechanisms, such as wires, cables, printed circuit board (PCB) traces, etc. Through link 150, signal processing circuit 140 and data processing circuit 155 may exchange information, such as demodulated data, control information or signals, status signals, etc., as needed.

[0131] Receiver 100 includes image rejection (IR) calibration circuit 165 that can be used to perform image rejection calibration, as described above. Receiver 100 also includes controller 160. Controller 160 uses output signal 160A to control the operation of IR calibration circuit 165. Controller 160 also uses output signal 160B to control the operation of DFS 10, for example, causing DFS 10 to provide output signal 10A as a test tone to the receiver. The test tone is typically injected into the receive path circuit at strategic locations. In Fig.21 In the exemplary embodiment shown, the test tone output by DFS 10 is applied at the input of low noise amplifier (LNA) 120. IR calibration circuit 165, residing after analog-to-digital converter (ADC) 135, utilizes LMS techniques (or another technique) to calibrate the image rejection of the receive path circuitry.

[0132] As described above, DFS according to various embodiments may be used to clock ADC 135 . Fig. 22 In this case, the DFS 10 provides an output signal 10A to the ADC 135 in response to a control signal 160B from the controller 160. The ADC 135 uses the output signal 10A of the DFS 10 as a clock signal in order to perform analog-to-digital conversion.

[0133] As described above, DFS according to various embodiments may be used to perform hybrid operations. Fig.23 In this embodiment, LO 125 is omitted (see Figure 4 -5). In contrast, the output signal 10A of the DFS 10 is used as the LO signal. The DFS 10 provides the output signal 10A to the ADC 135 in response to a control signal 160B from the controller 160. The mixer 130 uses the output signal 10A to mix the RF signal with the output signal 10A to generate I and Q (in-phase and quadrature) signals provided to the ADC 135.

[0134] As described above, DFS according to various embodiments may be used in an RF transmitter. Fig.24 A circuit arrangement of an RF transmitter (TX) 200 including the DFS 10 according to an exemplary embodiment is shown. The data processing circuit 155 provides a digital signal to a digital-to-analog converter (DAC) 202. The DAC 202 converts the digital signal to an analog signal and provides the analog signal to a mixer 204.

[0135] In response to a control signal 160B from the controller 160, the DFS 10 generates an output signal 10A having a desired frequency (typically within the RF range). The mixer 204 mixes the output signal of the DAC 202 with the output signal 10A of the DFS 10. The resulting output signal 204A of the mixer 204 may be provided to a power amplifier (not shown) or may be further processed as part of the operation of the transmitter 200.

[0136] It should be noted that the RF receiver 100 and the RF transmitter 200 shown in the figures and described above constitute only examples. As will be appreciated by those skilled in the art, DFS according to various embodiments may be used in various RF receivers (e.g., direct conversion, low intermediate frequency (low-IF), etc.) and RF transmitters (direct conversion, offset PLL, etc.).

[0137] It should also be noted that DFS according to various embodiments may also be used in an RF transceiver. For example, an RF transceiver may be implemented by combining the functionality and / or circuitry of an RF receiver including one or more DFS with the functionality and / or circuitry of an RF transmitter including one or more DFS, as will be appreciated by one of ordinary skill in the art. As will be appreciated by one of ordinary skill in the art, in some embodiments, one or more DFS may be shared between an RF receiver and an RF transmitter.

[0138] Furthermore, RF receivers, RF transmitters and / or RF transceivers including DFS according to various embodiments may be used in various communication arrangements, systems, subsystems, networks, etc., as desired. Fig.25 A circuit arrangement of an RF communication system 300 according to an exemplary embodiment is shown.

[0139] System 300 includes transmitter 200 coupled to antenna 105A. Transmitter 200 transmits an RF signal via antenna 105A. As described above, the RF signal may be received by receiver 100. Additionally or alternatively, transceiver 310A and / or transceiver 310B may receive the transmitted RF signal (via receiver 100).

[0140] In addition to receiving capabilities, transceivers 310A and 310B may also transmit RF signals. Receiver 100 may receive the transmitted RF signals in a standalone receiver, or via receiver circuitry of a non-transmitting transceiver.

[0141] Other systems or subsystems having different configurations and / or functions are also contemplated. For example, in some exemplary embodiments, two or more transceivers (e.g., transceiver 310A and transceiver 310B) may form a network, such as an ad hoc network, a mesh network, etc. As another example, in some exemplary embodiments, transceiver 310A and transceiver 310B may form part of a network, such as along with transmitter 200.

[0142] RF receivers and RF transmitters (such as the RF receiver 100 and RF transmitter 200 described above) can be used in various circuits, modules, subsystems and / or systems. For example, in some embodiments, such RF receivers can be integrated in an IC such as an MCU. Fig.26 FIG. 1 shows a circuit arrangement of an IC including an RF receiver 100 according to an exemplary embodiment, the RF receiver 100 including one or more DFS (e.g., Figure 21-23 shown).

[0143] The circuit arrangement includes an IC 550 constituting or including an MCU. The IC 550 includes a plurality of blocks (e.g., processor(s) 565, data converter 605, I / O circuit 585, etc.) that communicate with each other using a link 560. In an exemplary embodiment, the link 560 may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements (e.g., traces, devices, etc.) for transmitting information (such as data, commands, status information, etc.).

[0144] IC 550 may include a link 560 coupled to one or more processors 565, a clock circuit 575, and a power management circuit or power management unit (PMU) 580. In some embodiments, the processor(s) 565 may include circuits or blocks for providing information processing (or data processing or computing) functions, such as a central processing unit (CPU), an arithmetic logic unit (ALU), etc. In some embodiments, in addition or alternatively, the processor(s) 565 may include one or more DSPs. The DSP may provide various signal processing functions, such as arithmetic functions, filtering, delay blocks, etc., as needed. In some embodiments, some circuits in the processor(s) 565 may be used as needed to implement or realize the functions of various parts of the receiver 100 (such as those described above).

[0145] Reference again Fig.26 , clock circuit 575 can generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC 550. Clock circuit 575 can also control the timing of operations using link 560 as needed. In some embodiments, clock circuit 575 can provide one or more clock signals to other blocks in IC 550 via link 560.

[0146] In certain embodiments, the PMU 580 may reduce the clock speed of a device (e.g., IC 550), shut down a clock, reduce power, shut down power, disable (or shut down power or place it in a lower power consumption or sleep or inactive or idle state), enable (or power up or place it in a higher power consumption or normal or active state), or any combination of the foregoing with respect to a portion of a circuit or all components of a circuit, such as one or more modules in IC 550. Additionally, in response to a transition from an inactive state to an active state (including, but not limited to, when the processor(s) 565 transition from a low power or idle or sleep state to a normal operating state), the PMU 580 may turn on a clock, increase the clock rate, turn on power, increase power, or any combination of the foregoing.

[0147] Link 560 may be coupled to one or more circuits 600 via serial interface 595. Through serial interface 595, one or more circuits or blocks coupled to link 560 may communicate with circuit 600. As will be appreciated by one of ordinary skill in the art, circuit 600 may communicate using one or more serial protocols (such as SMBUS, I2C, or I2C). 2 C, SPI, etc.) for communication.

[0148] Link 560 may be coupled to one or more peripheral devices 590 via I / O circuitry 585. Through I / O circuitry 585, one or more peripheral devices 590 may be coupled to link 560 and may therefore communicate with one or more blocks (e.g., processor(s) 565, memory circuitry 625, etc.) coupled to link 560.

[0149] In an exemplary embodiment, peripherals 590 may include various circuits, blocks, etc. Examples include I / O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.). It should be noted that in some embodiments, some peripherals 590 may be external to IC 550. Examples include keypads, speakers, etc.

[0150] In some embodiments, I / O circuit 585 may be bypassed with respect to some peripherals. In such embodiments, some peripherals 590 may be coupled to and communicate with link 560 without using I / O circuit 585. In some embodiments, such peripherals may be external to IC 550, as described above.

[0151] Link 560 may be coupled to analog circuit 620 via data converter(s) 605. Data converter(s) 605 may include one or more ADCs 605A and / or one or more DACs 605B.

[0152] ADC 605A receives analog signal(s) from analog circuit 620 and converts the analog signal(s) into a digital format, which they transmit to one or more blocks coupled to link 560. Conversely, DAC(s) 605B receives digital signal(s) from one or more modules coupled to link 560 and converts the digital signal(s) into an analog format, which they transmit to analog circuit 620.

[0153] Analog circuit 620 may include various circuits that provide and / or receive analog signals. As will be appreciated by one of ordinary skill in the art, examples include sensors, transducers, etc. In some embodiments, analog circuit 620 may communicate with circuits external to IC 550 as needed to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks.

[0154] The control circuit 570 is coupled to the link 560. Thus, the control circuit 570 can communicate with and / or control the operation of the various blocks coupled to the link 560 by providing control information or signals. In some embodiments, the control circuit 570 also receives status information or signals from the various blocks coupled to the link 560. Furthermore, in some embodiments, the control circuit 570 facilitates (or controls or supervises) communication or cooperation between the various blocks coupled to the link 560.

[0155] In some embodiments, the control circuit 570 may initiate or respond to a reset operation or signal. As will be appreciated by one of ordinary skill in the art, the reset operation may cause a reset of one or more blocks of the link 560 coupled to the IC 550, etc. For example, the control circuit 570 may cause the PMU 580 and circuits such as the RF receiver 10 to reset to an initial state or a known state.

[0156] In an exemplary embodiment, the control circuit 570 may include various types and circuit blocks. In some embodiments, the control circuit 570 may include logic circuits, finite state machines (FSMs), or other circuits to perform operations such as those described above.

[0157] The communication circuit 640 is coupled to the link 560 and also to circuits or modules (not shown) external to the IC 550. Through the communication circuit 640, the various blocks (or generally the IC 550) coupled to the link 560 can communicate with external circuits or blocks (not shown) via one or more communication protocols. Examples of communication include USB, Ethernet, etc. In an exemplary embodiment, other communication protocols may be used, as will be understood by those of ordinary skill in the art, depending on factors such as the design or performance specifications of a given application.

[0158] As previously described, memory circuit 625 is coupled to link 560. Thus, memory circuit 625 may communicate with one or more blocks coupled to link 560, such as processor(s) 365, control circuit 570, I / O circuit 585, etc.

[0159] Memory circuit 625 provides storage for various information or data (such as operands, flags, data, instructions, etc.) in IC 550, as will be understood by one of ordinary skill in the art. Memory circuit 625 may support various protocols as desired, such as double data rate (DDR), DDR2, DDR3, DDR4, etc.

[0160] In some embodiments, storage read and / or write operations performed by memory circuit 625 involve the use of one or more blocks in IC 550, such as (one or more) processor 565. In some cases, a direct memory access (DMA) arrangement (not shown) allows for improved performance of memory operations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of data and memory circuit 625, rather than through a block such as (one or more) processor 565.

[0161] The memory circuit 625 may include various memory circuits or blocks. In the illustrated embodiment, the memory circuit 625 includes a non-volatile (NV) memory 635. Additionally or alternatively, the memory circuit 625 may include a volatile memory (not shown), such as a random access memory (RAM). The NV memory 635 may be used to store information related to the performance, control, or configuration of one or more blocks in the IC 550. For example, the NV memory 635 may store configuration information related to the RF receiver 100 and / or to the initial or ongoing configuration or control of the RF receiver 100 (including (one or more) DFS included in the RF receiver 100) as desired.

[0162] As mentioned, DFS according to various embodiments may also be used in RF transmitters.Such RF transmitters may be included in various electronic circuits, such as ICs. Fig. 27 A circuit arrangement of an IC 500 including an RF transmitter 200 including one or more DFSs is shown according to an exemplary embodiment. As described above, the RF transmitter 200 may be coupled to and operate with various blocks and circuits in the IC 550.

[0163] The various circuits and blocks used in the above and exemplary embodiments may be implemented in various ways and using various circuit elements or modules. For example, DFS 10, TDC 1005, MMD 1045, subtractor 1015, scaling circuit 1055, digital loop filter 1020, DCO 1025, DAC 1030, frequency divider 1035, SDM 1060, delay circuit 1050, LMS adaptive circuit 1040, residual error circuit 1010, jitter monitor circuit 1017, C-TDC 1100, F-TDC 1105, delay circuit 1110, control circuit 1115, trigger 1210, control circuit 1205, synchronous counter 1220, oscillator 1215, trigger 1275, encoder logic circuit 1270, MUX 1255, inverter 1250, wrap counter 1265, MUX control circuit 1260, one's complement circuit 1305, adder 1310, register 1325, scaling circuit 1315, adder 1320, register 1330, adder 1060A, adder 1060B, DDC 1060K, integrator 1060C, adder 1060D, integrator 1060F, adder 1060G, PRBS jitter circuit 1060E, quantizer 1060H, delay circuit 1060I, adder 1060J, scaling circuit 1060N, scaling circuit 1060P, scaling circuit 1060Q, inverter 1605, inverter 1610, and Figure 21-27 The various blocks shown containing digital or mixed-signal circuits may generally be implemented using gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., a field programmable gate array (FPGA) or other type of programmable logic), arithmetic logic units (ALUs), standard cells, custom cells, custom analog cells, etc., as desired and as would be understood by one of ordinary skill in the art.

[0164] In addition, analog circuits or mixed signal circuits or both may be included as needed, for example, power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), etc. The analog circuits in the above blocks and circuits may be implemented as desired using bias circuits, decoupling circuits, coupling circuits, power supply circuits, current mirrors, current and / or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, etc., and as will be understood by those of ordinary skill in the art. In addition to the analog circuits and digital circuits described above, and as will be understood by those of ordinary skill in the art, mixed signal circuits may also include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. As will be understood by those of ordinary skill in the art, the selection of circuits for a given implementation depends on a variety of factors. Such factors include design specifications, performance specifications, cost, IC or device area, available technology (such as semiconductor manufacturing technology), target market, target end users, etc.

[0165] With reference to the accompanying drawings, those of ordinary skill in the art will note that the various boxes shown may primarily depict conceptual functions and signal flows. Actual circuit implementations may or may not include individually identifiable hardware for each functional block, and may or may not use the specific circuits shown. For example, the functions of various blocks may be combined into one circuit block as desired. In addition, the functions of a single block in several circuit blocks may be implemented as desired. The choice of circuit implementation depends on various factors, such as the specific design and performance specifications of a given implementation. In addition to the embodiments in the present disclosure, other modifications and alternative embodiments will be apparent to those of ordinary skill in the art. Therefore, the present disclosure teaches those skilled in the art how to implement the disclosed concepts according to the exemplary embodiments, and is to be interpreted as exemplary only. As will be understood by those of ordinary skill in the art, the drawings may be drawn to scale or, where applicable, may not be drawn to scale.

[0166] The specific forms and embodiments shown and described constitute exemplary embodiments only. Without departing from the scope of the present disclosure, those skilled in the art may make various changes to the shape, size and arrangement of the components. For example, those skilled in the art may replace the elements shown and described with equivalent elements. Moreover, without departing from the scope of the present disclosure, those skilled in the art may use certain features of the disclosed concepts independently of the use of other features.

Claims

1. A digitally controlled oscillator (DCO), the DCO comprising: a first capacitor having a first terminal and a second terminal; a first inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the first capacitor; a second inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first capacitor; as well as a capacitor bank coupled in a II-configuration, wherein a first terminal of the II-configuration is coupled to the second terminal of the first inductor, and the second terminal of the II-configuration is coupled to the second terminal of the second inductor; a first inverter coupled in parallel with the first capacitor; a second inverter coupled back-to-back to the first inverter; and The first inductor and the second inductor are wound in opposite directions.

2. The DCO of claim 1, wherein the DCO further comprises a digital-to-analog converter (DAC) to vary the capacitance of the first capacitor in response to a first set of control bits supplied to the DAC from a loop filter.

3. The DCO of claim 2, wherein the DAC varies the capacitance of the capacitor bank further in response to a second set of control bits supplied to the DAC from the loop filter.

4. The DCO of claim 1, wherein the capacitor bank comprises a bank of three capacitors.

5. A digitally controlled oscillator (DCO), the DCO comprising: a first capacitor having a first terminal and a second terminal; a first inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the first capacitor; a second inductor having a first terminal and a second terminal, wherein the second terminal is coupled to the second terminal of the first capacitor; as well as a capacitor bank coupled in a II-configuration, wherein a first terminal of the II-configuration is coupled to the second terminal of the first inductor, and the second terminal of the II-configuration is coupled to the first terminal of the second inductor; a first inverter coupled in parallel with the first capacitor; a second inverter coupled back-to-back to the first inverter; and The first inductor and the second inductor are wound in the same direction.

6. The DCO of claim 5, wherein the DCO further comprises a digital-to-analog converter (DAC) to vary the capacitance of the first capacitor in response to a first set of control bits supplied to the DAC from a loop filter.

7. The DCO of claim 6, wherein the DAC varies the capacitance of the capacitor bank further in response to a second set of control bits supplied to the DAC from the loop filter.

8. The DCO of claim 5, wherein the capacitor bank comprises a bank of three capacitors.

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