Semiconductor devices and systems

Abstract

Semiconductor devices and systems are described herein. The present invention provides a semiconductor device having an integral A / D converter capable of acceleration. The semiconductor device includes: a Johnson counter 18 for transmitting a low-bit counter signal JC<3:0>; a low-bit latch circuit 11 for outputting a low-bit latch result signal through the low-bit counter signal JC<3:0> and a low-bit latch signal 14; a determination circuit 12 for outputting a high-bit latch signal 15 through the low-bit latch signal 14; and a high-bit counter signal GR for transmitting a high-bit counter signal GR. <n:3>A binary Gray converter circuit 20; and a high-bit counter signal GR <n:3>And the high-order latch signal 15 to output the high-order latch result signal of the high-order latch circuit 13.< / n:3>

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-233834 filed on December 13, 2018 including specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices and systems, for example, systems including semiconductor devices having integrated analog-to-digital (A / D) converter circuits and image sensors. Background Art

[0004] An image sensor includes a pixel portion in which a plurality of photosensitive elements are arranged in a matrix and an A / D conversion circuit for converting analog signals from the photosensitive elements into digital signals. In recent years, image sensors have increasingly required higher frame rates, higher image quality, and more pixels. In order to meet this demand, the A / D conversion circuit is also required to have a high speed.

[0005] For example, Patent Documents 1 and 2 disclose a technology of using an integral type A / D conversion circuit as an A / D conversion circuit used in an image sensor, which integral type A / D conversion circuit uses a counter circuit for counting time until the value of an analog signal reaches a reference value.

[0006] Prior art documents

[0007] Patent Documents

[0008] [Patent Document 1]

[0009] JP-A-2008-92091

[0010] [Patent Document 2]

[0011] JP-A-2013-229708 Summary of the invention

[0012] As a result of the inventor's research, it has been found that in the integral A / D converter circuits described in Patent Documents 1 and 2, when the speed increases, degradation and failure of DNL (differential nonlinearity) may occur. The inventor's research will be described below. Here, the research based on the integral A / D conversion circuit described in Patent Document 2 will be described.

[0013] Fig.17 1 is a block diagram showing the configuration of an integral A / D conversion circuit of a comparative example configured by the present inventors based on the integral A / D conversion circuit described in Patent Document 2. The image sensor 170 includes a pixel portion (not shown), a control circuit 171, a plurality of integral A / D conversion circuits 177, and a reference voltage generating circuit 181.

[0014] In the pixel portion, a plurality of photosensitive elements are arranged in a matrix, and an integral A / D conversion circuit 177 is arranged so as to correspond to each column of the pixel portion. An analog signal from the photosensitive element provided in the pixel portion is supplied as an input signal to the corresponding integral A / D conversion circuit 177, is converted into a digital signal by the integral A / D conversion circuit 177, and the digital signal is output as a result output. Since the integral A / D conversion circuit 177 corresponds to each column of the pixel portion, it may also be referred to as a column integral A / D conversion circuit.

[0015] The integrating A / D conversion circuit 177 includes a comparison circuit 178 and a latch circuit 179. The comparison circuit 178 compares the input signal with the reference voltage generated by the reference voltage generation circuit 181. The reference voltage is, for example, a ramp wave, and the voltage value changes linearly with time. When the voltage of the input signal exceeds the reference voltage, for example, the latch signal 184 as the output of the comparison circuit 178 is inverted. By inverting the latch signal 184, the latch circuit 179 outputs the counter signal lines 182<2:0>, 183<1>. <n:2>The lower counter signal JC<2:0> and the upper counter signal GR <n:2>Latch.

[0016] Here, the notation method used in this specification will be described. The numbers sandwiched between the above symbols <> and separated by the symbol : indicate the bit number, and the symbol : indicates all separated bit numbers. For example, the low bit counter signal JC<2:0> indicates the low bit counter signal JC<2:0>. <0> To JC <2> Similarly, the high-order counter signal GR <n:2>Indicated by the high counter signal GR <2> To GR <n>Additionally, the counter signal line 182<2:0> indicates that the low-order counter signal JC is sent. <0> To JC <2> Counter signal line 182 <0> To 182 <2> Similarly, the counter signal line 183 <n:2>Indicated by sending high counter signal GR <2> To GR <n>Counter signal line 183 <2> Up to 183 <n>Configuration.

[0017] When the latch signal 184 is inverted, the latch circuit 179 now turns the low-order counter signal JC <0> To JC <2> and high counter signal GR <2> To GR <n>Latch.

[0018] The control circuit 171 includes a Johnson counter 172 , a binary counter 173 , a binary Gray conversion circuit 174 for converting a binary code into a Gray code, a delay adjustment circuit 175 , and a synchronization circuit 176 .

[0019] A predetermined clock signal CLK is supplied to the Johnson counter 172. The Johnson counter 172 generates a lower-bit counter signal based on the supplied clock signal CLK, and the lower-bit counter signals vary with a phase difference from each other. A portion of the lower-bit counter signal generated by the Johnson counter 172 is supplied to the binary counter 173. The binary counter 173 counts the supplied lower-bit counter signal and generates a counter signal BC of a binary code. <n:2>The binary Gray conversion circuit 174 converts the counter signal BC <n:2>The binary Gray conversion circuit 174 converts the high-order counter signal into a Gray code and outputs the counter signal BC. That is, the binary Gray conversion circuit 174 converts the high-order counter signal BC into a Gray code based on the binary code. <n:2>To generate a high-order counter signal of a Gray code that changes only one logic value at a time.

[0020] The delay of the lower counter signal generated by the Johnson counter 172 is adjusted by the delay adjustment circuit 175 so as to delay the lower counter signal generated by the Johnson counter 172 by the delay caused by the binary counter 173 and the binary Gray conversion circuit 174. The lower counter signal whose delay is adjusted and the upper counter signal generated by the binary Gray conversion circuit 174 are supplied to the synchronization circuit 176. The synchronization circuit 176 adjusts the lower counter signal to be synchronized with the upper counter signal, and the lower counter signal is supplied from the synchronization circuit 176 to the counter signal line 182<2:0> as the lower counter signal JC<2:0>. The upper counter signal is supplied from the synchronization circuit 176 to the counter signal line 183 <n:2>As the high counter signal GR <n:2>.

[0021] For example, when the reference voltage starts to change, the Johnson counter 172 starts to count the clock signal CLK. Therefore, the latch circuit 179 in each integrated A / D conversion circuit 177 turns the high-bit counter signal GR <n:2>and the lower bit counter signal JC<2:0> are latched, and a digital signal corresponding to the input signal which is an analog signal is output as a result.

[0022] Fig.18 The low-order counter signal JC is shown <0> To JC <2> and high counter signal GR <2> To GR <n>An example timing diagram of the timing. Fig.18 The timing is shown for the case of an ideal bit counter signal. Fig.19 An example of a conversion table is shown, which shows the low-order counter signal JC <0> To JC <2> and high counter signal GR <2> To GR <5> The counter signal, the bit code represented by the counter signal, and the counter value represented by the bit code. Fig.18 In the example, when the bit counter signal is high, the logic value of the bit counter signal corresponds to Fig.19 When the bit counter signal is low, the logic value of the bit counter signal corresponds to Fig.19 "0" shown.

[0023] For example, if the low counter signal JC <0> To JC <2> At high level (logic value "1") and the high-bit counter signal GR <2> To GR <5> When the latch signal 184 is at a low level (logical value "0"), the latch signal 184 is inverted, and the latch circuit 179 that latches the low-order counter signal JC<2:0> latches the logical value "1". At this time, the logical value "0" is latched in the latch circuit 179 that latches the high-order counter signal GR<5:2>. As a result, the input signal is converted into Fig.19 The counter value "3" is shown and is output as the result output.

[0024] The number of columns of the pixel portion is, for example, several thousand to tens of thousands. Therefore, the repeater 180 is coupled to the counter signal lines 182<2:0>, 183 <n:2>The bit counter signal propagated through the counter signal lines 182 and 183 propagates through the counter signal lines while waveform shaping is performed by the repeater 180. The number of the counter signal lines 182 and 183 corresponds to the number of bits of the digital signal after A / D conversion, and is, for example, several tens.

[0025] Fig. 20 is a diagram showing an A / D conversion operation when an ideal A / D conversion is performed in a comparative example. Fig. 20 In the figure, on the left side of the arrow, the low-order counter signal JC is shown. <0> To JC <2> and high counter signal GR <2> To GR <3> The ideal time. Fig. 20 , on the right side of the arrow, the relationship between the analog input to the A / D conversion circuit 177 and the digital output from the A / D conversion circuit 177 is shown.

[0026] exist Fig. 20 , 1LSB indicates a period corresponding to the minimum input voltage (minimum input voltage change amount) that can be digitally converted by the A / D converter 177. Fig. 20 As shown, ideally, the lower counter signal JC and the upper counter signal GR change in units of 1 LSB in time, and no skew occurs. Fig. 20 As shown, the A / D conversion circuit 177 outputs a digital output that changes linearly in proportion to the change in the analog input. That is, the A / D conversion circuit 177 converts the analog input into a digital output at equal intervals, and the degradation of the DNL does not occur.

[0027] Fig.21 is a diagram showing an A / D conversion operation when DNL degradation occurs in a comparative example. Fig.21 In Fig. 20 In the same manner, the timings of the lower bit counter signal JC and the upper bit counter signal GR are shown on the left side of the arrows. Fig.21 shows the high-bit counter signal GR <2> is delayed and skewed. In this case, Fig.21 As shown on the right side of the arrow, the period corresponding to the counter value "3" becomes longer than the time 1LSB, and conversely, the period corresponding to the counter value "4" becomes shorter than the time 1LSB. That is, the A / D conversion circuit 177 converts the analog input into a digital signal at unequal intervals, and the DNL deteriorates.

[0028] Fig. 22 shows that when the delay due to skew is greater than Fig.21 The delay shown in FIG. 1 is longer than that in the comparative embodiment, and the A / D conversion operation of 1LSB is performed. Fig. 22 As shown on the left side of the arrow, Fig. 20 Compared with the ideal situation shown in the figure, the high-order counter signal GR <2> The change over time is longer than 1LSB. In this case, if Fig. 22 As shown on the right side of the arrow in , the period during which the digital output indicates the counter value "3" is longer than the time 1LSB, and the period during which the digital output should indicate the counter value "4" is extended. In other words, during the period during which the digital output should indicate the counter value "4", an impossible code (uncertain code) is output from the A / D conversion circuit 177, and an error occurs in the A / D conversion operation, resulting in a large error or failure.

[0029] That is, if there is a delay difference between the low-order counter signal JC and the high-order counter signal GR, the A / D conversion circuit 177 outputs an uncertain code or causes degradation of DNL. In this case, distortion, horizontal stripes, or image disturbances (spots) such as white dots or black dots appear in the image data acquired by the image sensor. That is, the skew of the counter signal used in the A / D conversion circuit greatly affects the A / D conversion characteristics and image quality.

[0030] like Fig.17 As shown, the low-order counter signal JC and the high-order counter signal GR generated by the control circuit 171 are distributed to many A / D conversion circuits 177 arranged in each column through counter signal lines 182 and 183. That is, the counter signal lines 182 and 183 are arranged so as to extend to send the counter signal to each of the plurality of A / D conversion circuits 177 arranged on thousands to tens of thousands of columns. The number of counter signals is determined by the resolution of the A / D conversion circuit 177. In this case, in order to prevent the image quality from being deteriorated, it is necessary to adjust the skew between the low-order counter signal JC and the high-order counter signal GR in the A / D conversion circuit 177 arranged in each column.

[0031] exist Fig.17 In the comparative example shown, the lower counter signal JC<2:0> and the upper counter signal GR are adjusted with high precision by the delay adjustment circuit 175 and the synchronization circuit 176. <n:2>The timing of the lower counter signal JC<2:0> and the upper counter signal GR need to be adjusted with high precision even in the A / D conversion circuits arranged in thousands of columns. <n:2>Therefore, in the comparative example, the area is increased by the delay adjustment circuit 175 and the synchronization circuit 176, and it is also necessary to adjust the delay of the counter signal in the A / D conversion circuit part arranged in the column with high accuracy.

[0032] In addition, since the frame rate and image quality of the image sensor are improved and the speed of the A / D conversion circuit is increased, the allowable skew request error is reduced, and the number of columns of the pixel part is increased due to the increase in the number of pixels, and the number of counter signal lines is increased due to the increase in the resolution of the A / D conversion circuit, which makes skew adjustment difficult and difficult to meet the skew request error.

[0033] Although the problem has been described using the comparative example based on Patent Document 2, even in the A / D conversion circuit described in Patent Document 1, if there is a skew between counter signals, DNL degradation or failure occurs and image quality deteriorates.

[0034] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0035] Ways to solve the problem

[0036] A semiconductor device according to one embodiment is as follows.

[0037] That is, a semiconductor device includes: a down-counter circuit for outputting a low-order counter signal; a low-order latch circuit for outputting a low-order latch result signal through a low-order counter signal and a low-order latch signal; a low-order decision circuit for outputting a high-order latch signal through a low-order latch signal; an up-counter circuit for outputting a high-order counter signal; and a high-order latch circuit for outputting a high-order latch result through a high-order counter signal and a high-order latch signal.

[0038] A semiconductor device according to another embodiment is as follows.

[0039] That is, a semiconductor device includes: a comparison voltage generating circuit for generating a reference voltage that changes linearly with the passage of time; a counter circuit that outputs a high-bit counter signal and a low-bit counter signal, each of the counter signals having a value that changes with the passage of time and includes a plurality of bit counter signals; a comparator circuit that compares an input signal with a reference voltage and outputs a low-bit latch signal when the input signal reaches a predetermined relationship with the reference voltage; a low-bit latch circuit that latches the low-bit counter signal in response to the low-bit latch signal; a decision circuit that outputs a high-bit latch signal in a period excluding an uncertain period in which the high-bit counter signal becomes uncertain based on the low-bit latch signal and a predetermined bit counter signal in the low-bit counter signal; a high-bit latch circuit that latches the high-bit counter signal in response to the high-bit latch signal; and an integral type A / D conversion circuit that outputs the high-bit counter signal latched by the high-bit latch circuit and the low-bit counter signal latched by the low-bit latch circuit as digital signals corresponding to the input signal.

[0040] [Effects of the Invention]

[0041] According to the embodiment, a semiconductor device including an integrating A / D converter capable of speeding up can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a block diagram showing the configuration of an image sensor related to the first embodiment.

[0043] Figure 2 is a block diagram showing the configuration of a column A / D converter circuit related to the first embodiment.

[0044] Figure 3 is a block diagram showing the configuration of an A / D converter circuit according to the first embodiment.

[0045] Figure 4 is a block diagram showing the configuration of a determination circuit related to the first embodiment.

[0046] Figure 5 (A) and (B) are timing charts for explaining the operation of the determination circuit related to the first embodiment.

[0047] Figure 6 is a timing chart showing the operation of the A / D conversion circuit related to the first embodiment.

[0048] Figure 7 : is a conversion table showing the correspondence relationship between the counter signal output from the counter circuit, the bit code, and the counter value related to the first embodiment.

[0049] Figure 8 is a timing chart for explaining the operation of the A / D conversion circuit related to the first embodiment.

[0050] Fig. 9 is a timing chart for explaining the operation of the A / D conversion circuit related to the first embodiment.

[0051] Fig.10 is a block diagram showing the configuration of a determination circuit related to the second embodiment.

[0052] Fig.11 is a timing chart showing the operation of the A / D conversion circuit related to the second embodiment.

[0053] Fig.12 is a block diagram showing the configuration of a determination circuit related to the third embodiment.

[0054] Fig.13 is a timing chart showing the operation of the A / D conversion circuit related to the third embodiment.

[0055] Fig.14 is a block diagram showing the configuration of an image sensor related to the fourth embodiment.

[0056] Fig.15 is a block diagram showing the configuration of a column A / D converter circuit related to the fifth embodiment.

[0057] Fig.16 is a timing chart showing the operation of the A / D conversion circuit related to the fifth embodiment.

[0058] Fig.17 is a block diagram showing the configuration of an integrating A / D conversion circuit of a comparative example considered by the inventors.

[0059] Fig.18 is a timing diagram showing the timing of the lower counter signal and the upper counter signal.

[0060] Fig.19 : is a diagram of a conversion table showing the correspondence relationship between the lower-bit counter signal, the upper-bit counter signal, the bit code, and the counter value represented by the bit code.

[0061] Fig. 20 is a diagram of the A / D conversion operation when ideal A / D conversion is performed in the comparative example.

[0062] Fig.21 is a diagram of the A / D conversion operation when DNL degradation occurs in the comparative example.

[0063] Fig. 22 is a diagram of the A / D conversion operation when the delay caused by the skew increases in the comparative example.

[0064] Fig.23 : is a diagram of a conversion table showing the correspondence between the bit code represented by the Gray code counter signal and the counter value represented by the bit code. DETAILED DESCRIPTION

[0065] Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the present disclosure is only an example, and those skilled in the art can easily think of appropriate changes, while maintaining the gist of the present invention is naturally included in the scope of the present invention. Additionally, although for the sake of clarity of description, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, the drawings are only examples and do not limit the interpretation of the present invention.

[0066] In the present specification and each drawing, the same reference numerals are assigned to the same elements as those described above with reference to the previous drawings, and a detailed description thereof may be appropriately omitted.

[0067] Figure 1 1 is a diagram showing the configuration of an image sensor related to the first embodiment. The image sensor 100 includes a control circuit 1, a row operation circuit 2, a pixel portion 3, a column A / D conversion circuit 7, a column operation circuit 8, and a decoder circuit 9. In the first embodiment, the pixel portion 3 and the above-mentioned circuits constituting the image sensor 100 are formed on one semiconductor chip by a well-known semiconductor manufacturing technology. That is, one semiconductor device includes the above-mentioned pixel portion 3 and the above-mentioned circuits.

[0068] The pixel portion 3 includes a plurality of photosensitive elements 10 arranged in a matrix, row control lines RL_0 to RL_n arranged in each row of the pixel portion 3, and column signal lines CL_0 to CL_m arranged in each column of the pixel portion 3. The photosensitive element 10 includes, for example, a photodiode PD, and is connected to the row control line arranged in the corresponding row and the column signal line arranged in the corresponding column.

[0069] The row operation circuit 2 is connected to the row control lines RL_0 to RL_n arranged in each row of the pixel section 3, and controls the operation timing of each row of the pixel section 3. For example, when acquiring an image, the row operation circuit 2 sequentially selects a row control line from the plurality of row control lines RL_0 to RL_n, and supplies a row control signal to the selected row control line. As a result, a plurality of photosensitive elements 10 connected to the row control line to which the row control signal is supplied are selected from the plurality of photosensitive elements 10 arranged in the pixel section 3. In the selected photosensitive element 10, electrons are excited by light in the photodiode PD, and an analog signal corresponding to the light is output to the column signal lines CL_0 to CL_m. The column signal lines CL_0 to CL_m are connected to the column A / D conversion circuit 7, and the analog signal corresponding to the light supplied to the column signal lines CL_0 to CL_m is converted into a corresponding digital signal by the column A / D conversion circuit 7.

[0070] The column operation circuit 8 is connected to the column A / D conversion circuit 7 and controls the operation timing of each column. For example, the column operation circuit 8 controls the column A / D conversion circuit 7 so that the digital signals converted by the column A / D conversion circuit 7 are sequentially supplied to the decoder circuit 9. The decoder circuit 9 decodes the digital signal supplied from the column A / D conversion circuit 7 and outputs the decoded signal as a count value.

[0071] The control circuit 1 performs overall control. For example, the control circuit 1 controls the timing of operating the row operation circuit 2 and the column operation circuit 8. The control circuit 1 controls the operation of the reference voltage generating circuit 4 in the column A / D conversion circuit 7 (which will be described later), and supplies the clock signal CLK to the counter circuit 5 in the column A / D conversion circuit 7.

[0072] The column A / D conversion circuit 7 includes a plurality of A / D conversion circuits 6 corresponding to each column of the pixel section 3, a reference voltage generating circuit 4, and a counter circuit 5. Each of the A / D conversion circuits 6 is connected to a column signal line arranged in a corresponding column of the pixel section 3. The reference voltage generating circuit 4 generates a ramp reference voltage whose voltage changes linearly with the lapse of time, and supplies a common reference voltage to the A / D conversion circuit 6 corresponding to each column via a common reference voltage line RVL. The counter circuit 5 generates a high-bit counter signal and a low-bit counter signal each composed of a plurality of bit counter signals based on a clock signal CLK from the control circuit 1, and outputs the high-bit counter signal and the low-bit counter signal to a counter signal line CTL arranged along a row of the pixel section 3. The A / D conversion circuit 6 corresponding to each column is connected to the counter signal line CTL, and the high-bit counter signal and the low-bit counter signal generated by the counter circuit 5 are distributed to the A / D conversion circuit 6 corresponding to each column.

[0073] Since the A / D conversion circuit 6 corresponding to each column is provided with a common reference voltage, a common upper counter signal and a common lower counter signal, the A / D conversion circuit 6 corresponding to each column can simultaneously convert analog signals provided via the column signal lines CL_0 to CL_m into digital signals.

[0074] exist Figure 1 In the figure, LTC represents a latch signal. When the ramp-shaped reference voltage reaches a predetermined voltage and returns to the initial voltage, it is notified from the control circuit 1 to the column operation circuit 8, and the column operation circuit 8 generates a latch signal LTC. As will be described later, the A / D conversion circuit 6 divides the digital signal corresponding to the analog signal into a low bit and a high bit, and outputs the divided digital signal. When the ramp-shaped reference voltage returns to the initial voltage, since the low-bit digital signal and the high-bit digital signal are provided to the decoder circuit 9, the decoder circuit 9 latches the low-bit digital signal and the high-bit digital signal at the moment when the latch signal LTC is provided, and decodes the latched digital signal. Although the latch signal LTC is output from the column operation circuit 8 in the figure, the latch signal LTC can also be output from the column A / D conversion circuit 7, the reference voltage generation circuit 4 or the control circuit 1.

[0075] exist Figure 1 In the figure, a line is drawn so as to indicate a plurality of lines when crossing a line. For example, since a crossing line " / " is drawn in the counter signal line CTL, the counter signal line CTL is a plurality of counter signal lines. On the other hand, since the reference voltage line RVL is not provided with a crossing line, the reference voltage line is one wiring.

[0076] Figure 2 is a block diagram showing the configuration of a column A / D conversion circuit related to the first embodiment.

[0077] The counter circuit 5 related to the first embodiment includes a Johnson counter 18, a binary counter 19, and a binary Gray conversion circuit 20 for converting a binary code into a Gray code.

[0078] The Johnson counter 18 generates a multi-phase clock signal having phases different from each other based on the clock signal CLK. In the first embodiment, a multi-phase clock signal of four phases is generated by the Johnson counter 18, and the generated multi-phase clock signal is provided as a lower-bit counter signal JC<3:0> to the counter signal line CTL-JC<3:0>. The lower-bit counter signal JC<3:0> of the multi-phase clock signal generated by the Johnson counter 18 is <3> The clock signal is provided to the binary counter 19. The binary counter 19 receives the provided low-order counter signal JC <3> Counting to generate a binary code counter signal BC <n:3>.

[0079] Binary code counter signal BC <n:3>The binary code conversion circuit 20 converts the signal into a Gray code counter signal, and the signal is fed from the binary Gray code conversion circuit 20 to the counter signal line CTL-GR. <n:3>, as the high-order counter signal GR <n:3>The counter signal line CTL-JC<3:0> and the counter signal line CTL-GR <n:3>Arranged so as to extend in parallel with the rows of the pixel portions 3 .

[0080] The A / D conversion circuit 6 related to the first embodiment converts the analog signal supplied from the pixel section 3 into an n-bit digital signal, and the A / D conversion circuit 6 outputs the n-bit digital signal as a lower bit counter signal JC<3:0> and an upper bit counter signal GR each formed of a plurality of bits. <n:3>In this case, the lower bit counter signal JC<3:0> represents the logic value on the lower bit side of the digital signal corresponding to the analog signal, and the lower bit counter signal JC <0> Indicates the logic value of the least significant bit on the low-order side. That is, the low-order counter signal JC <0> Indicates the change in the minimum change amount in the analog signal. In the lower counter signal JC<3:0>, according to the lower counter signal JC <0> , JC <1> , JC <2> and JC <3> Therefore, in the first embodiment, based on the lower bit counter signal JC representing the most significant bit, <3> To generate the high counter signal GR <n:3>The high-order counter signal GR <n:3>Indicates the logical value of the high-order side of the digital signal corresponding to the analog signal. Note that n is determined by the resolution of the A / D conversion circuit 6.

[0081] Each of the plurality of A / D conversion circuits 6 corresponding to each column of the pixel portion 3 is configured by an integral type A / D conversion circuit. Since the configurations of the A / D conversion circuits 6 are the same as each other, the A / D conversion circuit 6 corresponding to the column in which the column signal line CL_0 is arranged will be described as a representative.

[0082] The A / D conversion circuit 6 includes a comparison circuit 10, a low-bit latch circuit 11, a determination circuit 12, and a high-bit latch circuit 13. The comparison circuit 10 is connected to a reference voltage line RVL and a line signal line CL_0 of a corresponding column, and compares the reference voltage with the voltage of the analog signal from the column signal line CL_0. The comparison circuit 10 outputs a low-bit latch signal 14 at a moment when the relationship between the reference voltage and the analog signal is reversed as a result of the comparison. For example, when the analog signal exceeds the reference voltage, the comparator circuit 10 outputs a low-bit latch signal 14 at a moment when the analog signal exceeds the reference voltage. In other words, when the relationship between the reference voltage and the analog signal reaches a predetermined relationship, the comparison circuit 10 outputs a low-bit latch signal 14 at that moment.

[0083] The input terminal of the lower-bit latch circuit 11 is connected to the counter signal line CTL-JC<3:0> to which the lower-bit counter signal JC<3:0> is supplied, and the output (low-bit latch result signal) terminal of the lower-bit latch circuit 11 is connected to the output line 21. When the lower-bit latch signal 14 is supplied from the comparison circuit 10, the lower-bit latch circuit 11 latches the lower-bit counter signal JC<3:0> supplied to the input at this time, and outputs the latched lower-bit counter signal JC<3:0> to the output line 21.

[0084] A predetermined lower-bit counter signal among the lower-bit counter signal JC<3:0> and the lower-bit latch signal 14 is provided to a determination circuit (lower-bit determination circuit) 12. The determination circuit 12 outputs an upper-bit latch signal 15 to indicate whether the upper-bit counter signal is latched based on the lower-bit latch signal 14 and the predetermined lower-bit counter signal, which will be referred to later. Figure 4 and Figure 5 Describe in detail.

[0085] The input terminal of the high-order latch circuit 13 is connected to the counter signal line CTL-GR <n:3>, counter signal line CTL-GR <n:3>Supplied with the high counter signal GR <n:3>, and the output terminal is connected to the output line 21. When the high-bit latch signal 15 is supplied from the determination circuit 12, the high-bit latch circuit 13 supplies the high-bit counter signal GR supplied to the input at this time. <n:3>The latched high-bit counter signal (high-bit latch result signal) GR is output to the output line 21. <n:3>.

[0086] exist Figure 2 In FIG. 1 , reference numeral 17 denotes a repeater. Counter signal lines CTL-JC<3:0> and CTL-GR <n:3>The length of the low-order counter signal and the high-order counter signal is changed so that the low-order counter signal and the high-order counter signal are distributed to the A / D conversion circuit 6 corresponding to the column (ranging from several thousand to tens of thousands), and the low-order counter signal and the high-order counter signal are degraded due to the loss of the counter signal line, etc. Therefore, the repeater 17 for waveform shaping is connected to the counter signal line CTL-JC<3:0> and the counter signal line CTL-GR respectively at the position where the A / D conversion circuit 6 is arranged. <n:3>It is needless to say that the repeater 17 does not have to be provided in all the A / D conversion circuits 6, and the repeater 17 may be provided as necessary in order to reliably transmit the counter signal.

[0087] Figure 3 1 is a diagram showing the configuration of an A / D conversion circuit related to the first embodiment. Figure 3 As shown, the low-bit latch circuit 11 has input terminals D0 to D3, output terminals Q0 to Q3, and a clock terminal CK. The input terminals D0 to D3 are connected to the counter signal lines CTK-JC<3:0>, and the output terminals Q0 to Q3 are connected to the output signal line JC <0> To JC <3> At the moment when the voltage of the low-bit latch signal 14 supplied to the clock terminal CK is inverted to a low level, the low-bit latch circuit 11 latches the low-bit counter signal JC<3:0> supplied to the input terminals D0 to D3. The latched low-bit counter signal JC<3:0> is supplied to the output line JC <0> To JC <3> .

[0088] The high-order latch circuit 13 has input terminals D3 to Dn, output terminals Q3 to Qn, and a clock terminal CK. The input terminals D3 to Dn are connected to a counter signal line CTK-GR <n:3>, and the output terminals Q3 to Qn are connected to the output line GR <3> To GR <n>When the voltage of the high latch signal 15 supplied to the clock terminal CK is inverted from high level to low level, the high latch circuit 13 supplies the high counter signal GR supplied to the input terminals D3 to Dn. <n:3>Latch. The latched high-order counter signal GR <n:3>is supplied to the output line GR <3> To GR <n>.

[0089] like Figure 3 As shown, since the output line 21 includes the output line JC<3:0> corresponding to the low-order counter signal and the output line GR corresponding to the high-order counter signal <n:3>, the low-order counter signal latched by the low-order latch circuit 11 and the high-order counter signal latched by the high-order latch circuit 13 are provided in parallel to the decoder circuit 9. Even if there is a time difference between the moment when the low-order latch circuit 11 latches and the moment when the high-order latch circuit 13 latches, the high-order counter signal and the low-order counter signal are simultaneously latched in the decoder circuit 9 through the latch signal LTC, and the latched counter signals are decoded into a digital signal.

[0090] In the first embodiment, if Figure 3 As shown, the low counter signal JC <3> As a predetermined low bit counter signal, it is supplied to the determination circuit 12. Figure 1 and Figure 2 The set signal Set is omitted in the figure, and is provided from the control circuit 1 to the determination circuit 12.

[0091] Figure 4 is a diagram showing the configuration of a determination circuit related to the first embodiment. Figure 5 is a timing chart for explaining the operation of the determination circuit related to the first embodiment.

[0092] The determination circuit 12 includes a D-type flip-flop circuit (hereinafter referred to as D-FF) 12_1 having an inversion function and an AND circuit 12_2. A set signal Set is supplied from the control circuit 1 to a set terminal S of the D-FF 12_1, and a ground voltage (low level) is supplied to an input terminal D. In addition, an output of the AND circuit 12_2 is supplied to a clock terminal CK of the D-FF 12_1, and a high-bit latch signal 15 is output from an output terminal D.

[0093] The AND circuit 12_2 is not particularly limited, but has two inputs in the first embodiment. The first input of the AND circuit 12_2 is supplied with the inverted low-bit latch signal 14, and the second input is supplied with the low-bit counter signal JC <3> .

[0094] The D-FF 12_1 latches the low-level signal supplied to the terminal D according to the change of the output signal supplied to the clock terminal CK from the AND circuit 12_2 from the low level (logical value "0") to the high level (logical value "1"), and outputs the high-level latch signal 15 of the low level from the output terminal Q. In addition, when the set signal Set supplied to the set terminal S becomes a high level, the D-FF 12_1 outputs the high-level latch signal 15 output from the output terminal Q as a high level.

[0095] Figure 5 (A) shows when the low counter signal JC <3> At time t when the low-level latch signal 14 is at a high level, the timing changes from the high level to the low level. At time t, since the low-level latch signal 14 changes from a high level to a low level, the second input of the AND circuit changes from a low level to a high level. As a result, Figure 5 As shown in (A), the high-order latch signal 15 changes from a high level to a low level in synchronization with the low-order latch signal 14 at time t.

[0096] Figure 5 (B) shows the low-order counter signal JC <3> In the period of low level, the timing of the low latch signal 14 changing from high level to low level. In this case, when the low counter signal JC <3> When the signal changes from low level to high level (time t), the output of the AND circuit 12_2 changes from low level to high level. As a result, at time t, the high-bit latch signal 15 changes from high level to low level.

[0097] That is, in the low-order counter signal JC <3> During the period when the low-order latch signal 14 is at a low level, the determination circuit 12 maintains the high-order latch signal 15 at a high level even if the low-order latch signal 14 falls, and when the low-order counter signal JC <3> When the high level of the high-order latch signal 14 and the low level of the low-order latch signal 14 occur simultaneously, the high-order latch signal 15 is changed from a high level to a low level.

[0098] Results, such as Figure 5 As shown in (A), when the low counter signal JC <3> When the high-order latch circuit 13 is at a high level, the high-order counter signal GR <n:3>On the other hand, if Figure 5 As shown in (B), when the low counter signal JC <3> When the low-level latch signal 14 changes to a low level during the low-level period, the high-level latch circuit 13 waits for the low-level counter signal JC <3> The timing of the high-level counter signal GR <n:3>Latch.

[0099] Figure 6 1 is a timing chart showing the operation of the A / D conversion circuit related to the first embodiment. The figure shows the timing of the upper counter signal and the lower counter signal when no skew occurs in the counter signal. Figure 7 : is a conversion table showing the correspondence relationship between the counter signal output from the counter circuit related to the first embodiment, the bit code, and the counter value.

[0100] The analog signal supplied to the A / D conversion circuit 6 is converted into a digital count value corresponding to the value. Although not particularly limited, in the first embodiment, the analog signal is converted into a digital count value corresponding to the lower bit counter signal JC. <0> To JC <3> and high counter signal GR <3> To GR <n>The analog signal is converted into a counter value corresponding to the converted bit code.

[0101] exist Figure 7 In Figure 6 The lower counter signal JC shown in <0> To JC <3> Shown as JC <0> To JC <3> , and will Figure 6 The high-order counter signal GR shown in <3> To GR <5> The high-order counter signal GR <3> To GR <5> Shown as GR <3> To GR <5> .exist Figure 6 The high level of the bit counter signal is Figure 7 A high level is shown as a logic value "1", and a low level is shown as a logic value "0". Figure 7 As shown, the counter value corresponds one-to-one to the combination (bit code) of the logic values ​​of the low-order counter signal and the high-order counter signal.

[0102] Low counter signal JC <0> To JC <3> Constitute the low code, and the low counter signal JC <0> Corresponds to the least significant bit in the low-order code, and the position in the low-order code is JC <1> , JC <2> and JC <3> Similarly, the high-order counter signal GR <3> To GR <5> Constitutes the high-order code, the high-order counter signal GR <3> Corresponds to the least significant bit in the upper code, and the position in the upper code is GR <4> and GR <5> The order is higher.

[0103] Figure 2 The Johnson counter 18 shown in FIG. 1 counts the clock signal CLK and outputs Figure 6 The multi-phase low-order counter signal JC shown in <0> To JC <3> That is, the Johnson counter 18 outputs the low-order counter signal JC <0> To JC <3> , low counter signal JC <0> To JC <3> The voltage of changes at each time t1 corresponding to the minimum input voltage 1LSB of the A / D conversion circuit 6. In other words, the Johnson counter 18 outputs a low-bit code that changes by one bit at each time t1 corresponding to the minimum input voltage 1LSB. The cycle of each low-bit counter signal JC<3:0> is eight times the time t1. In other words, the cycle of the bit code on the lower side is eight times the time t1.

[0104] Figure 2 The binary counter 19 shown in FIG. 1 utilizes the low-order counter signal JC <3> The falling edge of is used as a trigger to operate. Binary counter 19 and binary Gray conversion circuit 20 ( Figure 2 ) Based on the low-order counter signal JC <3> Generates high counter signal GR <n:3>. High counter signal GR <n:3>Corresponds to the Gray code of n-2 bits. That is, the lower counter signal <3:0> corresponds to the 3 bits on the lower side in the counter value after decoding, and the upper counter signal GR <n:3>Corresponding to the n-2 positions on the upper side.

[0105] The lower counter signal JC<3:0> and the upper counter signal GR <n:3>The counter signal lines CTL-JC<3:0> and CTL-GR <n:3>Assign to Figure 2 The A / D conversion circuits 6 are shown located in thousands of columns.

[0106] Compared with the period in which the lower bit counter signal JC<3:0> changes, the upper bit counter signal GR <n:3>The changing cycle becomes longer. That is, the frequency of the lower counter signal JC<3:0> is higher than that of the upper counter signal GR <n:3>By increasing the frequency, the voltage drop on the counter signal line to be distributed in the low-order counter signal increases compared to the high-order counter signal with a low frequency. Therefore, a skew (time difference) may occur between the low-order counter signal and the high-order counter signal reaching the A / D conversion circuit 6.

[0107] In addition, even when the parasitic capacitance and parasitic resistance associated with the counter signal lines used to distribute the high-bit counter signals and the low-bit counter signals are different due to the influence of adjacent counter signal lines and / or other wiring, skew may occur between the bit counter signals arriving at the A / D conversion circuit 6.

[0108] In addition, if Figure 2 As shown, even in the case of generating the lower counter signal JC<3:0> and the upper counter signal GR <n:0>It is also possible to generate a skew between the lower and upper counter signals if the circuits used are different.

[0109] When a skew occurs, for example, relative to the low-order counter signal JC <3> The change timing of the high-bit counter signal GR may be delayed by tens of ps to several ns.

[0110] As reference Figure 4 and Figure 5 The determination circuit 12 determines the low-order counter signal JC <3> During the period when 1 is at a low level, the high latch signal 15 is maintained at a high level. Figure 6 In the low-order counter signal JC <3> During the period when the high-level counter signal GR <n:3>The change timing fluctuates due to the skew, and the high-order counter signal GR <n:3>is not latched by the high-order latch circuit 13. That is, the low-order counter signal JC <3> The period at the low level is a skew enabling period (allowed range) in which skew is allowed to occur. If the change of the high counter signal caused by the skew is considered as a state in which the high counter signal is uncertain, the skew enabling period can be considered as an uncertain period in which the high counter signal is allowed to be uncertain.

[0111] On the other hand, at the low counter signal JC <3> During the period when the high level is reached, the determination circuit 12 changes the high-level latch signal 15 to a low level in response to the low-level latch signal 14 changing to a low level. Figure 6 Middle and low counter signal JC <3> The period at the high level (the range represented by the dot) becomes the high-bit latchable period (possible range) in which the high-bit counter signal can be latched. In the first embodiment, each of the skew enable period and the high-bit latchable period is half of the cycle of the low-bit counter signal (time t1×4), and they appear alternately so as not to overlap each other in time. In other words, the period except the uncertain period becomes the high-bit latchable period, and in this period, the determination circuit 12 generates a low-level high-bit latch signal 15, and allows the high-bit latch circuit 13 to latch the high-bit counter signal.

[0112] Next, the operation when a skew occurs will be described. Figure 8 and Fig. 9 is a timing chart for explaining the operation of the A / D conversion circuit related to the first embodiment. Figure 8 shows the low-order counter signal JC <3> In the period of low level, the timing of the low latch signal 14 falling from high level to low level. On the other hand, Fig. 9 shows the low-order counter signal JC <3> Here, the operation of the A / D conversion circuit 6 corresponding to one column of the pixel section 3 will be described, but the operation of the A / D conversion circuit 6 corresponding to the remaining columns of the pixel section 3 is also the same.

[0113] like Figure 8 and Fig. 9 As shown, Figure 1 The reference voltage generating circuit 4 shown generates a reference voltage whose voltage changes linearly with the lapse of time. Figure 8 and Fig. 9 The reference voltage whose voltage decreases with the lapse of time is shown, but the reference voltage may be a voltage whose value increases with the lapse of time.

[0114] Using the pixel voltage from the pixel portion 3, the pixel voltage is supplied to the A / D conversion circuit 6 as an analog signal. Figure 8 and Fig. 9 As shown, when the voltage is reversed between the analog signal and the reference voltage, the comparison circuit 16 ( Figure 2 ) outputted low latch signal 14 drops from high level (H) to low level (L). Johnson counter 18 counts clock signal CLK and outputs low counter signal JC<3:0>. Figure 8 and Fig. 9 The lower counter signal JC<3:0> is shown with reference Figure 6 The lower counter signals JC<3:0> described above are the same.

[0115] exist Figure 8 In FIG. 1 , the dot-dash line indicates the timing of latching the low-order counter signal JC<3:0>. Fig.17 In the case of the comparative example described above, both the lower counter signal and the upper counter signal are latched at the timing indicated by the single-dot chain line. That is, the lower counter signal JC<3:0> and the upper counter signal GR <n:3>The low-level latch signal 14 is latched by falling to a low level. In the case of the comparative example, when the high-level counter signal GR <n:3>The change of the low counter signal JC <3> When the change in the input voltage is delayed, the high-order counter signal of the incorrect voltage level is latched according to the delay amount.

[0116] For example, when the high counter signal GR <3> In response to the low counter signal JC <3> When the high counter signal GR <3> The rise of is delayed due to the skew, even when the low latch signal 14 falls, assuming that the high counter signal GR <3> At a low level, the high-level counter signal GR is not correct at a high level. <3> is latched.

[0117] On the other hand, in the first embodiment, the low-order counter signal JC <3> When it is low, it is in the skew enable range, and when the low counter signal JC <3> Next, when it rises to a high level, the high latch signal 15 falls. Therefore, the high latch circuit 13 turns the high counter signal GR <n:3>As a result, even if the high counter signal GR <3> The rising edge of the high-order counter signal GR is delayed due to the skew, and the high-order latch circuit 13 can also store the correct high-level high-order counter signal GR <3> Latch.

[0118] Although the high counter signal GR <3> As an example, the description is given, but even when the high-bit counter signal GR <4> To GR <n>When the rising edge of is delayed, the high latch circuit 13 can also store the high counter signal GR of the correct voltage level (high level). <4> To GR <n>Similarly, even when the high-bit counter signal GR <3> To GR <n>When the falling edge of is delayed by the skew, the high-bit latch circuit 13 can also store the high-bit counter signal GR of the correct voltage level (low level). <3> To GR <n>Latch.

[0119] like Fig. 9 As shown, when the counter signal JC is at a low level <3> When the low-order latch signal 14 drops from high level to low level during the high-level period, the low-order latch circuit 11 latches the low-order counter signal JC<3:0> at the timing indicated by the single-dot chain line, and the high-order latch circuit 13 latches the high-order counter signal GR at the timing indicated by the double-dot chain line. <n:3>Therefore, even if the high-order counter signal GR is delayed due to, for example, skew <n:3>The high-bit latch circuit 13 can also store the high-bit counter signal GR of the correct voltage at the rising edge and / or falling edge of <n:3>Latch.

[0120] Despite Figures 6 to 8 This is not shown, but is generated each time an A / D conversion is completed. Figure 4 The set signal Set is shown. When the set signal Set is generated, the determination circuit 12 sets the voltage of the high-bit latch signal 15 to a high level.

[0121] In the above example, the conversion circuit 12 is based on the low-bit counter signal JC <3> Generates a high-bit latch signal 15, but the present invention is not limited thereto. Considering the high-bit counter signal GR <n:3>The conversion circuit 12 can calculate the period of time changed due to the skew based on the low-bit counter signal JC <0> To JC <2> Any one of the counter signals other than the low-order counter signal JC <3> To generate the high latch signal 15. For example, if the low counter signal JC is used <0> Replace the low counter signal JC <3> , the low-order counter signal JC <0> The period at the low level is set as the skew allowable range.

[0122] In the first embodiment, the most accurate time information (including the time t1 corresponding to the minimum input voltage 1LSB) is aggregated into the low-order counter signal JC<3:0> generated by the Johnson counter. Since the low-order counter signal JC<3:0> is generated by the Johnson counter, it is possible to prevent the change timing from varying due to the skew between the low-order counter signals JC<3:0>. On the other hand, even if the low-order counter signal JC<3:0> varies within the skew allowable range (time t1×4 corresponding to 4LSB), the high-order counter signal GR can be latched by the high-order latch signal 15 at a sufficiently stable time. <n:3>As a result, performance degradation such as DNL degradation and malfunction of the A / D conversion circuit can be prevented.

[0123] Since the high-bit latch signal 15 is set to the high-bit counter signal GR at an appropriate timing, <n:3>Latch, so when generating the lower counter signal JC<3:0> and the upper counter signal GR <n:3>When the counter circuit 5 does not need to ensure that the low-order counter signal JC<3:0> and the high-order counter signal GR <n:3>In addition, since the high-bit counter signal is latched by the high-bit latch signal 15 in each A / D conversion circuit 6 located in a plurality of columns, high-precision delay adjustment is not required when distributing the counter signal generated by the counter circuit 5 to a plurality of A / D conversion circuits 6. As a result, the A / D conversion circuit can achieve improvements in speed and DNL, ​​and the image sensor can improve performance such as high frame rate, high image quality, and a large number of pixels.

[0124] (Second embodiment) Fig.10 is a block diagram showing the configuration of a determination circuit related to the second embodiment. Fig.11 is a timing chart showing the operation of the A / D conversion circuit related to the second embodiment. The second embodiment provides that even when the high-bit counter signal GR <n:3>The A / D conversion circuit can prevent the characteristics from being degraded even when the fluctuation is greater than that in the first embodiment.

[0125] In the second embodiment, Figure 2 The determination circuit 12 shown in FIG. 1 becomes Fig.10 The determination circuit 12-1 shown is the same as that of the first embodiment except that the determination circuit is changed.

[0126] The determination circuit 12-1 includes a D-FF 12_1 and an AND circuit 12_3. The D-FF 12_1 is similar to Figure 4 The difference is that the clock terminal CK is provided with the output of the AND circuit 12_3 instead of the output of the AND circuit 12_2. The number of inputs of the AND circuit 12_3 is greater than the number of inputs of the AND circuit 12_2. That is, the AND circuit 12_3 includes an input in which the low-bit latch signal 14 is inverted and provided, an input in which the low-bit counter signal JC <0> To JC <2> Each of the inputs is inverted and provided, and the low-order counter signal JC <3> The input is provided.

[0127] When the low counter signal JC <0> To JC <2> Each of the low latch signal 14 becomes low level and the low counter signal JC <3> When the output of the AND circuit 12_3 becomes high, the DF 12_1 captures the ground voltage supplied to the input terminal D and outputs the high-bit latch signal 15 at a lower level.

[0128] Fig.11 Similar to Figure 6 The difference is that the skew allowable range is longer and the high-bit counter signal can be latched in a larger high-bit latchable range than Figure 6 That is, the determination circuit 12-1 is only in the low-order counter signal JC <0> To JC <2> At low level and low counter signal JC <3> Only in the period of high level can the high-bit latch signal 15 be output at a low level. Therefore, only this period becomes the high-bit latchable range, and the other periods become the skew allowable range. In this example, the skew allowable range is time t1×7. In this skew allowable range, even if the high-bit counter signal GR <n:3>The high-bit latch circuit 13 will not change the high-bit counter signal GR <n:3>latch, but can only be within the high latch range of the high counter signal GR <n:3>Latch.

[0129] Therefore, even if the high counter signal GR <n:3>Even if the fluctuation is significant, it can also prevent the A / D conversion circuit from deteriorating.

[0130] As the speed of the A / D conversion circuit is further increased, it is considered that the high-order counter signal GR caused by the skew is in the skew allowable range (t1×4) corresponding to 4LSB. <n:3>In the second embodiment, the skew allowable range is equal to the time (t1×7) of 7LSB. Therefore, even if the high-order counter signal GR <n:3>The delay due to the skew corresponding to the maximum 7LSB can also prevent the A / D conversion circuit from deteriorating.

[0131] In the determination circuit 12-1, the low-order counter signal JC <0> To JC <2> At low level and low counter signal JC <3> The period at the high level is set as the upper latchable range, but the present invention is not limited thereto. The combination of the lower bit counter signals supplied to the AND circuit 12_3 may be changed so that the timing at which the maximum margin can be ensured is for the higher order bit counter signal GR <n:3>The high bit of the fluctuation range can be latched. For example, if the low bit counter signal JC is changed <1> To JC <3> The inverted signal and the low-order counter signal JC <0> To be provided to AND circuit 12_3, only the low-order counter signal JC <0> The period at high level can be changed to high latch range.

[0132] (Third Embodiment) Fig.12 is a block diagram showing the configuration of a determination circuit related to the third embodiment. Fig.13 1 is a timing chart showing the operation of the A / D conversion circuit related to the third embodiment. In the second embodiment, the skew allowable range is expanded without changing the lower bit counter signal and the upper bit counter signal. The third embodiment provides an A / D conversion circuit with a wider skew allowable range by increasing the number of bits of the multi-phase clock signal generated by the Johnson counter 18 (i.e., the number of lower bit counter signals).

[0133] In the third embodiment, changing Figure 2 The Johnson counter 18 shown in FIG. 1 forms eight low-bit counter signals JC. <0> To JC <7> , and changes the binary counter 19 and the binary Gray converter 20 so that the low-order counter signal JC <7> Counting is performed to generate the high-order counter signal GR of the Gray code <4> To GR <7> .

[0134] Fig.12 The determination circuit 12-4 shown is similar to Fig.10 The difference is that an AND circuit 12_4 is used instead of the AND circuit 12_3. The AND circuit 12_4 has an input to which a signal obtained by inverting the low-bit latch signal 14 is supplied, and an input to which a signal obtained by inverting the low-bit counter signal JC is supplied. <0> To JC <6> The signal obtained by inverting each of the inputs is provided, and the low-order counter signal JC <7> The input is provided.

[0135] By using the determination circuit 12-4 configured as described above, as Fig.13 As shown, only the lower counter signal JC<6:0> is at a low level and the lower counter signal JC <7> The period at the high level becomes the high-bit latchable range, and the remaining period becomes the skew allowable range. In this example, the skew allowable range is the time corresponding to 15LSB (t1×15). That is, the high-bit counter signal GR caused by the skew <n:4>The change is mitigated to a period equal to 15LSB.

[0136] In the third embodiment, as in the second embodiment, by changing the combination of the lower-bit counter signals supplied to the AND circuit 12_4, the upper-bit latchable range can be changed according to the variation range of the upper-bit counter signal.

[0137] (Fourth embodiment) Fig.14 FIG. 4 is a block diagram showing the configuration of an image sensor related to the fourth embodiment. Fig.14 Similar to Figure 1 , the main differences will be explained. Fig.14 middle, Figure 1 The counter circuit 5 is configured by a high-speed counter circuit 5_1 and a low-speed digital circuit 5_2, and the counter signal line CTL is configured by a multi-phase clock signal line HML and a low-speed signal line LCL.

[0138] The clock signal CLK from the control circuit is supplied to the high-speed counter circuit 5_1. Based on the supplied clock signal CLK, the high-speed counter circuit 5_1 generates a multi-phase clock signal having a phase difference of, for example, a period corresponding to 1LSB, and supplies the generated multi-phase clock signal to the multi-phase clock signal line HML. The multi-phase clock signal line HML is arranged so as to extend a column portion formed by the A / D conversion circuit 6 positioned corresponding to each column of the pixel portion 3 and connected to each A / D conversion circuit 6. In each A / D conversion circuit 6, the multi-phase clock signal propagated through the multi-phase clock signal line HML is used as the lower bit counter signal described in the first embodiment.

[0139] The high-speed counter circuit 5_1 is composed of a CML (current mode logic) circuit using, for example, a CMOS transistor. The multi-phase clock signal is composed of a plurality of clock signals having the same frequency and different phases. Since the number of clock signals constituting the multi-phase clock signal is relatively small, adjustment of the skew in the column portion is also easy.

[0140] The low-speed digital circuit 5_2 is configured by a digital circuit (e.g., a binary counter, etc.) that operates based on a multi-phase clock signal. The low-speed signal formed by the low-speed digital circuit 5_2 is provided to a low-speed signal line LCL arranged in the column portion. Each A / D conversion circuit 6 positioned to the column uses the low-speed signal propagated through the low-speed signal line LCL as the high-bit counter signal described in the first embodiment. The high-bit counter signal is a periodically changing signal, but its frequency is lower than the frequency of the multi-phase clock signal constituting the low-bit counter signal, so that the skew in the column portion does not need to be finely adjusted. In addition, since each A / D conversion circuit 6 includes, for example, a low-bit latch circuit 11, a determination circuit 12, and a high-bit latch circuit 13 described in the first embodiment, even if there is a delay difference between the multi-phase clock signal and the low-speed clock signal or / and between the low-speed clock signal and the low-speed clock signal, the occurrence of a fault, etc. can be prevented.

[0141] (Fifth Embodiment) Fig.15 FIG. 4 is a block diagram showing the configuration of a column A / D conversion circuit related to the fifth embodiment. Fig.15 Similar to Figure 2 , the main differences will be explained. Fig.15 The main difference is that Figure 2 Each A / D conversion circuit 6 shown in FIG. 1 is added with a phase splitting circuit 30 and a least significant bit latch circuit 31 . Fig.16 is a timing chart showing the operation of the A / D conversion circuit related to the fifth embodiment.

[0142] The phase splitting circuit 30 receives the lower bit counter signal JC<3:0>, and generates a signal obtained by dividing the phase of the lower bit counter signal as a phase splitting signal (divided bit counter signal) 32. The phase splitting circuit 30 divides the phase of the lower bit counter signal JC<3:0>, which is a multi-phase clock signal, into two parts by using, for example, an SMD (Synchronous Mirror Delay) circuit or the like. For example, the phase splitting circuit 30 divides the phase of the lower bit counter signal JC<3:0> into two parts. <3> and JC <0> The phase difference between the two is divided into two equal parts, the voltage of the phase split signal 32 is increased at the timing obtained by dividing the phase difference into two equal parts, and ... <0> and JC <1> The timing obtained by dividing the phase difference between the two into two equal parts causes the voltage of the phase split signal 32 to drop. Fig.16 As shown, the phase splitting circuit 30 repeats such operation to generate the phase splitting signal 32, the voltage of which changes at a timing shifted by time t2 (half of t1) from the change of the low-order counter signal JC<3:0>, wherein one cycle is time t1×2.

[0143] The phase splitting signal 32 is not suitable for long-distance transmission because it is faster than the low-bit counter signal JC<3:0>. Therefore, in the fifth embodiment, each A / D conversion circuit 6 includes a phase splitting circuit 30. Although providing a phase splitting circuit 30 for each A / D conversion circuit 6 increases the area and power consumption, it is desirable to provide a common phase splitting circuit 30 for one to several hundred A / D conversion circuits 6.

[0144] The least significant bit latch circuit 31 is supplied with the lower latch signal 14 and the phase signal 32 from the phase splitting circuit 30. The least significant bit latch circuit 31 latches the supplied phase signal 32 in response to the lower latch signal 14 changing to the low level, and outputs it to the output line 21.

[0145] When the low-bit latch signal 14 becomes low level, the low-bit counter signal JC<3:0> and the phase split signal 32 are provided to the output line 21. As a result, the time corresponding to the minimum input voltage (minimum change) LSB convertible by the A / D conversion circuit 6 becomes the time t2 which is half of the time t1. In this case, Fig.16 As shown, the skew allowable range is time t2×14, and the high bit latchable range is time t2×2.

[0146] According to the fifth embodiment, the minimum input voltage that can be converted into a digital signal by the A / D converter 6 can be halved compared to the minimum input voltage of the first embodiment, and the resolution can be improved. In addition, the speed can be increased compared to the first embodiment.

[0147] For example, in the first embodiment, the high-order counter signal is GR <n:3>, and the lower counter signal is JC<3:0>. Therefore, for example, Figure 7 As shown in FIG. 1 , seven counter signals are required to represent counter values ​​from 0 to 32. When the same count value is represented by Gray code, such as Fig.23 As shown, it can be represented by six counter signals, and the number of counter signals can be reduced. However, as described in this embodiment, by dividing into a high-order counter signal and a low-order counter signal, a skew allowable range that allows the high-order counter signal to fluctuate due to skew can be provided, and the characteristics of the A / D conversion circuit can be prevented from deteriorating.

[0148] Despite Fig.15 1 and 2. The lower bit latch circuit 11 and the least significant bit latch circuit 31 are shown separately in FIG. 2, but the least significant bit latch circuit 31 may be integrated with the lower bit latch circuit 11 to form a single lower bit latch circuit.

[0149] exist Figure 2 In the embodiment, the Johnson counter 18 can be considered as a down counter circuit for transmitting a low-order counter signal. In this case, the binary counter 29 and the binary Gray conversion circuit 20 can be considered to constitute an up counter circuit for transmitting a high-order counter signal. In addition, the column conversion unit can be considered to be configured by a plurality of A / D conversion circuits and counter signal lines for transmitting a high-order counter signal and a low-order counter signal.

[0150] According to Embodiments 1 to 5, by adjusting the delay time for a small number of low-bit counter signals, the characteristics of the A / D conversion circuit can be prevented from being degraded due to skew, and the A / D conversion circuit can be operated at high speed. As a result, the frame rate, image quality, and the number of pixels of the image sensor can be increased. In addition, by using a Johnson counter as a counter circuit for generating a low-bit counter signal, a low-bit counter signal with almost no change in the delay time can be generated while reducing the adjustment of the delay time, and an A / D conversion circuit that can easily perform high-speed operation can be provided.

[0151] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A semiconductor device, comprising: a down counter circuit configured to output a low counter signal; an input signal determination circuit configured to compare a reference voltage with an input signal and output a low-bit latch signal; A low-bit latch circuit, configured to receive the low-bit counter signal and the low-bit latch signal to output a low-bit latch result signal; a low-bit determination circuit configured to receive the low-bit counter signal and the low-bit latch signal to output a high-bit latch signal; an up counter circuit configured to output a high counter signal; as well as A high-bit latch circuit is configured to receive the high-bit counter signal and the high-bit latch signal to output a high-bit latch result signal, wherein each of the lower bit counter signal and the upper bit counter signal comprises a plurality of bit counter signals, wherein the lower latch circuit latches the lower counter signal in response to the lower latch signal, and The lower bit determination circuit outputs the upper bit latch signal in a period excluding an indeterminate period in which the upper bit counter signal becomes indeterminate, based on the lower bit latch signal and a predetermined bit counter signal of the lower bit counter signal.

2. A semiconductor device comprising: A reference voltage generating circuit for generating a reference voltage that changes linearly with the passage of time; a counter circuit for generating a lower bit counter signal and an upper bit counter signal, each of the lower bit counter signal and the upper bit counter signal having a value that varies with the passage of time and including a plurality of bit counter signals; as well as An integrating A / D converter circuit, comprising: a comparator circuit for comparing an input signal with the reference voltage and outputting a low-bit latch signal when the input signal and the reference voltage reach a predetermined relationship; a low-bit latch circuit, for latching the low-bit counter signal in response to the low-bit latch signal; a determination circuit for outputting a high-bit latch signal in a period excluding an indeterminate period in which the high-bit counter signal becomes indeterminate based on the low-bit latch signal and a predetermined-bit counter signal in the low-bit counter signal; and A high-bit latch circuit is used to latch the high-bit counter signal in response to the high-bit latch signal, wherein the high-bit counter signal latched in the high-bit latch circuit and the low-bit counter signal latched in the low-bit latch circuit are output as digital signals corresponding to the input signal.

3. The semiconductor device according to claim 2, wherein the lower bit counter signal comprises a bit counter signal representing a minimum change in an analog signal to be converted by the integrating A / D converter circuit.

4. The semiconductor device according to claim 3, The integrating A / D converter circuit includes a decoder circuit for decoding the high-bit counter signal latched in the high-bit latch circuit and the low-bit counter signal latched in the low-bit latch circuit into a digital signal.

5. The semiconductor device according to claim 4, The determination circuit is provided with a plurality of bit counter signals among the lower bit counter signals as predetermined bit counter signals.

6. The semiconductor device according to claim 4, The counter circuit comprises: A low-bit counter circuit, outputting the low-bit counter signal; as well as The upper bit counter circuit outputs the upper bit counter signal based on the bit counter signal output from the lower bit counter circuit.

7. The semiconductor device according to claim 6, wherein the lower bit counter circuit includes a Johnson counter configured to output a plurality of signals having phases different from each other as the lower bit counter signal, and The upper-bit counter circuit includes a counter circuit for counting a predetermined signal among a plurality of signals output from the Johnson counter and outputting a Gray code signal as the upper-bit counter signal.

8. The semiconductor device according to claim 2, The counter circuit comprises: A low-bit counter circuit, used for outputting the low-bit counter signal; an upper bit counter circuit for outputting the upper bit counter signal based on the lower bit counter signal output from the lower bit counter circuit; as well as a phase divider circuit for dividing the phase between the bit counter signals output from the lower bit counter circuit and outputting the divided bit counter signals representing the minimum change of the analog signal to be converted in the integrating A / D converter circuit, and The lower bit latch circuit latches the lower bit counter signal and the divided bit counter signal in response to the lower bit latch signal.

9. A system comprising: A plurality of photosensitive elements are arranged in a matrix; a pixel portion having a plurality of signal lines arranged along columns of photosensitive elements arranged in a matrix and coupled to the photosensitive elements arranged in each column; A reference voltage generating circuit for generating a reference voltage that changes linearly with the passage of time; A counter circuit for outputting a high-bit counter signal and a low-bit counter signal, each of which includes a plurality of bit counter signals; a plurality of counter signal lines arranged along the rows of the photosensitive elements arranged in the matrix, for transmitting the high-bit counter signal and the low-bit counter signal; as well as a column converter unit arranged along each column direction, having a plurality of signal lines arranged in each column and a plurality of integrating type A / D converters arranged in each column, Each of the plurality of integrating A / D converters comprises: a comparator that outputs a low-bit latch signal by comparing an input signal provided from a corresponding signal line with the reference voltage; a lower bit latch circuit for latching a lower bit counter signal sent from a counter signal line in response to the lower bit latch signal; a determination circuit that outputs a high-bit latch signal in a period excluding an indeterminate period in which a high-bit counter signal becomes indeterminate based on the low-bit latch signal and a predetermined-bit counter signal in the low-bit counter signal; and The high-bit latch circuit latches the high-bit counter signal transmitted from the counter signal line in response to the high-bit latch signal.

10. The system according to claim 9, The counter circuit comprises: A first counter circuit, used for outputting the low-bit counter signal; a second counter circuit for generating the upper bit counter signal at a lower speed than the first counter circuit based on the bit counter signal output from the first counter circuit; as well as A decoder circuit is used to receive the high-bit counter signal latched in the high-bit latch circuit and the low-bit counter signal latched in the low-bit latch circuit, wherein the decoder circuit outputs a digital signal corresponding to an input signal provided from the photosensitive element through the signal line.

11. The system according to claim 9, wherein the column converter unit includes a phase splitting circuit which is arranged in a predetermined column of each column, is coupled to a counter signal line for transmitting the lower bit counter signal, and is used to generate a divided bit counter signal by dividing a phase difference between the lower bit counter signals, and The lower bit latch circuit latches the lower bit counter signal, and the lower bit latch circuit latches the lower bit counter signal and the divided bit counter signal in response to the lower bit latch signal.

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