Semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate having a cell region and an extension region; a channel structure disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate; a gate electrode layer surrounding the channel structure and stacked to be separated from each other in the first direction and extending in a second direction substantially perpendicular to the first direction; and a word line cutout that cuts the gate electrode layer in the first direction and extends continuously in the second direction. At least one word line cutout is an extended word line cutout having an extension portion, the extension portion having an area different from the area of ​​the remaining word line cutout located at the same level as the at least one word line cutout in a predetermined region extending in the second direction.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2018-0168796, filed on Dec. 24, 2018, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] Exemplary embodiments of the inventive concept relate to a vertical type semiconductor device including vertically stacked gate electrode layers and word line cutouts. Background Art

[0003] In order to achieve high integration of memory devices, vertical memory devices in which memory cells are stacked vertically from the surface of a substrate have been developed. In the vertical memory device, a columnar or cylindrical channel vertically protruding from the upper surface of the substrate is provided, and a plurality of gate lines and a plurality of insulating films in contact with the channel are stacked. In order to further increase the capacity of the vertical memory device, a greater number of gate lines and insulating films are stacked in the vertical direction. Summary of the invention

[0004] Exemplary embodiments of the inventive concept are directed to providing a vertical type semiconductor device capable of preventing a not-open defect phenomenon that may occur at a word line cut.

[0005] According to an exemplary embodiment, a semiconductor device includes a substrate having a cell region and an extension region, a plurality of channel structures arranged in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, and a plurality of gate electrode layers surrounding the channel structures. The gate electrode layers are spaced apart from each other in the first direction and extend in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a plurality of word line cuts that cut the gate electrode layers in the first direction and extend continuously in the second direction. At least one word line cut is an extended word line cut that includes an extension portion in a first predetermined region extending in the second direction, the extension portion having an area different from an area of ​​each of the remaining word line cuts other than the at least one word line cut that is located at the same level as the at least one word line cut.

[0006] According to an exemplary embodiment, a semiconductor device includes a substrate, a plurality of channel structures extending in a first direction substantially perpendicular to an upper surface of the substrate, and a gate electrode layer surrounding the channel structure. The gate electrode layers are stacked in a stepped shape to be spaced apart from each other in a first direction and to extend in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a plurality of word line cuts that cut the gate electrode layers in the first direction and extend in the second direction, and a connector that connects the gate electrode layers disposed on the same layer and protrudes from each of the gate electrode layers. The word line cuts include an extended word line cut having an extended portion and a separated word line cut separated by the connector.

[0007] According to an exemplary embodiment, a semiconductor device includes a substrate, a plurality of channel structures extending in a first direction substantially perpendicular to an upper surface of the substrate, and a plurality of gate electrode layers surrounding the channel structures. The gate electrode layers are separated from each other in the first direction and extend in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a plurality of common source lines that cut the gate electrode layers in the first direction and extend in the second direction, and a connector that connects the gate electrode layers disposed on the same layer and protrudes from each of the gate electrode layers. At least one of the common source lines is separated by the connector, and the width of the at least one common source line gradually increases in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0009] Figure 1A FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0010] Figure 1B FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0011] Figure 2 is along Figure 1A A cross-sectional view taken along line II'.

[0012] Figure 3 is along Figure 1A A cross-sectional view taken along line II-II'.

[0013] Figure 4 is along Figure 1A A cross-sectional view taken along line III-III'.

[0014] Figure 5 yes Figure 3 Magnified view of area E.

[0015] Figure 6 , Figure 7 , Fig. 8A and Figure 8B It is shown Figure 1A A plan view of a portion of a gate electrode layer is shown in FIG.

[0016] Fig.9A FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0017] Fig. 9B yes Fig.9A Perspective view of area F.

[0018] Fig.10 is along Fig.9A A cross-sectional view taken along line IV-IV'.

[0019] Fig.11 is along Fig.9A A cross-sectional view taken along line V-V'.

[0020] Fig.12 FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Like reference numerals may refer to like elements throughout the drawings.

[0022] It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0023] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0024] For ease of description, spatially relative terms such as "under," "beneath," "below," "below," "above," "on," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" may encompass both orientations of above and below.

[0025] It will be understood that when a component such as a film, region, layer or element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, the component can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or one or more intervening components may also be present.

[0026] Figure 1AFIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1B FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 2 is along Figure 1A A cross-sectional view taken along line II'. Figure 3 is along Figure 1A A cross-sectional view taken along line II-II'. Figure 4 is along Figure 1A A cross-sectional view taken along line III-III'. Figure 5 yes Figure 3 Magnified view of area E.

[0027] Reference Figure 1A , the semiconductor device 100 may include a cell region CEL in which a memory cell is formed and an extension region (or extension region) EXT in which the memory cell is connected to a line. Figure 1A A portion of the cell region CEL is shown. Although the extension region EXT is shown as being disposed on one side of the cell region CEL, the inventive concept is not limited thereto. For example, in an exemplary embodiment, the extension region EXT may be disposed on both sides of the cell region CEL. The peripheral circuit region may be disposed on the outer side of the extension region EXT, and a plurality of transistors constituting a drive circuit, a read / write circuit, and a control circuit may be disposed in the peripheral circuit region. Alternatively, the peripheral circuit region may be disposed below the cell region CEL and the extension region EXT.

[0028] Reference Figure 1A , Figure 1B , Figures 2 to 4 The semiconductor device 100 may include a substrate 101, a gate structure GS, a cell channel structure CH, a dummy channel structure DCH, a word line cutout WLC, a common source line 50, an insulating spacer 52, a contact CNT, a separation insulating pattern SSC, a mold insulating layer 40, upper insulating layers 41, 42, 43 and 44, a bit line BL and a connection line CL.

[0029] The substrate 101 may be a semiconductor substrate, and may include, for example, a silicon wafer, an epitaxially grown SiGe wafer, or a silicon-on-insulator (SOI) wafer.

[0030] The gate structure GS may be disposed on the substrate 101. The gate structure GS may be formed such that gate electrode layers 10 (10a to 101) and interlayer insulating layers 20 are alternately and repeatedly stacked in a direction substantially perpendicular to the substrate 101. The gate electrode layers 10 may be electrically separated from each other by the interlayer insulating layers 20.

[0031] Here, when a first component is described as extending in a direction substantially perpendicular or parallel to a second component or direction, it will be understood that the first component extends in a direction that is exactly perpendicular or parallel to the second component or direction, or extends in a direction that is approximately perpendicular or parallel to the second component or direction within a measurement error that would be understood by a person of ordinary skill in the art.

[0032] The gate electrode layer 10 and the interlayer insulating layer 20 may be paired, and the gate electrode layer 10 may extend in different lengths in the first direction, thereby providing a pad region PAD having a step. In an exemplary embodiment, the pad region PAD may form a step structure in the first direction. The contact CNT may be connected to the pad region PAD. The cell channel structure CH may extend in the first direction substantially perpendicular to the upper surface of the substrate 101.

[0033] The gate electrode layer 10 may provide the lowest ground selection line GSL closest to the substrate 101, word lines WL (10b to 10j) disposed on the ground selection line GSL, and string selection lines SSL disposed on the word lines WL. The ground selection line GSL and the string selection line SSL may both be formed as a multi-layer structure. The gate electrode layer 10 may further include a dummy word line disposed between the uppermost word line 10j farthest from the substrate 101 and the string selection line SSL (10k) and / or disposed between the lowest word line 10b closest to the substrate 101 and the ground selection line GSL (10a).

[0034] The gate electrode layers 10 may each include a metal material such as tungsten, copper, metal silicide, etc. The interlayer insulating layer 20 may include an oxide-based material such as silicon oxide, silicon oxycarbide, or silicon oxynitride.

[0035] The cell channel structure CH may extend substantially perpendicularly to the upper surface of the substrate 101 in the cell region CEL so that it passes through the gate electrode layer 10 and the interlayer insulating layer 20. The cell channel structure CH may be arranged in the second direction so that it defines a plurality of pad rows, and the plurality of pad rows may be arranged in the third direction. The cell channel structure CH may be arranged in a zigzag form on a flat surface. In an exemplary embodiment, a semiconductor pattern may also be arranged between the cell channel structure CH and the upper surface of the substrate 101. The semiconductor pattern may include, for example, single crystal silicon or polycrystalline silicon.

[0036] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0037] The gate electrode layer 10 may surround the cell channel structure CH. In addition, the gate electrode layers 10 may be spaced apart from each other in the first direction. In addition, the gate electrode layers 10 may extend in a second direction substantially perpendicular to the first direction.

[0038] Reference Figure 5 , the unit channel structure CH may include a channel 31, a dielectric film structure 32, and a buried insulating pattern 33. The channel 31 may have a hollow cylindrical shape or a hollow cup shape. For example, the channel 31 may include an outer surface in which an open internal space is formed. The channel 31 may include polycrystalline silicon or single crystal silicon, and may include p-type impurities such as boron (B) in some areas. The buried insulating pattern 33 may be arranged in the inner space of the channel 31 in a columnar or solid cylindrical shape. In an exemplary embodiment, the buried insulating pattern 33 may fill the inner space of the channel 31. The buried insulating pattern 33 may include an insulating material such as silicon dioxide as an example. In an exemplary embodiment, the channel 31 may have a columnar or solid cylindrical shape. For example, the channel 31 may not include an open internal space therein. In this case, the buried insulating pattern 33 may be omitted. The dielectric film structure 32 may surround the outer wall of the channel 31 and may have a basic straw shape or a cylindrical shell shape.

[0039] The dielectric film structure 32 may include a tunnel insulating film 32T, a charge storage film 32E, and a blocking film 32B sequentially stacked from the outer wall of the channel 31. The blocking film 32B may include a metal oxide such as silicon oxide, hafnium oxide, or aluminum oxide. The charge storage film 32E may include a nitride or a metal oxide such as silicon nitride, and the tunnel insulating film 32T may include an oxide such as silicon oxide. In an exemplary embodiment, the dielectric film structure 32 may have an oxide-nitride-oxide (ONO) stacked structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked.

[0040] In an exemplary embodiment, the gate structure GS may further include an interface pattern 32BK2 surrounding an outer wall of the gate electrode layer 10. The interface pattern 32BK2 may include a metal oxide such as aluminum oxide and / or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, and the like.

[0041] Refer again Figure 1A , Figure 1B , Figures 2 to 4 , a pad 34 may be formed on the cell channel structure CH. For example, the pad 34 may be electrically connected to the bit line BL and may function as a source / drain for transferring charges into the channel 31. The pad 34 may include polycrystalline silicon or single crystal silicon, and may further include n-type impurities such as phosphorus (P), arsenic (As), and the like.

[0042] The dummy channel structure DCH may extend in the extension region EXT in a direction substantially perpendicular to the upper surface of the substrate 101 so that it passes through the gate electrode layer 10 and the mold insulating layer 40. The dummy channel structure DCH may have a structure similar to that of the cell channel structure CH. However, unlike the cell channel structure CH, in an exemplary embodiment, the dummy channel structure DCH is not electrically connected to the bit line BL. The dummy channel structure DCH may be provided so as to ensure the stability of the structure during the manufacturing process. That is, in an exemplary embodiment, the cell channel structure CH is electrically connected to the bit line BL, and the dummy channel structure DCH is not electrically connected to the bit line BL and provides the stability of the structure.

[0043] The word line cutouts WLC may be arranged substantially parallel to the third direction. For example, the word line cutouts WLC may be arranged adjacent to each other in the third direction. At least some of the word line cutouts WLC may have the same shape, and portions of the word line cutouts WLC corresponding to each other in the third direction may have the same width in the third direction.

[0044] The word line cutouts WLC may extend in the second direction so that they cut the gate structure GS and the molded insulating layer 40 in the second direction. For example, the word line cutouts WLC may extend longitudinally in the second direction. The word line cutouts WLC may extend continuously in the second direction. For example, the word line cutouts WLC may extend continuously along the second direction without any discontinuity or opening therein. The gate electrode layer 10 and the interlayer insulating layer 20 may be divided into a plurality of blocks BK1 and BK2 by the word line cutouts WLC. The gate electrode layer 10 providing word lines in the blocks BK1 and BK2 may be divided into two unit electrodes UA1 and UA2 and two unit electrodes UA3 and UA4 by the word line cutouts WLC. For example, nine channel rows may be provided in one unit electrode. The word line cutouts WLC may cut the gate electrode layer 10 in the first direction.

[0045] In an exemplary embodiment, identical extended word line cutouts WLC1 may be alternately disposed substantially in parallel with the remaining word line cutouts WLC except for the extended word line cutouts WLC1 in the third direction.

[0046] The common source line 50 may be disposed inside the word line cutout WLC. The insulating spacer 53 may be formed on the sidewall of the common source line 50 and may extend in the second direction together with the common source line 50. The common source line 50 may be connected to a source region of the substrate 101. The source region may be formed by implanting impurities having a specific conductivity type into the substrate 101. For example, the source region may be a region doped with n-type impurities.

[0047] The separation insulating pattern SSC separates some of the gate electrode layers 10 disposed in the upper portion of the gate electrode layers 10 among the gate electrode layers 10 in the third direction. For example, the separation insulating pattern SSC may separate the two uppermost gate electrode layers 10K and 101 in the third direction. The separation insulating pattern SSC may separate one unit electrode UA1, UA2, UA3, or UA4 into two lower unit electrodes. The block BK1 including the two unit electrodes UA1 and UA2 and the block BK2 including the two unit electrodes UA3 and UA4 may include four lower unit electrodes. The four lower unit electrodes separated from each other may provide four string selection lines SSL for each of the blocks BK1 and BK2.

[0048] The contact CNT may be provided in the extension region EXT. The contact CNT may be connected to the pad region PAD of the gate electrode layer 10 by passing through the mold insulating layer 40 and the interlayer insulating layer 20. Figure 1A and Figure 1B , the contact CNT is shown as being disposed in each pad area PAD. However, the inventive concept is not limited thereto. For example, in an exemplary embodiment, some of the contacts CNT may be omitted. Therefore, in an exemplary embodiment, some of the pad areas PAD have the contact CNT disposed therein, and one or more of the pad areas PAD do not have the contact CNT disposed therein.

[0049] The word line cutout WLC may include at least one first word line cutout WLC1 and a plurality of second word line cutouts WLC2. In some areas, the first word line cutout WLC1 may include an extension portion 60 extending in width along a third direction. For example, the first word line cutout WLC1 extends longitudinally in the second direction, and its width extends in the third direction. The first word line cutout WLC1 may have substantially the same width in the second direction, except for the extension portion 60 having a different width from the remaining portion of the first word line cutout WLC1. For example, the width of the extension portion 60 in the third direction may be greater than the width of the remaining portion of the first word line cutout WLC1 in the third direction. In an exemplary embodiment, the extension portions 60 of a plurality of word line cutouts WLC may be aligned with each other in the second direction. In an exemplary embodiment, the extension portion 60 is disposed in the cell area CEL in an area close to the extension area EXT. For example, the extension portion 60 may be disposed in the cell area CEL in an area adjacent to the extension area EXT. The area in the cell area CEL in which the extension portion 60 is disposed may be directly adjacent to the extension area EXT, or there may be a space between the area and the extension area EXT. As Figure 1A and Figure 1BAs shown in FIG, the extension portion 60 may be disposed in the cell region CEL and extend from the cell region CEL into the extension region EXT in the second direction. Hereinafter, the first word line cutout WLC1 may be referred to as an extended word line cutout WLC1.

[0050] Herein, when two or more elements or values ​​are described as being substantially the same or approximately equal to each other, it is understood that these elements or values ​​are equivalent to each other, indistinguishable from each other, or distinguishable from each other but functionally identical to each other as will be understood by one of ordinary skill in the art. For example, when two or more elements or values ​​are substantially the same or substantially equal to each other but are not equivalent to each other, it is understood that the two or more elements or values ​​are approximately the same or equal to each other within a measurement error as will be understood by one of ordinary skill in the art.

[0051] In an exemplary embodiment, if Figure 1A As shown in , the first word line cutout WLC1 including the extension portion 60 may be disposed adjacent to both sidewalls of the gate structure GS. The non-opening phenomenon may easily occur at the word line cutout WLC disposed adjacent to both sidewalls of the gate structure GS. The non-opening phenomenon may refer to a phenomenon in which the word line cutout WLC is intended to provide an opening (or space) between adjacent structures, but the opening (or space) is not formed or maintained during and / or after manufacturing. Figure 1A In FIG. 1 , one extended word line cutout WLC1 is shown to be disposed on each of the two sidewalls of the gate structure GS. However, the inventive concept is not limited thereto. The extended word line cutout WLC1 may be disposed in a predetermined pattern or an irregular pattern in the third direction. For example, referring to Figure 1B , in the semiconductor device 100 , the extended word line cutouts WLC1 including the extended portion 60 and the second word line cutouts WLC2 not including the extended portion 60 may be alternately disposed in parallel to the third direction.

[0052] In an exemplary embodiment, in a plan view, the extended word line cutout WLC1 is disposed adjacent to two sidewalls of each of the gate electrode layers 10 spaced apart from each other in a third direction substantially perpendicular to the second direction.

[0053] In an exemplary embodiment, the common source line 50 may include at least one first common source line 51 and a plurality of second common source lines 52. The first common source line 51 may be disposed in the first word line cutout WLC1 and the second common source line 52 may be disposed in the second word line cutout WLC2. The first common source line 51 may include an extension pattern having an area (or a width in the third direction) different from that of other common source lines 50 at a predetermined position.

[0054] In an exemplary embodiment, the extension portion 60 of the word line cutout WLC and the extension pattern of the first common source line 51 disposed within the extension portion 60 may be disposed in the vicinity of a position at which the cell region CEL and the extension region EXT contact each other. The position at which the extension portion 60 of the word line cutout WLC is formed may be a position at which a non-opening phenomenon may easily occur during an etching process for forming the word line cutout WLC.

[0055] Figure 6 , Figure 7 , Fig. 8A and Figure 8B It is shown Figure 1A A plan view of a portion of a gate electrode layer is shown in FIG. Figure 1A , Figure 1B , Figures 2 to 7 , Fig. 8A and Figure 8B In the present invention, the same reference numerals refer to the same components. For ease of explanation, further description of previously described components or technical aspects will be omitted below.

[0056] Reference Figure 6 , the word line cutouts WLC11 and WLC21, the common source line 50 disposed in the word line cutouts WLC11 and WLC21, and the separation insulation pattern SSC may divide the uppermost gate electrode layer 101 disposed as the string selection line SSL into a plurality of lower unit electrodes 111, 121, and 131. In an exemplary embodiment, the extended word line cutout WLC1 may include a first portion and a second portion having different widths in the third direction. For example, the first portion may have a relatively narrow first width W1, and the second portion may have a relatively wide second width W2. For example, the first width W1 may be smaller than the second width W2. The second portion having the second width W2 corresponds to the above-mentioned extended portion 60.

[0057] The gate structure GS may be divided into a first region in which a first portion is disposed and a second region in which a second portion is disposed. For example, a second portion (i.e., an extended portion 60) of the extended word line cutout WLC1 having a second width W2 may be disposed in the second region, and a remaining portion of the extended word line cutout WLC1 having a first width W1 may be disposed in the first region. The first width W1 (or the area of ​​the first portion) of the first portion (i.e., the remaining portion) may be substantially equal to a width Wk1 (or an area) of a portion disposed in the first region of the second word line cutout WLC2 excluding the extended portion 60. The second width W2 (or the area of ​​the second portion) of the second portion may be different from a width Wk1 (or an area) of a portion disposed in the second region of the second word line cutout WLC2. For example, the area of ​​the second portion of the extended word line cutout WLC1 may be relatively larger than the area of ​​a corresponding portion of the second word line cutout WLC2 in the third direction.

[0058] In an exemplary embodiment, the uppermost extended word line cutout WLC1 may include an uppermost extended portion 60 located at a level equal to that of the uppermost gate electrode layer 10 located at an uppermost level among the gate electrode layers 10. In addition, the lowermost extended word line cutout WLC1 may include a lowermost extended portion 60 located at a level equal to that of the lowermost gate electrode layer 10 located at a lowermost level among the gate electrode layers 10 and having an area relatively smaller than that of the uppermost extended portion 60. The lowermost extended portion 60 may have a width greater than or equal to a width of a portion disposed in an area other than a predetermined area among the word line cutout WLC located at the same level as the lowermost extended portion 60.

[0059] Reference Figure 7 The word line cutouts WLC1k and WLC2k, the common source line 50, and the separation insulating pattern SSC may divide the upper gate electrode layer 10k provided as the string connection line SSL into a plurality of lower unit electrodes 11k, 12k, and 13k. Figure 6 Similarly, the extended word line cutout WLC1k may include a third portion and a fourth portion having different widths in the third direction. The third portion may be disposed in the first region, and the fourth portion may be disposed in the second region. The third portion may have a relatively narrow third width W3, and the fourth portion may have a relatively wide fourth width W4. The fourth portion having the fourth width W4 may correspond to the above-mentioned extended portion 60. For example, the third width W3 may be smaller than the fourth width W4. Referring to Figure 6 and Figure 7 , the value of W4 / W3 can be basically less than or equal to the value of W2 / W1.

[0060] Reference Figure 1A and Fig. 8A , the word line cutouts WLC1a and WLC2a and the common source line 50 may divide the lowermost gate electrode layer 10a provided as the ground selection line GSL into a plurality of unit electrodes UA1 (11a) and UA2. In an exemplary embodiment, the extended word line cutout WLC1a may include a fifth portion and a sixth portion having different widths in the third direction. The fifth portion may be provided in the first region, and the sixth portion may be provided in the second region. For example, the fifth portion may have a relatively narrow fifth width W5, and the sixth portion may have a relatively wide sixth width W6. The sixth portion having the sixth width W6 may correspond to the above-mentioned extended portion 60. The fifth width W5 may be smaller than the sixth width W6. The fifth width W5 may be substantially smaller than or equal to the first width W1 (see Figure 6 ) and / or a third width W3 (see Figure 7 ). The sixth width W6 may be smaller than the second width W2 (see Figure 6 ) and / or a fourth width W4 (see Figure 7 ). The fifth width W5 may be substantially equal to the width Wka. Figure 6 and Fig. 8A , the value of W6 / W5 can be smaller than W2 / W1.

[0061] Reference Figure 8B In an exemplary embodiment, the extended word line cutout WLC1a located at a level equal to that of the lowermost gate electrode layer 10a may be formed such that the seventh width W7 of the portion disposed in the first region is substantially equal to the eighth width W8 of the portion disposed in the second region. The seventh width W7 and the eighth width W8 may be substantially equal to the width Wka.

[0062] Fig.9A FIG. 1 schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 9B yes Fig.9A Perspective view of area F. Fig.10 is along Fig.9A A cross-sectional view taken along line IV-IV'. Fig.11 is along Fig.9A A cross-sectional view taken along the line V-V'. Fig. 9B In order to facilitate the description, the Fig.9A Some components are shown in area F. Figure 1A , Figure 1B , Figures 2 to 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig.10 and Fig.11 In the present invention, the same reference numerals refer to the same components. For ease of description, further description of previously described components and technical aspects will be omitted below.

[0063] Reference Fig.9A , Fig. 9B , Fig.10 and Fig.11 , the semiconductor device 100 may include a gate structure GS, a connection 70 , a cell channel structure CH, a dummy channel structure DCH, an extended word line cutout WLC1 , a separated word line cutout WLC3 , a common source line 50 , and a contact CNT.

[0064] In an exemplary embodiment, the gate structure GS may be formed such that the gate electrode layers 10 and the interlayer insulating layers 20 are alternately stacked in a first direction substantially perpendicular to the substrate 101. The gate structure GS may be divided into a plurality of blocks BK1 and BK2 by word line cutouts WLC1 and WLC3 extending in the first direction. A common source line 50 and an insulating spacer 53 may be provided in each of the word line cutouts WLC1 and WLC3.

[0065] The gate electrode layer 10 and the interlayer insulating layer 20 may be paired, and the gate electrode layer 10 may extend in different lengths in the second direction, so as to provide pad regions PAD (PAD1 to PAD4) each having a step. Some pad regions PAD may have steps in both the second direction and the third direction. The pad regions PAD may form a first hierarchical structure in the second direction. Fig. 9B and Fig.11 As shown in FIG, the third pad region PAD3 may have a step with another third pad region PAD3 disposed adjacent thereto and may form a second staircase structure in the third direction. The fourth pad region PAD4 may also have a step with another fourth pad region PAD4 disposed adjacent thereto and may form a second staircase structure in the third direction.

[0066] The gate structure GS may include a first block BK1 and a second block BK2. The first block BK1 and the second block BK2 may each have a structure in which each of a plurality of pad areas PAD (PAD1 to PAD4) is disposed in mirror symmetry. In an exemplary embodiment, the structure of the pad area PAD in the first block BK1 is identical to the structure of the pad area PAD in the second block BK2.

[0067] The separation word line cutout WLC3 may include a first separation word line cutout WLC3a and a second separation word line cutout WLC3b. A connector 70 may be disposed between the first separation word line cutout WLC3a and the second separation word line cutout WLC3b. The first separation word line cutout WLC3a may extend longitudinally from the connector 70 to the extension region EXT in the second direction, and the second separation word line cutout WLC3b may extend longitudinally from the connector 70 to the cell region CEL in the second direction. The extended word line cutout WLC1 may be disposed between two separation word line cutouts adjacent in the third direction (e.g., between the first separation word line cutout WLC3a and the second separation word line cutout WLC3b).

[0068] The connector 70 may divide the separation word line cutout WLC3 into a first separation word line cutout WLC3a and a second separation word line cutout WLC3b. The connector 70 may be formed to protrude in the third direction from the gate electrode layer (10a to 10j) extending in the second direction. The connector 70 may connect two unit electrodes UA1 and UA2 located at the same level with each other among the gate electrode layers 10a to 10j and two unit electrodes UA3 and UA4 located at the same level with each other. In an exemplary embodiment, the connector 70 may be disposed in a region corresponding to the second pad region PAD2 along the third direction in a plan view thereof. In an exemplary embodiment, the connector 70 is not connected to the gate electrode layers 10l and 10k disposed as the string selection line SSL in the gate structure GS.

[0069] The extended word line cutout WLC1 may include an extended portion 60. The extended portion 60 may have a width and an area in the third direction that are larger than the width and the area of ​​the portion of the separated word line cutout WLC3 corresponding to the extended portion 60 in the third direction. When the semiconductor device 100 does not include the extended word line cutout WLC1 (i.e., when the extended portion 60 is not present), during the process of forming the word line cutout, a loading effect may occur due to a mask pattern set on the connector 70. Due to the loading effect, a non-opening phenomenon of the lowermost gate electrode layer (ground selection line GSL) may occur. Therefore, the semiconductor device 100 according to an exemplary embodiment of the inventive concept can prevent the non-opening phenomenon by forming the extended portion 60 having a large area at a position where the loading effect occurs due to the connector 70.

[0070] like Fig. 9B As shown in the exemplary embodiment, the extended portion 60 of the extended word line cutout WLC1 has an area (or width) different from the area (or width) of the remaining word line cutouts (e.g., WLC3b) located at the same level that are not extended word line cutouts in a predetermined region in the second direction. This configuration can also be applied to Figure 1A , Figure 1B , Figures 2 to 7 , Fig. 8A and Figure 8B The word line cutout is shown in FIG.

[0071] Still like Fig. 9B As shown in , in an exemplary embodiment, the gate electrode layers 10 may be stacked in a step shape to be spaced apart from each other in a first direction and to extend in a second direction substantially perpendicular to the first direction.

[0072] Fig.12 Schematically illustrates a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1A , Figure 1B , Figures 2 to 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B as well as Figures 10 to 12 In the present invention, the same reference numerals refer to the same components. For ease of explanation, further description of previously described components or technical aspects will be omitted below.

[0073] Reference Fig.12 , the semiconductor device 100 may include an extended separated word line cutout WLC4 each having a width gradually increasing in the third direction, a common source line 50 disposed in the extended word line cutout WLC4, and an insulating spacer 53. The extended separated word line cutout WLC4 may include a first extended separated word line cutout WLC4a and a second extended separated word line cutout WLC4b. A connector 70 may be disposed between the first extended separated word line cutout WLC4a and the second extended separated word line cutout WLC4b. The first extended separated word line cutout WLC4a may extend longitudinally from the connector 70 to the cell region CEL in the second direction, and the second extended separated word line cutout WLC4b may extend longitudinally from the connector 70 to the extended region EXT in the second direction.

[0074] In an exemplary embodiment, the width of at least one of the first and second extended separated word line cutouts WLC4a and WLC4b may gradually increase in the third direction as they become closer to the connector 70 in the second direction. For example, as at least one of the first and second extended separated word line cutouts WLC4a and WLC4b extends longitudinally in the second direction toward the connector 70, its width gradually increases in the third direction. Fig.12 , although only the width of the first extended separated word line cutout WLC4a is shown as gradually increasing in the third direction, the inventive concept is not limited thereto. For example, in an exemplary embodiment, the width of the second extended separated word line cutout WLC4b may also gradually increase in the third direction. A step may be formed on the extended separated word line cutout WLC4, and the width of a portion adjacent to the connector 70 in the third direction related to the step may be greater than the width of a portion farther from the connector 70 in the third direction.

[0075] The width of the common source line 50 disposed in the extended separated word line cutout WLC4 having a gradually increasing width in the third direction may also gradually increase as the common source line 50 is closer to the connection member 70 in the second direction. A step may also be formed on the sidewall of the common source line 50, and the width of a portion adjacent to the connection member 70 in the third direction related to the step may be greater than the width of a portion farther from the connection member 70 in the third direction.

[0076] According to an exemplary embodiment of the inventive concept, a plurality of word lines formed on the same layer of a semiconductor device can be connected to each other through a connector. During the process of forming a word line cut, the semiconductor device can prevent the phenomenon of not opening by including an extension at a position affected by a load effect caused by the connector. As a result, the contact and / or line structure of the semiconductor device is reduced by the connector, so that the stability of the semiconductor device is improved, and the capacity and integration density of the semiconductor device are also increased. In addition, only the area of ​​the extension is increased without increasing the overall area of ​​the word line cut, so that the reliability of the semiconductor device can be ensured by fully ensuring the separation distance between the word line cut and the channel.

[0077] In an exemplary embodiment of the inventive concept, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells having active areas disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each underlying level of the array.

[0078] In an exemplary embodiment of the inventive concept, a 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. The following patent documents, which are incorporated herein by reference, describe suitable configurations for a three-dimensional memory array, wherein the three-dimensional memory array is configured as multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0079] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined in the claims.

Claims

1. A semiconductor device, comprising: substrate, including the cell region and the extension region; a plurality of channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate; a plurality of gate electrode layers surrounding the plurality of channel structures, wherein the plurality of gate electrode layers are spaced apart from each other in a first direction and extend in a second direction substantially perpendicular to the first direction; and a plurality of word line cuts, cutting the plurality of gate electrode layers in a first direction and continuously extending in a second direction; wherein the plurality of word line cutouts include a first word line cutout having an extended portion and a second word line cutout spaced apart from the first word line cutout in a third direction perpendicular to the first direction and the second direction, The width of the extended portion of the first word line cutout in the third direction is greater than the width of the remaining portion of the first word line cutout except the extended portion in the third direction. wherein the second word line cutout includes a first portion disposed at the same level as the extended portion of the first word line cutout in the third direction and a second portion disposed at the same level as the remaining portion of the first word line cutout in the third direction, and The width of the first portion of the second word line cutout in the third direction is substantially the same as the width of the second portion of the second word line cutout in the third direction.

2. The semiconductor device according to claim 1, wherein A width of the extended portion in the third direction is greater than a width of the first portion of the second word line cutout in the third direction.

3. The semiconductor device according to claim 1, wherein The extension portion is provided in the cell region in a region adjacent to the extension region.

4. The semiconductor device according to claim 1, wherein The extension portion is disposed in the cell region and extends into the extension region in the second direction.

5. The semiconductor device according to claim 1, wherein In a plan view, the first word line cutout is disposed adjacent to two sidewalls of each of the plurality of gate electrode layers that are spaced apart from each other in the third direction.

6. The semiconductor device according to claim 1, wherein The first word line cutouts are arranged alternately with the second word line cutouts in the third direction and are parallel to the second direction.

7. The semiconductor device according to claim 1, further comprising: an insulating common source line spacer disposed in each of the plurality of word line cutouts; as well as A conductive common source line is disposed in each of the plurality of word line cutouts.

8. The semiconductor device according to claim 1, wherein The extensions include: an uppermost expansion portion located at a level equal to a level of an uppermost gate electrode layer located at an uppermost level among the plurality of gate electrode layers; and The lowermost extension portion is located at a level equal to that of a lowermost gate electrode layer located at a lowermost level among the plurality of gate electrode layers and has an area relatively smaller than that of the uppermost extension portion.

9. The semiconductor device according to claim 1, wherein: The remaining portion of the first word line cutout has the same width in the third direction as the second portion of the second word line cutout has.

10. A semiconductor device, comprising: substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrode layers surrounding the plurality of channel structures, wherein the plurality of gate electrode layers are stacked in a step-shaped form to be spaced apart from each other in a first direction and extend in a second direction substantially perpendicular to the first direction; a plurality of word line cuts cutting the plurality of gate electrode layers in a first direction and extending in a second direction; and a connection member connecting gate electrode layers provided on the same layer and protruding from each of the plurality of gate electrode layers, The plurality of word line cutouts include an extended word line cutout having an extended portion and a separated word line cutout spaced apart from the extended word line cutout in a third direction perpendicular to the first direction and the second direction, the separated word line cutouts being separated by a connecting member, The width of the extended portion of the extended word line cutout in the third direction is greater than the width of the remaining portion of the extended word line cutout except the extended portion in the third direction. wherein the separated word line cutout includes a first portion disposed at the same level as the extended portion of the extended word line cutout in the third direction and a second portion disposed at the same level as the remaining portion of the extended word line cutout in the third direction, and The width of the first portion of the separation word line cutout in the third direction is substantially the same as the width of the second portion of the separation word line cutout in the third direction.

11. The semiconductor device according to claim 10, wherein The width of the extension portion in the third direction is greater than the width of the first portion of the separation word line cutout in the third direction.

12. The semiconductor device according to claim 10, wherein: The extended word line cutout is disposed between the separated word line cutouts spaced apart from each other along the third direction.

13. The semiconductor device according to claim 10, wherein: The substrate includes a cell region in which a plurality of cell channel structures are disposed and an extension region in which a plurality of pad regions are disposed in a stepped shape; and The expansion portion is arranged in the unit region and the connecting member is arranged in the expansion region.

14. The semiconductor device according to claim 13, wherein: The extension portion extends from the cell region into the extension region in the second direction.

15. The semiconductor device according to claim 14, wherein: Each of the plurality of gate electrode layers includes a ground selection line, a word line, and a string selection line sequentially stacked in a first direction from an upper surface of the substrate, The string selection lines are separated from each other and extend on the same layer, and The word lines are connected by connectors and extend on the same layer.

16. The semiconductor device according to claim 15, wherein In a plan view, the extended portion extends to a pad region of a string selection line.

17. The semiconductor device according to claim 15, wherein: An area of ​​the expansion portion located at a level equal to that of the string selection line is relatively larger than an area of ​​the expansion portion located at a level equal to that of the ground selection line.

18. The semiconductor device according to claim 10, wherein The extended word line cutouts are arranged alternately with the separated word line cutouts in the third direction and are parallel to the second direction.

19. The semiconductor device according to claim 10, wherein: The substrate includes a cell region in which a cell channel structure is disposed and an extension region in which a contact connected to a gate electrode layer is disposed; The separated word line cuts include a first separated word line cut extending in the second direction relative to the connection member toward the cell region and a second separated word line cut extending in the second direction relative to the connection member toward the extension region; and The expansion portion is disposed at a position corresponding to the first separated word line cutout in the second direction.

20. A semiconductor device, comprising: substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrode layers surrounding the plurality of channel structures, wherein the plurality of gate electrode layers are spaced apart from each other in a first direction and extend in a second direction substantially perpendicular to the first direction; a plurality of common source lines cutting through the gate electrode layer in a first direction and extending in a second direction; and a connection member connecting gate electrode layers provided on the same layer and protruding from each of the plurality of gate electrode layers, wherein at least one common source line among the plurality of common source lines is separated by a connection member to form ends facing each other at a position adjacent to the connection member, and The width of the at least one common source line gradually increases along the second direction toward the connecting member, and does not decrease along the second direction toward the connecting member, so that the at least one common source line includes a first portion and a second portion, the first portion extends from one of the end portions along the second direction away from the connecting member and has a first width, and the second portion extends from the first portion along the second direction away from the connecting member and has a second width smaller than the first width.

Images