Power transistor and amplifier with harmonic termination circuit and manufacturing method

Abstract

Embodiments of an RF amplifier and an RF amplifier device include a transistor, a multi-stage bandpass filter circuit, and a harmonic termination circuit. The bandpass filter circuit includes: a first connection node, the first connection node is coupled to an amplifier input; a first inductive element, the first inductive element is coupled between the first connection node and a ground reference node; a first capacitor, the first capacitor is coupled between the first connection node and a second connection node; a second capacitor, the second capacitor is coupled between the second connection node and the ground reference node; and a second inductive element, the second inductive element is coupled between the second connection node and a transistor input. The harmonic termination circuit includes a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of the operating fundamental frequency of the RF amplifier.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate generally to radio frequency (RF) amplifiers, and more particularly, to broadband power transistor devices and amplifiers and methods of making such devices and amplifiers. Background Art

[0002] Wireless communication systems employ power amplifiers to increase the power of radio frequency (RF) signals. For example, in a cellular base station, a Doherty power amplifier may form part of the last amplification stage in the transmission chain before providing the amplified signal to an antenna for radiation over the air interface. High gain, high linearity, stability, and high levels of power added efficiency are characteristics of a desirable power amplifier in such wireless communication systems.

[0003] In the field of power amplifier device design, achieving concurrent multi-band, wideband amplification is becoming increasingly desirable. For example, in order to successfully design a wideband power amplifier device for concurrent multi-band, wideband operation in a Doherty power amplifier circuit, it is desirable to be able to achieve a good wideband fundamental match (e.g., more than 20% fractional bandwidth) to properly handle harmonic frequency interactions and achieve wide video bandwidth. However, achieving these goals continues to present challenges to power amplifier device designers. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided a radio frequency (RF) amplifier, comprising:

[0005] a transistor die having a transistor and a transistor input terminal;

[0006] A multi-stage bandpass filter circuit is coupled between the first input of the first amplification path and the transistor input terminal, wherein the multi-stage bandpass filter circuit comprises:

[0007] a first connection node coupled to the first input;

[0008] a first inductive element coupled between the first connection node and a ground reference node;

[0009] The second connection node;

[0010] a first capacitor coupled between the first connection node and the second connection node;

[0011] a second capacitor coupled between the second connection node and the ground reference node; and

[0012] a second inductor element coupled between the second connection node and the transistor input terminal; and

[0013] A harmonic termination circuit includes a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node, wherein the harmonic termination circuit resonates at a harmonic frequency of the fundamental frequency of operation of the RF amplifier.

[0014] In one or more embodiments, the transistor is a gallium nitride transistor.

[0015] In one or more embodiments, the second inductive element comprises a first plurality of bond wires; and

[0016] The third inductive element includes a second plurality of bond wires.

[0017] In one or more embodiments, the input-side harmonic termination circuit resonates at a second harmonic frequency of the operating fundamental frequency.

[0018] In one or more embodiments, the RF amplifier further comprises:

[0019] A baseband decoupling circuit is coupled between the second connection node and the ground reference node, wherein the baseband decoupling circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and the ground reference node.

[0020] In one or more embodiments, the baseband decoupling circuit further includes a bypass capacitor coupled in parallel across one or more of the plurality of components of the baseband decoupling circuit.

[0021] In one or more embodiments, the bypass capacitor is coupled in parallel across the envelope inductor, and wherein the envelope inductor and the bypass capacitor form a parallel resonant circuit close to a center operating frequency of the RF amplifier.

[0022] In one or more embodiments, the input circuit further includes a fourth inductive element coupled between the first input and the first connection node, wherein the fourth inductive element includes a plurality of bond wires.

[0023] In one or more embodiments, the input circuit further comprises:

[0024] a resistor coupled in parallel with the first capacitor between the first connection node and the second connection node; and

[0025] A DC blocking capacitor is coupled in series with a first inductive element coupled between the first connection node and a ground reference node.

[0026] In one or more embodiments, the RF amplifier further comprises:

[0027] Second amplification path;

[0028] a power splitter having a power splitter input configured to receive an RF signal, a first output coupled to the first input of the first amplification path, and a second output coupled to the second input of the second amplification path, wherein the power splitter is configured to split the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output; and

[0029] A combining node is configured to receive and combine the amplified RF signals produced by the first amplification path and the second amplification path.

[0030] In one or more embodiments, the RF amplifier is a Doherty power amplifier.

[0031] According to a second aspect of the present invention, there is provided a packaged radio frequency (RF) amplifier device comprising:

[0032] device substrate;

[0033] an input lead coupled to the device substrate;

[0034] an output lead coupled to the device substrate;

[0035] a transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input coupled to the input lead, and a transistor output coupled to the output lead;

[0036] a multi-section bandpass filter circuit coupled to the input lead and the transistor input, wherein the multi-section bandpass filter circuit comprises:

[0037] a first connection node coupled to the input lead;

[0038] a first inductive element coupled between the first connection node and a ground reference node;

[0039] The second connection node;

[0040] a first capacitor coupled between the first connection node and the second connection node;

[0041] a second capacitor coupled between the second connection node and the ground reference node; and

[0042] a second inductor element coupled between the second connection node and the transistor input terminal; and

[0043] A harmonic termination circuit includes a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node, wherein the harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

[0044] In one or more embodiments, the packaged RF amplifier device further comprises:

[0045] An integrated passive device is coupled to the device substrate, wherein the first inductive element, the first capacitance, and the second capacitance are integrally formed with or connected to the integrated passive device.

[0046] In one or more embodiments, the packaged RF amplifier device further comprises:

[0047] an integrated passive device coupled to the device substrate, wherein at least some of the components of the multi-section bandpass filter circuit are integrally formed with or connected to the integrated passive device, and wherein the second inductive element includes a first plurality of bond wires connected between the integrated passive device and the transistor die.

[0048] In one or more embodiments, the third capacitor is integrally formed with or connected to the integrated passive device; and

[0049] The third inductive element includes a second plurality of bond wires connected between the integrated passive device and the transistor die.

[0050] According to a third aspect of the present invention, there is provided a method of manufacturing an RF amplifier device, the method comprising the steps of:

[0051] coupling an input lead to a device substrate;

[0052] coupling an output lead to the device substrate;

[0053] coupling a transistor die to the device substrate between the input lead and the output lead, wherein the transistor die includes a transistor and a transistor input terminal;

[0054] A multi-stage bandpass filter circuit is coupled between the input lead and the transistor input terminal, wherein the multi-stage bandpass filter circuit comprises:

[0055] a first connection node coupled to the input lead;

[0056] a first inductive element coupled between the first connection node and a ground reference node;

[0057] The second connection node;

[0058] a first capacitor coupled between the first connection node and the second connection node;

[0059] a second capacitor coupled between the second connection node and the ground reference node; and

[0060] a second inductor element coupled between the second connection node and the transistor input terminal; and

[0061] A harmonic termination circuit is coupled between the transistor input and the ground reference node, wherein the harmonic termination circuit includes a third inductive element and a third capacitor connected in series and resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

[0062] In one or more embodiments, coupling the multi-stage bandpass filter circuit between the input lead and the transistor input terminal comprises:

[0063] coupling an integrated passive device to the device substrate between the transistor die and the input lead, wherein the first integrated passive device includes the first inductive element, the first capacitance, the second capacitance, and first and second connection nodes in the form of first and second bonding pads;

[0064] coupling a fourth inductive element between the input lead and the first connection node by coupling a first plurality of bond wires between the input lead and the first connection node; and

[0065] coupling the second inductive element between the second connection node and the transistor input terminal by coupling a second plurality of bond wires between the second connection node and the transistor input terminal;

[0066] The integrated passive device further comprises the third capacitor; and

[0067] Coupling the harmonic termination circuit between the transistor input and the ground reference node includes coupling a third plurality of bond wires between the transistor input and the third capacitor.

[0068] In one or more embodiments, the method further comprises:

[0069] A baseband decoupling circuit is coupled between the second connection node and the ground reference node, wherein the baseband decoupling circuit includes a plurality of components, wherein the plurality of components includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and the ground reference node.

[0070] In one or more embodiments, coupling the multi-stage bandpass filter circuit between the input lead and the transistor input includes coupling an integrated passive device to the device substrate between the transistor die and the input lead, wherein the first integrated passive device includes the first inductive element, the first capacitor, the second capacitor, the envelope resistor, the envelope inductor, and the envelope capacitor.

[0071] In one or more embodiments, coupling the harmonic termination circuit between the transistor input and the ground reference node includes coupling a third plurality of bond wires between the transistor input and the third capacitor.

[0072] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following drawings, wherein like reference numerals refer to like elements throughout the drawings.

[0074] Figure 1 is a schematic circuit diagram of a power amplifier circuit according to an example embodiment;

[0075] Figures 2A-2F Various example embodiments of baseband decoupling circuits are shown;

[0076] Figure 3 is a simplified schematic diagram of a Doherty power amplifier according to an example embodiment;

[0077] Figure 4 is a top view of a packaged RF power amplifier device including two parallel amplification paths according to an example embodiment;

[0078] Figure 5is a top view of a portion of a packaged RF power amplifier device including a portion of a power transistor and an input impedance matching circuit according to an example embodiment;

[0079] Figure 6 is taken along line 6-6 according to an exemplary embodiment Figure 5 a cross-sectional side view of a portion of an RF power amplifier device; and

[0080] Figure 7 is a flow chart of a method for manufacturing a packaged RF power amplifier device including an embodiment of an input impedance matching circuit according to an example embodiment. DETAILED DESCRIPTION

[0081] In the field of high power radio frequency (RF) power amplification for cellular base stations and other applications, broadband power amplification using silicon-based devices (e.g., laterally diffused metal oxide semiconductor (LDMOS) power transistor devices with output matching networks) has been successfully achieved. However, such silicon-based devices exhibit relatively low efficiency and power density when compared to the efficiency and power density of gallium nitride (GaN)-based power amplifier devices. Therefore, GaN-based power amplifier devices have been increasingly considered for high power broadband applications. However, there are challenges in achieving broadband power amplification (e.g., fractional bandwidth exceeding 20%) using GaN technology.

[0082] For example, it is known that the nonlinear input capacitance of RF power devices including GaN transistors generates harmonics and intermodulation distortion that can degrade efficiency and linearity. Second harmonic termination also plays an important role in the overall performance of power amplifier designs using GaN-based transistors. Without knowledge of the second harmonic impedance at the current source termination plane, it is very difficult to tune a power amplifier to achieve a relatively high fractional bandwidth with good performance. In addition, for broadband applications, the second harmonic termination may vary significantly across a large bandwidth, which further increases the difficulty of circuit tuning.

[0083] To overcome these and other challenges of designing broadband power amplifiers using GaN-based devices, embodiments disclosed herein may use a multi-section (e.g., two-section) bandpass filter topology to achieve broadband input impedance matching at the fundamental frequency. Input-side harmonic termination circuitry is added near the gate terminal using bond wire connections and RF capacitors. Some specific embodiments of the subject matter of the present invention include an input harmonic termination circuit system that includes an integrated capacitor (e.g., a metal-insulator-metal (MIM) capacitor) and an inductor (e.g., in the form of a bond wire array) coupled in series between the transistor input and a ground reference. The harmonic termination circuit system embodiments may be used to control the second harmonic impedance across a very wide (e.g., more than 20%) fractional bandwidth at a relatively low impedance (e.g., close to a short circuit). This may be useful for achieving relatively high efficiency for broadband applications.

[0084] The parallel capacitor in the input side impedance matching circuit is desirably selected to meet broadband impedance matching. More specifically, the parallel capacitor in the input side matching circuit has a sufficiently high capacitance value (e.g., greater than 60 pF) to provide an acceptable RF low impedance point (e.g., a quasi RF cold point). The RF low impedance point represents a low impedance point in the circuit for RF signals. A baseband decoupling circuit with good RF isolation is connected to the quasi RF cold point.

[0085] Figure 1 is a schematic diagram of an RF power amplifier circuit 100. In an embodiment, the circuit 100 includes: an input 102 (e.g., a first conductive package lead); an input impedance matching circuit 110; a harmonic termination circuit 130; a transistor 140; an output impedance matching circuit 150; baseband decoupling (BBD) circuits 160, 162 (also referred to as video bandwidth circuits); and an output lead 104 (e.g., a second conductive package lead). Each of the input 102 and the output 104 may be more generally referred to as an "RF input / output (I / O)".

[0086] The input impedance matching circuit 110, the harmonic termination circuit 130, and the baseband decoupling circuit 160 may be collectively referred to as an "input circuit". Similarly, the output impedance matching circuit 150 and the baseband decoupling circuit 162 may be collectively referred to as an "output circuit". Although the transistor 140 and the various elements of the input impedance matching circuit 110, the output impedance matching circuit 150, the baseband decoupling circuits 160, 162, and the harmonic termination circuit 130 are shown as a single component, the purpose of the depiction is only for ease of explanation. Based on the description herein, those skilled in the art will understand that the transistor 140 and / or certain elements of the input impedance matching circuit 110, the harmonic termination circuit 130, the output impedance matching circuit 150, and the baseband decoupling circuits 160, 162 may each be implemented as multiple components (e.g., connected in parallel or in series with each other). Additionally, embodiments may include single-path devices (e.g., including a single input lead, a single output lead, a single transistor, etc.), dual-path devices (e.g., including two input leads, two output leads, two transistors, etc.), and / or multi-path devices (e.g., including two or more input leads, two or more output leads, two or more transistors, etc.). Additionally, the number of input / output leads may not be the same as the number of transistors (e.g., for a given set of input / output leads, there may be multiple transistors operating in parallel). Thus, the following description of transistor 140 and the various elements of input impedance matching circuit 110, harmonic termination circuit 130, output impedance matching circuit 150, and baseband decoupling circuits 160, 162 is not intended to limit the scope of the inventive subject matter to only the illustrated embodiments.

[0087] The input 102 and the output 104 may each include a conductor configured to enable the circuit 100 to be electrically coupled to an external circuit system (not shown). More specifically, in an embodiment, the input 102 and the output 104 are physically positioned to span between the exterior and interior of the device package. The input impedance matching circuit 110, the harmonic termination circuit 130, and the baseband decoupling circuit 160 are electrically coupled between the input 102 and the first terminal 142 (e.g., the gate terminal) of the transistor 140. Similarly, the output impedance matching circuit 150 and the baseband decoupling circuit 162 are electrically coupled between the second terminal 144 (e.g., the drain terminal) of the transistor 140 and the output 104. The third terminal 145 (e.g., the source terminal) of the transistor 140 is coupled to the ground reference node.

[0088] According to an embodiment, transistor 140 is the main active component of circuit 100. Transistor 140 includes a control terminal 142 and two current conducting terminals 144, 145, wherein the current conducting terminals 144, 145 are separated spatially and electrically by a variable conductivity channel. For example, transistor 140 may be a field effect transistor (FET) including a gate terminal (control terminal 142), a drain terminal (first current conducting terminal 144), and a source terminal (second current conducting terminal 145). According to an embodiment and using the nomenclature generally applied to FETs in a non-limiting manner, the gate terminal 142 of transistor 140 is coupled to input impedance matching circuit 110, harmonic termination circuit 130, and baseband decoupling circuit 160, the drain terminal 144 of transistor 140 is coupled to output impedance matching circuit 150 and baseband decoupling circuit 162, and the source terminal 145 of transistor 140 is coupled to ground (or another voltage reference). By changing the control signal provided to the gate terminal of transistor 140, the current between the current conducting terminals of transistor 140 can be modulated.

[0089] According to various embodiments, transistor 140 is a III-V field effect transistor (eg, a high electron mobility transistor (HEMT)) having a relatively low drain-source capacitance Cds when compared to silicon-based FETs (eg, LDMOS FETs). Figure 1 , the drain-source capacitance of transistor 140 is represented by capacitor 146 between the drain terminal of transistor 140 and transistor output 144. More specifically, capacitor 146 is not a physical component, but rather, it models the drain-source capacitance of transistor 140. According to an embodiment, the drain-source capacitance of transistor 140 can be less than about 0.2 pF / W. In addition, in some embodiments, transistor 140 can be a GaN FET, but in other embodiments, transistor 140 can be another type of III-V transistor (e.g., gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb)) or another type of transistor with relatively low drain-source capacitance.

[0090] As described above, the input impedance matching circuit 110, the harmonic termination circuit 130, and the baseband decoupling circuit 160 are electrically coupled between the input 102 and the first terminal 142 (e.g., the gate terminal) of the transistor 140. According to one embodiment, the first inductive element 112 (e.g., a first set of bond wires) is coupled between the input 102 and the input impedance matching circuit 110. More specifically, the first inductive element 112 is coupled between the input 102 and a first node 113 (also referred to as a "connection node") that substantially corresponds to the input of the input impedance matching circuit 110. In addition to functioning as an electrical connection between the input 102 and the input impedance matching circuit 110, the first inductive element 112 may also add reactance to the final transformed impedance provided by the input impedance matching circuit 110.

[0091] Input impedance matching circuit 110 is coupled between connection node 113 and control terminal 142 (e.g., gate terminal) of transistor 140. Input impedance matching circuit 110 is configured to transform (e.g., increase) the gate impedance of transistor 140 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range of about 2 ohms to about 10 ohms or higher) at node 102. This is advantageous because it allows a printed circuit board level (PCB level) matching interface from the driver stage to have an impedance that can be implemented with minimal losses and variations in high volume manufacturing (e.g., a "user-friendly" matching interface).

[0092] According to an embodiment, the input impedance matching circuit 110 has a two-stage bandpass filter configuration including a series inductive element 116, a series capacitor 120, a parallel inductive element 118, and a parallel capacitor 114. According to an embodiment, the series inductive element 116 and the parallel capacitor 114 form a low-pass filter of the bandpass filter configuration, and the parallel inductive element 118 and the series capacitor 120 form a high-pass filter of the bandpass filter configuration. The bandpass configuration allows for wideband operation at RF frequencies, which is not easily achievable using simpler matching networks.

[0093] A series capacitor 120 and a series inductor element 116 (e.g., a second set of bond wires) are coupled in series between the input 102 (or more specifically, the inductor 112 or the connection node 113) and the control terminal 142 of the transistor 140. More specifically, a first end of the series capacitor 120 is coupled to the first node 113, a second end of the series capacitor 120 is coupled to the second node 115 (also referred to as the “connection node”), and the series inductor element 116 is coupled between the second node 115 and the control terminal 142 of the transistor 140.

[0094] A shunt inductive element 118 is coupled between the first node 113 and ground (or another voltage reference). As will be described in more detail later, in embodiments where a DC gate bias is provided via the input 102 rather than via the gate terminal bias circuit 190 described below, a DC blocking capacitor 119 may be connected in series with the third inductive element 118. A first end of the shunt capacitor 114 is coupled to the second node 115, and a second end of the shunt capacitor 114 is coupled to ground (or another voltage reference).

[0095] According to an embodiment, the inductance value of the inductive element 112 may be in a range between about 150 picohenry (pH) and about 400 pH, the inductance value of the inductive element 116 may be in a range between about 80 pH and about 250 pH, the inductance value of the shunt inductor 118 may be in a range between about 100 pH and about 350 pH, the capacitance value of the series capacitor 120 may be in a range between about 25 picofarads (pF) and about 50 pF, and the capacitance value of the shunt capacitor 114 may be in a range between about 60 pF and about 200 pF. It is desirable that the shunt capacitor 114 has a relatively large capacitance (e.g., greater than about 60 pF) to provide an acceptable RF low impedance point at the node 115. In other embodiments, the component values ​​of some or all of the above components may be less than or greater than the ranges given above.

[0096] According to an embodiment, the harmonic termination circuit 130 is coupled between the control terminal 142 (e.g., the gate terminal) of the transistor 140 and ground (or another voltage reference). The harmonic termination circuit 130 includes an inductive element 132 (e.g., a third set of bond wires) and a capacitor 134 coupled in series between the control terminal 142 of the transistor 140 and ground (or another voltage reference), and this series element combination acts as a low impedance path to ground for signal energy at a harmonic frequency (e.g., the second harmonic of the operating fundamental frequency of the circuit 100). According to an embodiment, the inductance value of the inductive element 132 can be in a range between about 100pH and about 1nH, and the capacitance value of the capacitor 134 can be in a range between about 1pF and about 100pF, but the values ​​of these components can also be outside these ranges. For example, at an example operating fundamental frequency of 2.0 gigahertz (GHz) (whose second harmonic is 4.0GHz), the inductance value of the inductive element 132 can be about 120pH and the capacitance value of the capacitor 134 can be about 12pF. As will be explained later, the desired inductance and / or capacitance values ​​for achieving a low impedance path to ground for signal energy at the second harmonic frequency may be affected by the mutual coupling between the bond wires used to implement inductors 116 and 132 .

[0097] It is desirable that the shunt capacitor 114 has a relatively large capacitance (e.g., greater than about 60 pF) to provide an RF low impedance point at the node 115. In other words, the node 115 represents a low impedance point in the circuit for RF signals. According to an embodiment, a first (in-package) baseband decoupling (BBD) circuit 160 is coupled between the node 115 (e.g., at or at another RF low impedance point coupled to the node 115) and a ground reference node. The first baseband decoupling circuit 160 can be used to improve the low frequency resonance (LFR) of the circuit 100 caused by the interaction between the input matching circuit 110 and the bias feed (not shown) by presenting a low impedance at the envelope frequency and / or a high impedance at the RF frequency. From an RF matching perspective, the first baseband decoupling circuit 160 can be considered to be essentially "invisible" because it primarily implements impedance at the envelope frequency (i.e., the baseband decoupling circuit 160 provides a termination for the envelope frequency of the circuit 100). As will be discussed later in conjunction with Figures 2A-2F As discussed in more detail, in various embodiments, the first baseband decoupling circuit 160 may have any of a variety of different circuit configurations.

[0098] In an embodiment, amplifier circuit 100 may also include a gate-end bias circuit 190 coupled to node 115, which may function as a second (out-of-package) baseband decoupling circuit coupled substantially in parallel with first baseband decoupling circuit 160. A drain-end bias circuit (not shown) configured in a similar (or different) manner may be coupled to node 158. Bias circuit 190 includes a series-coupled inductive element 192 (e.g., Figure 5 One or more bonding wires 592; and Figure 4 192 and a bias lead 492 of the inductor 192 are coupled in series) and a capacitor 196, wherein an intermediate node 193 is located between the inductor / capacitor combination. According to an embodiment, the inductance value of the inductive element 192 can be in a range between about 1500pH and about 2500pH, and the capacitance value of the capacitor 196 can be in a range between about 8,000 nanofarads (nF) and about 12,000nF, but the inductance and / or capacitance values ​​can also be lower or higher.

[0099] To provide a gate bias voltage to gate terminal 142 of transistor 140, an external bias circuit (not shown) may be connected to node 193 (eg, a remote end of a bias lead) and a bias voltage may be provided through this node. A drain bias voltage may be provided to node 158 in a similar manner.

[0100] In other embodiments, either or both of the input side or output side bias circuits may not be included. In such embodiments, an external bias circuit may instead be connected to the input 102 or the output 104, and one or more bias voltages may be provided through the input 102 and / or the output 104. For example, in an embodiment where the gate bias is provided through the input 102, the circuit 100 also includes a resistor 122 coupled in parallel with the capacitor 120 between the nodes 113 and 115, and a DC blocking capacitor 119 connected in series with the inductor 118. When the resistor 122 and the DC blocking capacitor 119 are included, the resistor 122 and the DC blocking capacitor 119 are each configured to provide a high impedance at RF frequencies. According to an embodiment, the resistance value of the resistor 122 may be in the range of about 50 ohms to about 150 ohms, and the capacitance value of the DC blocking capacitor 119 may be in the range of about 50 pF to about 300 pF, but the resistance and capacitance values ​​of these components may also be lower or higher. Although Figure 1 The third inductive element 118 and the DC blocking capacitor 119 are shown in a particular series arrangement (e.g., the third inductive element 118 is directly connected to the node 113), but in other embodiments, the order of the third inductive element 118 and the DC blocking capacitor 119 may be reversed (e.g., the DC blocking capacitor 119 is directly connected to the node 113, as shown in FIG. Figure 5 Again, and as indicated by depicting resistor 122 and DC blocking capacitor 119 with dashed lines, resistor 122 and DC blocking capacitor 119 may be excluded from circuit 100 in embodiments where the gate bias voltage is provided by gate terminal bias circuit 190.

[0101] On the output side of circuit 100, output impedance matching circuit 150 is coupled between first current conducting terminal 144 (e.g., drain terminal) of transistor 140 and output 104. Output impedance matching circuit 150 is configured to match the output impedance of circuit 100 to the input impedance of an external circuit or component (not shown) that may be coupled to output 104. Output impedance matching circuit 150 may have any of a variety of different circuit configurations, and Figure 1 More specifically, in Figure 1In the non-limiting example shown, the output impedance matching circuit 150 includes two inductive elements 152, 154 and a shunt capacitor 156. The first inductive element 152 (e.g., a fourth set of bond wires) is coupled between a first current conducting terminal 144 (e.g., a drain terminal) of the transistor 140 and the output 104. In an embodiment, the second inductive element 154 (e.g., a fifth set of bond wires) is coupled between the first current conducting terminal 144 of the transistor 140 and a node 158, which corresponds to another RF low impedance point. In an embodiment, a second end of the shunt capacitor 156 is coupled to ground (or another voltage reference).

[0102] Again, the RF low impedance point 158 ​​represents a low impedance point in the circuit for RF signals. According to an embodiment, another baseband decoupling circuit 162 is coupled between the RF low impedance point 158 ​​and the ground reference node. Again, the baseband decoupling circuit 162 can be used to further improve the LFR of the circuit 100 caused by the interaction between the output impedance matching circuit 150 and the bias feed (not shown) by presenting a low impedance at the envelope frequency and / or a high impedance at the RF frequency. From the perspective of RF matching, the baseband decoupling circuit 162 can also be regarded as "invisible".

[0103] If we now combine Figures 2A-2F As described, in various embodiments, the baseband decoupling circuits 160, 162 may have any of a variety of different circuit configurations. For example, Figures 2A-2F Baseband decoupling circuits (eg, Figure 1 Six example embodiments of baseband decoupling circuits 160, 162) are provided. Figures 2A-2F In each of the baseband decoupling circuits 200, 201, 202, 203, 204, 205, a baseband decoupling circuit 200, 201, 202, 203, 204, 205 is coupled to a connection node 215 (eg, Figure 1 In addition, each baseband decoupling circuit 200-205 includes an envelope inductor 262L coupled in series between the connection node 215 and the ground. en v. Envelope resistor 264R env and envelope capacitor 266C env .exist Figure 2A-2E In each of the above, a first end of envelope inductor 262 is coupled to node 215, and a second end of envelope inductor 262 is coupled to node 280. A first end of envelope resistor 264 is coupled to node 280, and a second end of envelope resistor 264 is coupled to node 282. A first end of envelope capacitor 266 is coupled to node 282, and a second end of envelope capacitor 266 is coupled to ground (or another voltage reference). Figure 2A-2EIn FIG. 1 , the order of the series components between node 215 and the ground reference node is envelope inductor 262, envelope resistor 264, and envelope capacitor 266, but in other embodiments, the order of the components in the series circuit may be different. For example, in Figure 2F , envelope resistor 264 is coupled between node 215 and node 284, envelope inductor 262 is coupled between node 284 and node 286, and envelope capacitor 266 is coupled between node 286 and ground (or another voltage reference).

[0104] refer to Figures 2A-2F And according to an embodiment, the envelope inductor 262 may be implemented as an integrated inductor (eg, Figure 5 The inductor 562 of FIG. 21 is implemented as a discrete inductor and / or as a set of bond wires that couple the connection node 215 to the envelope resistor 264 (e.g., through the node 280). For example, and as will be described in detail later, the envelope inductor 262 can be integrally formed as an integrated passive device (IPD) (e.g., Figure 4-6 483). For example, the inductance value of envelope inductance 262 can be in the range of about 5 pH to about 2000 pH. It is desirable that the inductance value of envelope inductance 262 is less than about 500 pH (e.g., in an embodiment, as low as 50 pH or possibly even lower). In other embodiments, the value of envelope inductance 262 can be lower or higher than the ranges given above.

[0105] In an embodiment, the envelope resistor 264 may be implemented as an integrated resistor (eg, Figure 5 The envelope resistor 264 may be formed as an IPD (eg, a resistor 564 of FIG. 1 ) or, in another embodiment, may be implemented as a discrete resistor. Figure 4-6 In some examples, envelope capacitor 266 and envelope inductor 262 may provide additional parasitic resistance that may be considered to form part of the overall resistance of envelope resistor 264. In an embodiment, the resistance value of envelope resistor 264 may be in a range between about 0.1 ohms and about 5.0 ohms, although the resistance value of envelope resistor 264 may be outside of this range.

[0106] In an embodiment, envelope capacitor 266 may be implemented as an integrated capacitor (eg, Figure 5 The envelope capacitor 266 may be formed as an IPD (e.g., a chip capacitor). Figure 4-6In an embodiment, the capacitance value of the envelope capacitor 266 may be in a range between about 1 nF and about 1 microfarad (μF), but the capacitance value of the envelope capacitor 266 may also be outside this range.

[0107] Figure 2A The first embodiment of the baseband decoupling circuit 200 shown in FIG. 1 includes a simple series combination of an envelope inductor 262, an envelope resistor 264, and an envelope capacitor 266. In contrast, in Figure 2B-2F In the embodiment of the present invention, the baseband decoupling circuits 201-205 may include one or more "bypass" or "shunt" capacitors 268, 270, 272, 274, 276, 278C. para , the capacitor is coupled in parallel with the envelope inductor 262 and / or the envelope resistor 264. In some embodiments, each of the bypass capacitors 268, 270, 272, 274, 276, 278 can be implemented as a discrete capacitor (e.g., Figure 5 , 6 578) or in other embodiments, is implemented as an integrated capacitor. In each of these embodiments, the capacitance value of bypass capacitors 268, 270, 272, 274, 276, 278 can be in the range of about 3.0 pF to about 1400 pF. In other embodiments, the value of any one of bypass capacitors 268, 270, 272, 274, 276, 278 can be lower or higher than the range given above.

[0108] exist Figure 2B In the baseband decoupling circuit 201, the bypass capacitor 268C para 215 and is coupled in parallel with envelope inductor 262. More specifically, envelope inductor 262 and a first end of bypass capacitor 268 are coupled to node 215, and envelope inductor 262 and a second end of bypass capacitor 268 are coupled to node 280.

[0109] exist Figure 2C In the baseband decoupling circuit 202, the bypass capacitor 270C para 2 and is coupled in parallel with envelope resistor 264. More specifically, envelope resistor 264 and a first end of bypass capacitor 270 are coupled to node 280, and envelope resistor 264 and a second end of bypass capacitor 270 are coupled to node 282.

[0110] exist Figure 2D In the baseband decoupling circuit 203, the bypass capacitor 272C para Coupled in parallel with envelope inductor 262 and envelope resistor 264. More specifically, bypass capacitor 272 is coupled across nodes 215 and 282.

[0111] exist Figure 2E In the baseband decoupling circuit 204, the first bypass capacitor 274C paral coupled in parallel with the envelope inductor 262, and the second bypass capacitor 276C para2 215 and is coupled in parallel with envelope resistor 264. More specifically, envelope inductor 262 and a first end of first bypass capacitor 274 are coupled to node 215, and second ends of envelope inductor 262 and first bypass capacitor 274 are coupled to node 280. Additionally, envelope resistor 264 and a first end of second bypass capacitor 276 are coupled to node 280, and second ends of envelope resistor 264 and second bypass capacitor 276 are coupled to node 282.

[0112] refer to Figure 2B , 2E The baseband decoupling circuits 201, 204 and 205 of 2F, the parallel coupled inductor 262 and capacitors 268, 274 or 278 form a parallel resonant circuit with a frequency close to the center operating frequency of the device or circuit (e.g., circuit 100) to which the circuits 201, 204 or 205 are combined. As used herein and according to an embodiment, the term "close to the center operating frequency" means "within 20% of the center operating frequency." Thus, for example, when the center operating frequency of the device is 2.0 gigahertz (GHz), the frequency "close to the center operating frequency" corresponds to a frequency falling within the range of 1.8 GHz to 2.2 GHz. Although 2.0 GHz is given as an example center operating frequency, the center operating frequency of the device may also be different from 2.0 GHz. In alternative embodiments, the term "close to the center operating frequency" may mean "within 10% of the center operating frequency" or "within 5% of the center operating frequency."

[0113] Due to L env / / C para A parallel resonant circuit with a frequency close to the center operating frequency of the device is formed, so the parallel resonant circuit L env / / C para It behaves essentially as an open circuit for this frequency. Therefore, RF energy near the center operating frequency that may be present at node 215 coupled to circuits 201, 204, or 205 will pass through parallel resonant circuit L env / / C para This deflection can be provided even with relatively low inductance values ​​for inductor 262. For these reasons, circuits 201, 204, and 205 can significantly improve the LFR of a device or circuit (e.g., circuit 100) into which they are incorporated by presenting low impedance at envelope frequencies and high impedance at RF frequencies.

[0114] exist Figure 2C , 2DIn each of the embodiments of the baseband decoupling circuits 202, 203, 204 of 200 and 2E, a bypass capacitor 270, 272, or 276 is coupled in parallel with the envelope resistor 264. Because the capacitor 270, 272, or 276 can be used to route the RF current around the envelope resistor 264, the circuits 202, 203, 204 can result in a reduction in the RF current dissipated by the envelope resistor 264. This feature of the circuits 202, 203, 204 can also be used to better protect the envelope resistor 264 from potential damage due to excess current that might otherwise flow through the envelope resistor 264 in the absence of the bypass capacitors 270, 272, or 276.

[0115] Each of circuits 201-205 can improve device efficiency when compared to circuit 200 because the circuits 201-205 allow less RF current to flow through (and be dissipated by) envelope resistor 264. Additionally, since circuits 201-205 present a high impedance to RF frequencies near the center operating frequency of the device into which the baseband decoupling circuits are incorporated, connecting circuits 201-205 to an RF low impedance point (e.g., Figure 1 The RF low impedance point 115 or 158) is not important, but the circuits 201-205 can be connected to the RF low impedance point. Conversely, the benefits of the circuits 201-205 can be achieved even when the circuits 201-205 are coupled to nodes that exhibit higher RF impedance. This situation includes other nodes in the input impedance matching circuit and the output impedance matching circuit.

[0116] Refer again Figure 1 And as will be combined later Figure 4-6 As described in more detail, various embodiments of the RF amplifier device may include at least one input-side integrated passive device (IPD) assembly (e.g., Figure 4-6 IPD assemblies 480, 481) and at least one output-side IPD assembly (eg, Figure 4 The one or more input-side IPD assemblies (e.g., IPD assemblies 480, 481) include portions of the input circuit 110, the harmonic termination circuit 130, and the baseband decoupling circuit 160. Similarly, the one or more output-side IPD assemblies (e.g., IPD assemblies 482, 483) include portions of the output circuit 150 and the baseband decoupling circuit 162. More specifically, each IPD assembly may include a semiconductor substrate having one or more integrated passive components. In a particular embodiment, each input-side IPD assembly may include parallel capacitors 114 and 134 and portions of the baseband decoupling circuit 160 (e.g., Figures 2A-2FIn other specific embodiments, each output-side IPD assembly may include a parallel capacitor 156 and a component of the baseband decoupling circuit 162 (e.g., Figures 2A-2F Components 262, 264, 266, 268, 270, 272, 274, 276, 278).

[0117] In other embodiments, some portions of the input impedance matching circuit 110 and the output impedance matching circuit 150 and the baseband decoupling circuits 160, 162 may be implemented as different / discrete components or as parts of other types of assemblies (e.g., low temperature co-fired ceramic (LTCC) devices, small PCB assemblies, etc.). In still other embodiments, some portions of the input impedance matching circuit 110 and / or the output impedance matching circuit 150 may be coupled to and / or integrated within a semiconductor die including the transistor 140. The following detailed description of embodiments including an IPD assembly should not be considered to limit the subject matter of the present invention, and the term "passive device substrate" or "IPD substrate" means any type of structure including a passive device, including an IPD, an LTCC device, a transistor die, a PCB assembly, etc.

[0118] Figure 1 The RF amplifier circuit 100 may be used as a single path amplifier that receives an RF signal at an input 102, amplifies the signal through a transistor 140, and produces an amplified RF signal at an output 104. Alternatively, multiple instances of the RF amplifier circuit 100 may be used to provide a multipath amplifier such as a Doherty power amplifier or another type of multipath amplifier circuit.

[0119] For example, Figure 3 is a simplified schematic diagram of a Doherty power amplifier 300 in which an embodiment of the RF power amplifier circuit 100 may be implemented. The amplifier 300 includes an input node 302, an output node 304, a power divider 306 (or splitter), a main amplifier path 320, a peaking amplifier path 321, and a combining node 380. A load 390 may be coupled to the combining node 380 (e.g., via an impedance transformer, not shown) to receive an amplified RF signal from the amplifier 300.

[0120] The power divider 306 is configured to split the power of the input RF signal received at the input node 302 into a main portion and a peaking portion of the input signal. The main input signal is provided to the main amplifier path 320 at the power divider output 308, and the peaking input signal is provided to the peaking amplifier path 321 at the power divider output 309. During operation in a full power mode in which both the main amplifier 340 and the peaking amplifier 341 supply current to the load 390, the power divider 306 divides the input signal power between the amplifier paths 320, 321. For example, the power divider 306 can divide the power equally so that approximately half of the input signal power is provided to each path 320, 321 (e.g., for a symmetric Doherty amplifier configuration). Alternatively, the power divider 306 can divide the power unequally (e.g., for an asymmetric Doherty amplifier configuration).

[0121] Essentially, the power divider 306 divides the input RF signal supplied at the input node 302, and the divided signals are amplified along the main amplifier path 320 and the peaking amplifier path 321, respectively. The amplified signals are then combined in phase at the combining node 380. Importantly, phase consistency between the main amplifier path 320 and the peaking amplifier path 321 is maintained across the frequency band of interest to ensure that the amplified main and peaking signals arrive at the combining node 380 in phase and therefore ensure proper Doherty amplifier operation.

[0122] Each of the main amplifier 340 and the peaking amplifier 341 includes one or more single-stage power transistor integrated circuits (ICs) or multi-stage power transistor ICs (or power transistor dies) for amplifying the RF signal conducted through the amplifiers 340, 341. According to various embodiments, all amplifier stages or the final amplifier stage of either or both of the main amplifier 340 and / or the peaking amplifier 341 may be implemented, for example, using III-V field effect transistors (e.g., HEMTs) such as GaN FETs (or another type of III-V transistors, including GaAsFETs, GaP FETs, InP FETs, or InSb FETs). In some embodiments, where only one of the main amplifier 340 or the peaking amplifier 341 is implemented as a III-V FET, the other amplifier may be implemented as a silicon-based FET (e.g., an LDMOS FET).

[0123] Although the main power transistor IC and the peaking power transistor IC can have the same size (e.g., in a symmetric Doherty configuration), the main power transistor IC and the peaking power transistor IC can also have unequal sizes (e.g., in various asymmetric Doherty configurations). In an asymmetric Doherty configuration, one or more peaking power transistor ICs are typically larger than one or more main power transistor ICs by a certain multiplier. For example, the one or more peaking power transistor ICs can be twice the size of the one or more main power transistor ICs, so that the one or more peaking power transistor ICs have twice the current carrying capacity of the one or more main power transistor ICs. Peaking amplifier IC-main amplifier IC size ratios other than a 2:1 ratio can also be implemented.

[0124] During operation of the Doherty amplifier 300, the main amplifier 340 is biased to operate in the class AB mode and the peaking amplifier 341 is biased to operate in the class C mode. At low power levels where the power of the input signal at node 302 is below the turn-on threshold level of the peaking amplifier 341, the amplifier 300 operates in a low power (or back-off) mode in which the main amplifier 340 is the only amplifier supplying current to the load 390. When the power of the input signal exceeds the threshold level of the peaking amplifier 341, the amplifier 300 operates in a high power mode in which both the main amplifier 340 and the peaking amplifier 341 supply current to the load 390. At this point, the peaking amplifier 341 provides active load modulation at the combining node 380, thereby allowing the current of the main amplifier 340 to continue to increase linearly.

[0125] The input impedance matching network 310 and the output impedance matching network 350 (input MNm, output MNm) can be implemented at the input and / or output of the main amplifier 340. Similarly, the input impedance matching network 311 and the output impedance matching network 351 (input MNp, output MNp) can be implemented at the input and / or output of the peaking amplifier 341. In each case, the matching networks 310, 311, 350, 351 can be used to transform the gate impedance and drain impedance of the main amplifier 340 and the peaking amplifier 341 into more desirable system-level impedances and manipulate the signal phase to ensure proper Doherty amplifier operation. All or part of the input impedance matching network 310, 311 and the output impedance matching network 350, 351 can be implemented in a power transistor package including the main amplifier 340 and / or the peaking amplifier 341, or some parts of the input impedance matching network 310, 311 and the output impedance matching network 350, 351 can be implemented on a PCB or other substrate on which the power transistor package is mounted.

[0126] In addition, as will be described in detail later, embodiments of the inventive subject matter include harmonic frequency termination circuits 330, 331 coupled between the inputs of the amplifiers 340, 341 and a ground reference. The harmonic frequency termination circuits 330, 331 are configured to control harmonic impedance across a relatively wide fractional bandwidth. For example, the harmonic frequency termination circuits 330, 331 can provide a low impedance path to ground for signal energy at the second harmonic of the center operating frequency fo (also referred to herein as the "operating fundamental frequency") of the amplifier 300.

[0127] The Doherty amplifier 300 has a "non-inverting" load network configuration. In the non-inverting configuration, the input circuit is configured such that the input signal supplied to the peaking amplifier 341 is delayed by 90 degrees relative to the input signal supplied to the main amplifier 340 at the center operating frequency fo of the amplifier 300. To ensure that the main input RF signal and the peaking input RF signal arrive at the main amplifier 340 and the peaking amplifier 341 with a phase difference of approximately 90 degrees, as is essential for proper Doherty amplifier operation, the phase delay element 382 applies a phase delay of approximately 90 degrees to the peaking input signal. For example, the phase delay element 382 may include a quarter wave transmission line or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0128] In order to compensate for the resulting 90 degree phase delay difference between the main amplifier path 320 and the peaking amplifier path 321 at the inputs of the amplifiers 340, 341 (i.e., to ensure that the amplified signals arrive at the combining node 380 in phase), the output circuit is configured to apply a phase delay of approximately 90 degrees to the signal between the output of the main amplifier 340 and the combining node 380. This is achieved by an additional delay element 384. An alternative embodiment of the Doherty amplifier may have an "inverting" load network configuration. In this configuration, the input circuit is configured such that the input signal supplied to the main amplifier 340 is delayed by approximately 90 degrees relative to the input signal supplied to the peaking amplifier 341 at the center operating frequency fo of the amplifier 300, and the output circuit is configured to apply a phase delay of approximately 90 degrees to the signal between the output of the peaking amplifier 341 and the combining node 380.

[0129] The amplifiers 340 and 341, along with the harmonic frequency termination circuits 330, 331 and portions of the matching networks 310, 311, 350, 351, may be implemented in a discrete packaged power amplifier device. In such a device, the input leads and output leads are coupled to a substrate, and each amplifier 340, 341 may include a single-stage power transistor or multiple-stage power transistors that are also coupled to the substrate. The harmonic frequency termination circuits 330, 331 and portions of the input matching networks 310, 311 and the output matching networks 350, 351 may be implemented as additional components within the packaged device. Additionally, as described in detail below, baseband decoupling circuits (e.g., in Figures 2A-2F As shown in Figure 1 Embodiments of the VBW circuits 160, 162) may also be implemented as additional components within the packaged device.

[0130] For example, Figure 4 is a top view of an embodiment of a packaged RF amplifier device 400, which embodies Figure 1 Two parallel instances of the circuit 100 can be used to provide a Doherty amplifier (e.g., Figure 3 Doherty amplifier 300) in an amplifier (e.g., Figure 3 amplifiers 340, 341) and portions of the matching network (e.g., Figure 3 310, 311, 350, 351). In addition, as will be described in more detail below, the device 400 includes two input-side IPD assemblies 480, 481, each of which includes an input impedance matching circuit 410, 411 (e.g., Figure 1 , 3 circuits 110, 310, 311), baseband decoupling circuits 460, 461 (for example, Figure 1 circuit 160) and harmonic termination circuits 430, 431 (e.g., Figure 1 , 3 In addition, the device 400 includes two output-side IPD assemblies 482, 483, each of which includes an output impedance matching circuit 450, 451 (e.g., Figure 1 , 3 circuits 150, 350, 351) and baseband decoupling circuits 462, 463 (e.g., Figure 1 Part of the circuit 162).

[0131] In an embodiment, the device 400 includes a flange 406 (or "device substrate") that includes a rigid conductive substrate having a thickness sufficient to provide structural support for the various electrical components and elements of the device 400. In addition, the flange 406 can act as a heat sink for the transistor dies 440, 441 and other devices mounted on the flange 406. The flange 406 has a top surface and a bottom surface ( Figure 4 Only a central portion of the top surface is visible in the figure) and a generally rectangular perimeter corresponding to the perimeter of device 400.

[0132] Flange 406 is formed of a conductive material and can be used to provide a ground reference node for device 400. For example, various components and elements can have ends electrically coupled to flange 406, and when device 400 is incorporated into a larger electrical system, flange 406 can be electrically coupled to system ground. At least the top surface of flange 406 is formed of a layer of conductive material, and possibly the entire flange 406 is formed of a bulk conductive material.

[0133] In an embodiment, isolation structure 408 is attached to the top surface of flange 406. Isolation structure 408, formed of a rigid electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads 402-405, 492-495 and flange 406). In an embodiment, isolation structure 408 has a frame shape comprising a substantially closed four-sided structure with a central opening. Figure 4 As shown, isolation structure 408 may have a substantially rectangular shape, or isolation structure 408 may have another shape (eg, annular, oval, etc.).

[0134] The portion of the top surface of the flange 406 exposed by the opening in the isolation structure 408 is referred to herein as the "active area" of the device 400. The transistor dies 440, 441 along with the IPD assemblies 480, 481, 482, 483 are positioned within the active device area of ​​the device 400, as will be described in more detail later. For example, the transistor dies 440, 441 and the IPD assemblies 480-483 may be coupled to the top surface of the flange 406 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic bonding.

[0135] The device 400 accommodates two amplification paths (indicated by arrows 420, 421), wherein each amplification path 420, 421 represents the circuit 100 ( Figure 1 ). When combined into a Doherty amplifier (e.g. Figure 3 ), the amplification path 420 may correspond to the main amplifier path (eg, Figure 3 The main amplifier path 320 of FIG. 1 ), and the amplifier path 421 may correspond to a peaking amplifier path (eg, Figure 3 In some instances, the order may be switched, where amplification path 420 may correspond to the peaking amplifier path and amplification path 421 may correspond to the main amplifier path.

[0136] Each path 420, 421 includes an input lead 402, 403 (e.g., Figure 1 Input 102), output leads 404, 405 (e.g., Figure 1 output 104), one or more transistor dies 440, 441 (e.g., Figure 1 The transistor 140 or Figure 3 amplifiers 340, 341), input impedance matching circuits 410, 411 (e.g., Figure 1 The input impedance matching circuit 110 or Figure 3 , input matching networks 310, 311), output impedance matching circuits 450, 451 (e.g., Figure 1 The output impedance matching circuit 150 or Figure 3 output matching network 350, 351), input-side baseband decoupling circuit 460, 461 (for example, Figure 1 Baseband decoupling circuit 160), output side baseband decoupling circuit 462, 463 (for example, Figure 1 Baseband decoupling circuit 162), input side harmonic terminal circuit 430, 431 (for example, Figure 1 , 3 Some embodiments may also have an output-side harmonic termination circuit (not shown).

[0137] The input and output leads 402-405 are mounted on the top surface of the isolation structure 408, on opposite sides of the central opening, and thus the input and output leads 402-405 are elevated above the top surface of the flange 406 and are electrically isolated from the flange 406. Typically, the input and output leads 402-405 are oriented to allow for the attachment of bond wires between the input and output leads 402-405 and components and elements within the central opening of the isolation structure 408.

[0138] Each transistor die 440, 441 includes an integrated power FET, wherein each FET has a control terminal (e.g., a gate terminal) and two current conducting terminals (e.g., a drain terminal and a source terminal). The control terminal of the FET within each transistor die 440, 441 is coupled to the input leads 402, 403 through the input impedance matching circuit 410, 411. In addition, one current conducting terminal (e.g., the drain terminal) of the FET within each transistor die 440, 441 is coupled to the output leads 404, 405 through the output impedance matching circuit 450, 451. In an embodiment, the other current conducting terminal (e.g., the source terminal) of the FET within each transistor die 440, 441 is electrically coupled to the flange 406 (e.g., to ground) through the die 440, 441.

[0139] Will be combined later Figure 5 and 6 Describing embodiments of input impedance matching circuits 410, 411, baseband decoupling circuits 460, 461, and harmonic termination circuits 430, 431 in more detail, Figure 5 and 6 The components of these circuits 410, 411, 430, 431, 460, 461 are shown in more detail. Figure 5 and 6 As illustrated, some of the components of these circuits may be implemented within the IPD assemblies 480, 481. Briefly, each input impedance matching circuit 410, 411 is coupled between an input lead 402, 403 and a control terminal of a FET within a transistor die 440, 441. Each input-side baseband decoupling circuit 460, 461 is coupled between a node 415, 416 (e.g., a conductive bond pad) within the IPD assemblies 480, 481 and a ground reference (e.g., flange 406). Each harmonic termination circuit 430, 431 is coupled between a control terminal (e.g., a gate terminal) of a FET within a transistor die 440, 441 and a ground reference (e.g., flange 406).

[0140] Some of the components of the output impedance matching circuits 450, 451 and the baseband decoupling circuits 462, 463 may be implemented within the IPD assemblies 482, 483. Briefly, each output impedance matching circuit 450, 451 is coupled between a current conducting end (e.g., drain end) of a FET within the transistor die 440, 441 and the output lead 404, 405. Each baseband decoupling circuit 462, 463 is coupled between a node 458, 459 (e.g., an RF low impedance point in the form of a conductive bond pad) within the IPD assemblies 482, 483 and a ground reference (e.g., flange 406).

[0141] In addition to the input and output leads 402-405, the device 400 may also include bias circuitry (e.g., including Figure 1 The bias circuit 190). Figure 4 In an embodiment, each of the bias circuits includes an inductive element (e.g., Figure 1 192), and each of the input side (gate) bias circuits further includes capacitors 496, 497 (e.g., Figure 1 For example, each capacitor 496, 497 may be a discrete capacitor having a first end coupled to the bias leads 492, 493 and a second end coupled to a ground reference node (e.g., on a PCB to which the device 400 is connected).

[0142] The inductive element of each bias circuit may include, for example, bias leads 492, 493, 494, 495 and one or more bond wires (e.g., bonding wires) coupling each bias lead 492-495 to a control terminal (e.g., gate terminal) or a current conducting terminal (e.g., drain terminal) of a FET within each transistor die 440, 441. Figure 5 The remote end of each bias lead 492-495 can be electrically coupled to an external bias circuit (not shown) that provides a bias voltage to the control terminal or current conduction terminal of each FET through the bias leads 492-495. When the gate bias voltage is provided through the gate leads 492, 493, the resistor 522 described below (for example, Figure 1 resistor 122) and capacitor 519 (e.g., Figure 1 405). In other embodiments, either or both of the input side or output side bias circuits may not be included. In such embodiments, external bias circuits may instead be connected to the input leads 402, 403 or the output leads 404, 405, and one or more bias voltages may be provided via the input leads 402, 403 and / or the output leads 404, 405.

[0143] exist Figure 4 In the example of the embodiment of the present invention, the device 400 includes two transistor dies 440, 441 that work substantially in parallel, but another semiconductor device may also include a single transistor die or more than two transistor dies. In addition, the device 400 includes two input-side IPD assemblies 480, 481 and two output-side IPD assemblies 482, 483 that also work substantially in parallel. It should be understood that more or fewer IPD assemblies 480-483 may also be implemented.

[0144] According to an embodiment, the device 400 is incorporated in an air cavity package, wherein the transistor dies 440, 441, the IPD assembly 480-483 and various other components are positioned within an enclosed air cavity. Basically, the air cavity is defined by the flange 406, the isolation structure 408 and a cap (not shown) covering and contacting the isolation structure 408 and the leads 402-405, 492-495. Figure 4 4, an example inner perimeter of the cap is indicated by a dashed box 409, while the outer perimeter will be generally aligned with the outer perimeter of the flange 406. In other embodiments, the components of the device 400 may be incorporated into an overmolded package (i.e., a package in which the electrical components within the active device area are encapsulated with a non-conductive mold compound and portions of the leads 402-405, 492-495 may also be surrounded by the mold compound). In an overmolded package, the isolation structure 408 may not be included.

[0145] Now, referring to the apparatus 400 ( Figure 4 ) of a portion of the enlarged view Figure 5 and 6 , the portion includes an embodiment of an input impedance matching circuit 410, a baseband decoupling circuit 460 and a harmonic termination circuit 430. More specifically, Figure 5 FIG. 4 is a top view of the lower left input side portion 500 of the packaged RF power amplifier device 400 along the amplifier path 420. The portion 500 ( Figure 5 ) includes a portion of the power transistor die 440, a portion of the input lead 402, and an input side IPD assembly 480. To enhance understanding, Figure 6 Including a section taken along line 6-6 according to an exemplary embodiment Figure 5 500 is a cross-sectional side view of a portion of an RF power amplifier device. More specifically, Figure 6 is a cross-sectional view through input lead 402, IPD assembly 480, a portion of flange 406, and transistor die 440. Figure 6 As shown, the power transistor die 440 and the IPD assembly 480 are coupled to the conductive flange 406, and the input lead 402 is electrically isolated from the conductive flange 406 (e.g., using the isolation structure 408). It should be noted that the input side portion of the device 400 along the amplifier path 421 can be connected to the conductive flange 406. Figure 5 and 6 The portion 500 shown in FIG. 5 is substantially the same.

[0146] The power transistor die 440 includes a transistor input terminal 542 (e.g., a conductive bonding pad) that is electrically connected within the power transistor die 440 to a control terminal (e.g., a gate terminal) of a single or final stage FET 630 integrated within the die 440. As previously discussed, each FET 630 may include a III-V field effect transistor (e.g., a HEMT) such as a GaN FET (or another type of III-V transistor, including a GaAs FET, a GaP FET, an InP FET, or an InSb FET). More specifically, each FET 630 may be integrally formed in and on a base semiconductor substrate 632 (e.g., a GaN substrate, a GaN-on-silicon substrate, a GaN-on-silicon carbide substrate, etc.). The conductive connection between the control terminal (e.g., the gate terminal) of the FET 630 and the input terminal 542 of the die 440 may be formed by a stacked structure 634 of alternating dielectric layers and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. Conductive layer 636 on the bottom surface of die 440 may provide a ground node (eg, a source terminal, which may be connected to conductive layer 636 (and thus conductive flange 406) using a substrate through-via or a doped sinker region (not shown)).

[0147] The IPD assembly 480 may also include a base semiconductor substrate 682 (e.g., a silicon substrate, a silicon carbide substrate, a GaN substrate, or another type of semiconductor substrate, which may be referred to herein as an "IPD substrate") and a stacked structure 684 of alternating dielectric layers and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, various electrical components of the input impedance matching circuit 410, the baseband decoupling circuit 460, and the harmonic termination circuit 430 are integrally formed within and / or connected to the IPD assembly 480. These electrical components may be electrically connected to conductive bonding pads (e.g., bonding pads 415, 513, 533) at the top surface of the IPD assembly 480, and may also be electrically connected to the conductive flange 406 (e.g., to ground) using substrate vias to a conductive layer 686 on the bottom surface of the IPD assembly 480.

[0148] First, the connection between the transistor die 440 and the input lead 402 through the input impedance matching circuit 410 will be described in more detail. More specifically, the input lead 402 is coupled to the input terminal 542 of the transistor die 440 through an instance of the input impedance matching circuit 410. The input terminal 542 is in turn electrically coupled to the control terminal (e.g., gate terminal) of the FET within the transistor die 440.

[0149] For example, in an embodiment, the input impedance matching circuit 410 may include three inductive elements 512, 516, 518 (eg, Figure 1 Inductive elements 112, 116, 118), a series capacitor 520 (e.g., Figure 1 The series capacitor 120) and the parallel capacitor 514 (e.g., Figure 1 The first inductor element 512 (eg, Figure 1 The inductive element 112 of the embodiment may be implemented as a conductive bonding pad 513 (eg, corresponding to the conductive bonding pad 513) coupled to the input lead 402 and the top surface of the IPD assembly 480. Figure 1 The first set of bonding wires between the connection nodes 113 of the first inductor element 516 (eg, Figure 1 The inductor element 116) may be implemented as a bonding pad 415 (corresponding to Figure 1 A second set of bonding wires between the connection node 115 of the transistor die 440 and the input terminal 542 of the transistor die 440. Figure 5 To avoid confusion, only one of the bond wires in the group of bond wires that comprise the inductor element 516 is circled and numbered with reference numeral 516. It should be understood that the inductor element 516 includes all bond wires that are coupled between the bonding pad 415 and the input terminal 542. Finally, the third inductor element 518 (e.g., Figure 1 The inductive element 118) can be implemented as one or more transmission line segments (e.g., coils, as shown) that are integrally formed as part of the IPD assembly 480 and electrically coupled between the bonding pad 513 and a ground reference (e.g., flange 406).

[0150] In the illustrated embodiment, the DC blocking capacitor 519 (e.g., Figure 1 A DC blocking capacitor 119) is coupled between the bonding pad 513 and the third inductive element 518. However, as previously described, when the gate bias voltage is provided by a separate gate bias circuit (e.g., by gate leads 492 and 493), the DC blocking capacitor 519 can be excluded. When the DC blocking capacitor 519 is included, the DC blocking capacitor 519 can be implemented as a metal-insulator-metal (MIM) capacitor (or a plurality of parallel-coupled MIM capacitors) that is integrally formed as part of the IPD assembly 480, wherein the MIM capacitor includes a first conductive electrode and a second conductive electrode (formed by a patterned portion of a conductive layer of the buildup structure 684) that are aligned with each other and electrically separated by a dielectric material of the buildup structure 684. Alternatively, the DC blocking capacitor 519 can be implemented as one or more discrete capacitors ("chip capacitors") connected to the top surface of the IPD assembly 480.

[0151] A series capacitor 520 (eg, Figure 1The first end of the series capacitor 120 is directly or indirectly coupled to the bonding pad 513 (corresponding to Figure 1 113), and the second end of the series capacitor 520 is directly or indirectly coupled to the conductive bonding pad 415 (corresponding to Figure 1 A series capacitor 520 (e.g., Figure 1 The series capacitor 120) can be implemented as a discrete capacitor (a plurality of discrete capacitors coupled in parallel, such as Figure 4 Alternatively, series capacitor 520 may be implemented as a MIM capacitor (or a plurality of parallel coupled MIM capacitors) that is integrally formed as part of IPD assembly 480.

[0152] In the illustrated embodiment, one or more resistors 522 (e.g., Figure 1 4 and 5. In some embodiments, the first embodiment of the present invention relates to a first gate biasing device 480 that is provided by a gate biasing circuit 492 (e.g., via gate leads 492 and 493) and a second gate biasing device 480 that is provided by a gate biasing circuit 492 (e.g., via gate leads 492 and 493) that is coupled in parallel with one or more capacitors 520. However, as previously described, when the gate bias voltage is provided by a separate gate biasing circuit (e.g., via gate leads 492 and 493), resistor 522 may be excluded. According to an embodiment, when resistors 522 are included, each resistor 522 may be integrally formed as part of IPD assembly 480. For example, each resistor 522 may be a polysilicon resistor formed by a polysilicon layer on or within buildup structure 684.

[0153] According to an embodiment, the parallel capacitor 514 (eg, Figure 1 A first electrode (or end) of the shunt capacitor 114) is electrically coupled to the conductive bonding pad 415 (and thus to one or more capacitors 520 and bonding wires 516), and a second electrode (or end) of the shunt capacitor 514 is electrically coupled to the conductive flange (e.g., using a conductive substrate via extending through the semiconductor substrate 682). The shunt capacitor 514 can be implemented as a MIM capacitor (or a group of parallel-coupled MIM capacitors) that is integrally formed as part of the IPD assembly 480. In a more specific embodiment, the first electrode of the shunt capacitor 514 is "directly connected" to the bonding pad 415, where "directly connected" means electrically connected, possibly with one or more conductive traces and / or conductive vias, without the use of intervening circuit elements (i.e., circuit elements having more than one trace inductance, where a "trace inductance" is an inductance of less than about 100 pH). Because shunt capacitor 514 and bond pad 415 are "directly connected," and bond pad 415 also has only one trace inductance, in embodiments, bond wire 516 and shunt capacitor 514 may also be considered "directly connected." In alternative embodiments, shunt capacitor 514 may be implemented using one or more discrete capacitors coupled to the top surface of IPD assembly 480 or using another type of capacitor.

[0154] According to an embodiment, the inductance value of the bonding wire 512 may be in a range between about 150 pH and about 400 pH, the inductance value of the bonding wire 516 may be in a range between about 80 pH and about 250 pH, the inductance value of the shunt inductor 518 may be in a range between about 100 pH and about 350 pH, the capacitance value of the series capacitor 520 may be in a range between about 25 pF and about 50 pF, the resistance value of the resistor 522 may be in a range between about 50 ohms and about 150 ohms, and the capacitance value of the shunt capacitor 514 may be in a range between about 60 pF and about 200 pF. The capacitance value of the DC blocking capacitor 519 may be in a range between about 50 pF and about 300 pF. In other embodiments, the component values ​​of some or all of the above components may be less than or greater than the ranges given above.

[0155] As mentioned above, in an embodiment, the baseband decoupling circuit 460 is included in the input-side IPD assembly 480. In various embodiments, each baseband decoupling circuit 460 can have any of a variety of configurations, such as but not limited to Figures 2A-2F One of the configurations shown in . Figure 5 and 6 The corresponding Figure 2F In an embodiment of the baseband decoupling circuit 205, the baseband decoupling circuit 460 includes a circuit electrically connected to the node 415 (eg, Figure 1 , 2F An envelope resistor 564 (eg, between a node 115, 215) that may correspond to or be coupled to an RF low impedance point and a ground reference (eg, flange 406) may be provided. Figure 2F resistor 264), envelope inductor 562 (e.g., Figure 2F Inductor 262) and envelope capacitor 566 (e.g., Figure 2F In addition, each baseband decoupling circuit 460 includes a bypass capacitor 578 (e.g., Figure 2F Bypass capacitor 278). Figure 5 and 6 In the illustrated embodiment, two instances of the parallel combination of envelope inductor 562 and bypass capacitor 578 are implemented on opposite sides of IPD assembly 480. More specifically, in the illustrated embodiment, the parallel combination of envelope inductor 562 and capacitor 578 is connected in parallel between envelope resistor 564 and envelope capacitor 566. In alternative embodiments, baseband decoupling circuit 460 may include only one instance of the combination of envelope inductor 562 and capacitor 578 or more than two instances of the combination of envelope inductor 562 and capacitor 578.

[0156] exist Figure 5 and 6 In an embodiment of the present invention, envelope resistors 564 are integrally formed as part of IPD assembly 480. For example, each envelope resistor 564 can be a polysilicon resistor formed from a polysilicon layer on or within buildup structure 684 and electrically coupled between node 418 and the parallel combination of envelope inductor 562 and bypass capacitor 578. In other alternative embodiments, envelope resistors 564 can be formed from tungsten silicide or another material, can be thick film resistors or thin film resistors, or can be discrete components coupled to the top surface of IPD assembly 480.

[0157] The envelope inductor 562 may also be integrally formed as part of the IPD assembly 480, such as Figure 5 and 6 For example, each envelope inductor 562 can be a patterned conductor formed by one or more portions of one or more conductive layers of the buildup structure 684, wherein a first end of the conductor is electrically coupled to the envelope resistor 564, and a second end of the conductor is electrically coupled to a first end of the envelope capacitor 566. In alternative embodiments, each envelope inductor 562 can be implemented as a plurality of bond wires or spiral inductors (e.g., on or near the top surface of the IPD assembly 480) or as a discrete inductor coupled to the top surface of the IPD assembly 480.

[0158] In an embodiment, a bypass capacitor 578 is coupled in parallel with each envelope inductor 562. Each of the bypass capacitors 578 can be, for example, a discrete capacitor connected to the top surface of the IPD assembly 480 (e.g., using solder, conductive epoxy, or other means). More specifically, a first end of each bypass capacitor 578 can be electrically coupled to the envelope resistor 564 and to a first end of the envelope inductor 562, and a second end of each bypass capacitor 578 can be connected to a second end of the envelope inductor 562 and to a first end of the envelope capacitor 566.

[0159] For example, each bypass capacitor 578 may be a multilayer capacitor (e.g., a multilayer ceramic capacitor) having interleaved electrodes in parallel and wrapped end terminations. Alternatively, each bypass capacitor 578 may form part of a separate IPD (e.g., a MIM capacitor formed on a semiconductor substrate) or may be a capacitor formed integrally with the semiconductor substrate of the IPD assembly 480 (e.g., a MIM capacitor). Alternatively, each bypass capacitor 578 may be implemented as some other type of capacitor capable of providing the desired capacitance for the baseband decoupling circuit 460.

[0160] The envelope capacitor 566 is electrically coupled between a ground reference node (e.g., a conductive layer 686 at the bottom surface of each IPD assembly 480) and the parallel combination of the envelope inductor 562 and the bypass capacitor 578. For example, the capacitor 566 can be a MIM capacitor formed integrally with the IPD substrate of the IPD assembly 480. In some embodiments, the capacitor 566 can be formed in a stacked structure 684 that is completely above the semiconductor substrate 682, or the capacitor 566 can have a portion that extends into the semiconductor substrate 682 or is otherwise coupled to or in contact with the semiconductor substrate 682. According to an embodiment, the capacitor 566 can be formed by a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The dielectric material of the capacitor 566 can include one or more layers of polysilicon, various oxides, nitrides, or other suitable materials. In various embodiments, the first electrode and the second electrode of capacitor 566 may include horizontal portions of a conductive layer (e.g., portions parallel to the top and bottom surfaces of IPD assembly 480) and / or interconnected vertical portions of a conductive layer (e.g., portions parallel to the sides of IPD assembly 480). Additionally, the first electrode and the second electrode of capacitor 566 may be formed from a metal layer and / or from a conductive semiconductor material (e.g., polysilicon). Alternatively, each envelope capacitor 566 may be a discrete capacitor connected to the top surface of IPD assembly 480, for example (e.g., using solder, conductive epoxy, or other means). As will be appreciated by those skilled in the art based on the description herein, although Figure 6 A specific dual plate capacitor structure for capacitors 514, 534, and 566 is shown in FIG. 5 , but various other capacitor structures may alternatively be utilized.

[0161] As previously combined Figure 1 As discussed, harmonic termination circuit 430 is also connected between the control terminal (e.g., gate terminal) of the FET within each transistor die 440 and a ground reference (e.g., connected to conductive layer 686 on the bottom surface of IPD assembly 480). Figure 5 and 6 In the embodiment of the present invention, the harmonic termination circuit 430 includes a parallel inductor 532 (eg, Figure 1 The parallel inductive element 132) and the parallel capacitor 534 (e.g., Figure 1 The shunt inductor 532 may be implemented as a set of bond wires, with a first end of the bond wire connected to the input terminal 542 of the die 440 (and thus to the control terminal of the FET), and a second end of the bond wire connected to a conductive bond pad 533 exposed at the top surface of the IPD assembly 480. To avoid Figure 5In the example of FIG. 5 , only one bonding wire of a group of bonding wires including the inductor element 532 is circled and numbered with reference numeral 532, and Figure 5 Only one capacitor 534 is numbered in FIG. 4. It should be understood that the inductive element 532 includes all bond wires coupled between the bond pad 533 and the input terminal 542. Within the IPD assembly 480, the bond pad 533 is electrically connected to a first end of the shunt capacitor 534, and a second end of the shunt capacitor 534 is electrically connected (e.g., using a substrate through-via) to a ground reference (e.g., electrically connected to a conductive layer 686 on the bottom surface of the IPD assembly 480).

[0162] According to an embodiment, the shunt capacitor 534 of the harmonic termination circuit 430 may be implemented as a capacitor integrally formed with the IPD substrate of the IPD assembly 480. For example, the shunt capacitor 534 may be implemented as an integrated MIM capacitor that includes a first conductive electrode and a second conductive electrode (formed by a patterned portion of the conductive layer of the buildup structure 684) that are aligned with each other and electrically separated by the dielectric material of the buildup structure 684. In an embodiment, the first electrode (or end) of the shunt capacitor 534 is electrically coupled to the conductive bonding pad 533, and the second electrode (or end) of the shunt capacitor 534 is electrically coupled to the conductive flange 406 (e.g., using a substrate through-via). In a more specific embodiment, the first electrode of the shunt capacitor 534 is "directly connected" (as previously defined) to the bonding pad 533. Because the shunt capacitor 534 and the bonding pad 533 are "directly connected", and the bonding pad 533 also has only one trace inductance, in an embodiment, the bonding wire 532 and the shunt capacitor 534 may also be considered to be "directly connected". In alternative embodiments, shunt capacitor 534 may be implemented using discrete capacitors coupled to the top surface of IPD assembly 480 or using another type of capacitor.

[0163] According to an embodiment, harmonic termination circuit 430 acts as a low impedance path to ground for signal energy at a harmonic frequency (e.g., the second harmonic of the operating fundamental frequency of device 400). More specifically, the component values ​​of shunt capacitor 532 and shunt capacitor 534 are selected so that the series combination of shunt capacitor 532 and shunt capacitor 534 resonates at or near the second harmonic frequency. For example, the operating fundamental frequency of device 400 can be in the range of about 800 megahertz (MHz) to about 6.0 gigahertz (GHz), and thus the second harmonic frequency (and the resonant frequency of circuit 430) can be in the range of about 1.6 GHz to about 12.0 GHz. According to an embodiment, the inductance value of inductor 532 can be in the range of about 80pH to about 1nH, and the capacitance value of capacitor 534 can be in the range of about 1pF to about 100pF, but the values ​​of these components can also be outside of these ranges. As described above in conjunction with Figure 1 As discussed, for example, at an operating fundamental frequency of 2.0 GHz (whose second harmonic is 4.0 GHz), the inductance value of the inductor 532 may be approximately 120 pH, and the capacitance value of the capacitor 534 may be approximately 12 pF. However, the designed inductance value and / or capacitance value may be affected by the mutual coupling between the bond wires used to implement the inductors 516, 532.

[0164] More specifically and in accordance with an embodiment, the bond wires corresponding to the inductive elements 516 and 532 are physically configured and arranged relative to each other to exhibit predictable mutual coupling between adjacent groups of bond wires during operation. More specifically, the bond wire profiles (e.g., the height and shape of each group of bond wires) and their proximity to other bond wires produce predictable mutual coupling during operation, which produces different effective inductance values ​​of the inductive elements 516 and 532 during operation compared to the self-inductance values ​​of the inductive elements 516 and 532 when each inductor is considered in isolation (i.e., without the influence of mutual inductance from other inductors).

[0165] Furthermore, as discussed above, the bias circuit (e.g., Figure 1 The bias circuit 190 of the embodiment may also be coupled to the control terminal (e.g., gate terminal) of the transistor 630, and in one embodiment, such connection is made through the IPD assembly 480. More specifically, in an embodiment, a first end of at least one bonding wire 592 may also be connected to the conductive bonding pad 415, and a second end of the bonding wire 592 may be connected to the bias lead (e.g., Figure 4When a bias voltage is provided to the bias lead by an external bias circuit, the bias voltage can be transmitted to the gate terminal of the FET within the transistor die 440 through the bonding wire 592, the conductive landing pad 415, the bonding wire 516, and the conductive landing pad 542. According to an embodiment, the bonding wire 592 and the bias lead (e.g., Figure 4 The inductance value of the series combination of the bias lead 492) can be in the range of about 500pH to about 3000pH, but the inductance value can also be lower or higher.

[0166] Figure 4-6 An embodiment of an RF amplifier device including input leads and output leads coupled to a substrate (e.g., using intermediate electrical isolation) and a transistor die also coupled to the substrate between the input leads and the output leads is shown. Such an RF amplifier device may be particularly suitable for high power amplification. It will be understood by those skilled in the art based on the description herein that various embodiments may also be implemented using different forms of packaging or construction. For example, one or more amplification paths including embodiments of the subject matter of the present invention may be coupled to a substrate such as a PCB, a leadless package (e.g., a quad flat no-lead (QFN) package) or another type of package. In such an embodiment, the input and output of the one or more amplification paths may be implemented using a conductive ground or other input / output (I / O) structure. Such an implementation may be particularly suitable for low power amplification systems, for example, including a relatively low power Doherty amplifier, in which the main amplification path and the peaking amplification path (including a bare transistor die, an IPD, a bias circuit, etc.), a power divider, a delay and impedance inverting element, a combiner, and other components may be coupled to a substrate. It should be understood that the implementation of the subject matter of the present invention is not limited to the illustrated embodiments.

[0167] Figure 7 is a method for manufacturing a packaged RF power amplifier device (e.g., Figure 4 The packaged RF power amplifier device includes an input impedance matching circuit and an output impedance matching circuit, an input-side baseband decoupling circuit and an output-side baseband decoupling circuit, and an input-side harmonic termination circuit and an output-side harmonic termination circuit (for example, Figures 2A-2F , 400-205, 410, 411, 430, 431, 450, 451, 460-463) of the circuits 200-205, 410, 411, 430, 431, 450, 451, 460-463 ... Figure 4-6According to an embodiment, each input IPD (e.g., IPD 480, 481) includes components of an impedance matching circuit, a baseband decoupling circuit, and a harmonic termination circuit. For example, each input IPD may include one or more integrated series capacitors (e.g., Figure 1 , 5 , 6 capacitors 120, 520), one or more integrated parallel capacitors (e.g., Figure 1 , 2, 5, 6 capacitors 114, 119, 134, 266, 514, 519, 534, 566), one or more inductive elements (e.g., Figure 1 , 2, 5, 6 inductive elements 118, 262, 518, 562) and one or more resistors (e.g., Figure 1 As previously described, in embodiments where the bias is provided via the bias lead, components associated with the DC bias implemented via the input terminal may be excluded (e.g., Figure 1 , 5 19 and resistors 122 and 522). In accordance with an embodiment, each output IPD (e.g., IPD 482, 483) also includes components of an impedance matching circuit and a baseband decoupling circuit. In addition to forming the passive components of each IPD, forming each IPD also includes forming various conductive features (e.g., conductive layers and vias) that facilitate electrical connections between the various components of each circuit. For example, forming the IPD may also include forming various accessible connection nodes at the surface of each IPD substrate. As previously discussed, the connection nodes may include conductive bonding pads that may receive inductive elements (e.g., Figure 5 , 6 In addition, in block 704, some components (e.g., Figure 5 , 6 When the capacitors 520, 578) are implemented as discrete components (rather than integrated components), these discrete components can be coupled to conductors exposed at the surface of each IPD to form one or more IPD assemblies.

[0168] At block 706, for air cavity embodiments, an isolation structure (e.g., Figure 4The device substrate (e.g., flange 406) is coupled to an isolation structure 408 (e.g., an isolation structure 408) through the device substrate. In addition, one or more active devices (e.g., transistors 440, 441) and IPD assemblies (e.g., IPD assemblies 480-483) are coupled to a portion of the top surface of the substrate exposed through the opening in the isolation structure. Leads (e.g., input and output leads 402-405 and bias leads 492-495, if included) are coupled to the top surface of the isolation structure. For overmolded (e.g., encapsulated) device embodiments, the isolation structure may not be included, and the substrate and leads may form part of a lead frame.

[0169] In block 708, one or more input leads, one or more transistors, one or more IPD assemblies, and one or more output leads are electrically coupled together. For example, as previously discussed, electrical connections may be made using bonding wires between various device components and elements. For example, some of the bonding wires correspond to input matching circuits or output matching circuits (e.g., Figure 4-6 bonding wires 512, 516) and harmonic terminal circuits (e.g., Figure 4-6 Finally, in block 710, the device is capped (e.g., for an air cavity package) or encapsulated (e.g., using a molding compound for an overmolded package). The device can then be incorporated into a larger electrical system (e.g., a Doherty amplifier or other type of electrical system).

[0170] An embodiment of an RF amplifier includes: a transistor die having a transistor and a transistor input; a multi-section bandpass filter circuit; and a harmonic termination circuit. The multi-section bandpass filter circuit is coupled between a first input of a first amplification path and the transistor input, and the multi-section bandpass filter circuit includes: a first connection node, the first connection node coupled to the first input; a first inductive element, the first inductive element coupled between the first connection node and a ground reference node; a second connection node; a first capacitor, the first capacitor coupled between the first connection node and the second connection node; a second capacitor, the second capacitor coupled between the second connection node and the ground reference node; and a second inductive element, the second inductive element coupled between the second connection node and the transistor input. The harmonic termination circuit includes a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of the fundamental frequency of operation of the RF amplifier.

[0171] An embodiment of a packaged RF amplifier device includes: a device substrate; an input lead and an output lead coupled to the device substrate; a transistor die coupled to the device substrate; and a multi-section bandpass filter circuit coupled between the input lead and the transistor input. The transistor die includes a transistor, a transistor input coupled to the input lead, and a transistor output coupled to the output lead. The multi-section bandpass filter circuit includes: a first connection node, the first connection node coupled to the input lead; a first inductive element, the first inductive element coupled between the first connection node and a ground reference node; a second connection node; a first capacitor, the first capacitor coupled between the first connection node and the second connection node; a second capacitor, the second capacitor coupled between the second connection node and the ground reference node; and a second inductive element, the second inductive element coupled between the second connection node and the transistor input. The packaged RF amplifier also includes a harmonic termination circuit, the harmonic termination circuit including a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

[0172] An embodiment of a method of manufacturing an RF amplifier device includes: coupling an input lead and an output lead to a device substrate; coupling a transistor die to the device substrate between the input lead and the output lead; coupling a multi-section bandpass filter circuit between the input lead and the transistor input; and coupling a harmonic termination circuit between the transistor input and a ground reference node. The transistor die includes a transistor and a transistor input. The multi-section bandpass filter circuit includes: a first connection node, the first connection node coupled to the input lead; a first inductive element, the first inductive element coupled between the first connection node and the ground reference node; a second connection node; a first capacitor, the first capacitor coupled between the first connection node and the second connection node; a second capacitor, the second capacitor coupled between the second connection node and the ground reference node; and a second inductive element, the second inductive element coupled between the second connection node and the transistor input. The harmonic termination circuit includes a third inductive element and a third capacitor connected in series. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device.

[0173] The above detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as superior or preferable to other embodiments. Furthermore, it is not intended to be bound by any expressed or implied theory presented in the previous technical field, background, or detailed description.

[0174] The connecting lines shown in the various accompanying drawings included herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of this theme. In addition, some terms may also be used for reference only and are therefore not intended to be restrictive in this article, and the terms "first", "second" and other such numerical terms referring to structures do not imply sequence or order, unless the context clearly indicates.

[0175] As used herein, a "node" refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current or quantity exists. In addition, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise distinguished, even if the signals are received or output at a common node).

[0176] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that an element is directly and not necessarily mechanically engaged to another element (or is directly communicated with another element). Similarly, unless otherwise expressly stated, "coupled" means that an element is directly or indirectly and not necessarily mechanically engaged to another element (or is directly or indirectly communicated with another element by electrical or other means). Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in the embodiments of the depicted subject matter.

[0177] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the subject matter claimed for protection in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing one or more described embodiments for those skilled in the art. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the scope defined by the claims, including equivalents or foreseeable equivalents known at the time of filing this patent application.

Claims

1. A radio frequency (RF) amplifier, characterized in that: It includes: a transistor die having a transistor and a transistor input terminal; A multi-stage bandpass filter circuit is coupled between the first input of the first amplification path and the transistor input terminal, wherein the multi-stage bandpass filter circuit comprises: a first connection node coupled to the first input; a first inductive element coupled between the first connection node and a ground reference node; The second connection node; a first capacitor coupled between the first connection node and the second connection node; a second capacitor coupled between the second connection node and the ground reference node; and a second inductor element coupled between the second connection node and the transistor input terminal; and a harmonic termination circuit comprising a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node, wherein the harmonic termination circuit resonates at a harmonic frequency of the fundamental frequency of operation of the RF amplifier, A baseband decoupling circuit is coupled between the second connection node and the ground reference node, wherein the baseband decoupling circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the second connection node and the ground reference node.

2. The RF amplifier according to claim 1, characterized in that The transistor is a gallium nitride transistor.

3. The RF amplifier according to claim 1, wherein: The second inductive element comprises a first plurality of bond wires; and The third inductive element includes a second plurality of bond wires.

4. The RF amplifier according to claim 1, characterized in that The harmonic termination circuit resonates at a second harmonic frequency of the operating fundamental frequency.

5. The RF amplifier according to claim 1, characterized in that: It further includes a fourth inductive element coupled between the first input and the first connection node, wherein the fourth inductive element includes a plurality of bond wires.

6. The RF amplifier according to claim 1, wherein: It further includes: a resistor coupled in parallel with the first capacitor between the first connection node and the second connection node; and A DC blocking capacitor is coupled in series with a first inductive element coupled between the first connection node and a ground reference node.

7. The RF amplifier according to claim 1, characterized in that It further includes: Second amplification path; a power splitter having a power splitter input configured to receive an RF signal, a first output coupled to the first input of the first amplification path, and a second output coupled to the second input of the second amplification path, wherein the power splitter is configured to split the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output; and A combining node is configured to receive and combine the amplified RF signals produced by the first amplification path and the second amplification path.

8. A packaged radio frequency (RF) amplifier device, characterized in that It includes: device substrate; an input lead coupled to the device substrate; an output lead coupled to the device substrate; a transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input coupled to the input lead, and a transistor output coupled to the output lead; a multi-section bandpass filter circuit coupled to the input lead and the transistor input, wherein the multi-section bandpass filter circuit comprises: a first connection node coupled to the input lead; a first inductive element coupled between the first connection node and a ground reference node; The second connection node; a first capacitor coupled between the first connection node and the second connection node; a second capacitor coupled between the second connection node and the ground reference node; and a second inductor element coupled between the second connection node and the transistor input terminal; and a harmonic termination circuit comprising a third inductive element and a third capacitor connected in series between the transistor input and the ground reference node, wherein the harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the packaged RF amplifier device, A baseband decoupling circuit is coupled between the second connection node and the ground reference node, wherein the baseband decoupling circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the second connection node and the ground reference node.

9. A method of manufacturing an RF amplifier device, characterized in that The method comprises the following steps: coupling an input lead to a device substrate; coupling an output lead to the device substrate; coupling a transistor die to the device substrate between the input lead and the output lead, wherein the transistor die includes a transistor and a transistor input terminal; A multi-stage bandpass filter circuit is coupled between the input lead and the transistor input terminal, wherein the multi-stage bandpass filter circuit comprises: a first connection node coupled to the input lead; a first inductive element coupled between the first connection node and a ground reference node; The second connection node; a first capacitor coupled between the first connection node and the second connection node; a second capacitor coupled between the second connection node and the ground reference node; and a second inductor element coupled between the second connection node and the transistor input terminal; and coupling a harmonic termination circuit between the transistor input and the ground reference node, wherein the harmonic termination circuit comprises a third inductive element and a third capacitor connected in series and the harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the RF amplifier device, A baseband decoupling circuit is coupled between the second connection node and the ground reference node, wherein the baseband decoupling circuit includes a plurality of components, wherein the plurality of components includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the second connection node and the ground reference node.

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