An analog front-end circuit applicable to human pulse signals

Abstract

The present invention discloses an analog front - end circuit applicable to human body pulse signals, including capacitors C1, C’1, C2, C’2, C L and C’ L , pseudo - resistors R pseudo and R’ pseudo , and a transconductance amplifier. The pseudo - resistor includes PMOS transistors M15, M16, M19 and M20, and NMOS transistors M17, M18 and Mc. The analog front - end circuit of the present invention can achieve an extremely low low - frequency cut - off point, reduce the overall chip area, lower the cost of chip tape - out, is beneficial to improving the integration degree, and meets the requirements of small volume and low power consumption of biomedical portable devices. In addition, for the pseudo - resistor structure of the present invention, its resistance value can reach up to GΩ at most. Compared with the existing pseudo - resistor structures, it improves the linearity of the pseudo - resistor, increases the integration degree, and the total harmonic distortion is less than 1%.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to an analog front-end circuit applicable to human pulse signals. Background Art

[0002] With the rapid development of social economy and science and technology, people pay more attention to their own physical health conditions, and the biomedical field has developed rapidly. In addition, the continuous combination and innovation of microelectronics technology and biomedicine have made it more convenient, intelligent, and efficient. For example, some portable devices such as smart phones and smart bracelets have functions such as heart rate monitoring and blood oxygen measurement. The continuous introduction of healthcare elements into portable electronic products makes it easier to obtain information such as pulse, blood oxygen, body temperature, and blood pressure, which characterize the human health level.

[0003] However, due to the characteristics of small amplitude, low frequency, and easy interference of human pulse signals, the preprocessing of signals is indispensable. A high-performance signal processing circuit should be able to amplify weak signals, filter out irrelevant signals outside the main signal frequency, and provide input guarantee for subsequent analog-to-digital conversion. At the same time, when designing the signal processing circuit, it should be considered that excessive noise and offset should not be introduced, and it should have a high common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR).

[0004] Since the frequency of human pulse signals is concentrated in the range of 0.5Hz - 5Hz, and the highest does not exceed 40Hz, for the analog front-end circuit of human pulse signals, it is necessary to design an extremely low low-frequency cut-off point to remove noise frequencies outside the signal. To meet the design requirements of an extremely low low-frequency cut-off point, the following several schemes are currently available: 1. Using discrete devices, resistors and capacitors are used to meet the design requirements of an extremely low low-frequency cut-off point, but this scheme will increase the power consumption of the integrated circuit and is not conducive to integration. 2. Using integrated resistors and integrated capacitors to meet the design requirements of an extremely low low-frequency cut-off point. Although this scheme can improve the integration of the circuit, the maximum value of the existing integrated resistor does not exceed megohm (MΩ), and the integrated capacitor does not exceed 50pF. In addition, due to process reasons, the resistor is easily affected, and the accuracy of the resistor value is also greatly affected. Therefore, this scheme also far fails to meet the design requirements of an extremely low low-frequency cut-off point. 3. Specifically designing a filter circuit. Although this scheme can meet the design requirements of an extremely low low-frequency cut-off point, it additionally increases the power consumption and does not meet the requirement of low power consumption. 4. Using the MOS transistor pseudo-resistor structure to meet the design requirements of an extremely low low-frequency cut-off point, but the current pseudo-resistor structure has poor linearity and large fluctuations in the change of the pseudo-resistor value. Summary of the Invention

[0005] Aiming at the problems of small amplitude and low frequency of human pulse signals, the present invention provides an analog front-end circuit applicable to human pulse signals.

[0006] To solve the above problems, the present invention is implemented through the following technical solutions:

[0007] An analog front-end circuit applicable to human pulse signals, the analog front-end circuit includes capacitors C1, C’1, C2, C’2, C L and C’ L , pseudo-resistors R pseudo and R’ pseudo , and a transconductance amplifier OTA; one end of capacitor C1 forms the positive input terminal of the analog front-end circuit and is connected to the input voltage signal Vin+, and the other end of capacitor C1 is connected to the positive input terminal of the OTA; one end of capacitor C’1 forms the negative input terminal of the analog front-end circuit and is connected to the input voltage signal Vin-, and the other end of capacitor C’1 is connected to the negative input terminal of the transconductance amplifier; one end of capacitor C2 is connected to the positive input terminal of the transconductance amplifier, and the other end is connected to the negative output terminal of the transconductance amplifier; one end of capacitor C’2 is connected to the negative input terminal of the transconductance amplifier, and the other end is connected to the positive output terminal of the transconductance amplifier; the A end of pseudo-resistor R pseudo is connected to the positive input terminal of the transconductance amplifier, and the B end is connected to the negative output terminal of the transconductance amplifier; the A end of pseudo-resistor R’ pseudo is connected to the negative input terminal of the transconductance amplifier, and the B end is connected to the positive output terminal of the transconductance amplifier; one end of capacitor C L is connected to the negative output terminal of the transconductance amplifier and forms the negative output terminal of the analog front-end circuit, and the other end of capacitor C L is connected to the ground terminal; one end of capacitor C’ L is connected to the negative output terminal of the transconductance amplifier and forms the positive output terminal of the analog front-end circuit, and the other end of capacitor C’ L is connected to the ground terminal.

[0008] In the above solution, capacitors C1 and C’1 have the same model, capacitors C2 and C’2 have the same model, and capacitors C L and C’ L have the same model.

[0009] In the above solution, pseudo-resistors R pseudo and R’ pseudo have the same structure.

[0010] In the above solution, the pseudo resistor includes PMOS transistors M15, M16, M19, and M20, and NMOS transistors M17, M18, and Mc; the gates of PMOS transistor M15, the gate of PMOS transistor M16, the source and substrate of NMOS transistor M17, the source and substrate of NMOS transistor M18, the gate of PMOS transistor M19, the gate of PMOS transistor M20, and the drain of NMOS transistor Mc are connected; the drain and substrate of PMOS transistor M15, the gate of NMOS transistor M18, and the source of PMOS transistor M19 are connected; the drain and substrate of PMOS transistor M16, the gate of NMOS transistor M17, and the source of PMOS transistor M20 are connected; the source of PMOS transistor M15 is connected to the source of PMOS transistor M16; the drains of NMOS transistors M17 and M18 are connected and connected to voltage VDD; the substrate and drain of NMOS transistor Mc are connected and connected to voltage VSS; the gate of NMOS transistor Mc is connected to voltage V control connection; the substrate and drain of PMOS transistor M19 are connected and form terminal A of the pseudo resistor; the substrate and drain of PMOS transistor M20 are connected and form terminal B of the pseudo resistor.

[0011] In the above solution, PMOS transistors M15, M16, M19, and M20 have the same model, and NMOS transistors M17 and M18 have the same model.

[0012] In the above solution, the transconductance amplifier includes PMOS transistors M1, M2, M7 - M14, NMOS transistors M3 - M6, resistors Rs1 - Rs4, and a current source Ibias; the gate of PMOS transistor M1 forms the positive input terminal of the transconductance amplifier; the gate of PMOS transistor M2 forms the negative input terminal of the transconductance amplifier; the gate and drain of PMOS transistor M9, the gate of PMOS transistor M10, and one end of the DC power supply Ibias are connected, and the other end of the DC power supply Ibias is grounded; the substrate and source of PMOS transistor M2, the source and substrate of PMOS transistor M1, and the drain of PMOS transistor M10 are connected; the gates of PMOS transistors M7, M8, the substrate and source of PMOS transistor M12, and the substrate and source of PMOS transistor M13 are connected; the drain and gate of PMOS transistor M11 are connected to the drain and gate of PMOS transistor M12; the drain and gate of PMOS transistor M13 are connected to the drain and gate of PMOS transistor M14; the drain of PMOS transistor M1, the drain and gate of NMOS transistor M4, and the gate of NMOS transistor M3 are connected; the drain of PMOS transistor M2, the drain and gate of NMOS transistor M5, and the gate of NMOS transistor M6 are connected; the substrate and source of PMOS transistors M9, M10, M7, and M8 are connected to the voltage VDD; the substrate and source of PMOS transistor M3 are connected to one end of resistor Rs1; the substrate and source of NMOS transistor M4 are connected to one end of resistor Rs2; the substrate and source of NMOS transistor M5 are connected to one end of resistor Rs3; the substrate and source of PMOS transistor M6 are connected to one end of resistor Rs4; the other ends of resistors Rs1 - Rs4 are grounded simultaneously; the drain of NMOS transistor M3, the drain of NMOS transistor M7, and the substrate and source of PMOS transistor M11 are connected and form the positive output terminal Vout+ of the transconductance amplifier; the drain of NMOS transistor M6, the drain of PMOS transistor M8, and the substrate and source of PMOS transistor M13 are connected and form the negative output terminal Vout- of the transconductance amplifier.

[0013] In the above solution, PMOS transistors M1 and M2 have the same model, NMOS transistors M3, M4, M5, and M6 have the same model, PMOS transistors M7 and M8 have the same model, PMOS transistors M9 and M10 have the same model, PMOS transistors M11, M12, M13, and M14 have the same model, and resistors Rs1 - Rs4 have the same model.

[0014] Compared with the prior art, the analog front-end circuit of the present invention can achieve an extremely low low-frequency cut-off point, reduce the overall chip area, lower the cost of chip tape-out, facilitate improving the integration level, and meet the requirements of small size and low power consumption for biomedical portable devices. In addition, for the pseudo-resistance structure of the present invention, the maximum resistance value can reach GΩ. Compared with the existing pseudo-resistance structures, the linearity of the pseudo-resistance is improved, the integration level is increased, and the total harmonic distortion (THD) is less than 1%. Description of the Drawings

[0015] Figure 1 It is the overall structure diagram of an analog front-end circuit applicable to human pulse signals;

[0016] Figure 2 is Figure 1 the circuit schematic diagram of the OTA in

[0017] Figure 3 is Figure 1 the circuit schematic diagram of the pseudo-resistance in

[0018] Figure 4 (a) and (b) are two common structural diagrams of pseudo-resistances;

[0019] Figure 5 is the curve graph for adjusting different low cut-off points f L by changing different voltages. Detailed Embodiments

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0021] An analog front-end circuit applicable to human pulse signals, the overall circuit architecture of which is as Figure 1 shown. The circuit includes: capacitors C1, C’1, C2, C’2, C L , C’ L , pseudo-resistances R pseudo , R’ pseudo , and an OTA (transconductance amplifier). One end of capacitor C1 forms the positive input terminal of the analog front-end circuit and is connected to the input voltage signal Vin+. The other end of capacitor C1 is connected to the positive input terminal of the OTA. One end of capacitor C’1 forms the negative input terminal of the analog front-end circuit and is connected to the input voltage signal Vin-. The other end of capacitor C’1 is connected to the negative input terminal of the transconductance amplifier. One end of capacitor C2 is connected to the positive input terminal of the transconductance amplifier, and the other end is connected to the negative output terminal of the transconductance amplifier. One end of capacitor C’2 is connected to the negative input terminal of the transconductance amplifier, and the other end is connected to the positive output terminal of the transconductance amplifier. Pseudo-resistance R pseudoThe A terminal of [component] is connected to the positive input terminal of the transconductance amplifier, and the B terminal is connected to the negative output terminal of the transconductance amplifier. The pseudo-resistor R’ pseudo The A terminal of [component] is connected to the negative input terminal of the transconductance amplifier, and the B terminal is connected to the positive output terminal of the transconductance amplifier. The capacitor C L One end of [capacitor] is connected to the negative output terminal of the transconductance amplifier and forms the negative output terminal of the analog front-end circuit. The capacitor C L The other end is connected to the ground terminal. The capacitor C’ L One end of [capacitor] is connected to the negative output terminal of the transconductance amplifier and forms the positive output terminal of the analog front-end circuit. The capacitor C’ L The other end is connected to the ground terminal. Among them, the capacitors C1 and C’1 have the same model, the capacitors C2 and C’2 have the same model, the capacitors C L and C’ L have the same model, and the pseudo-resistors R pseudo and R’ pseudo have exactly the same structure.

[0022] The analog front-end circuit of the present invention adopts a fully differential structure and is divided into three parts according to the signal processing effect: amplification, high-pass, and low-pass. The amplification factor of the amplification part is determined by the capacitors C1, C’1, C2, and C’2. The capacitive coupling structure circuit is used to determine the amplification factor of the weak signal. The high-pass filtering part is realized by the pseudo-resistors R pseudo , R’ pseudo , and the capacitors C2 and C’2. The pseudo-resistor structure and the capacitor form a low cut-off frequency point. The low-pass filtering part is realized by the gm (transconductance) of the OTA and the capacitors C L , C’ L . The transconductance gm of the transconductance amplifier and the load capacitor form a high cut-off frequency point.

[0023] The amplification factor A required for the signal is determined by the ratio of C1 / C2 v :

[0024]

[0025] Since there is noise in the signal, this part of the noise needs to be suppressed. A low-frequency high-pass pole f is formed between the pseudo-resistor R pseudo and C2 L :

[0026]

[0027] And the pseudo-resistor R pseudo can change the resistance value by adjusting the voltage to achieve an appropriate low cut-off frequency. The gm (transconductance) of the OTA (transconductance amplifier) and C L form a high cut-off frequency point f H :

[0028]

[0029] At this time, a band-pass filter is formed to achieve the effect of suppressing noise other than the pulse signal.

[0030] The analog front-end circuit of the present invention has stable closed-loop gain and low-noise characteristics. The circuit gain is determined by C1 and C2 and is approximately equal to C1 / C2. Capacitor C1 is used as AC coupling at the input end to reduce the DC offset voltage from the electrode. The AC coupling structure solves the problem of DC drift, can also reduce common-mode interference and improve the power supply rejection ratio of the circuit. The DC feedback path is provided by the pseudo-resistor R pseudo which generates an extremely high resistance value, can provide a stable DC operating point, and the pseudo-resistor R pseudo and the feedback capacitor C2 form a low-frequency high-pass pole, which can reduce the interference of low-frequency noise. This circuit adopts a fully differential form to enhance the power supply rejection ratio and common-mode rejection ratio, thereby reducing the interference of power supply noise and common-mode noise. The mid-frequency gain A m of the circuit is also determined by C1 and C2:

[0031]

[0032] is approximately equal to the ratio of C1 and C2. It is necessary to select an appropriate mid-frequency gain for the amplifier because too low a gain will affect the amplification performance of the entire circuit, while too high a gain will reduce the accuracy of the amplifier.

[0033] The structure of the OTA of the present invention is referred to in the appendix Figure 2, the circuit includes: PMOS transistors M1, M2, M7 - M14, NMOS transistors M3 - M6, resistors Rs1 - Rs4, and current source Ibias. The gate of PMOS transistor M1 forms the positive input terminal of the transconductance amplifier. The gate of PMOS transistor M2 forms the negative input terminal of the transconductance amplifier. The gate and drain of PMOS transistor M9, the gate of PMOS transistor M10, and one end of the DC power supply Ibias are connected, and the other end of the DC power supply Ibias is grounded. The substrate and source of PMOS transistor M2, the source and substrate of PMOS transistor M1, and the drain of PMOS transistor M10 are connected. The gates of PMOS transistors M7, M8, the substrate and source of PMOS transistor M12, and the substrate and source of PMOS transistor M13 are connected. The drain and gate of PMOS transistor M11 are connected to the drain and gate of PMOS transistor M12. The drain and gate of PMOS transistor M13 are connected to the drain and gate of PMOS transistor M14. The drain of PMOS transistor M1, the drain and gate of NMOS transistor M4, and the gate of NMOS transistor M3 are connected. The drain of PMOS transistor M2, the drain and gate of NMOS transistor M5, and the gate of NMOS transistor M6 are connected. The substrate and source of PMOS transistors M9, M10, M7, and M8 are connected to voltage VDD. The substrate and source of PMOS transistor M3 are connected to one end of resistor Rs1. The substrate and source of NMOS transistor M4 are connected to one end of resistor Rs2. The substrate and source of NMOS transistor M5 are connected to one end of resistor Rs3. The substrate and source of PMOS transistor M6 are connected to one end of resistor Rs4. The other ends of resistors Rs1 - Rs4 are grounded simultaneously. The drain of NMOS transistor M3, the drain of NMOS transistor M7, and the substrate and source of PMOS transistor M11 are connected and form the positive output terminal Vout+ of the transconductance amplifier. The drain of NMOS transistor M6, the drain of PMOS transistor M8, and the substrate and source of PMOS transistor M13 are connected and form the negative output terminal Vout- of the transconductance amplifier. Among them, PMOS transistors M1 and M2 have the same model, NMOS transistors M3, M4, M5, and M6 have the same model, PMOS transistors M7 and M8 have the same model, PMOS transistors M9 and M10 have the same model, PMOS transistors M11, M12, M13, and M14 have the same model, and resistors Rs1 - Rs4 have the same model.

[0034] The OTA circuit of the present invention includes a common-mode feedback module and a two-stage amplification module. The common-mode feedback module includes PMOS transistors M11, M12, M13, and M14; the two-stage amplification module includes PMOS transistors M1, M2, M9, M10, NMOS transistors M3, M4, M5, M6, resistors Rs1-Rs4, and a current source Ibias. The OTA adopts a fully differential structure. The OTA circuit consists of a common-mode feedback circuit and a two-stage amplifier, where the common-mode feedback circuit can provide a stable DC operating point, and the amplifier circuit uses two-stage source followers in cascade. Since the negative feedback of the differential circuit cannot control the output voltage of the amplifier, an additional common-mode feedback circuit is required to stabilize the output DC level of the fully differential amplifier. The circuit uses PMOS transistors as the input pair, and by increasing the area of the input pair transistors M1 and M2, the flicker noise interference in the low-frequency band can also be reduced. By connecting resistors in series with the source terminals of NMOS transistors M3, M4, M5, and M6 respectively, the output impedance of the OTA circuit can be increased, signal distortion can be reduced, linearity can be improved, and thus circuit noise can be reduced. The input voltage is first applied to the gates of the input pair transistors M1 and M2 of the source follower, so that the source electrodes of PMOS transistors M1 and M2 drive the load, and then the output voltage of the first-stage operational amplifier is used as the input voltage of the second-stage symmetric source follower, where most of the voltage drop of the input voltage falls on resistor Rs.

[0035] The pseudo-resistor R of the present invention pseudo and R' pseudo The structure is referred to in the appendix Figure 3 , the circuit includes PMOS transistors M15, M16, M19, and M20, and NMOS transistors M17, M18, and Mc. The gates of PMOS transistor M15, the gate of PMOS transistor M16, the source and substrate of NMOS transistor M17, the source and substrate of NMOS transistor M18, the gate of PMOS transistor M19, the gate of PMOS transistor M20, and the drain of NMOS transistor Mc are connected. The drain and substrate of PMOS transistor M15, the gate of NMOS transistor M18, and the source of PMOS transistor M19 are connected. The drain and substrate of PMOS transistor M16, the gate of NMOS transistor M17, and the source of PMOS transistor M20 are connected. The source of PMOS transistor M15 is connected to the source of PMOS transistor M16. The drains of NMOS transistor M17 and NMOS transistor M18 are connected and connected to voltage VDD. The substrate and drain of NMOS transistor Mc are connected and connected to voltage VSS. The gate of NMOS transistor Mc is connected to voltage V control connected. The substrate and drain of PMOS transistor M19 are connected and form terminal A of the pseudo-resistor. The substrate and drain of PMOS transistor M20 are connected and form terminal B of the pseudo-resistor. Among them, PMOS transistors M15, M16, M19, and M20 have the same model, NMOS transistors M17 and M18 have the same model, and resistors Rs1-Rs4 have the same model.

[0036] The important part of the pseudo-resistor is the auxiliary circuit, which is used to ensure that the MOS transistor operates in the subthreshold region to obtain a high impedance. Attached Figure 4 The auxiliary circuit of the pseudo-resistor shown in (a) can be that the gate is connected to nodes AB. Attached Figure 4 The auxiliary circuit of the pseudo-resistor shown in (b) can also be that the gates of two MOS transistors are connected to obtain a constant gate voltage. Attached Figure 4 The pseudo-resistors in (a) and (b) can obtain high impedance under low V AB conditions, but under high V AB conditions, since the PMOS transistor obtains carriers, the impedance decreases, resulting in poor linearity.

[0037] To solve the above problems, the present invention uses differential pair transistors as the working area control circuit. In addition, transistors M19 and M20 are added at both ends of the pseudo-resistor. The value of the differential pair node V E is equal to the average value of nodes V C and V D minus the average value of V GS of NMOS transistors M17 and M18:

[0038]

[0039] The NMOS transistor M c acts as a current source and is controlled by the voltage V control . The closer the voltage value of V control is to the negative voltage VSS, the smaller the current Ic passing through Mc and the voltage value V GS3，4 decreases, causing the impedance of transistors M15 and M16 to increase. This structure operates in the subthreshold region, and the resistance value can be adjusted in the range from MΩ to GΩ. The V GS of the MOS transistor is controlled by the differential pair. The feasibility of the circuit is verified using the Cadence Spectre simulation design environment and TSMC.18um for simulation technical parameters.

[0040] Based on the Cadence Spectre simulation of the 0.18um CMOS process, the input signal frequency is a sine wave of 0.5Hz and the amplitude is 0.5mV. Among them, the sine wave with a phase of 0° is connected to the input signal terminal Vin+, and the sine wave with a phase of 180° is connected to the input signal terminal Vin-. The AC analysis of the circuit is performed, and the simulation results are as Figure 5 shown. The impedance of the pseudo-resistor is changed according to different Vcontrol to change different low cut-off points f LAs can be seen from the figure, the voltage Vcontrol changes from -1.65V to -1.3V, the low cut-off frequency point changes from 0.5Hz to 300Hz, the overall power consumption of the circuit is about 3uW, the CMRR is 110dB, and the PSRR is 68dB. These simulation results illustrate the effectiveness of the present invention.

[0041] It should be noted that although the embodiments described above of the present invention are illustrative, they are not limitations of the present invention. Therefore, the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other embodiments obtained by those skilled in the art under the inspiration of the present invention are deemed to be within the protection scope of the present invention.

Claims

1. An analog front-end circuit applicable to human pulse signals, characterized in that The analog front-end circuit includes capacitors C1, C’1, C2, C’2, C L and C’ L , pseudo-resistors R pseudo and R’ pseudo , and a transconductance amplifier; One end of capacitor C1 forms the positive input terminal of the analog front-end circuit and is connected to the input voltage signal Vin+, and the other end of capacitor C1 is connected to the positive input terminal of the OTA; One end of capacitor C’1 forms the negative input terminal of the analog front-end circuit and is connected to the input voltage signal Vin-, and the other end of capacitor C’1 is connected to the negative input terminal of the transconductance amplifier; One end of capacitor C2 is connected to the positive input terminal of the transconductance amplifier, and the other end is connected to the negative output terminal of the transconductance amplifier; One end of capacitor C’2 is connected to the negative input terminal of the transconductance amplifier, and the other end is connected to the positive output terminal of the transconductance amplifier; The A end of pseudo-resistor R pseudo is connected to the positive input terminal of the transconductance amplifier, and the B end is connected to the negative output terminal of the transconductance amplifier; The A end of pseudo-resistor R’ pseudo is connected to the negative input terminal of the transconductance amplifier, and the B end is connected to the positive output terminal of the transconductance amplifier; One end of capacitor C L is connected to the negative output terminal of the transconductance amplifier and forms the negative output terminal of the analog front-end circuit, and the other end of capacitor C L is connected to the ground terminal; One end of capacitor C’ L is connected to the negative output terminal of the transconductance amplifier and forms the positive output terminal of the analog front-end circuit, and the other end of capacitor C’ L is connected to the ground terminal; Pseudo-resistor R pseudo and R' pseudo have the same structure, including PMOS transistors M15, M16, M19 and M20, and NMOS transistors M17, M18 and Mc; the models of PMOS transistors M15, M16, M19 and M20 are the same, and the models of NMOS transistors M17 and M18 are the same; the gates of PMOS transistor M15, the gate of PMOS transistor M16, the source and substrate of NMOS transistor M17, the source and substrate of NMOS transistor M18, the gate of PMOS transistor M19, the gate of PMOS transistor M20, and the drain of NMOS transistor Mc are connected; the drain and substrate of PMOS transistor M15, the gate of NMOS transistor M18, and the source of PMOS transistor M19 are connected; the drain and substrate of PMOS transistor M16, the gate of NMOS transistor M17, and the source of PMOS transistor M20 are connected; the source of PMOS transistor M15 is connected to the source of PMOS transistor M16; the drains of NMOS transistors M17 and M18 are connected and connected to the voltage VDD; the substrate and drain of NMOS transistor Mc are connected and connected to the voltage VSS; the gate of NMOS transistor Mc is connected to the voltage V control connection; the substrate and drain of PMOS transistor M19 are connected and form terminal A of the pseudo-resistor; the substrate and drain of PMOS transistor M20 are connected and form terminal B of the pseudo-resistor.

2. The analog front-end circuit applicable to human body pulse signals according to claim 1, characterized in that, Capacitors C1 and C'1 have the same model number, capacitors C2 and C'2 have the same model number, and capacitors C L and C' L have the same model number.

3. The analog front-end circuit applicable to human body pulse signals according to claim 1 is characterized in that, The transconductance amplifier includes PMOS transistors M1, M2, M7 - M14, NMOS transistors M3 - M6, resistors Rs1 - Rs4, and a current source Ibias; The gate of PMOS transistor M1 forms the positive input terminal of the transconductance amplifier; the gate of PMOS transistor M2 forms the negative input terminal of the transconductance amplifier; The gate and drain of PMOS transistor M9, the gate of PMOS transistor M10, and one end of the DC power supply Ibias are connected, and the other end of the DC power supply Ibias is grounded; the substrate and source of PMOS transistor M2, the source and substrate of PMOS transistor M1, and the drain of PMOS transistor M10 are connected; The gate of PMOS transistor M7, the gate of PMOS transistor M8, the substrate and source of PMOS transistor M12, and the substrate and source of PMOS transistor M13 are connected; The drain and gate of PMOS transistor M11 are connected to the drain and gate of PMOS transistor M12; the drain and gate of PMOS transistor M13 are connected to the drain and gate of PMOS transistor M14; The drain of PMOS transistor M1, the drain and gate of NMOS transistor M4, and the gate of NMOS transistor M3 are connected; the drain of PMOS transistor M2, the drain and gate of NMOS transistor M5, and the gate of NMOS transistor M6 are connected; The substrate and source of PMOS transistor M9, the substrate and source of PMOS transistor M10, the substrate and source of PMOS transistor M7, and the substrate and source of PMOS transistor M8 are connected to the voltage VDD; The substrate and source of PMOS transistor M3 are connected to one end of resistor Rs1; the substrate and source of NMOS transistor M4 are connected to one end of resistor Rs2; the substrate and source of NMOS transistor M5 are connected to one end of resistor Rs3; the substrate and source of PMOS transistor M6 are connected to one end of resistor Rs4; the other ends of resistors Rs1 - Rs4 are grounded simultaneously; The drain of NMOS transistor M3, the drain of NMOS transistor M7, and the substrate and source of PMOS transistor M11 are connected and form the positive output terminal Vout+ of the transconductance amplifier; the drain of NMOS transistor M6, the drain of PMOS transistor M8, and the substrate and source of PMOS transistor M13 are connected and form the negative output terminal Vout- of the transconductance amplifier.

4. The analog front-end circuit applicable to human body pulse signals according to claim 3, characterized in that, PMOS transistors M1 and M2 have the same model, NMOS transistors M3, M4, M5, and M6 have the same model, PMOS transistors M7 and M8 have the same model, PMOS transistors M9 and M10 have the same model, PMOS transistors M11, M12, M13, and M14 have the same model, and resistors Rs1 - Rs4 have the same model.

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