Graphics processing unit, computing system and operation method thereof

Abstract

A computing system is provided. The computing system includes: a memory configured to store a shader program; and a graphics processing unit (GPU) configured to obtain the shader program stored in the memory in a profile mode, the GPU configured to perform the following operations: insert one or more monitor association codes into the shader program; compile the shader program with the one or more monitor association codes inserted into a language that can be processed by multiple cores; and obtain runtime performance characteristics of the shader program by executing the compiled shader program and the one or more monitor association codes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0174223 filed in the Korean Intellectual Property Office on December 31, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a graphics processing unit (GPU), and more particularly, to a GPU for deriving runtime performance characteristics, a computing system, and an operating method thereof. Background Art

[0004] A graphics processing unit (GPU) processes a graphics application programming interface (API) (e.g., OpenGL, OpenCL, or Vulkan) to implement various graphics effects in various electronic devices. Programs should be edited according to predetermined rules of the standard API so that they can be processed in the GPU. Programs to be processed in the GPU may include vertex shaders, geometry shaders, and pixel shaders for image generation.

[0005] Vertex shaders, geometry shaders, and pixel shaders are compiled and linked and used in a program. The GPU executes the program in multiple cores (or multiple threads) in a parallel manner (e.g., in the form of multiple single instructions, multiple data (SIMD)). In this case, it may not be easy to monitor the runtime characteristics of individual shader programs in the GPU. Summary of the invention

[0006] One or more example embodiments provide a method of deriving runtime performance characteristics of a graphics processing unit (GPU), and more particularly, provide a GPU including a compiler for inserting monitor-associated code during compilation, a computing system, and an operating method thereof.

[0007] According to aspects of an example embodiment, a computing system is provided, comprising: a memory configured to store a shader program; and a graphics processing unit (GPU) configured to obtain the shader program stored in the memory in a profile mode, the GPU being configured to perform the following operations: inserting one or more monitor association codes into the shader program; compiling the shader program with the one or more monitor association codes inserted into a language that can be processed by multiple cores; and obtaining runtime performance characteristics of the shader program by executing the compiled shader program and the one or more monitor association codes.

[0008] According to one aspect of an example embodiment, a method for operating a computing system is provided, the method comprising: in response to a profile command comprising a graphics command, outputting a shader program comprising a plurality of code blocks; inserting a monitor-associated code into each of at least a portion of the plurality of code blocks; compiling the shader program into which the monitor-associated code is inserted; obtaining a runtime performance characteristic of the shader program by executing the plurality of code blocks and the monitor-associated code in a plurality of cores; recording the obtained runtime performance characteristic of the shader program in a memory shared by the plurality of cores; and in response to termination of the shader program, outputting the recorded runtime performance characteristic of the shader program.

[0009] According to one aspect of an example embodiment, a graphics processing unit (GPU) is provided, comprising: a compiler configured to receive a program including a plurality of code blocks, the compiler comprising a monitor-associated code injector, the monitor-associated code injector configured to insert one or more monitor-associated codes into each of at least a portion of the plurality of code blocks, and the compiler configured to compile the one or more monitor-associated codes and the program in a profile mode; a plurality of cores configured to execute the compiled program and the one or more monitor-associated codes in parallel, and configured to obtain runtime performance characteristics of the program based on execution of the one or more monitor-associated codes; and a shared memory configured to store the obtained runtime performance characteristics of the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or other aspects will become more apparent by describing certain example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a computing system according to an example embodiment;

[0012] Figure 2 is a block diagram illustrating operation in a profile mode according to an example embodiment;

[0013] Figure 3 is a flow chart illustrating operation of a computing system in a profile mode according to an example embodiment;

[0014] Figure 4 is a flowchart illustrating the operation of a compiler according to an example embodiment;

[0015] Figure 5 is a diagram showing an insertion monitor association code according to an example embodiment;

[0016] Figure 6 is a diagram illustrating a monitoring operation according to an example embodiment;

[0017] Figure 7 is a flow chart illustrating the operation of a code block having monitor code inserted therein according to an example embodiment;

[0018] Figure 8 is a diagram showing a monitoring operation according to another example embodiment;

[0019] Fig. 9 is a diagram showing a list of runtime performance characteristics according to an example embodiment;

[0020] Fig.10 is a diagram showing a monitoring operation according to another example embodiment;

[0021] Fig.11 is a block diagram illustrating operation in a profile mode according to another example embodiment; and

[0022] Fig.12 is a block diagram illustrating a graphic processor according to example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram illustrating a computing system 10 according to an example embodiment. Figure 1 , the computing system 10 may include a processor 100, a graphics processing unit (GPU) 200, and a system memory 300. Although not shown in Figure 1 Although not shown in FIG. 1 , computing system 10 may also include a display, input / output interfaces, and a system bus.

[0025] Computing system 10 may refer to any computing system including GPU 200. As non-limiting examples, computing system 10 may be a fixed computing system (e.g., a desktop computer, a server, a television set-top box, a video game console), or a portable computing system (e.g., a laptop computer, a mobile phone, a wearable device, a portable media player, a desktop personal computer (PC), an e-book reader, etc.).

[0026] The processor 100 may receive user input from the outside. In addition, the processor 100 may execute a series of commands (or programs) stored in the system memory 300, may process data stored in the system memory 300, and may allow the GPU 200 to perform a task in the graphics pipeline. In some embodiments, the processor 100 may include two or more cores.

[0027] In some embodiments, the processor 100 and the GPU 200 may be an integrated circuit (IC). For example, the IC may be at least a portion of a processing chip within a chip package and a system on chip (SoC). In an example, the processor 100 and the GPU 200 may be implemented in different ICs (or different chip packages). In another example, the processor 100 and the GPU 200 may also be implemented in a single IC (or a single chip package).

[0028] The system memory 300 may include one or more computer-readable storage media. The system memory 300 may be used to transmit or store desired program codes in the form of commands and / or data structures, and may include any medium that can be accessed by the processor 100 or the GPU 200. For example, in some embodiments, the system memory 300 may include a volatile memory (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LP DDR) SDRAM, a graphic DDR (GDDR) SDRAM, or a rambus dynamic random access memory (RDRAM)), and in some embodiments, may include a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM)).

[0029] In some embodiments, system memory 300 may be a non-transitory storage medium. The term "non-transitory" may mean that the storage medium is not implemented as a carrier wave or a propagating signal. However, the term "non-transitory" does not mean that system memory 300 cannot be moved or that the stored contents are static. In an example, system memory 300 may be removed from computing system 10 and moved to another system (or device).

[0030] System memory 300 may include application programs 310 and / or application program interfaces (APIs) 320. For example, application programs 310 may make calls to API 320 in order to produce a desired result in the form of a series of graphical images.

[0031] The application 310 may be driven by the processor 100, and the processor 100 may offload a portion of the tasks related to the application 310 to the GPU 200. For example, the processor 100 may offload tasks requiring large-scale parallel operations (eg, graphics processing tasks) to the GPU 200.

[0032] When offloading tasks, the processor 100 may communicate with the GPU 200 based on the API 320. For example, the API 320 may include at least one of a DirectX API, an OpenGL API, an OpenCL API, and a Vulkan API. In another example, those skilled in the art will appreciate that the processor 100 may communicate with the GPU 200 using any other arbitrary communication technology not based on the API 320.

[0033] GPU 200 can receive commands provided by processor 100, and can perform parallel operations related to various tasks. GPU 200 may include compiler 210 and multiple cores 220. For example, GPU 200 may receive a shader program from processor 100, and may use compiler 210 to convert the shader program into a language (e.g., machine language) that can be processed using multiple cores 220. A shader program, which is an algorithm for generating a color change of an object, may refer to a unit or shape of software or firmware to be executed on GPU 200. In an example embodiment, a shader program may include multiple code blocks. A shader program may include multiple code blocks. For example, multiple code blocks may be code units that are sequentially executed without waiting for external resources and / or branching into another code. A detailed description thereof will be provided later.

[0034] For example, the processor 100 may execute an application such as a video game, and thus may generate graphics data. The processor 100 may output the graphics data to the GPU 200, and the GPU 200 may process the graphics data according to the graphics pipeline. For example, the GPU 200 may execute one or more shader programs in order to process the graphics data.

[0035] Hereinafter, an example embodiment is described based on a shader program. However, this is only for ease of explanation, and those skilled in the art will understand that the present disclosure is applicable to other programs, such as deep learning related programs, blockchain related programs, and general computing programs other than shader programs.

[0036] In an example embodiment, the GPU 200 may operate in a profile mode based on the instructions of the program 100, and thus may measure the runtime characteristics of the shader program. The profile mode may be a mode in which the performance characteristics of each shader program are derived, and the execution of the shader program is identified based on the derived performance characteristics of each shader program. For example, the runtime characteristics may be driving characteristics of the shader program in a real shader program driving environment, and may indicate characteristics that consider access to external resources or branches of code.

[0037] In an example embodiment, in profile mode, the compiler 210 may insert monitor association code into at least a portion of a plurality of code blocks included in the shader program. In an example, the monitor association code may be a monitor code, which is a code for monitoring the performance characteristics of the corresponding code block. In another example, the monitor association code may be a branch code, which indicates branching into the monitor code for monitoring the performance characteristics of the code block. In an example embodiment, the monitor code may export information (such as, but not limited to, shader program number, timestamp, mask execution, resource scoreboard, branch condition satisfaction / dissatisfaction, call count, type of requested resource, and type of used resource by monitoring operation), and the exported information may be stored in a memory (e.g., a buffer). A detailed description thereof will be provided later.

[0038] Figure 2 is a block diagram illustrating operation in a profile mode according to an example embodiment.

[0039] refer to Figure 2 , the processor 100 may include a shader program manager 110 and a performance analyzer 120. The shader program manager 110 may output the shader program SH to the GPU 200 based on the input graphics command. In an example, the shader program manager 110 may receive a graphics command required to drive the application 310, may select a shader program SH stored in the system memory 300 based on the received graphics command, and may output the selected shader program to the GPU 200.

[0040] In an example embodiment, the shader program manager 110 may receive a profile mode command P_CMD and may output various signals so that the GPU 200 may operate in a profile mode based on the received profile mode command P_CMD. The profile mode, which is a mode for measuring the performance of the GPU 200, may include a graphics command. The shader program manager 110 may output a shader program SH in response to the profile mode command P_CMD, and the GPU 200 may monitor runtime performance characteristics regarding the shader program SH.

[0041] In an example embodiment, the performance analyzer 120 may receive a runtime performance characteristic list RT_ST from the GPU 200, and may extract performance data PF about each shader program based on the received runtime performance characteristic list RT_ST. For example, the performance analyzer 120 may receive and analyze the runtime performance characteristic list RT_ST of each shader program stored in the shared memory 230 of the GPU 200. The performance analyzer 120 may analyze at least one of the total execution time of the shader program, the efficiency of the shader program, the instruction issuance efficiency, and the statistical value about whether the branch condition is satisfied for each branch point based on the runtime performance characteristic list RT_ST.

[0042] The GPU 200 may include a compiler 210, a plurality of cores 220, a shared memory 230, and a timer 240. The compiler 210 may convert various signals received from the shader program manager 110 into a form (e.g., a form of machine language) that can be executed by the plurality of cores 220. For example, the compiler 210 may use the shader program received from the shader program manager 110 as a source code to perform compilation of the shader program SH, thereby generating a shader program having a form that can be executed in each of the plurality of cores 220. For example, the compiler 210 may perform compilation using a plurality of instruction set architectures (ISAs).

[0043] The compiler 210 may include a monitor-associated code injector 212. In an example embodiment, when a compilation operation is performed in a profile mode, the compiler 210 may use the monitor-associated code injector 212 to insert the monitor-associated code into a portion of the shader program SH. In an example, the monitor-associated code injector 212 may insert the monitor-associated code into at least a portion of a code block included in the shader program SH. The monitor-associated code injector 212 may insert the monitor-associated code into a code block among the code blocks for which runtime performance characteristics need to be monitored.

[0044] In an example, the monitor-associated code injector 212 can insert the monitor-associated code at the starting point or the end point of the code block. In another example, the monitor-associated code injector 212 can insert the monitor-associated code at a point where the monitoring result can be obtained immediately after executing the branch code. The branch code can be a conditional statement, for example, an if statement. In another example, the monitor-associated code injector 212 can insert the monitor-associated code at a point where the compiler 210 can access external resources.

[0045] In an example embodiment, the monitor-associated code may include a monitor code, which is a code for directly monitoring the performance characteristics of a code block including the monitor-associated code therein and recording the monitoring results in the shared memory 230. For example, when the amount of code for monitoring is relatively small, the monitor-associated code injector 212 may insert the monitor code into the code block as the monitor-associated code. However, the embodiment is not limited thereto.

[0046] In another example embodiment, the monitor-associated code may be a branch code indicating branching into the monitor code for monitoring the performance characteristics of the code block and recording the monitoring results in the shared memory 230. For example, when the amount of code for monitoring is relatively large, the monitor-associated code injector 212 may insert the branch code as the monitor-associated code into the code block. However, the embodiment is not limited thereto.

[0047] In an example embodiment, the monitor code inserted by the monitor-associated code injector 212 may export information (e.g., but not limited to, shader program number, timestamp, mask execution, resource scoreboard, branch condition satisfied / unsatisfied, call count of shader program, type of requested resource, and type of used resource by monitoring operation of runtime performance characteristics), and may store the exported information in the shared memory 230. In an example, when a particular code block is executed on one of the plurality of cores 220, the monitor code may derive a timestamp based on time information received from the timer 240.

[0048] The shared memory 230 may store data generated when processing various instructions including the shader program SH received from the processor 100. For example, image data may be generated when the shader program SH is executed in the plurality of cores 220. For example, the image data may be cached in the shared memory 230 and then may be transmitted to the processor 100.

[0049] In an example embodiment, the runtime performance characteristics of each shader program SH obtained according to the monitor association code may be stored in the shared memory 230. For example, the shared memory 230 may include a rendering buffer divided in units of draw calls. The monitor code may record the runtime performance characteristics derived according to the execution of the shader program SH in the rendering buffer corresponding to the draw call to which the corresponding shader program SH belongs. In an example embodiment, in response to the termination of the execution of all shader programs, the shared memory 230 may output the recorded runtime performance characteristics list RT_ST to the processor 100. In another example embodiment, the processor 100 may output an additional signal requesting the runtime performance characteristics list RT_ST to the GPU 200, and the shared memory 230 may output the runtime performance characteristics list RT_ST to the processor 100 based on the output additional signal.

[0050] The GPU according to the present disclosure can insert a monitor-associated circuit (or monitor-associated code) during compilation, thereby easily monitoring runtime performance characteristics in a GPU that executes programs in a parallel manner. In addition, a computing system including a GPU according to the present disclosure can derive runtime performance characteristics in a real program-driven environment, and can perform performance analysis based on the derived runtime performance characteristics, thereby improving the accuracy of the analysis. In addition, in the monitoring operation according to the present disclosure, the shader program is executed during the time that is otherwise wasted due to waiting for shared resources. Therefore, the analysis of the shader program can be performed at a relatively high speed.

[0051] Figure 3 is a flow chart illustrating operation of a computing system in a profile mode according to an example embodiment.

[0052] refer to Figure 3 , the processor 100 may select a shader program SH according to the graphics command, and may output the selected shader program SH (operation S10). For example, the processor 100 may use the shader program manager 110 to select a shader program SH included in the system memory 300 based on the graphics command included in the profile mode command P_CMD, and may output the selected shader program SH to the GPU 200.

[0053] The GPU 200 may insert the monitor-associated code into the received shader program SH and may compile it (operation S20). For example, the compiler 210 that receives the shader program SH may insert a plurality of monitor-associated codes into the shader program SH using the monitor-associated code injector 212. The compiler 210 may compile the shader program into which the monitor-associated code is inserted, thereby converting the shader program into a form that can be executed in the plurality of cores 220. In another example, the monitor-associated code injector 212 may compile the shader program SH and then may also insert the monitor-associated code in a compiled format.

[0054] The GPU 200 may execute the shader program including the monitor association code, and thus may store the derived shader runtime characteristics (operation S30). The GPU 200 may drive the shader program including the monitor association code to be executed in parallel with the plurality of cores 220. For example, in the plurality of cores 220, the shader program may be executed in parallel in a single instruction multiple data (SIMD) manner. The GPU 200 may store the runtime performance characteristics of the shader program derived by executing the monitor association code in the shared memory 230. For example, the GPU 200 may record the runtime performance characteristics of the corresponding shader program included in the shared memory 230 in a rendering buffer corresponding to a draw call to which the shader program belongs.

[0055] The GPU 200 may determine whether the execution of all shader programs received from the processor 100 is terminated (operation S40). When there are remaining shader programs to be executed, the GPU 200 may execute the remaining shader programs in the plurality of cores 220.

[0056] When the execution of all shader programs is terminated, the GPU 200 may output a runtime performance characteristics list RT_ST to the processor 100 (operation S50). The runtime performance characteristics list RT_ST may include runtime performance characteristics for each shader program. For example, the shared memory 230 may store a runtime performance characteristics list RT_ST including runtime characteristics derived from the monitor association code, and may output the runtime performance characteristics list RT_ST to the processor 100 in response to the termination of the execution of all shader programs. In an example embodiment, the processor 100 may generate performance data PF for each shader program based on the runtime performance characteristics list RT_ST using the performance analyzer 120. The performance data PF may reflect runtime performance characteristics with improved accuracy, thereby providing an analysis with improved performance.

[0057] Figure 4is a flowchart illustrating a method of operation of a compiler according to an example embodiment.

[0058] refer to Figure 4 , the compiler 210 may receive the shader program SH (operation S110 ). For example, the shader program SH may be selected and output by the shader program manager 110 .

[0059] The compiler 210 may determine whether the compiler 210 operates in the profile mode based on a signal received from the processor 100 (operation S120). For example, the processor 100 may include a profile mode related signal in the output of the shader program SH, and may output the profile mode related signal along with the output of the shader program SH, and the compiler 210 may determine whether the current mode is the profile mode based on the profile mode related signal. Alternatively, the processor 100 may output a separate profile mode related signal, and the compiler 210 may determine whether the current mode is the profile mode based on the separate profile mode related signal.

[0060] In response to determining that the current mode is not the profile mode, the compiler 210 may perform a compile operation on the received shader program SH (operation S140). On the other hand, in response to determining that the current mode is the profile mode, the compiler 210 may search for the insertion position of the monitor-associated code (operation S130). In an example embodiment, the compiler 210 may search for the insertion position of the monitor-associated code in units of code blocks constituting the shader program SH. For example, a code block may be a collection unit of codes that are sequentially executed without waiting for external resources and / or branching into another code. For example, the compiler 210 may search for the starting point or the ending point of the code block as the insertion position. In another example, the compiler 210 may search for a point at which a monitoring result can be obtained immediately after executing a branch code such as a conditional statement, and the searched point may be used as the insertion position. In another example, the compiler 210 may search for a point at which the compiler 210 accesses an external resource as the insertion position.

[0061] The compiler 210 may insert a plurality of monitor-associated codes into the shader program SH according to the found monitor-associated code insertion position, and may compile the shader program SH (operation S150). However, the embodiment is not limited thereto. The compiler 210 may compile the shader program SH, and then may insert the monitor-associated code into the position found in operation S130 in a compiled format. For example, the operation of searching for the monitor-associated code insertion position and the operation of inserting the monitor-associated code may be performed by the monitor-associated code injector 212 included in the compiler 210.

[0062] Figure 5is a diagram illustrating an insertion monitor association code according to an example embodiment.

[0063] refer to Figure 5 , the shader program SH may include a plurality of code blocks CB_1 to CB_M (where M is a positive integer equal to or greater than 2). Each code block in the plurality of memory blocks may include a plurality of codes. For example, the first code block CB_1 may include P codes C1_1 to C1_P (where P is a positive integer equal to or greater than 2), and the Mth code block CB_M may include Q codes CM_1 to CM_Q (where Q is a positive integer equal to or greater than 2).

[0064] In an example embodiment, each of the plurality of code blocks CB_1 to CB_M may be a code unit that is sequentially executed without waiting for external resources and / or branching into another code. For example, when the Pth code C1_P in the first code block CB_1 is an access code for external resources, in response to the termination of the first code block CB_1, another code block (e.g., the Mth code block CB_M) may be executed at a point where the external resources may be accessed. In another example, the Pth code C1_P in the first code block CB_1 may be a code for a conditional statement (or if statement) and for performing operations when the condition of the conditional statement is satisfied, and the first code CM_1 of another code block (e.g., the Mth code block CB_M) may be a code for performing operations when the condition of the conditional statement is not satisfied (or the operation of the else statement).

[0065] In an example embodiment, during compilation, the monitor association code may be inserted into each code block. In detail, the first monitor association code MAC_1 may be inserted into the first code block CB_1, and the Mth monitor association code MAC_M may be inserted into the Mth code block CB_M. In an example, the monitor association code (e.g., MAC_1 or MAC_M) may be a monitor code, which is a code for directly monitoring the performance characteristics of the corresponding code block. In another example, the monitor association code (e.g., MAC_1 or MAC_M) may be a branch code, which indicates branching into a monitor code for monitoring the performance characteristics of a code block.

[0066] Figure 6 is a view illustrating a monitoring operation according to an example embodiment.

[0067] refer to Figure 6, a first monitor code MC_1 as a monitor association code may be inserted into the first code block CB_1, and an Mth monitor code MC_M as a monitor association code may be inserted into the Mth code block CB_M. In detail, the first monitor code MC_1 may be a code for directly monitoring the runtime performance characteristics of the first code block CB_1, and the Mth monitor code MC_M may be a code for directly monitoring the runtime performance characteristics of the Mth code block CB_M. For example, the Pth code C1_P in the first code block CB_1 may be an access code for a resource RS stored in the shared memory 230. In other words, in response to executing the Pth code C1_P, a resource request RQ_RS may be input into the shared memory 230.

[0068] In an example embodiment, the first monitor code MC_1 may be inserted after the Pth code C1_P. For example, the compiler 210 may insert and compile the first monitor code MC_1 after the Pth code C1_P by using the monitor-associated code injector 212, and may execute the first monitor code MC_1 in the core after executing the Pth code C1_P.

[0069] In an example embodiment, in response to executing the first monitor code MC_1, a first runtime performance characteristic RT_ST_1 may be derived and recorded as a runtime performance characteristic list RT_ST of the shared memory 230. For example, the first runtime performance characteristic RT_ST_1 may include information about a shader program number, a timestamp, and a type of requested resource.

[0070] For example, the Mth code block CB_M may include the first code CM_1 using the resource RS according to the resource request RQ_RS. In other words, the first code block CB_1 may request the external resource RS, and the Mth code block CB_M may use the resource RS when the resource RS is available.

[0071] In an example embodiment, the Mth monitor code MC_M may be inserted at the starting point of the Mth code block CB_M. For example, the compiler 210 may insert the Mth monitor code MC_M at a position before the first code CM_1 in the Mth code block CB_M and compile it by using the monitor-associated code injector 212, and the Mth monitor code MC_M may be the first to be executed among the codes of the Mth code block CB_M.

[0072] In an example embodiment, in response to executing the Mth monitor code MC_M, the Mth runtime performance characteristic RT_ST_M may be derived and recorded as a runtime performance characteristic list RT_ST of the shared memory 230. For example, the Mth runtime performance characteristic RT_ST_M may include information about a shader program number, a timestamp, and a type of used resources.

[0073] Since the timestamp information is included in each of the first runtime performance characteristic RT_ST_1 and the Mth runtime performance characteristic RT_ST_M, the actual runtime performance characteristics including the available time of the external resource RS can be derived. For example, the resource RS stored in the shared memory 230 can be a shared resource (e.g., a texture) required to drive the plurality of cores 220.

[0074] In the code block CB_1 requesting access to the external shared resource RS, the first monitor code MC_1 may be inserted at the end point of the code block, and when the requested resource RS is used in another code block, the monitoring operation of the first monitor code MC_1 may be performed during the waiting time of the resource RS. That is, since the monitoring operation is performed during the time wasted in actual execution, the profile of the shader program may be performed at a relatively high speed.

[0075] Figure 7 is a flow chart showing the operation of a code block having monitor code inserted therein according to an example embodiment. For example, Figure 7 It can be shown Figure 6 The code blocks CB_1 and CB_M are shown.

[0076] refer to Figure 7 , when the first code block CB_1 is executed in the core, it may be determined whether a code for requesting an external resource is executed (operation S210). When the first code block CB_1 is executed in the core and the code for requesting an external resource is not executed, the core may sequentially execute the next code (operation S215).

[0077] When the code for requesting the external resource is executed in the core, the core may execute the first monitor code MC_1 (operation S220). In an example embodiment, the first monitor code MC_1 may be inserted using the monitor-associated code injector 212 included in the compiler 210 when compiling the shader program SH. Based on the execution of the first monitor code MC_1 in the core, the first runtime performance characteristics of the first code block CB_1 may be derived and recorded in the shared memory 230. In an example embodiment, when the first code block CB_1 includes the code for requesting the external resource RS, the first monitor code MC_1 may be inserted at the end point of the first code block CB_1.

[0078] In response to the code for requesting an external resource executed in the first code block CB_1 (e.g., the Pth code C1_P), the availability of the resource of the Mth code block CB_M using the resource RS accessed according to the resource request RQ_RS may be determined (operation S230). Since the resource RS may be requested and used in each of the plurality of cores 220 driven in parallel, there may be a certain waiting time from the resource request RQ_RS to the availability of the resource RS.

[0079] When the external resource RS is available, the core may execute the Mth monitor code MC_M in the Mth code block CB_M (operation S240). In an example embodiment, the Mth monitor code MC_M may be inserted by using the monitor-associated code injector 212 included in the compiler 210 when the shader program SH is compiled. Based on executing the Mth monitor code MC_M in the core, the Mth runtime performance characteristic RT_ST_M of the Mth code block CB_M may be derived and recorded in the shared memory 230. In an example embodiment, when the Mth code block CB_M includes a code that uses the requested external resource RS, the Mth monitor code MC_M may be inserted at the starting point of the Mth code block CB_M.

[0080] Figure 8 is a view illustrating a monitoring operation according to another example embodiment.

[0081] refer to Figure 8 , the first monitor code MC_1a as the monitor association code may be inserted into the first code block CB_1a, and the Mth monitor code MC_Ma as the monitor association code may be inserted into the Mth code block CB_Ma. For example, the first code block CB_1a may include a code for a conditional statement and for performing an operation when the condition of the conditional statement is met. In detail, the first code block CB_1a may include a code for an if statement and for performing an operation when the condition of the if statement is met.

[0082] In an example embodiment, the first monitor code MC_1a may be inserted after the P-th code C1_Pa, which is the last code among the codes for executing the operation when the condition is satisfied. For example, the compiler 210 may insert the first monitor code MC_1a after the P-th code C1_Pa using the monitor-associated code injector 212 and compile it, and the first monitor code MC_1a may be executed in the core after executing the P-th code C1_Pa.

[0083] In an example embodiment, the first runtime performance characteristic RT_ST_1a may be derived according to the execution of the first monitor code MC_1a, and the first runtime performance characteristic RT_ST_1a may be recorded as a runtime performance characteristic list RT_STa of the shared memory 230a. For example, the first runtime performance characteristic RT_ST_1a may include information corresponding to a shader program number, a timestamp, and satisfaction of a condition of a conditional statement.

[0084] For example, the Mth code block CB_Ma may include a code for performing an operation when a condition of the conditional statement of the first code block CB_1a is not satisfied. In detail, the Mth code block CB_Ma may include a code for performing an operation corresponding to an else statement.

[0085] In an example embodiment, the Mth monitor code MC_Ma may be inserted at the starting point of the Mth code block CB_Ma. For example, the compiler 210 may insert and compile the Mth monitor code MC_Ma at a position before the first code CM_1a in the Mth code block CB_Ma by using the monitor-associated code injector 212, and the Mth monitor code MC_Ma may be the first to be executed among the codes of the Mth code block CB_Ma.

[0086] In an example embodiment, the Mth runtime performance characteristic RT_ST_Ma may be derived according to the execution of the Mth monitor code MC_Ma, and the Mth runtime performance characteristic RT_ST_Ma may be recorded as a runtime performance characteristic list RT_STa of the shared memory 230a. For example, the Mth runtime performance characteristic RT_ST_Ma may include information corresponding to the shader program number, the timestamp, and the non-satisfaction of the condition of the conditional statement.

[0087] Fig. 9 is a view illustrating a runtime performance characteristic list according to an example embodiment.

[0088] refer to Fig. 9 , the runtime performance feature list RT_ST may be stored in the shared memory 230. The runtime performance feature list RT_ST may include shader runtime performance features SH_ST1 to SH_STK (where K is a positive integer equal to or greater than 2) for each of the plurality of shader programs. In an example embodiment, each of the shader runtime performance features SH_ST1 to SH_STK may include a runtime performance feature list for a code block (e.g., Figure 6 RT_ST_1 or RT_ST_M).

[0089] In an example embodiment, each of the shader runtime performance characteristics SH_ST1 to SH_STK may include a shader program number 231, a timestamp 232, a mask execution 233, a resource scoreboard 234, a satisfied / unsatisfied branch condition 235, and a call count 236. For example, the shader program number 231 may include a rendering index and draw call information.

[0090] Although not shown in the drawings, each of the shader runtime performance characteristics SH_ST1 to SH_STK may include statistical values ​​about the invocation of commands. For example, each of the shader runtime performance characteristics SH_ST1 to SH_STK may include the number of times a command is called, the number of times an arithmetic logic unit (ALU) is used, the number of times a shared memory is accessed, the number of pipeline stalls and their causes.

[0091] Although not shown in the drawings, each of the shader runtime performance characteristics SH_ST1 to SH_STK may include information related to synchronization. For example, each of the shader runtime performance characteristics SH_ST1 to SH_STK may include shared memory latency, delay time due to synchronization primitives, and execution time of atomic instructions.

[0092] Fig.10 is a view illustrating a monitoring operation according to another example embodiment.

[0093] refer to Fig.10 , the first branch code JMP_MC_1b as the monitor association code may be inserted into the first code block CB_1b, and the Mth branch code JMP_MC_Mb as the monitor association code may be inserted into the Mth code block CB_Mb. In detail, each of the first branch code JMP_MC_1b and the Mth branch code JMP_MC_Mb may be a branch code indicating branching into the general monitor code MCb for monitoring the performance characteristics of the code block. For example, the Pth code C1_Pb of the first code block CB_1b may be an access code for the resource RS stored in the shared memory 230, such as Figure 6 However, the embodiment is not limited thereto. The first code block CB_1b may include code for performing an operation when the condition of the conditional statement is satisfied, as shown above in Figure 8 Described in .

[0094] In an example embodiment, the first branch code JMP_MC_1b may be inserted after the P-th code C1_Pb. For example, the compiler 210 may insert the first branch code JMP_MC_1b after the P-th code C1_Pb and compile it by using the monitor-associated code injector 212, and the first branch code JMP_MC_1b may be executed in the core after the P-th code C1_Pb is executed. Based on the execution of the first branch code JMP_MC_1b, the general monitor code MCb may be executed. In an example embodiment, based on the execution of the general monitor code MCb with respect to the first code block CB_1b, the runtime performance characteristics with respect to the first code block CB_1b may be derived and recorded in a shared memory (e.g., see Figure 6 230).

[0095] For example, the first code CM_1b of the Mth code block CB_Mb may be a code using the resource RS, as described above in Figure 6 However, the embodiment is not limited thereto. The Mth code block CB_Mb may include code for performing an operation when a condition of a conditional statement included in the first code block CB_1b is satisfied, as described above in Figure 8 Described in .

[0096] In an example embodiment, the Mth branch code JMP_MC_Mb may be inserted at the starting point of the Mth code block CB_Mb. For example, the compiler 210 may insert the Mth branch code JMP_MC_Mb at a position before the first code CM_1b in the Mth code block CB_Mb and compile it by using the monitor-associated code injector 212, and the Mth monitor code JMP_MC_Mb may be the first to be executed among the codes of the Mth code block CB_Mb. Based on the execution of the Mth branch code JMP_MC_Mb, the general monitor code MCb may be executed. In an example embodiment, based on the execution of the general monitor code MCb with respect to the Mth code block CB_Mb, the runtime performance characteristics with respect to the Mth code block CB_Mb may be derived and recorded in a shared memory (e.g., see Figure 6 230).

[0097] Fig.11 is a block diagram illustrating operation in profile mode according to another example embodiment. Figure 2 The description of redundant configuration is omitted.

[0098] refer to Fig.11, the shader program manager 205c may be included in the GPU 200c. For example, the processor 100c may output the profile mode command P_CMDc to the GPU 200c, and the shader program manager 205c may output the shader program SHc to the compiler 210c in response to the profile mode command P_CMDc. Therefore, the GPU 200c may output a runtime performance characteristic list RT_STc including runtime performance characteristics about each shader program in response to the profile mode command P_CMDc. The processor 100c may generate performance data PFc based on the runtime performance characteristic list RT_STc output in response to the profile mode command P_CMDc by using the performance analyzer 120c.

[0099] Fig.12 is a block diagram showing a graphics processor according to an example embodiment. Fig.12 As shown, GPU 400 may include a command processor 410 , a pipeline controller 430 , a front-end pipeline 450 , a back-end pipeline 470 , and a programmable processor 490 .

[0100] The command processor 410 may receive a command from the host, may interpret the received command, and thus convert the command into a command that can be processed by the pipeline. The command processor 410 may provide the converted command to the pipeline controller 430.

[0101] The pipeline controller 430 may extract information required in the front-end pipeline 450 and the back-end pipeline 470 from the command received from the command processor 410, and may perform pipeline configuration based on the extracted information. In addition, the pipeline controller 430 may convert the command received from the command processor 410 into a command that can be processed by the front-end pipeline 450 and the back-end pipeline 470, and may provide the converted command to the front-end pipeline 450 and the back-end pipeline 470.

[0102] According to an example embodiment, GPU 400 may insert multiple monitor association codes into a shader program during compilation in profile mode, as described above in Figures 1 to 11 Therefore, the runtime performance characteristics reflecting the real program-driven environment can be easily monitored, and the monitoring results can be obtained.

[0103] According to exemplary embodiments, at least one of the components, elements, modules or units described herein may be embodied as various hardware, software and / or firmware structures that perform the above-mentioned various functions. For example, at least one of these components, elements or units may use a direct circuit structure (e.g., memory, processor, logic circuit, lookup table, etc.), which may perform various functions by the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements or units may be specifically implemented by a module, program or a portion of code that contains one or more executable instructions for performing a specific logical function and is performed by one or more microprocessors or other control devices. In addition, at least one of these components, elements or units may also include a processor, microprocessor, etc. such as a central processing unit (CPU) that performs various functions, or may be implemented by it. Two or more of these components, elements or units may be combined into a single component, element or unit that performs all operations or functions of two or more components, elements or units combined. In addition, at least part of the functions of at least one of these components, elements or units may be performed by another of these components, elements or units. In addition, although the bus is not shown in some block diagrams, the communication between components, elements or units may be performed by the bus. The functional scheme of the above-mentioned example embodiment can be implemented as an algorithm executed on one or more processors. In addition, the components, elements, or units or processing steps represented by the blocks can use any number of related art technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0104] Although one or more exemplary embodiments have been described with reference to the drawings, persons skilled in the art will recognize that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.

Claims

1. A computing system comprising: A memory configured to store a shader program, the shader program comprising a plurality of code blocks, each of the plurality of code blocks comprising a plurality of codes to be executed sequentially; as well as A graphics processing unit (GPU) is configured to obtain the shader program stored in the memory in a profile mode, and the GPU is configured to perform the following operations: inserting one or more monitor association codes into the shader program; compiling the shader program with the one or more monitor associated codes inserted into a language that can be processed by multiple cores; as well as obtaining a runtime performance characteristic of the shader program by executing the compiled shader program and the one or more monitor associated codes, wherein a first code block among the plurality of code blocks includes a first code for requesting a resource shared by at least two or more cores among the plurality of cores, and the inserting includes inserting a first monitor-associated code at a position after the first code, the first monitor-associated code and the first code being the last codes in the first code block, and Wherein, obtaining the runtime performance characteristic comprises: requesting the resource by executing the first code; and During a waiting period until the requested resource is available, the runtime performance characteristics of the first code block are obtained by executing the first monitor-associated code, the first code block being terminated at the moment the requested resource is available.

2. The computing system of claim 1, wherein: The inserting includes inserting the one or more monitor-associated codes into each code block of at least a portion of the plurality of code blocks.

3. The computing system of claim 2, wherein: A second code block among the plurality of code blocks includes a second code for using the resource, and the inserting includes inserting a second monitor-associated code at a starting point of the second code block.

4. The computing system of claim 3, wherein: The runtime performance characteristics of the first code block include information related to at least one of a shader program number, a timestamp generated based on an execution time of the first code block, or the resource.

5. The computing system of claim 2, wherein: A third code block among the plurality of code blocks includes a conditional statement and code for performing an operation when a condition of the conditional statement is satisfied, and The inserting includes inserting a third monitor-associated code at an end point of the third code block.

6. The computing system of claim 5, wherein: Obtaining the runtime performance characteristic includes: obtaining the runtime performance characteristic of the third code block by executing the third monitor-associated code, and The runtime performance characteristic of the third code block includes information related to at least one of a shader program number, a timestamp generated based on an execution time of the third code block, or satisfaction of the conditional statement.

7. The computing system of claim 5, wherein: A fourth code block among the plurality of code blocks includes code for performing an operation when a condition of the conditional statement is not satisfied, and The inserting includes inserting a fourth monitor-associated code at a starting point of the fourth code block.

8. The computing system of claim 7, wherein: Obtaining the runtime performance characteristics includes obtaining the runtime performance characteristics of the fourth code block by executing the fourth monitor associated code, and the runtime performance characteristics of the fourth code block include information related to a shader program number, a timestamp generated based on an execution time of the fourth code block, and at least one of the conditional statements is not satisfied.

9. The computing system of claim 1, wherein: The GPU further includes a shared memory configured to store resources shared by at least two or more cores of the plurality of cores, and Obtaining the runtime performance characteristics includes storing the obtained runtime performance characteristics in the shared memory.

10. The computing system of claim 9, wherein: The GPU is further configured to output the runtime performance characteristics stored in the shared memory based on termination of execution of the shader program.

11. The computing system of claim 1, wherein: The one or more monitor-associated codes include monitor code for directly monitoring performance characteristics of a code block in which the one or more monitor-associated codes are inserted.

12. The computing system of claim 1, wherein: The one or more monitor-associated codes include a branch code that indicates a branch to a general monitor code for monitoring performance characteristics of a code block.

13. A method of operating a computing system, the method comprising: In response to a profile command including a graphics command, outputting a shader program including a plurality of code blocks, each of the plurality of code blocks including a plurality of codes to be executed sequentially; inserting monitor-associated code into each code block of at least a portion of the plurality of code blocks; compiling the shader program into which the monitor associated code is inserted; obtaining a runtime performance characteristic of the shader program by executing the plurality of code blocks and the monitor associated code in a plurality of cores; recording the obtained runtime performance characteristics of the shader program in a memory shared by the plurality of cores; as well as In response to termination of the shader program, outputting the recorded runtime performance characteristics of the shader program, wherein a first code block among the plurality of code blocks includes a first code for requesting a resource shared by at least two or more cores among the plurality of cores, and the inserting includes inserting a first monitor-associated code at a position after the first code, the first monitor-associated code and the first code being the last codes in the first code block, and Wherein, obtaining the runtime performance characteristic comprises: requesting the resource by executing the first code; and During a waiting period until the requested resource is available, the runtime performance characteristics of the first code block are obtained by executing the first monitor-associated code, the first code block being terminated at the moment the requested resource is available.

14. The method according to claim 13, wherein: Obtaining the runtime performance characteristic includes: generating a timestamp according to the execution of the monitor-associated code, wherein the timestamp corresponds to the execution time of a code block including the monitor-associated code.

15. The method according to claim 13, further comprising: Performance data about the shader program is generated based on the output runtime performance characteristics of the shader program.

16. The method according to claim 15, wherein: The generating includes: based on the output runtime performance characteristics of the shader program, analyzing at least one of the total execution time of the shader program, the efficiency of the shader program, the instruction issuance efficiency, and the statistical value on whether the branch condition is satisfied for each branch point.

17. The method according to claim 13, wherein: The runtime performance characteristics of the shader program include information related to at least one of a shader program number, a timestamp, mask execution, a resource scoreboard, branch condition satisfied / unsatisfied, and a call count.

18. A graphics processing unit (GPU), comprising: a compiler configured to obtain a program including a plurality of code blocks, the compiler including a monitor-associated code injector configured to insert one or more monitor-associated codes into each code block of at least a portion of the plurality of code blocks, and the compiler configured to compile the one or more monitor-associated codes and the program in a profile mode; a plurality of cores configured to execute the compiled program and the one or more monitor-associated codes in parallel and configured to obtain runtime performance characteristics of the program based on execution of the one or more monitor-associated codes; as well as a shared memory configured to store the obtained runtime performance characteristics of the program, Each of the plurality of code blocks includes a plurality of codes to be executed sequentially. wherein a first code block among the plurality of code blocks includes a first code for requesting a resource shared by at least two or more cores among the plurality of cores, and the inserting includes inserting a first monitor-associated code at a position after the first code, the first monitor-associated code and the first code being the last codes in the first code block, and Wherein, the first core of the at least two or more cores is configured as: requesting the resource by executing the first code; and During a waiting period until the requested resource is available, the runtime performance characteristics of the first code block are obtained by executing the first monitor-associated code, the first code block being terminated at the moment the requested resource is available.

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