Capacitance Detection Circuit of Touch Device, Touch Device and Electronic Device

Abstract

The present application provides a capacitance detection circuit for a touch device. The capacitance detection circuit is connected to a capacitor under test in a touch screen of the touch device. The capacitance detection circuit includes: a capacitance control delay circuit for generating a first clock signal according to a reference clock signal and the capacitance value of the capacitor under test, the first clock signal and the reference clock signal having a first delay time; a DLL circuit including a digital phase detector and a digitally controlled delay circuit, the digital phase detector outputting a first digital signal; the digitally controlled delay circuit for controlling the delay time of a second clock signal according to the reference clock signal and the first digital signal, the second clock signal and the reference clock signal having a second delay time; when the DLL circuit is locked, the difference between the first delay time and the second delay time is N periods of the reference clock signal, and the first digital signal output by the digital phase detector is used to determine the capacitance value of the capacitor under test.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of capacitance detection, and more particularly, to a capacitance detection circuit, a capacitance detection system, and an electronic device. Background Art

[0002] Capacitive touch devices are widely used in electronic devices. For example, they can be used as input devices to provide input information such as position, movement, force, and duration. The core part of a capacitive touch device is a capacitance detection circuit. In the related art of capacitance detection, time-domain based capacitance detection is a mainstream detection method. The specific implementation is to charge the capacitor to be measured, convert the charge quantity of the capacitor to be measured into voltage, or convert the change in the charge charged into the capacitor to be measured into voltage, and further process the voltage to determine the capacitance value of the capacitor to be measured. For example, the voltage is sampled by an analog-to-digital converter (ADC) and converted into a digital signal, and then capacitance detection can be performed based on the digital signal. Using the above method for capacitance detection is affected by circuit noise, reducing the detection accuracy of capacitance detection. Summary of the Invention

[0003] Embodiments of the present application provide a capacitance detection circuit for a touch device, a touch device, and an electronic device, which can reduce the influence of circuit noise on capacitance detection, thereby improving the detection accuracy of capacitance detection.

[0004] In a first aspect, the present application provides a capacitance detection circuit for a touch device. The touch device further includes a touch screen, the touch screen includes a plurality of capacitors to be measured, the capacitance detection circuit is connected to the capacitors to be measured, and the capacitance detection circuit includes:

[0005] A capacitance control delay circuit for generating a first clock signal according to a reference clock signal and the capacitance value of the capacitor to be measured, wherein the first clock signal has a first delay time relative to the reference clock signal, and the first delay time is positively correlated with the capacitance value of the capacitor to be measured;

[0006] A delay locked loop (DLL) circuit, including: a digital phase detector and a digitally controlled delay circuit. The digital phase detector includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the digital phase detector is connected to the output terminal of the capacitance control delay circuit, and the second input terminal of the digital phase detector is connected to the output terminal of the digitally controlled delay circuit;

[0007] The digital phase detector is configured to receive the first clock signal and the second clock signal output by the digitally controlled delay circuit, and output a first digital signal according to the phases of the first clock signal and the second clock signal. The output terminal of the digital phase detector is used to output the first digital signal;

[0008] The digitally controlled delay circuit is configured to control the delay time of the output second clock signal according to the reference clock signal and the first digital signal, and output the second clock signal to the second input terminal of the digital phase detector. The second clock signal has a second delay time relative to the reference clock signal;

[0009] Wherein, when the DLL circuit is locked, the difference between the first delay time and the second delay time is N periods of the reference clock signal, N is an integer, and the first digital signal output by the digital phase detector when the DLL circuit is locked is used to determine the capacitance value of the capacitor under test.

[0010] In some alternative implementation manners, when the DLL circuit is locked, the first delay time is equal to the second delay time.

[0011] In some alternative implementation manners, the DLL circuit further includes:

[0012] A processing circuit, connected to the digital phase detector and the digitally controlled delay circuit, is configured to receive the first digital signal output by the digital phase detector, process the first digital signal, and output the processed first digital signal to the input terminal of the digitally controlled delay circuit. The processed first digital signal is used to control the delay time of the second clock signal. The processing includes at least one of the following: integration processing, signal amplification or attenuation processing, and filtering processing.

[0013] In some alternative implementation manners, the digitally controlled delay circuit includes:

[0014] A digital-to-analog converter (DAC), including an input terminal and an output terminal. The input terminal is connected to the output terminal of the processing circuit. The DAC is configured to convert the first digital signal obtained by processing by the processing circuit into a first analog signal, and the output terminal is used to output the first analog signal;

[0015] An analog control delay line, including a first input terminal, a second input terminal, and an output terminal. The first input terminal of the analog control delay line is connected to the output terminal of the DAC for receiving the first analog signal. The second input terminal of the analog control delay line is used for inputting the reference clock signal. The analog control delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the reference clock signal. The output terminal of the analog control delay line is used for outputting the second clock signal.

[0016] In some alternative implementation manners, the analog control delay line includes a plurality of cascaded delay units. Each delay unit includes a first end and a second end. The first end of each delay unit is used for inputting the reference clock signal. The second end of each delay unit is used for inputting the first analog signal. The first analog signal is used for controlling the corresponding delay time of each delay unit. The second delay time is the total delay time of the plurality of delay units.

[0017] In some alternative implementation manners, the first analog signal is an analog voltage, and the analog control delay line is a voltage-controlled delay line VCDL.

[0018] In some alternative implementation manners, the capacitance detection circuit further includes:

[0019] A processing unit, configured to determine whether the capacitance value of the capacitor under test changes relative to the base capacitance according to the processed first digital signal output by the processing circuit when the DLL is locked, where the base capacitance is the capacitance value of the capacitor under test when the touch screen is not touched.

[0020] In some alternative implementation manners, the capacitor under test is formed by a detection electrode and a driving electrode in the touch screen, or the capacitor under test is formed by a detection electrode and ground in the touch screen, or the capacitor under test is formed by a detection electrode and an external object in the touch screen.

[0021] In some alternative implementation manners, part or all of the capacitance detection circuit is integrated in a touch sensing chip.

[0022] In a second aspect, the present application further provides a touch device, including:

[0023] A touch screen, including a capacitor under test;

[0024] A capacitance detection circuit as in the first aspect or any one of the alternative implementation manners in the first aspect. The capacitance detection circuit is connected to the capacitor under test, and the capacitance detection circuit is used for detecting the capacitance value of the capacitor under test.

[0025] In a third aspect, the present application also provides an electronic device, including the touch device in the second aspect or any optional implementation manner in the second aspect.

[0026] Based on the above technical solution, by configuring the capacitance control delay circuit and the digitally controlled delay circuit to control the delay time based on the same reference clock signal, it is possible to make the delay time of the second clock signal output by the digitally controlled delay circuit related to the delay time of the first clock signal output by the capacitance control delay circuit. The delay time of the second clock signal is controlled according to the first digital signal output by the digital phase detector, that is, the first digital signal is related to the delay time of the first clock signal, and the delay time of the first clock signal is related to the capacitance value of the capacitor under test. Therefore, the first digital signal is related to the capacitance value of the capacitor under test, and the capacitance value of the capacitor under test can be determined according to the first digital signal.

[0027] Therefore, the present application performs capacitance detection based on the principle that different capacitance values can generate different clock delays, without the need to perform a charging and discharging process in the time domain on the capacitor under test, which is beneficial to reducing the influence of circuit noise on the capacitance detection process, and thus can improve the accuracy of capacitance detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a capacitance detection device according to an embodiment of the present application.

[0029] Figure 2 is a schematic structural diagram of a digitally controlled delay circuit according to an embodiment of the present application.

[0030] Figure 3 is a schematic circuit diagram of a voltage-controlled delay line according to an embodiment of the present application.

[0031] Figure 4 is a schematic block diagram of a capacitance detection system according to an embodiment of the present application.

[0032] Figure 5 is a schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the above objects, features, and advantages of the present application more obvious and understandable, the following detailed description of the specific embodiments of the present application is provided with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art.

[0034] In addition, the described features and structures can be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art should realize that the technical solutions of the present application can also be practiced without one or more of the specific details, or by using other structures, components, etc. In other cases, well-known structures or operations are not shown or described in detail to avoid obscuring the invention.

[0035] Further, the following terms are exemplary and are not intended to be limiting in any way. After reading the present application, those skilled in the art will recognize that these term expressions apply to technologies, methods, physical elements, and systems (whether currently known or not), including their extensions inferred or inferable by those skilled in the art after reading the present application.

[0036] Figure 1 is a schematic block diagram of a capacitance detection circuit 10 according to an embodiment of the present application. The capacitance detection circuit 10 is connected to a capacitor 20 to be measured, as Figure 1 shown, the capacitance detection circuit 10 includes:

[0037] A capacitance control delay circuit 11, configured to generate a first clock signal CLK1 according to a reference clock signal CLK_REF and the capacitance value of the capacitor 20 to be measured. Wherein, the first clock signal CLK1 has a first delay time relative to the reference clock signal CLK_REF, and the first delay time is positively correlated with the capacitance value of the capacitor 20 to be measured;

[0038] A delay locked loop DLL circuit 12, including: a digital phase detector 121 and a digitally controlled delay circuit 123. Wherein, the digital phase detector includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the digital phase detector 121 is connected to the output terminal of the capacitance control delay circuit 11, and the second input terminal of the digital phase detector 121 is connected to the output terminal of the digitally controlled delay circuit 123;

[0039] The digital phase detector 121 is configured to receive the first clock signal CLK1 and a second clock signal CLK2 output by the digitally controlled delay circuit 121, and output a first digital signal D1 according to the phase offset between the first clock signal CLK1 and the second clock signal CLK2. The output terminal of the digital phase detector 121 is configured to output the first digital signal D1;

[0040] The digitally controlled delay circuit 123 is used to control the delay time of the second clock signal CLK2 according to the reference clock signal CLK1 and the first digital signal D1, and input the second clock signal CLK2 to the second input terminal of the digital phase detector 121. The second clock signal CLK2 has a second delay time relative to the reference clock signal CLK_REF;

[0041] Wherein, when the DLL circuit 12 is locked, the difference between the first delay time and the second delay time is N periods of the reference clock signal, N is an integer, and the first digital signal D1 output by the digital phase detector 121 when the DLL circuit 12 is locked is used to determine the capacitance value of the capacitor under test 20.

[0042] In the embodiment of the present application, the reference clock signal CLK_REF can be generated by a reference clock source with low noise. The implementation manner of this reference clock source can refer to the relevant implementation of the prior art, and the present application does not limit this.

[0043] In the embodiment of the present application, the capacitance control delay circuit 11 is a delay circuit controlled by the capacitance value of the capacitor under test 20, that is, the change in the capacitance value of the capacitor under test 20 can change the delay time of the clock signal output by the capacitance control delay circuit 11. Specifically, the capacitance control delay circuit 11 can generate a first clock signal CLK1 according to the capacitance value of the capacitor under test 20. The first clock signal CLK1 has a first delay time relative to the reference clock signal CLK_REF input to the capacitance control delay circuit 11. This first delay time is positively correlated with the capacitance value of the capacitor under test 20, that is, the larger the capacitance value of the capacitor under test 20, the larger the delay time of the first clock signal CLK1 relative to the reference clock signal CLK_REF, that is, the delay time of the first clock signal CLK1 can reflect the magnitude of the capacitance value of the capacitor under test 20.

[0044] The DLL circuit 12 can control the delay time of the output second clock signal CLK2 according to the reference clock signal CLK_REF so that the second clock signal CLK2 and the first clock signal CLK1 are aligned in clock phase. When the DLL circuit 12 is locked, or in other words, when the phases are aligned, the second clock signal CLK2 has a second delay time relative to the reference clock signal CLK_REF. The difference between the first delay time and the second delay time is N periods of the reference clock signal CLK_REF, where N is an integer. Typically, N is zero.

[0045] Specifically, the DLL circuit 12 includes a digital phase detector 121 and a digitally controlled delay circuit 123. The digital phase detector 121 detects the phase relationship between the first clock signal CLK1 output by the capacitance control delay circuit 11 and the second clock signal CLK2 output by the digitally controlled delay circuit 123, and outputs a first digital signal D1. For example, if the phase of the first clock signal CLK1 is ahead of the phase of the second clock signal CLK2, the first digital phase detector 121 may output 1, or if the phase of the first clock signal CLK1 lags behind the phase of the second clock signal CLK2, the first digital phase detector 121 may output 0, or vice versa, as long as the adjustment logic of the delay time of the digitally controlled delay circuit 123 makes corresponding adjustments.

[0046] Further, the input clock signal of the digitally controlled delay circuit 123 is also the reference clock signal CLK_REF. The digitally controlled delay circuit 123 can control the delay time of the second clock signal CLK2 according to the reference clock signal CLK_REF and the first digital signal D1 output by the digital phase detector 121, and output the adjusted second clock signal CLK2 to the second input terminal 1212 of the digital phase detector 121.

[0047] By detecting the phase offset between these two clock signals through the digital phase detector 121 and outputting the corresponding digital signal, further, the digitally controlled delay circuit 123 controls the second delay time of the second clock signal CLK2 relative to the reference clock signal CLK_REF according to this digital signal, and finally locks the delay time between the first clock signal CLK1 and the second clock signal CLK2 to N periods of the reference clock signal CLK. At this time, the DLL circuit 12 reaches stability, or is locked, and the output of the digital phase detector 121 is also stable.

[0048] In a specific implementation, when the DLL circuit 12 is locked, the first delay time of the first clock signal CLK1 relative to the reference clock signal CLK_REF and the second delay time of the second clock signal CLK2 relative to the reference clock signal CLK_REF can be controlled to be equal, that is, the first clock signal CLK1 and the second clock signal CLK2 have the same delay time relative to the reference clock signal CLK_REF. In other words, the first clock signal CLK1 and the second clock signal CLK1 are synchronized. In this case, the working state of the DLL circuit 12 is more stable, and correspondingly, the output of the digital phase detector 121 is also more stable. Hereinafter, taking the first delay time and the second delay time being equal as an example, the embodiments of the present application will be described, but the present application is not limited thereto.

[0049] In summary, in the present application, by designing to use the same reference clock signal as the common reference clock of the capacitor-controlled delay circuit 11 and the digitally controlled delay circuit 123, in this way, the capacitor-controlled delay circuit 11 can generate a first clock signal CLK1 having a first delay time relative to the reference clock signal CLK_REF, and the digitally controlled delay circuit 123 can generate a second clock signal CLK2 having a second delay time relative to the reference clock signal CLK_REF. When the DLL circuit 12 is locked, the first delay time and the second delay time are equal.

[0050] According to the working principle of the capacitor-controlled delay circuit 11, the first delay time of the first clock signal CLK1 output by it relative to the reference clock signal CLK_REF is positively correlated with the capacitance value of the capacitor under test 20, and the second delay time is equal to the first delay time, so the second delay time is positively correlated with the capacitance value of the capacitor under test 20. And the second delay time is controlled according to the first digital signal D1, that is, the second delay time is related to the first digital signal. Therefore, the capacitance value of the capacitor under test 20 can be determined according to the first digital signal. The present application performs capacitance detection based on the principle that different capacitance values can generate different clock delays, and does not require the charging and discharging process of the capacitor under test in the time domain, which is beneficial to reducing the influence of circuit noise on the capacitance detection process, thereby improving the accuracy of capacitance detection.

[0051] Optionally, the digital phase detector 121 can be implemented by a binary phase detector (Binary Phase Detector, Binary PD), or a binary phase frequency detector (Binary Phase Frequency Detector, Binary PFD), etc., or other equivalent circuits can also be used, as long as the phase offset between signals can be converted into a digital signal to gradually approximate the phase of the signal. The present application does not limit this.

[0052] Optionally, in some embodiments of the present application, as Figure 1 shown, the DLL circuit 12 may further include:

[0053] A processing circuit 122, connected to the digital phase detector 121 and the digitally controlled delay circuit 123, is configured to receive the first digital signal D1 output by the digital phase detector 121, process the first digital signal, and output the processed first digital signal D1' to the digitally controlled delay circuit 123, so that the digitally controlled delay circuit 123 can control the delay time of the second clock signal CLK2 based on the processed first digital signal D1'.

[0054] In some embodiments of the present application, the processing of the first digital signal D1 by the processing circuit 122 includes but is not limited to at least one of the following: integration processing, amplification or reduction processing, and filtering processing.

[0055] It can be understood that different DLL circuits 12 correspond to corresponding performance indicators, such as the capacitance value range of capacitors that can be measured, stability, signal-to-noise ratio (SNR), etc. The processing circuit 123 can perform corresponding processing on the first digital signal according to the corresponding performance indicators to meet the performance indicators. In one implementation, the processing circuit 122 can perform integration processing on the first digital signal D1 output by the digital phase detector 121, and further perform amplification or reduction processing so that the capacitance value of the capacitor to be measured falls within the capacitance value range of the capacitance detection circuit. Further, filtering processing can also be performed on the digital signal after amplification or reduction processing. In another implementation, the processing circuit 122 can also first perform amplification or reduction processing on the first digital signal D1, then perform integration processing, and finally perform filtering processing and output to the digitally controlled delay circuit 123, or other processing methods can also be used to process the first digital signal as long as the performance requirements of the DLL circuit can be met. The present application does not limit this.

[0056] It should be noted that the first digital signal D1 output by the digital phase detector 121 for determining the capacitance value of the capacitor to be measured 20 can mean that the first digital signal can be directly used to determine the capacitance value of the capacitor to be measured 10, or it can also mean the signal after the processing circuit 122 processes the first digital signal, that is, D1' can be used to determine the capacitance value of the capacitor to be measured.

[0057] It should also be noted that the first digital signal D1 output by the digital phase detector 121 for determining the capacitance value of the capacitor to be measured 20 can include that the first digital signal D1 output by the digital phase detector 121 is used to determine the change in the capacitance value of the capacitor to be measured 20, or whether a change occurs, etc.

[0058] According to the aforementioned capacitance detection principle, the processed first digital signal D1’ can be used to control the magnitude of the second delay time. That is, the processed first digital signal D1’ is related to the second delay time. Since the second delay time is equal to the first delay time, the processed first digital signal D1’ is related to the first delay time. The first delay time is positively correlated with the capacitance value of the capacitor under test, so the processed first digital signal D1’ is related to the capacitance value of the capacitor under test. Therefore, the capacitance value of the capacitor under test can be determined according to the processed first digital signal D1’.

[0059] Optionally, in some embodiments, the capacitor under test 20 can be, for example but not limited to, a sensing element in a touch device, such as a capacitor under test in the touch screen of a capacitive touch device. Specifically, the touch device includes a touch panel, which can also be referred to as a touch screen. The capacitor under test 20 is formed by a driving electrode and a detection electrode on the touch panel, or the capacitor under test 20 can be formed by a detection electrode on the touch panel and ground, or the capacitor under test 20 can be formed by a detection electrode on the touch panel and an external object. Here, the external object is a conductor, such as but not limited to a user's finger, etc. In this scenario, the capacitance value of the capacitor under test 20 can be used to determine whether the touch device is touched. For example, it can be determined whether the touch device is touched according to whether the capacitance value of the capacitor under test 20 changes. Optionally, whether the capacitance value of the capacitor under test 20 changes can be whether the capacitance value of the capacitor under test 20 changes relative to the base capacitance. Here, the base capacitance is the capacitance value of the capacitor under test 20 when it is not contacted or approached by an external object, and this capacitance value can also be called the nominal capacitance.

[0060] Optionally, in some embodiments of the present application, the capacitance detection circuit 10 may further include:

[0061] A processing unit, configured to determine whether the capacitance value of the capacitor under test changes relative to the base capacitance according to the processed first digital signal output by the processing circuit when the DLL is locked, where the base capacitance is the capacitance value of the capacitor under test 20 when it is not contacted or approached by an external object. For example, taking a touch device as an example, the base capacitance is the capacitance value of the capacitor under test 20 when the touch screen of the touch device is not touched by an external object.

[0062] Taking the above capacitive touch detection scenario as an example, the processing unit can first determine the first digital signal output by the processing circuit 122 when the touch device is not touched, denoted as the nominal digital signal D1’_REF. This nominal digital signal D1’_REF corresponds to the basic capacitance C_REF of the capacitor to be measured, and the two can be obtained through conversion by a specific relationship.

[0063] Furthermore, it can be determined whether the touch device is touched according to the processed first digital signal D1’. For example, it can be determined whether the touch device is touched according to the change of the first digital signal D1’ output by the processing circuit 122 relative to the nominal digital signal D1’_REF. As an example, if the processed first digital signal D1’ changes relative to the nominal digital signal D1’_REF, or the change amount is greater than a certain threshold, it can be determined that the touch device is touched; otherwise, it is determined that the touch device is not touched.

[0064] In other embodiments, the processed first digital signal D1’ can also be further processed and converted into a corresponding capacitance value C, and then it can be further determined whether the touch device is touched according to the capacitance value C. For example, it can be determined whether the touch device is touched according to the change of the capacitance value C corresponding to the processed first digital signal D1’ relative to the basic capacitance C_REF. As an example, if the capacitance value C corresponding to the processed first digital signal changes relative to the basic capacitance C_REF, or the change amount is greater than a certain threshold, it can be determined that the touch device is touched; otherwise, it is determined that the touch device is not touched.

[0065] Optionally, in some embodiments, the processing unit can be the processing unit in the device or apparatus where the capacitance detection circuit 10 is installed. For example, if part or all of the capacitance detection circuit 10 can be integrated in the touch sensing chip of the touch device, the touch sensing chip is electrically connected to the touch panel and is used to drive the touch panel to perform touch sensing operations. The processing unit can be the processing unit in the touch device, or it can also be the main control module in the electronic device where the touch device is located.

[0066] It should be understood that in the embodiments of the present application, the digitally controlled delay circuit 123 can provide clock signals with different phases through internal delay stages, and it can be implemented by any circuit that controls the delay time according to digital signals. The embodiments of the present application do not limit this.

[0067] Next, in combination with Figure 2 , a typical implementation of the digitally controlled delay circuit 123 will be described. As Figure 2 shown, the digitally controlled delay circuit 123 includes:

[0068] The digital-to-analog converter DAC1231 includes an input end and an output end. The input end is connected to the output end of the processing circuit 122. The DAC1231 is configured to convert the first digital signal D1' obtained after being processed by the processing circuit 122 into a first analog signal A1, and the output end is used to output the first analog signal A1.

[0069] The analog control delay line 1232 includes a first input end, a second input end, and an output end. The first input end of the analog control delay line 1232 is connected to the output end of the DAC1231 for receiving the first analog signal A1. The second input end of the analog control delay line 1232 is used to input the reference clock signal CLK_REF. The analog control delay line 1232 is configured to control the delay time of the output second clock signal CLK2, i.e., the second delay time, according to the first analog signal A1 and the reference clock signal CLK_REF, and the output end of the analog control delay line 1232 is used to output the second clock signal CLK2.

[0070] Since the DLL circuit 12 is a negative feedback system, through the negative feedback mechanism, the phase misalignment between the first clock signal CLK1 and the second clock signal CLK2 will be gradually reduced until it disappears. At this time, the analog signal output by the DAC remains stable and the DLL circuit 12 is locked.

[0071] In some embodiments, the first analog signal A1 may be an analog voltage or an analog current. Correspondingly, the analog control delay line 1232 may be a voltage-controlled delay line (VCDL) or a current-controlled delay line (CCDL). Hereinafter, taking the first analog signal as an analog voltage as an example, a typical implementation of the VCDL will be described. Of course, it may also be implemented in other ways, which is not limited herein.

[0072] As Figure 3 shown, the analog control delay line 1232 includes a plurality of cascaded delay units 12321. Each delay unit 12321 includes a first end and a second end. The first end of each delay unit 12321 is used to input the reference clock signal CLK_REF, and the second end of each delay unit 12321 is used to input the first analog signal (taking the first analog signal as an analog voltage V-REF as an example). The first analog signal V-REF is used to control the corresponding delay time of each delay unit 12321, and the delay time of the second clock signal CLK2 is the total delay time of the plurality of delay units.

[0073] Specifically, each stage of the VCDL delay unit can output a certain phase shift. The degree of phase shift output by each stage of the VCDL delay unit is controlled by the analog voltage V-REF. The total delay of all the delay units constitutes the delay of the analog control delay line 1232, that is, the delay time of the second clock signal CLK2. The digital phase detector 121 compares the phase of the first clock signal CLK1 and the second clock signal CLK2 and outputs a corresponding digital signal. This digital signal is processed and then converted into an analog signal, such as the analog voltage V-REF. This analog voltage V-REF is used to change the delay time of the delay unit in the VCDL.

[0074] In some embodiments, the analog control delay line 1232 can use inverters to implement the delay unit and use a valid state machine to select the output signal.

[0075] Specifically, in the VCDL, a single delay unit represents the minimum delay time, such as the delay time of a basic inverter. Since each inverter can shift the phase by 180 degrees, the VCDL can output at the even-numbered inverter outputs to provide the corresponding phase. The VCDL needs to select the signal with the phase closest to the phase of the first clock signal CLK1 as the output clock signal for feedback. Therefore, the output signal to be implemented in the VCDL is not necessarily the output of the last stage of the VCDL, that is, the second clock signal is not necessarily output at the last stage of the VCDL, but it must be output at the position closest to the phase of the first clock signal CLK1. Specifically, a corresponding signal can be generated by the valid state machine to select the output signal.

[0076] In a specific implementation, the delay of each delay unit has a certain relationship with the RC time constant in the delay unit. The larger the time constant, the larger the delay. The delay of each stage of the delay unit can be adjusted by changing the time constant of the delay unit, such as the impedance R or the load capacitance C.

[0077] Therefore, in the embodiments of the present application, by configuring the capacitance control delay circuit 11 and the analog control delay line 1232 to control the delay time based on the same reference clock signal, it is possible to make the delay time of the second clock signal related to the delay time of the first clock signal. The delay time of the second clock signal is controlled by the first analog signal A1, so it is possible to make the first analog signal A1 related to the delay time of the first clock signal. Further, the first analog signal A1 is obtained according to the processed first digital signal. Therefore, the processed first digital signal is related to the delay time of the first clock signal, that is, related to the capacitance value of the capacitor under test. Therefore, the change in the capacitance value of the capacitor under test can be determined according to the processed first digital signal.

[0078] The present application also provides a capacitance detection system 40, as Figure 4 shown. The capacitance detection system 40 includes: a capacitor under test 41 and a capacitance detection circuit 42. The capacitance detection circuit 42 is connected to the capacitor under test 41, and the capacitance detection circuit 42 is configured to detect the capacitance value of the capacitor under test 41.

[0079] Optionally, in some embodiments, the capacitance detection system is a touch device, and the capacitance value of the capacitor under test is used to determine whether the touch device is touched.

[0080] Optionally, the touch device may be a capacitive touch device. For example, a mutual capacitance touch device or a self-capacitance touch device.

[0081] In a mutual capacitance-based touch system, the touch screen may include (for example) a driving area and a sensing area, such as driving lines (or driving electrodes) and sensing lines (or detection electrodes). As an example, the driving lines may form multiple rows, and the sensing lines may form multiple columns (for example, orthogonal). Touch pixels may be disposed at the intersections of the rows and columns. During operation, the rows may be excited with an alternating current (AC) waveform, and mutual capacitance may be formed between the rows and columns of the touch pixels. When an object approaches the touch pixel, some of the charges coupled between the row and column of the touch pixel may instead be coupled to the object. This reduction in the charges coupled to the touch pixel may result in a net reduction in the mutual capacitance between the row and column and a reduction in the AC waveform coupled to the touch pixel. This reduction in the charge-coupled AC waveform may be detected and measured by the touch system to determine whether there is a touch and the touch position of the object on the touch screen. For a mutual capacitance touch screen, the capacitor under test is formed by the detection electrode and the driving electrode on the mutual capacitance touch screen.

[0082] In contrast, in a self-capacitance-based touch system, each touch pixel may be formed by an individual electrode that forms a self-capacitance to ground. When an object approaches the touch pixel, another capacitance to ground may be formed between the object and the touch pixel. This additional capacitance to ground may cause a net increase in the self-capacitance experienced by the touch pixel. This increase in self-capacitance may be detected and measured by the touch system to determine whether there is a touch and the position of the object when it touches the touch screen. For a self-capacitance touch screen, the capacitor under test is formed by the detection electrode on the touch screen and ground, or the capacitor under test 20 is formed by the detection electrode on the touch screen and an external object. The external object is, for example but not limited to, a conductive object such as a user's finger.

[0083] The touch panel of the touch device of the present application can be a touch screen externally attached above the display panel, or integrated in the display panel (Incell), etc. All these technical solutions should fall within the protection scope of the present application.

[0084] In addition, the capacitance detection system 40 can also be a fingerprint sensing device. Correspondingly, the capacitance detection circuit 42 is the capacitance detection circuit in the fingerprint sensing device. The capacitor under test 41 is the capacitor under test in the fingerprint sensing device.

[0085] The embodiment of the present application also provides an electronic device. Figure 5 FIG. shows a schematic structural diagram of the electronic device 50 according to the embodiment of the present application, as Figure 5 shown. The electronic device may include a capacitance detection system 51, and the capacitance detection system 51 can be Figure 4 the capacitance detection system 40 in

[0086] It should be understood that the electronic device 100 according to the embodiment of the present application may include, but is not limited to, a smart phone, a tablet computer, a computer, a laptop computer, a smart wearable device, a smart door lock, etc. To implement the basic functions of the electronic device, in addition to including the modules or components shown above, the electronic device in the embodiment of the present application may also include other necessary modules or components. Taking the electronic device as a smart phone as an example, it may further include a communication module, a speaker, a microphone, a battery, etc.

[0087] The above-mentioned processing unit may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step executed by the above-mentioned processing unit can be completed by the integrated logic circuit of the hardware in the processor or instructions in the form of software. The above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by a hardware decoding processor, or completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0088] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A capacitance detection circuit for a touch device, the touch device further comprising a touch screen, the touch screen including a plurality of capacitors to be measured, the capacitance detection circuit being connected to the capacitors to be measured, characterized in that, the capacitance detection circuit includes: a capacitance control delay circuit for generating a first clock signal according to a reference clock signal and the capacitance value of the capacitor to be measured, wherein the first clock signal has a first delay time relative to the reference clock signal, and the first delay time is positively correlated with the capacitance value of the capacitor to be measured; a delay-locked loop circuit including a digital phase detector and a digitally controlled delay circuit, wherein the digital phase detector includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the digital phase detector being connected to the output terminal of the capacitance control delay circuit, and the second input terminal of the digital phase detector being connected to the output terminal of the digitally controlled delay circuit; the digital phase detector is a binary phase detector or a binary phase discriminator and frequency discriminator; the digital phase detector is configured to receive the first clock signal and a second clock signal output by the digitally controlled delay circuit, and output a first digital signal according to the phases of the first clock signal and the second clock signal, and the output terminal of the digital phase detector is configured to output the first digital signal; the digitally controlled delay circuit is configured to control the delay time of the output second clock signal according to the reference clock signal and the first digital signal, and output the second clock signal to the second input terminal of the digital phase detector, the second clock signal having a second delay time relative to the reference clock signal; wherein, when the delay-locked loop circuit is locked, the difference between the first delay time and the second delay time is N periods of the reference clock signal, N being an integer, and the first digital signal output by the digital phase detector when the delay-locked loop circuit is locked is used to determine the capacitance value of the capacitor to be measured.

2. The capacitance detection circuit according to claim 1, characterized in that, when the delay-locked loop circuit is locked, the first delay time is equal to the second delay time.

3. The capacitance detection circuit according to claim 1, characterized in that, the delay-locked loop circuit further includes: a processing circuit connected to the digital phase detector and the digitally controlled delay circuit, configured to receive the first digital signal output by the digital phase detector, process the first digital signal, and output the processed first digital signal to the input terminal of the digitally controlled delay circuit, the processed first digital signal being used to control the delay time of the second clock signal, and the processing includes at least one of the following: integral processing, signal amplification or reduction processing, filtering processing.

4. The capacitance detection circuit according to claim 3, characterized in that, the digitally controlled delay circuit includes: A digital-to-analog converter, including an input end and an output end, the input end is connected to the output end of the processing circuit, the digital-to-analog converter is used to convert a first digital signal obtained by processing through the processing circuit into a first analog signal, and the output end is used to output the first analog signal; An analog control delay line, including a first input end, a second input end and an output end, the first input end of the analog control delay line is connected to the output end of the digital-to-analog converter for receiving the first analog signal, the second input end of the analog control delay line is used to input the reference clock signal, the analog control delay line is used to control the delay time of the second clock signal according to the first analog signal and the reference clock signal, and the output end of the analog control delay line is used to output the second clock signal.

5. The capacitance detection circuit according to claim 4, characterized in that, the analog control delay line includes a plurality of cascaded delay units, each delay unit includes a first end and a second end, the first end of each delay unit is used to input the reference clock signal, the second end of each delay unit is used to input the first analog signal, the first analog signal is used to control the corresponding delay time of each delay unit, and the second delay time is the total delay time of the plurality of cascaded delay units.

6. The capacitance detection circuit according to claim 4, characterized in that, the first analog signal is an analog voltage, and the analog control delay line is a voltage-controlled delay line.

7. The capacitance detection circuit according to claim 3, characterized in that, the capacitance detection circuit further includes: a processing unit, configured to determine whether there is a change in the capacitance value of the capacitor under test relative to the basic capacitance according to the processed first digital signal output by the processing circuit when the delay-locked loop circuit is locked, wherein the basic capacitance is the capacitance value of the capacitor under test when it is not contacted or approached by an external object.

8. The capacitance detection circuit of the touch device according to claim 7, characterized in that, the capacitor under test is formed by a detection electrode and a driving electrode in the touch screen, or the capacitor under test is formed by a detection electrode in the touch screen and ground, or the capacitor under test is formed by a detection electrode in the touch screen and an external object.

9. The capacitance detection circuit of the touch device according to claim 1, characterized in that, part or all of the capacitance detection circuit is integrated in a touch sensing chip.

10. A touch device, characterized in that, including: a touch screen, including a capacitor under test; the capacitance detection circuit according to any one of claims 1 to 9, the capacitance detection circuit is connected to the capacitor under test, and the capacitance detection circuit is used to detect the capacitance value of the capacitor under test.

11. An electronic device, characterized in that, including the touch device according to claim 10. ​

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