Image Sensor

Abstract

An image sensor is provided. The image sensor may include: a substrate including a first surface and a second surface opposite to each other; a device isolation layer extending into the substrate and having a surface flush with the second surface of the substrate; an active area defined by the device isolation layer; a photoelectric device located in the substrate and configured to convert light into charge; a microlens on the first surface; a transfer gate in the active area on the second surface and configured to transfer charge to a floating diffusion node; and a source follower gate on the device isolation layer and the active area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0001561 filed on January 7, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to image sensors. Background Art

[0004] An image sensor is a device, such as a semiconductor device, that converts an optical image into an electrical signal. Image sensors can be divided into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors can be abbreviated as CMOS image sensors (CIS). CIS can include a plurality of pixels arranged in two dimensions. Each pixel can include an optoelectronic device such as a photodiode (PD). The optoelectronic device can convert incident light into an electrical signal.

[0005] Recently, the continuous development of the computer industry and the communication industry has led to a growing demand for image sensors with improved performance in various fields such as digital cameras, portable cameras, personal communication systems (PCS), game devices, security cameras, medical micro cameras, robots, etc. In addition, as semiconductor devices become more integrated, image sensors are also more integrated. Summary of the invention

[0006] Aspects of the present disclosure provide image sensors, including more highly integrated image sensors.

[0007] However, aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to some example embodiments of the present invention, an image sensor may be provided. The image sensor may include: a substrate having a first surface and a second surface opposite to each other; a device isolation layer extending into the substrate and having a surface flush with the second surface of the substrate; an active area defined by the device isolation layer; an optoelectronic device located in the substrate and configured to convert light into charge; a microlens on the first surface; a transfer gate, in the active area on the second surface, the transfer gate is configured to transfer charge to a floating diffusion node; and a source follower gate extending over the device isolation layer and the active area.

[0009] According to some example embodiments of the present invention, an image sensor may be provided. The image sensor includes: a substrate including a first surface and a second surface opposite to each other; a device isolation layer extending into the substrate and having a surface flush with the second surface of the substrate; an active area defined by the device isolation layer, the active area including first to third shared pixel areas sequentially arranged in a first direction, wherein the first to third shared pixel areas respectively include first to third source follower gates, wherein each of the first to third shared pixel areas includes at least four pixel areas arranged in a grid, wherein at least two pixel areas are aligned in the first direction, and at least two pixel areas are aligned in a second direction intersecting the first direction, wherein the first source follower gate extends over at least two pixel areas of the first shared pixel area, wherein the second source follower gate extends over at least two pixel areas of the second shared pixel area, and wherein the third source follower gate extends over at least two pixel areas of the third shared pixel area.

[0010] According to some example embodiments of the present invention, an image sensor may be provided. The image sensor includes: a substrate including an active region and a device isolation layer; first to fourth photoelectric devices located in the active region; first to fourth transfer transistors located between the first to fourth photoelectric devices and a floating diffusion node on the substrate, respectively; a source follower transistor on the substrate, wherein the source follower transistor has a floating diffusion node as a gate node; and a selection transistor connected in series with the source follower transistor on the substrate, wherein the source follower transistor is located on the active region and the device isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various aspects and features of the present disclosure, including those discussed above, will become more apparent by describing in detail some example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating an image sensor according to some embodiments of the present disclosure;

[0013] Figure 2 is a conceptual diagram showing a sensor array of an image sensor according to some embodiments of the present disclosure;

[0014] Figure 3 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure;

[0015] Figure 4 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure;

[0016] Figure 5 is along Figure 4 A cross-sectional view taken along line AA';

[0017] Figure 6 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure;

[0018] Figure 7 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure;

[0019] Figure 8 It is shown Figure 7 A plan view of the shape of a source follower gate;

[0020] Fig. 9 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure;

[0021] Fig.10 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure;

[0022] Fig.11 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure;

[0023] Fig.12 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure;

[0024] Fig.13 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure;

[0025] Fig.14 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure; and

[0026] Fig.15 It is shown Fig.14 A plan view of the shape of the select gate. DETAILED DESCRIPTION

[0027] In the following, reference will be made to Figures 1 to 5 An image sensor according to some embodiments of the present disclosure is described.

[0028] Figure 1 is a block diagram illustrating an image sensor according to some embodiments of the present disclosure.

[0029] Reference Figure 1According to some embodiments of the present disclosure, the image sensor includes: a sensor array 10 in which pixels including optoelectronic devices are two-dimensionally arranged, a timing generator 20, a row decoder 30, a row driver 40, a correlated double sampler (CDS) 50, an analog-to-digital converter (ADC) 60, a latch 70, and a column decoder 80. Figure 1 There may be other components in the image sensor, but their discussion is omitted here for brevity.

[0030] The sensor array 10 includes a plurality of unit pixels arranged in two dimensions. The plurality of unit pixels can convert an optical image into an electrical output signal. The sensor array 10 is driven by receiving a plurality of drive signals such as a row selection signal, a reset signal, and a charge transfer signal from a row driver 40. In addition, the converted electrical output signal is provided to a correlated double sampler 50 through a vertical signal line.

[0031] The timing generator 20 provides timing signals and control signals to the row decoder 30 and the column decoder 80 .

[0032] The row driver 40 provides a plurality of driving signals configured to drive a plurality of unit pixels to the sensor array 10 having active pixels according to the decoding result in the row decoder 30. Generally, when the unit pixels are arranged in a matrix form, the driving signal is provided for each row.

[0033] The correlated double sampler 50 receives and holds and samples the output signal formed on the active pixel sensor array 10 through the vertical signal line. That is, a specific noise level and a signal level based on the output signal are double sampled to output a difference level corresponding to the difference between the noise level and the signal level.

[0034] The analog-to-digital converter 60 converts an analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

[0035] The latch 70 latches the digital signal and sequentially outputs the latched signal to the image signal processing unit ( Figure 1 not shown).

[0036] Figure 2 is a conceptual diagram illustrating a sensor array of an image sensor according to some embodiments of the present disclosure.

[0037] Reference Figure 2 , the sensor array 10 may be arranged such that the plurality of pixels P1 to P24 are aligned in a plurality of rows and columns. Figure 2 24 pixels in four rows and six columns are shown, but this is only an example and the present embodiment is not limited thereto. That is, the number of rows, columns, and pixels of the sensor array 10 may vary.

[0038] The plurality of pixels P1 to P24 may be aligned in a first direction X and a second direction Y. The second direction Y may be a direction intersecting the first direction X. For example, the second direction Y may be a direction perpendicular to the first direction X. The first direction X may be a row direction in which the plurality of pixels P1 to P24 are aligned. The second direction Y may be a column direction in which the plurality of pixels P1 to P24 are aligned.

[0039] A plurality of pixels P1 to P24 may constitute a plurality of shared pixels SP1 to SP6. Specifically, the first pixel P1 to the fourth pixel P4 may constitute a first shared pixel SP1, and the fifth pixel P5 to the eighth pixel P8 may constitute a second shared pixel SP2. The ninth pixel P9 to the twelfth pixel P12 may constitute a third shared pixel SP3, and the thirteenth pixel P13 to the sixteenth pixel P16 may constitute a fourth shared pixel SP4. The seventeenth pixel P17 to the twentieth pixel P20 may constitute a fifth shared pixel SP5, and the twenty-first pixel P21 to the twenty-fourth pixel P24 may constitute a sixth shared pixel SP6.

[0040] The first to third shared pixels SP1 to SP3 may be sequentially arranged in the first direction X. The fourth to sixth shared pixels SP4 to SP6 may be sequentially arranged in the first direction X. In other words, the first to third shared pixels SP1 to SP3 may be sequentially arranged in the first row in the first direction X, and the fourth to sixth shared pixels SP4 to SP6 may be sequentially arranged in the second row in the first direction X. The first to third shared pixels SP1 to SP3 and the fourth to sixth shared pixels SP4 to SP6 may be aligned in the second direction Y. Specifically, the first to fourth shared pixels SP1 and SP4 are aligned in the second direction Y, and the second to fifth shared pixels SP2 and SP5 are aligned in the second direction Y. In addition, the third to sixth shared pixels SP3 and SP6 may be aligned in the second direction Y. In other words, the first to second shared pixels SP1 and SP2 may be aligned in the first column in the second direction Y, the third to fourth shared pixels SP3 and SP4 may be aligned in the second column in the second direction Y, and the fifth to sixth shared pixels SP5 and SP6 may be aligned in the third column in the second direction Y.

[0041] The first pixel P1 and the second pixel P2 of the first shared pixel SP1 are aligned with each other in the first direction X, and the third pixel P3 and the fourth pixel P4 are aligned with each other in the first direction X. The first pixel P1 and the third pixel P3 are aligned with each other in the second direction Y, and the second pixel P2 and the fourth pixel P4 are aligned with each other in the second direction Y. In other words, the first pixels P1 to the fourth pixels P4 of the first shared pixel SP1 may be arranged in a grid, in which at least two pixels (e.g., the first pixel P1 and the second pixel P2) are aligned in the first direction X, and at least two pixels (e.g., the first pixel P1 and the third pixel P3) are aligned in the second direction Y.

[0042] Figure 3 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure. Figure 3 yes Figure 2 : An equivalent circuit diagram of the first shared pixel SP1.

[0043] Reference Figure 3 The first shared pixel SP1 includes first to fourth photoelectric devices PD1 to PD4, first to fourth transfer transistors TX1 to TX4, a reset transistor RX, a first source follower SF, and first and second selection transistors SX1 and SX2.

[0044] The first to fourth photoelectric devices PD1 to PD4 absorb incident light and accumulate charges corresponding to the amount of light. A photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof may be applied to the first to fourth photoelectric devices PD1 to PD4. Figure 3 The photodiode shown is an example.

[0045] The first photoelectric device PD1 to the fourth photoelectric device PD4 are respectively coupled to the first transfer transistor TX1 to the fourth transfer transistor TX4, and the first transfer transistor TX1 to the fourth transfer transistor TX4 are configured to transfer the accumulated charge to the floating diffusion node FD. Specifically, the first photoelectric device PD1 is coupled to the first transfer transistor TX1, and the second photoelectric device PD2 is coupled to the second transfer transistor TX2. The third photoelectric device PD3 is coupled to the third transfer transistor TX3, and the fourth photoelectric device PD4 is coupled to the fourth transfer transistor TX4.

[0046] Each transmission transistor TX1 to TX4 includes a respective transmission gate TG1 to TG4. The first transmission transistor TX1 includes a first transmission gate TG1, and the second transmission transistor TX2 includes a second transmission gate TG2. The third transmission transistor TX3 includes a third transmission gate TG3, and the fourth transmission transistor TX4 includes a fourth transmission gate TG4.

[0047] The first transfer gate TG1 is included in the first pixel P1, and the second transfer gate TG2 is included in the second pixel P2. The third transfer gate TG3 is included in the third pixel P3, and the fourth transfer gate TG4 is included in the fourth pixel P4.

[0048] The floating diffusion node FD is a region for converting charges into voltage. Since the floating diffusion node FD has parasitic capacitance, charges are accumulatively stored.

[0049] The first source follower SF amplifies a potential change of the floating diffusion node FD receiving charges accumulated in each of the first to fourth photo devices PD1 to PD4 and outputs the potential change to the output line VOUT through the first and second selection transistors SX1 and SX2 .

[0050] That is, the first source follower SF includes a first source follower SF1 and a first source follower gate SFG. The first source follower gate SFG receives the voltage of the floating diffusion node FD as a signal and amplifies the signal.

[0051] The first source follower SF may be disposed in only one first shared pixel SP1. The first source follower SF may be responsible for amplifying the first pixel P1 to the fourth pixel P4. That is, the first pixel P1 to the fourth pixel P4 may share one first source follower SF.

[0052] The reset transistor RX periodically resets the floating diffusion node FD. The reset transistor RX may be formed by a MOS transistor that is driven by a bias voltage provided by a reset gate RG that applies a predetermined bias voltage (i.e., a reset signal). When the reset transistor RX is turned on by the bias voltage provided by the reset gate RG, a predetermined potential provided to the drain of the reset transistor RX, such as a power supply voltage VDD, is applied to the floating diffusion node FD.

[0053] Only one reset transistor RX may be disposed in the first shared pixel SP1. The reset transistor RX may be configured to reset each of the first to fourth pixels P1 to P4. That is, the first to fourth pixels P1 to P4 may share one reset transistor RX.

[0054] The first selection transistor SX1 and the second selection transistor SX2 may select a pixel to be read based on a row. Each of the first selection transistor SX1 and the second selection transistor SX2 may be formed by a MOS transistor driven by a bias voltage (i.e., a row selection signal) provided by the first selection gate SEL1 and the second selection gate SEL2. When the first selection transistor SX1 and / or the second selection transistor SX2 is turned on by the bias voltage provided by the first selection gate SEL1 and the second selection gate SEL2, the output of the first source follower SF may be provided to the drain of the first selection transistor SX1 and the second selection transistor SX2 and transmitted to the output line VOUT.

[0055] The first selection transistor SX1 and the second selection transistor SX2 may be arranged only in the first shared pixel SP1. The first selection transistor SX1 and the second selection transistor SX2 may be configured to select each of the first pixel P1 to the fourth pixel P4. That is, the first pixel P1 to the fourth pixel P4 may share two of the first selection transistor SX1 and the second selection transistor SX2.

[0056] The first selection transistor SX1 includes a first selection gate SEL1, and the second selection transistor SX2 includes a second selection gate SEL2.

[0057] The circuit structure of the first shared pixel SP1 can be Figure 2 The circuit structures of the other shared pixels (ie, the second shared pixel SP2 to the sixth shared pixel SP6) are the same. In order to simplify the description, the description of the circuit structures of the second shared pixel SP2 to the sixth shared pixel SP6 will be omitted.

[0058] Figure 4 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure. Figure 4 This is the layout of the first shared pixel SP1. Figure 2 The second to sixth shared pixels SP2 to SP6 may have the same layout as that of the first shared pixel SP1. In order to simplify the description, the description of the second to sixth shared pixels SP2 to SP6 is omitted.

[0059] Reference Figure 4According to some embodiments of the present disclosure, the image sensor includes a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, a fourth pixel region PR4, a device isolation layer 130, a first transfer gate TG1 to a fourth transfer gate TG4, a first floating diffusion node FD1 to a fourth floating diffusion node FD4, a reset gate RG, a dummy gate Dummy, a first source follower gate SFG, a first selection gate SEL1, a second selection gate SEL2, a first wiring 300 and a second wiring 200.

[0060] Figure 2 The first shared pixel SP1 includes first to fourth pixels P1 to P4. The first to fourth pixels P1 to P4 may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4, respectively. The first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 may be separated from each other by a device isolation layer 130.

[0061] The first pixel region PR1 and the second pixel region PR2 are aligned with each other in the first direction X, and the third pixel region PR3 and the fourth pixel region PR4 are aligned with each other in the first direction X. The first pixel region PR1 and the third pixel region PR3 are aligned with each other in the second direction Y, and the second pixel region PR2 and the fourth pixel region PR4 are aligned with each other in the second direction Y.

[0062] The device isolation layer 130 may completely separate the first pixel region PR1, the second pixel region PR2, the third pixel region PR3 and the fourth pixel region PR4. The device isolation layer 130 may electrically isolate the first pixel region PR1, the second pixel region PR2, the third pixel region PR3 and the fourth pixel region PR4.

[0063] The first transfer gate TG1 may be located in the first pixel region PR1, and the second transfer gate TG2 may be located in the second pixel region PR2. The third transfer gate TG3 may be located in the third pixel region PR3, and the fourth transfer gate TG4 may be located in the fourth pixel region PR4.

[0064] The first to fourth floating diffusion nodes FD1 to FD4 may correspond to Figure 3The first floating diffusion node FD1 to the fourth floating diffusion node FD4 may be respectively disposed in the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. The first floating diffusion node FD1 to the fourth floating diffusion node FD4 may be connected to each other. The first floating diffusion node FD1 to the fourth floating diffusion node FD4 may be respectively coupled to the first transfer transistor TX1 to the fourth transfer transistor TX4.

[0065] Therefore, the use of the gate electrode TG1 to the gate electrode TG4 can be changed according to whether the first gate electrode TG1 to the fourth gate electrode TG4 are operated. Figure 3 Therefore, Figure 2 The first to fourth pixels P1 to P4 may respectively use floating diffusion nodes FD connected to each other.

[0066] The reset gate RG may be located in the first pixel region PR1. The reset gate RG may be symmetrically positioned with the dummy gate Dummy and at least a portion of the first source follower gate SFG. For example, the reset gate RG and the dummy gate Dummy may be placed at symmetrical positions relative to the device isolation layer 130 in the first pixel region PR1 and the second pixel region PR2. The reset gate RG may be configured to reset the Figure 2 The first to fourth floating diffusion nodes FD4 of the first to fourth pixels P1 to P4 are connected to each other.

[0067] The dummy gate Dummy may be located in the second pixel region PR2. The dummy gate Dummy may be formed for uniformity of the reset gate RG and the first source follower gate SFG. Therefore, the dummy gate Dummy may be formed at a position symmetrical to the reset gate RG in the first direction X. The dummy gate Dummy may not actually work at all.

[0068] The first source follower gate SFG may be formed on the third pixel region PR3 and the fourth pixel region PR4. The first source follower gate SFG may be formed on the device isolation layer 130 and the third pixel region PR3 and the fourth pixel region PR4. That is, the first source follower gate SFG may also be formed on the device isolation layer 130 between the third pixel region PR3 and the fourth pixel region PR4.

[0069] The first source follower gate SFG may extend in the first direction X. The first source follower gate SFG may be connected to the first to fourth floating diffusion nodes FD1 to FD4 , for example, via the first wiring 300 .

[0070] The first selection gate SEL1 may be located in the third pixel region PR3. The second selection gate SEL2 may be located in the fourth pixel region PR4. The first selection gate SEL1 and the second selection gate SEL2 may select a pixel to be read out from among the first to fourth pixels P1 to P4.

[0071] The first wiring 300 may connect the first floating diffusion node FD1, the second floating diffusion node FD2, the third floating diffusion node FD3, and the fourth floating diffusion node FD4 to the first source follower gate SFG. The first wiring 300 may be disposed at an upper level higher than the first floating diffusion node FD1, the second floating diffusion node FD2, the third floating diffusion node FD3, and the fourth floating diffusion node FD4 and the first source follower gate SFG.

[0072] The second wiring 200 may connect the first selection gate SEL1 and the second selection gate SEL2. Therefore, the first selection gate SEL1 and the second selection gate SEL2 may be controlled to the same gate voltage.

[0073] Figure 5 is along Figure 4 A cross-sectional view taken along line AA'.

[0074] Reference Figure 5 According to the present embodiment, the image sensor includes a substrate 100, a third photoelectric device PD3, a fourth photoelectric device PD4, a device isolation layer 130, a liner 160, a filling layer 170, a first planarization layer 180, a side anti-reflection layer 190, 200, a first color filter 200, a second color filter 1200, a second planarization layer 210, a first microlens 220, a second microlens 1220, a protective layer 230, a first interlayer insulating layer 320, a first selection gate SEL1, a second selection gate SEL2, a first selection spacer 340, a second selection spacer 350, a first source follower gate SFG, a source follower spacer 310, a first contact 360, a second contact 370, a third contact 380 and a second interlayer insulating layer 330.

[0075] The substrate 100 includes a first surface 100a and a second surface 100b opposite to each other. The first surface 100a of the substrate 100 may be a front surface of the substrate 100, and the second surface 100b of the substrate 100 may be a back surface of the substrate 100. However, the present disclosure is not limited thereto.

[0076] The substrate 100 may be configured by using, for example, a P-type or N-type bulk substrate, a P-type or N-type epitaxial layer grown on a P-type bulk substrate, or a P-type or N-type epitaxial layer grown on an N-type bulk substrate. In addition to a semiconductor substrate, the substrate 100 may also be a substrate such as an organic plastic substrate.

[0077] The substrate 100 may be divided by the device isolation layer 130. The region of the substrate 100 divided by the device isolation layer 130 may be an active region. Figure 4 The first pixel region PR1 , the second pixel region PR2 , the third pixel region PR3 , and the fourth pixel region PR4 may be active regions.

[0078] The third and fourth photoelectric devices PD3 and PD4, for example, photodiodes, are formed in the substrate 100 at the active region. The third and fourth photoelectric devices PD3 and PD4 may be formed close to the first surface 100a of the substrate 100, but the present disclosure is not limited thereto.

[0079] As described above, the third photoelectric device PD3 and the fourth photoelectric device PD4 may be photodiodes, phototransistors, photogates, pinned photodiodes, or combinations thereof.

[0080] The device isolation layer 130 may be formed in the substrate 100. The device isolation layer 130 may define an active region in the substrate 100. The device isolation layer 130 may be formed at the edge of each active region. Each active region may be defined as a space closed by the device isolation layer 130. The planar cross-sectional shape of the device isolation layer 130 may be a closed curve in the form of a ring.

[0081] The device isolation layer 130 may be formed in the boundary isolation trench 120. The boundary isolation trench 120 may be formed in the substrate 100 by etching in a depth direction. The boundary isolation trench 120 may be formed on the second surface 100b of the substrate 100 and extend in the direction of the first surface 100a. The boundary isolation trench 120 may reach the second surface 100b of the substrate 100 and completely penetrate the substrate 100.

[0082] The width of the boundary isolation trench 120 may be constant, such as Figure 5 Alternatively, the boundary isolation trench 120 may have a tapered shape such that its width becomes narrower toward the first surface 100a. However, the present disclosure is not limited thereto.

[0083] As shown in the figure, the device isolation layer 130 may be filled with a liner 160 which will be described later, and a filling layer 170 formed on the liner 160 .

[0084] Alternatively, the device isolation layer 130 may be filled with a single material. In this case, the device isolation layer 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0085] For example, the low-k material may include, for example, flowable oxide (FOX), doline silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphorescent glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material or a combination thereof, but the present invention is not limited thereto.

[0086] The liner 160 may be formed on the second surface 100b of the substrate 100 and on the surface (side surface) of the boundary isolation trench 120. The liner 160 may be formed on the entire surface or a portion of the second surface 100b of the substrate 100.

[0087] When the third photoelectric device PD3 and the fourth photoelectric device PD4 formed in the pixel region are N-type, the liner 160 may be formed as P-type. The liner 160 may reduce dark current by reducing electron-hole pairs (EHP) thermally generated on the second surface 100b of the substrate 100. In some cases, the liner 160 may be omitted.

[0088] The liner 160 may include, for example, a metal oxide film or a metal nitride film, and the metal may be selected from the group consisting of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). The liner 160 may include at least one of La, Pr, Ce, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Tm, Yb, Lu, and Y. In addition, the liner 160 may be formed of a hafnium oxynitride film or an aluminum oxynitride film.

[0089] Although the liner 160 is illustrated as a single layer in the drawings, it may be a stacked structure in which two or more layers formed of the same or different materials are combined.

[0090] The filling layer 170 may be formed on the liner 160. The filling layer 170 may completely fill the boundary isolation trench 120. The filling layer 170 may prevent reflection of light incident from the outside. The filling layer 170 may include a material having a refractive index different from that of the liner 160. For example, the filling layer 170 may be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin, a combination thereof, or a laminate thereof.

[0091] The double-layer structure of the liner 160 and the filling layer 170 may have an anti-reflection function due to the difference in refractive index, and thus, reflection of light incident on the second surface 100b of the substrate 100 may be prevented.

[0092] The material / thickness of the filling layer 170 may be changed according to the wavelength of light used in the photolithography process. For example, a thickness of about 50 to The silicon oxide film has a thickness of about 300 to A silicon nitride film of is stacked and used as the filling layer 170. However, the present disclosure is not limited thereto.

[0093] The first planarization layer 180 may be formed under the filling layer 170. The first planarization layer 180 may include, for example, at least one of a silicon oxide-based material, a silicon nitride-based material, a resin, or a combination thereof.

[0094] When the lower surface of the device isolation layer 130 is uneven, the first planarization layer 180 may fill the lower surface of the device isolation layer 130 of the filling layer 170 and the liner layer 160 in a planar manner.

[0095] The first planarization layer 180 may include at least one of a silicon oxide-based material, a silicon nitride-based material, a resin, and a combination thereof. For example, as the first planarization layer 180, a However, the present disclosure is not limited thereto.

[0096] The first color filter 200 may be formed below the first planarization layer 180. The first color filter 200 may filter the remaining wavelength band of the incident light except for a specific color. Therefore, the light passing through the first color filter 200 may be light of a specific color. The light passing through the first color filter 200 may pass through the upper structure and reach the third photoelectric device PD3. The third photoelectric device PD3 may generate current by the incident light.

[0097] The first color filter 200 may be an infrared filter instead of a visible light filter. In this case, the first color filter 200 may pass only light in the infrared region.

[0098] The second color filter 1200 may also be formed under the first planarization layer 180. The second color filter 1200 may also filter the remaining wavelength band of the incident light except for the specific color. The specific color of the second color filter 1200 may be a color different from the specific color of the first color filter 200. However, in the image sensor according to some embodiments of the present disclosure, the first color filter 200 and the second color filter 1200 may be color filters for the same color.

[0099] The light having passed through the second color filter 1200 may pass through the upper structure and reach the fourth photoelectric device PD4. The fourth photoelectric device PD4 may generate current by the incident light.

[0100] The second color filter 1200 may be an infrared filter instead of a visible light filter. In this case, the second color filter 1200 may pass only light in the infrared region.

[0101] The side anti-reflection layer 190 may be formed under the first planarization layer 180. The side anti-reflection layer 190 may cover a portion of the first planarization layer 180. The side anti-reflection layer 190 may overlap the device isolation layer 130 in a vertical direction. That is, the side anti-reflection layer 190 may be disposed at the edge of the active region.

[0102] The side anti-reflection layer 190 may be disposed on the side surface of the first color filter 200. Specifically, the first color filter 200 may cover the side surface and the lower surface of the side anti-reflection layer 190. That is, the height of the lower surface of the side anti-reflection film 190 may be higher than the height of the lower surface of the first color filter 200.

[0103] The side anti-reflection layer 190 can prevent the incident light passing through the first color filter 200 and the second color filter 1200 from being reflected or scattered laterally. That is, the photons reflected or scattered at the interface between the first color filter 200 and the second color filter 1200 and the first planarization layer 180 can be prevented from moving to other active areas. Since the side anti-reflection layer 190 functions at the interface as described above, it can cover only a portion of the side surface of the first color filter 200 and the second color filter 1200.

[0104] The side anti-reflection layer 190 may include a metal. The side anti-reflection layer 190 may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0105] The second planarization layer 210 may be formed in a flat manner under the first color filter 200 and the second color filter 1200. The second planarization layer 210 may include, for example, at least one of a silicon oxide-based material, a silicon nitride-based material, a resin, and a combination thereof. Although the second planarization layer 210 is shown as a single layer, it is only exemplary and the present disclosure is not limited thereto.

[0106] Despite Figure 5 2 shows that the second planarization layer 210 and the first planarization layer 180 are formed below and above the first color filter 200 and the second color filter 1200, respectively, but the present disclosure is not limited thereto. For example, the planarization layer may be formed only below the first color filter 200 and the second color filter 1200, and the planarization layer may be formed only above the first color filter 200 and the second color filter 1200. Alternatively, the planarization layer may not exist above and below the first color filter 200 and the second color filter 1200.

[0107] The first microlens 220 and the second microlens 1220 may be formed under the second planarization layer 210. As shown, the first microlens 220 and the second microlens 1220 may have a downwardly convex shape. The convex shape of the first microlens 220 and the second microlens 1220 may focus incident light on the active area.

[0108] The first microlens 220 and the second microlens 1220 may be made of an organic material such as photoresist (PR). However, the present disclosure is not limited thereto, and the first microlens 220 and the second microlens 1220 may be formed of an inorganic material.

[0109] Forming the first microlens 220 and the second microlens 1220 using an organic material may be performed, for example, by forming an organic material pattern under the second planarization layer 210 and performing heat treatment. The organic material pattern may be changed into the first microlens 220 and the second microlens 1220 by heat treatment.

[0110] The protective layer 230 may be formed to have a predetermined thickness along the surfaces of the first microlens 220 and the second microlens 1220. The protective layer 230 may be an inorganic oxide film. For example, a silicon oxide film (SiO2), a titanium oxide film (TiO2), a zirconium oxide film (ZrO2), a hafnium oxide film (HfO2), a laminated film thereof, and / or a combined film thereof may be used.

[0111] In particular, low temperature oxide (LTO), which is a silicon oxide film, can be used as the protective layer 230. Since LTO is manufactured at a low temperature (about 100° C. to 200° C.), damage to the underlying layer can be reduced. In addition, since LTO is amorphous, its surface is smooth, and reflection, refraction, and scattering of incident light can be minimized.

[0112] Since the first microlens 220 and the second microlens 1220 are made of organic materials, they may be easily affected by external impact. Therefore, the protective layer 230 protects the first microlens 220 and the second microlens 1220 from external impact. In addition, there may be a tiny space between adjacent microlenses, and the protective layer 230 may fill the space.

[0113] When the space between the adjacent microlenses and the first and second microlenses 220 and 1220 is filled, the condensing efficiency of the incident light can be improved because the reflection, refraction and scattering of the incident light reaching the space between the adjacent microlenses and the first and second microlenses 220 and 1220 can be reduced.

[0114] The first planarization layer 180, the second planarization layer 210, the first color filter 200, the second color filter 1200, the first microlens 220, the second microlens 1220, and the protective layer 230 may be formed in a downward direction of the second surface 100b of the substrate 100. Hereinafter, constituent elements formed in an upward direction of the first surface 100a of the substrate 100 will be described.

[0115] The first source follower gate SFG may be formed on the active region of the first surface 100a of the substrate 100 and on the device isolation layer 130. The first source follower gate SFG may extend over the two active regions (the third pixel region PR3 and the fourth pixel region PR4).

[0116] The source follower spacer 310 may be formed on a side surface of the first source follower gate SFG. The source follower spacer 310 may include oxide, nitride, and / or oxynitride.

[0117] The first selection gate SEL1 may be formed in the active region or in a portion thereof (e.g., the third pixel region PR3). The second selection gate SEL2 may be formed in the active region or in a portion thereof (e.g., the fourth pixel region PR4). The first selection gate SEL1 and the second selection gate SEL2 may be electrically connected to the first contact 360 and the second contact 370, respectively.

[0118] The first selection spacer 340 may be formed on a side surface of the first selection gate SEL1. The second selection spacer 350 may be formed on a side surface of the second selection gate SEL2. The first selection spacer 340 and the second selection spacer 350 may include oxide, nitride, and / or oxynitride.

[0119] The first interlayer insulating layer 320 may be formed on the first surface 100 a of the substrate 100 . The first interlayer insulating layer 320 may be formed on the active region and the device isolation layer 130 .

[0120] A first interlayer insulating layer 320 may be formed on the first selection gate SEL1 , the first selection spacer 340 , the second selection gate SEL2 , the second selection spacer 350 , the first source follower gate SFG, and the source follower spacer 310 .

[0121] The first interlayer insulating layer 320 may include at least one of an oxide film, a nitride film, and an oxynitride film.

[0122] The first contact 360 may be connected to the first selection gate SEL1. The second contact 370 may be connected to the second selection gate SEL2. The third contact 380 may be connected to the first source follower gate SFG. The first contact 360, the second contact 370, and the third contact 380 may be formed by a first interlayer insulating layer.

[0123] The second interlayer insulating layer 330 may be formed on the first interlayer insulating layer 320. The second interlayer insulating layer 330 may include at least one of an oxide film, a nitride film, and an oxynitride film. Figure 4 The first wiring 300 and the second wiring 200 may be formed in the second interlayer insulating layer 330. The first wiring 300 may be in contact with the third contact 380, and the second wiring 200 may be in contact with the first contact 360 and the second contact 370.

[0124] In the image sensor according to the present embodiment, the first source follower gate SFG may be formed over two pixel regions in a shared pixel. Therefore, noise may be reduced by increasing the area of ​​the first source follower gate SFG.

[0125] In addition, except for the case where there are multiple first source follower gates SFG and the multiple first source follower gates SFG are connected at the upper level by wiring, only one source follower gate can be used, and a structure for upper wiring is not required. Therefore, the space margin of the entire image sensor device can be ensured. Therefore, the range of options for determining the width and length of other components in the layout design can be widened.

[0126] In the following, reference will be made to Figures 6 to 8 An image sensor according to some embodiments of the present disclosure is described, and repeated descriptions of the above embodiments are simplified or omitted.

[0127] Figure 6 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure. Figure 6 yes Figure 2 : An equivalent circuit diagram of the first shared pixel SP1.

[0128] Reference Figure 6 , the image sensor according to some embodiments of the present disclosure includes a second source follower SF′ and a third selection transistor SX3 .

[0129] The second source follower SF′ may include a second source follower gate SFG′.

[0130] The third selection transistor SX3 may cooperate with the first selection transistor SX1 and the second selection transistor SX2 to select pixels to be read on a row basis. As more selected transistors are arranged in parallel, faster reactions may be achieved.

[0131] The third selection transistor SX3 may be connected in series with the second source follower gate SFG′, and may be connected in parallel with the first and second selection transistors SX1 and SX2 .

[0132] Figure 7 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure.

[0133] Figure 8 It is shown Figure 7 A plan view of the shape of the source follower gate.

[0134] Reference Figure 7 and Figure 8 The second source follower gate SFG′ may be formed over the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. That is, the second source follower gate SFG′ may include a first portion L1 extending in the first direction X and a second portion L2 extending in the second direction Y.

[0135] Therefore, the second source follower gate SFG′ is formed on the device isolation layer 130 between the third pixel region PR3 and the fourth pixel region PR4 , and on the device isolation layer 130 between the second pixel region PR2 and the fourth pixel region PR4 .

[0136] Since the second source follower gate SFG′ has a wider area, the noise of the signal can be minimized. In addition, since the metal area of ​​the first to fourth floating diffusion regions FD1 to FD4 is relatively small, the coupling effect of the parasitic capacitance can be suppressed.

[0137] In the following, reference will be made to Fig. 9 An image sensor according to some embodiments of the present disclosure is described, and repeated descriptions of the above embodiments are simplified or omitted.

[0138] Fig. 9 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure.

[0139] Reference Fig. 9 The image sensor according to some embodiments of the present disclosure includes a first shared pixel SP1, a second shared pixel SP2, and a third shared pixel SP3. The first shared pixel SP1, the second shared pixel SP2, and the third shared pixel SP3 may be separated from each other by a device isolation layer 130.

[0140] The first shared pixel SP1, the second shared pixel SP2, and the third shared pixel SP3 may be sequentially arranged in the first direction X. The second shared pixel SP2 includes the fifth pixel P5 to the eighth pixel P8. The fifth pixel P5 to the eighth pixel P8 may include the fifth pixel region PR5, the sixth pixel region PR6, the seventh pixel region PR7, and the eighth pixel region PR8, respectively. The fifth pixel region P5, the sixth pixel region P6, the seventh pixel region P7, and the eighth pixel region P8 may be separated from each other by the device isolation layer 130.

[0141] The fifth pixel region PR5 and the sixth pixel region PR6 are aligned with each other in the first direction X, and the seventh pixel region PR7 and the eighth pixel region PR8 are aligned with each other in the first direction X. The fifth pixel region PR5 and the seventh pixel region PR7 are aligned with each other in the second direction Y, and the sixth pixel region PR6 and the eighth pixel region PR8 are aligned with each other in the second direction Y.

[0142] The ninth pixel region PR9 and the tenth pixel region PR10 are aligned with each other in the first direction X, and the eleventh pixel region PR11 and the twelfth pixel region PR12 are aligned with each other in the first direction X. The ninth pixel region PR9 and the eleventh pixel region PR11 are aligned with each other in the second direction Y, and the tenth pixel region PR10 and the twelfth pixel region PR12 are aligned with each other in the second direction Y.

[0143] The fifth transfer gate TG5 may be located in the fifth pixel region PR5, and the sixth transfer gate TG6 may be located in the sixth pixel region PR6. The seventh transfer gate TG7 may be located in the seventh pixel region PR7, and the eighth transfer gate TG8 may be located in the eighth pixel region PR8.

[0144] The ninth transfer gate TG9 may be located in the ninth pixel region PR9, and the tenth transfer gate TG10 may be located in the tenth pixel region PR10. The eleventh transfer gate TG11 may be located in the eleventh pixel region PR11, and the twelfth transfer gate TG12 may be located in the twelfth pixel region PR12.

[0145] The fifth to eighth floating diffusion nodes FD5 to FD8 are respectively disposed in the fifth pixel region PR5, the sixth pixel region PR6, the seventh pixel region PR7, and the eighth pixel region PR8. The fifth to eighth floating diffusion nodes FD5 to FD8 may be connected to each other. The fifth to eighth floating diffusion nodes FD5 to FD8 may be respectively coupled to the fifth to eighth transmission gates TG5 to TG8.

[0146] The ninth floating diffusion node FD9 to the twelfth floating diffusion node FD12 may be respectively disposed in the ninth pixel region PR9, the tenth pixel region PR10, the eleventh pixel region PR11, and the twelfth pixel region PR12. The ninth floating diffusion node FD9 to the twelfth floating diffusion node FD12 may be connected to each other. The ninth floating diffusion node FD9 to the twelfth floating diffusion node FD12 may be respectively coupled to the ninth transmission gate TG9 to the twelfth transmission gate TG12.

[0147] The first reset gate RG1 may be located in the first pixel region PR1. The first reset gate RG1 may be configured to reset the first floating diffusion node FD1 to the fourth floating diffusion node FD4. The second reset gate RG2 may be located in the fifth pixel region PR5. The second reset gate RG2 may be configured to reset the fifth floating diffusion node FD5 to the eighth floating diffusion node FD8. The third reset gate RG3 may be located in the ninth pixel region PR9. The third reset gate RG3 may be configured to reset the ninth floating diffusion node FD9 to the twelfth floating diffusion node FD12.

[0148] The first dummy gate Dummy1 may be located in the second pixel region PR2. The second dummy gate Dummy2 may be located in the sixth pixel region PR6. The third dummy gate Dummy3 may be located in the tenth pixel region PR10.

[0149] The first_first source follower gate SFG1 may be formed on the third pixel region PR3 and the fourth pixel region PR4. The first_second source follower gate SFG2 may be formed on the seventh pixel region PR7 and the eighth pixel region PR8. The first_third source follower gate SFG3 may be formed on the eleventh pixel region PR11 and the twelfth pixel region PR12. The first_first source follower gate SFG1, the first_second source follower gate SFG2, and the first_third source follower gate SFG3 may also be formed on the device isolation layer 130.

[0150] The third selection gate SEL3 may be located in the seventh pixel region PR7, and the fourth selection gate SEL4 may be located in the eighth pixel region PR8. The fifth selection gate SEL5 may be located in the eleventh pixel region PR11, and the sixth selection gate SEL6 may be located in the twelfth pixel region PR12.

[0151] The third wiring 301 may connect the fifth floating diffusion node FD5, the sixth floating diffusion node FD6, the seventh floating diffusion node FD7, and the eighth floating diffusion node FD8 to the first_first source follower gate SFG1. The fourth wiring 302 may connect the ninth floating diffusion node FD9, the tenth floating diffusion node FD10, the eleventh floating diffusion node FD11, and the twelfth floating diffusion node FD12 to the first_second source follower gate SFG2.

[0152] The third selection gate SEL3 and the fourth selection gate SEL4 may be connected to each other by the fifth wiring 201. Therefore, the third selection gate SEL3 and the fourth selection gate SEL4 may be controlled by the same gate voltage.

[0153] The sixth wiring 202 can connect the fifth selection gate SEL5 and the sixth selection gate SEL6. Therefore, the fifth selection gate SEL5 and the sixth selection gate SEL6 can be controlled with the same gate voltage.

[0154] In the following, reference will be made to Fig.10 An image sensor according to some embodiments of the present disclosure is described, and repeated descriptions of the above embodiments are simplified or omitted.

[0155] Fig.10 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure.

[0156] Reference Fig.10 , the image sensor according to some embodiments of the present disclosure includes a second_first source follower gate SFG1 ′, a second_second source follower gate SFG2 ′, and a second_third source follower gate SFG3 ′.

[0157] The second_first source follower gate SFG1′ may be formed on the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. The second_second source follower gate SFG2′ may be formed on the sixth pixel region PR6, the seventh pixel region PR7, and the eighth pixel region PR8. The second_third source follower gate SFG3′ may be formed on the tenth pixel region PR10, the eleventh pixel region PR11, and the twelfth pixel region PR12.

[0158] In the following, reference will be made to Fig.11 and Fig.12 An image sensor according to some embodiments of the present disclosure is described, and repeated descriptions of the above embodiments are simplified or omitted.

[0159] Fig.11 is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure. Fig.12is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure. For convenience, Fig.11 yes Fig.12 The equivalent circuit diagram of the first shared pixel SP1 is shown in FIG. The equivalent circuit diagram of the second shared pixel SP2 and the third shared pixel SP3 is shown in FIG. Fig.12 The equivalent circuit is basically the same.

[0160] Reference Fig.11 and Fig.12 , the image sensor according to the embodiment of the present disclosure includes a first_first source follower SF1, a first_first selection transistor SX1′, and a first_second selection transistor SX2′.

[0161] The first_first source follower SF1 includes a first_first source follower gate SFG1. The first_first selection transistor SX1' includes a first_first selection gate SEL_S1, and the first_second selection transistor SX2' includes a first_second selection gate SEL_S2.

[0162] The first_first selection gate SEL_S1 may extend to a shared pixel adjacent to the first shared pixel SP1 in the first direction X. The first_second selection gate SEL_S2 may be formed on the first shared pixel SP1 and the second shared pixel SP2. That is, the first_second selection gate SEL_S2 may be formed on the fourth pixel region PR4 and the seventh pixel region PR7.

[0163] The first_third selection gate SEL_S3 may be formed on the second shared pixel SP2 and the third shared pixel SP3. The first_third selection gate SEL_S3 may be formed on the eighth pixel region PR8 and the eleventh pixel region PR11. The first_fourth selection gate SEL_S4 may be formed to extend from the twelfth pixel region PR12 to the adjacent shared pixel. The first_first selection gate SEL_S1, the first_second selection gate SEL_S2, the first_third selection gate SEL_S3, and the first_fourth selection gate SEL_S4 may also be formed on the device isolation layer 130.

[0164] In the image sensor according to this embodiment, the selection gate may also be connected to the device isolation layer to reduce the wiring portion connected to the selection gate, while achieving the effect of reducing noise as the area increases, thereby improving coupling.

[0165] In the following, reference will be made to Figures 13 to 15 An image sensor according to some embodiments of the present disclosure is described, and repeated descriptions of the above embodiments are simplified or omitted.

[0166] Fig.13is an equivalent circuit diagram of a shared pixel of an image sensor according to some embodiments of the present disclosure, and Fig.14 is a layout diagram of shared pixels of an image sensor according to some embodiments of the present disclosure.

[0167] Fig.15 It is shown Fig.14 The plan view of the shape of the second selection gate. Although for convenience, Fig.15 The shape of the second_second selection gate SEL_S2 ′ is shown, but the shapes of other selection gates may be the same as that of the second_second selection gate SEL_S2 ′.

[0168] Reference Fig.13 and Fig.15 , the image sensor according to an embodiment of the present disclosure includes a second_first source follower SF1 ′, a second_first selection transistor SX1 ″, and a second_second selection transistor SX2 ″.

[0169] The second_first source follower SF1 ′ includes a second_first source follower gate SFG1 ′. The second_first selection transistor SX1 ″ includes a second_first selection gate SEL_S1 ′, and the second_second selection transistor SX2 ″ includes a second_second selection gate SEL_S2 ′.

[0170] The second_first selection gate SEL_S1′ may extend to a shared pixel adjacent to the first shared pixel SP1 in the first direction X. The second_second selection gate SEL_S2′ may be formed over the first shared pixel SP1 and the second shared pixel SP2. That is, the second_second selection gate SEL_S2′ may be formed over the second pixel region PR2, the fourth pixel region PR4, and the seventh pixel region PR7.

[0171] The second_third selection gate SEL_S3′ may be formed on the second shared pixel SP2 and the third shared pixel SP3. The second_third selection gate SEL_S3′ may be formed on the sixth pixel region PR6, the eighth pixel region PR8, and the eleventh pixel region PR11. The second_fourth selection gate SEL_S4′ may be formed on the adjacent shared pixels in the tenth pixel region PR10 and the twelfth pixel region PR12. The second_first selection gate SEL_S1′, the second_second selection gate SEL_S2′, the second_third selection gate SEL_S3′, and the second_fourth selection gate SEL_S4′ may also be formed on the device isolation layer 130.

[0172] The second selection gate SEL_S2 ′ may include a third portion L3 extending in the first direction X and a fourth portion L4 extending in the second direction Y.

[0173] In the image sensor according to this embodiment, the selection gate may also be connected to the device isolation layer to reduce the wiring portion connected to the selection gate, while achieving the effect of reducing noise as the area increases, thereby improving coupling.

[0174] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the inventive concept as defined in the appended claims. Therefore, it is desired that the present embodiments be considered in all respects as illustrative rather than restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present disclosure.

Claims

1. An image sensor, comprising: a substrate including a first surface and a second surface opposite to each other; a device isolation layer extending through the substrate and having a surface flush with the second surface of the substrate; an active area defined by the device isolation layer; an optoelectronic device disposed in the substrate and configured to convert light into electric charge; microlenses on the first surface; a transfer gate in an active region on the second surface, the transfer gate configured to transfer the charge to a floating diffusion node; as well as a source follower gate extending over the device isolation layer and the active region, wherein the active area includes a first pixel area, a second pixel area, a third pixel area, and a fourth pixel area separated from each other by the device isolation layer in a first direction and a second direction intersecting the first direction, The floating diffusion node is a first floating diffusion node, the image sensor further includes a second floating diffusion node, a third floating diffusion node and a fourth floating diffusion node, and the first floating diffusion node to the fourth floating diffusion node are respectively located in the first pixel region to the fourth pixel region, The image sensor further includes a first selection gate and a second selection gate on the third pixel region and the fourth pixel region respectively. wherein the source follower gate is located between the first selection gate and the second selection gate in the first direction, The source follower gate extends along the first direction on the third pixel region and the fourth pixel region, and Wherein, in the second direction, the source follower gate is located between the first floating diffusion node and the third floating diffusion node and between the second floating diffusion node and the fourth floating diffusion node.

2. The image sensor according to claim 1, wherein: The optoelectronic device is a first optoelectronic device, the image sensor further includes a second optoelectronic device, a third optoelectronic device and a fourth optoelectronic device, the first optoelectronic device to the fourth optoelectronic device are respectively located in the first pixel region to the fourth pixel region, The first to fourth floating diffusion nodes correspond to each of the first to fourth optoelectronic devices.

3. The image sensor according to claim 1, further comprising: an interlayer insulating layer, on the active region and the device isolation layer; as well as A first wiring is provided in the interlayer insulating layer, the first wiring connecting the first floating diffusion node to the fourth floating diffusion node to each other.

4. The image sensor according to claim 1, wherein: The transfer gate is a first transfer gate, and the image sensor further includes a second transfer gate, a third transfer gate and a fourth transfer gate, wherein the first transfer gate to the fourth transfer gate are respectively located in the first pixel region to the fourth pixel region and are respectively connected to the first floating diffusion node to the fourth floating diffusion node. 5 . The image sensor of claim 1 , further comprising a reset gate located in the first pixel region and configured to reset the first floating diffusion node to the fourth floating diffusion node.

6. The image sensor according to claim 1, wherein: The source follower gate is connected to each of the first to fourth floating diffusion nodes, and Wherein the source follower gate extends over at least two of the pixel regions. 7 . The image sensor according to claim 6 , further comprising a dummy gate formed on the second pixel region.

8. The image sensor according to claim 6, in, The source follower gate also extends over the second pixel region.

9. An image sensor, comprising: a substrate including a first surface and a second surface opposite to each other; a device isolation layer extending into the substrate and having a surface flush with the second surface of the substrate; an active area defined by the device isolation layer, the active area comprising a first shared pixel area, a second shared pixel area, and a third shared pixel area sequentially arranged in a first direction; a transfer gate in an active region on the second surface, the transfer gate configured to transfer charge to a floating diffusion node, The first shared pixel region, the second shared pixel region and the third shared pixel region respectively include a first source follower gate, a second source follower gate and a third source follower gate, wherein each of the first to third shared pixel regions comprises at least four pixel regions arranged in a grid, wherein at least two pixel regions are aligned in the first direction, and at least two pixel regions are aligned in a second direction intersecting the first direction, wherein the first source follower gate extends over at least two pixel regions of the first shared pixel region, wherein the second source follower gate extends over at least two pixel regions of the second shared pixel region, wherein the third source follower gate extends over at least two pixel regions of the third shared pixel region, and The image sensor further includes: a first shared selection gate extending over a pixel region where the first source follower gate extends and over a pixel region where the second source follower gate extends; and a second shared selection gate extending over a pixel region where the second source follower gate extends and over a pixel region where the third source follower gate extends.

10. The image sensor according to claim 9, wherein: The first source follower gate extends over three pixel regions of the first shared pixel region, wherein the second source follower gate extends over three pixel regions of the second shared pixel region, and The third source follower gate extends over three pixel regions of the third shared pixel region.

11. The image sensor according to claim 9, wherein: The first shared select gate includes a first portion extending in the first direction and a second portion extending in the second direction.

12. An image sensor, comprising: a substrate, including an active region and a device isolation layer; First to fourth optoelectronic devices are located in the active region; First to fourth transfer transistors are respectively located between the first to fourth photoelectric devices and a floating diffusion node on the substrate; a source follower transistor on the substrate, wherein the source follower transistor has the floating diffusion node as a gate node; and a select transistor connected in series with the source follower transistor on the substrate, wherein the source follower transistor is located on the active region and the device isolation layer, The first transmission transistor to the fourth transmission transistor respectively have a first transmission gate to a fourth transmission gate, wherein the source follower transistor has a source follower gate, wherein the active area includes a first pixel area, a second pixel area, a third pixel area, and a fourth pixel area separated from each other by the device isolation layer in a first direction and a second direction intersecting the first direction, The floating diffusion node is a first floating diffusion node, the image sensor further includes a second floating diffusion node, a third floating diffusion node and a fourth floating diffusion node, the first floating diffusion node to the fourth floating diffusion node are respectively located in the first pixel region to the fourth pixel region, The image sensor further includes a first selection gate and a second selection gate on the third pixel region and the fourth pixel region respectively. wherein a source follower gate of the source follower transistor is located between the first selection gate and the second selection gate in the first direction, The source follower gate extends along the first direction on the third pixel region and the fourth pixel region, and Wherein, in the second direction, the source follower gate is located between the first floating diffusion node and the third floating diffusion node and between the second floating diffusion node and the fourth floating diffusion node.

13. The image sensor according to claim 12, wherein: The device isolation layer extends into the substrate.

14. The image sensor according to claim 13, wherein: The device isolation layer includes a filling layer and a liner layer surrounding the filling layer.

15. The image sensor according to claim 12, wherein: The planar cross-sectional shape of the device isolation layer is a closed curve.

Images