SRAM devices and their fabrication methods

Abstract

An SRAM device and its formation method are disclosed. The formation method includes: providing a substrate comprising a first type of device region and a second type of device region; the first type of SRAM device having a maximum channel width; both the first and second type of device regions comprising a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; forming a stacked structure on the substrate, comprising a first sacrificial layer and a channel layer; the width of each stacked structure in the second type of device region being equal to a preset width of the corresponding transistor region in the first type of device region; performing a channel width adjustment process; in the second type of device region, removing a portion of the channel layer width from any one or two of the transistor regions (transmission gate transistor region, pull-down transistor region, and pull-up transistor region); after removing the portion of the channel layer width, removing the first sacrificial layer; and after removing the first sacrificial layer, forming a gate structure spanning the channel layer. This invention uses the same design layout to form the stacked structure, saving design costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to an SRAM device and a method for forming the same. Background Technology

[0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important component of digital systems. SRAM (Static Random Access Memory) has become an indispensable part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can store data as long as it is powered, without the need for constant refreshing.

[0003] The reliability of SRAM is crucial for ensuring the stable and safe operation of electrical applications. Currently, there is room for improvement in both the manufacturing process and the reliability verification process for SRAM. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide an SRAM device and a method for forming the same, which saves design costs, simplifies the verification process, and improves verification efficiency.

[0005] To address the aforementioned problems, this invention provides an SRAM device, comprising: a substrate, including a base and a plurality of bottom fins protruding from the substrate and extending along a first direction; the substrate includes a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device; the first type SRAM device has a maximum channel width; both the first and second type device regions include a plurality of memory cell regions; each memory cell region includes adjacent and centrally symmetrical first and second sub-cell regions; both the first and second sub-cell regions include a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region; the bottom fins of the same transistor region in the first and second type device regions have equal widths; and a channel layer structure, suspended in the substrate. Above the bottom fin, the channel layer structure includes one or more spaced channel layers along the longitudinal direction. The channel layer structure extends along the first direction. In the first type of device region, the sidewall of the channel layer along the second direction is flush with the sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction. In the second type of device region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, along the second direction, the sidewall of the channel layer is recessed inward relative to the sidewall of the bottom fin of the corresponding transistor region. The second direction is perpendicular to the first direction. A gate structure is located on the substrate and spans the plurality of channel layer structures along the second direction. The gate structure includes a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer surrounding and covering the gate dielectric layer.

[0006] Accordingly, embodiments of the present invention also provide a method for forming an SRAM device, comprising: providing a substrate including a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device, wherein the first type SRAM device has a maximum channel width, and both the first type device region and the second type device region include a plurality of memory cell regions, each memory cell region including an adjacent and centrally symmetrical first sub-cell region and a second sub-cell region, each of the first sub-cell region and the second sub-cell region including a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region, wherein a stacked structure extending along a first direction is formed on the substrate of the transmission gate transistor region, the pull-down transistor region, and the pull-up transistor region, the stacked structure including one or more stacked channel layers, each channel layer including a first sacrificial layer and a channel layer located on the first sacrificial layer, the stacked structure extending along the first direction. The first direction includes a channel region, wherein the stacked structure of each transistor region in the first type of device region has a corresponding preset width, and the width of each stacked structure in the second type of device region is equal to the preset width of the corresponding transistor region in the first type of device region; a channel width adjustment process is performed, in the second type of device region, in any one or two of the transistor regions of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, along the second direction, a portion of the width of the channel layer in the channel region is removed, the second direction being perpendicular to the first direction; after removing a portion of the width of the channel layer in the channel region, a first sacrificial layer in the channel region is removed; after removing the first sacrificial layer in the channel region, a gate structure spanning the channel layer is formed in the channel region, the gate structure including a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer surrounding and covering the gate dielectric layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the SRAM device provided by this invention, in the first type of device region, the sidewall of the channel layer along the second direction is flush with the sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction. In the second type of device region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, the sidewall of the channel layer is recessed inward relative to the sidewall of the bottom fin of the corresponding transistor region along the second direction. During the formation of the SRAM device, the bottom fin and the stacked structure containing the channel layer are usually formed in the same etching step. Then, along the second direction, a portion of the width of the channel layer is removed to form the channel layer structure. Therefore, for different types of SRAM devices, the width of the bottom fin of the same transistor region is consistent. That is to say, the present invention... In this embodiment, for SRAM devices with different performance requirements, the same design layout can be used to form the stacked structure. It is only necessary to remove a portion of the channel layer along the second direction in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region according to the operating current requirements of each transistor region of the second type of SRAM device, to form a channel layer with a width smaller than the width of the bottom fin. This avoids the need for separate layout design for different types of SRAM devices, saving design costs. Moreover, in the second type of SRAM devices, there is always a case where the width of the channel layer is smaller than the width of the bottom fin. Therefore, only the yield and reliability verification of the first type of SRAM device with the largest channel width is required, which simplifies the verification process and improves verification efficiency.

[0009] In the formation method provided by this invention, the width of each stacked structure in the second type of device region is equal to the preset width of the corresponding transistor region in the first type of device region. After forming the stacked structure, in the second type of device region, in any one or two of the transistor regions of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, a portion of the channel layer in the channel region is removed along the second direction. Thus, for different types of SRAM devices, the same design layout can be used to form the stacked structure. It is only necessary to remove a portion of the channel layer in the channel region along the second direction in any one or two of the transistor regions of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region according to the operating current requirements of each transistor region of the second type of SRAM device, forming channel layers of different widths. This avoids separate layout design for different types of SRAM devices, saving design costs. Moreover, in the second type of device region, there is a step of reducing the channel layer width along the second direction. Therefore, after forming the SRAM device, only the yield and reliability verification of the first type of SRAM device with the largest channel width needs to be performed, simplifying the verification process and improving verification efficiency. Attached Figure Description

[0010] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming an SRAM device;

[0011] Figures 8 to 12 This is a schematic diagram of the structure of an embodiment of the SRAM device of the present invention;

[0012] Figures 13 to 15 This is a schematic diagram of another embodiment of the SRAM device of the present invention;

[0013] Figures 16 to 28 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming an SRAM device according to the present invention;

[0014] Figures 29 to 30 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming an SRAM device according to the present invention;

[0015] Figures 31 to 33 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming an SRAM device according to the present invention. Detailed Implementation

[0016] Currently, the design cost of SRAM devices needs to be reduced, the verification process needs to be simplified, and the verification efficiency needs to be improved. This paper analyzes the reasons why these aspects need to be addressed by examining a method for fabricating an SRAM device.

[0017] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming an SRAM device.

[0018] For ease of illustration, Figure 1 Only the base is shown. Figure 2 This is a top view of any memory cell in the first type of device region. Figure 3 (a) is Figure 2 Cross-sectional view along the AA direction. Figure 3 (b) is Figure 2 Cross-sectional view along the BB direction. Figure 4 This is a top view of any memory cell in the second type of device region. Figure 5 (a) is Figure 4 Cross-sectional view along the AA direction. Figure 5 (b) is Figure 4 Cross-sectional view along the BB direction. Figure 6 This is a top view of any memory cell in the third type of device region. Figure 7 (a) is Figure 6 Cross-sectional view along the AA direction. Figure 7 (b) is Figure 6 A cross-sectional view along the BB direction.

[0019] refer to Figure 1 A substrate 10 is provided, including a first type device region 10P for forming a first type SRAM device, a second type device region 10D for forming a second type SRAM device, and a third type device region 10V for forming a third type SRAM device.

[0020] Reference Figure 2 , Figure 4 and Figure 6 The first type of device region 10P, the second type of device region 10D, and the third type of device region 10V each include multiple memory cell regions S. Each memory cell region S includes a first sub-cell region S1 and a second sub-cell region S2 that are adjacent and centrally symmetrical. Each first sub-cell region S1 and the second sub-cell region S2 includes a transmission gate transistor region PG, a pull-down transistor region PD, and a pull-up transistor region PU. The channel width ratios of the transmission gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU are different for the first type of SRAM device, the second type of SRAM device, and the third type of SRAM device.

[0021] Reference Figure 2 and Figure 3 In the first type of device region 10P, a plurality of channel layers 23 are formed above the substrate 10. The channel layers 23 are spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:2:2. A gate structure 50 is formed on the substrate 10, spanning and surrounding the plurality of channel layers 23. The channel layers 23 and the gate structure 50 are used to constitute the first type of SRAM device.

[0022] In the first type of device region 10P, the width of the channel layer 23 is defined using a first layout.

[0023] Reference Figure 4 and Figure 5 In the second type of device region 10D, a plurality of channel layers 23 are formed above the substrate 10. The channel layers 23 are spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:1. A gate structure 50 is formed on the substrate 10, spanning and surrounding the plurality of channel layers 23. The channel layers 23 and the gate structure 50 are used to constitute the second type of SRAM device.

[0024] In the second type of device region 10D, the width of the channel layer 23 is defined using a second layout.

[0025] Reference Figure 6 and Figure 7 In the third type of device region 10V, a plurality of channel layers 23 are formed above the substrate 10. The channel layers 23 are spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:2. A gate structure 50 is formed on the substrate 10, spanning and surrounding the plurality of channel layers 23. The channel layers 23 and the gate structure 50 are used to constitute the third type of SRAM device.

[0026] In the third type of device region 10V, the width of the channel layer 23 is defined using a third layout.

[0027] Based on the operating current requirements of different types of SRAM devices for each transistor region, the channel width ratios of the first type SRAM device, the second type SRAM device, and the third type SRAM device are different in the transmission gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU. Therefore, it is necessary to use a first layout to form the first type SRAM device, a second layout to form the second type SRAM device, and a third layout to form the third type SRAM device, respectively. In other words, layout design is required for different types of SRAM devices, which greatly increases the design cost. Moreover, after forming different types of SRAM devices, yield and reliability verification are required for the first type SRAM device, the second type SRAM device, and the third type SRAM device, respectively. The verification process is cumbersome and the verification efficiency is low.

[0028] To address the aforementioned technical problem, this invention provides a method for forming an SRAM device. The width of each stacked structure in the second type of device region is equal to a preset width of the corresponding transistor region in the first type of device region. After forming the stacked structure, in the second type of device region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, along a second direction, a portion of the channel layer width in the channel region is removed. Therefore, for different types of SRAM devices, the same design layout can be used to form the stacked structure, requiring only adjustments based on the second type of SRAM device for each transistor. To meet the operating current requirements of the transistor region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, a portion of the channel layer width is removed along the second direction to form channel layers of different widths. This avoids separate layout design for different types of SRAM devices, saving design costs. Moreover, in the second type of device region, there is a step of reducing the channel layer width along the second direction. Therefore, after forming the SRAM device, only the yield and reliability verification of the first type of SRAM device with the largest channel width needs to be performed, simplifying the verification process and improving verification efficiency.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 8 to 12 This is a schematic diagram of an embodiment of the SRAM device of the present invention. For ease of illustration, Figure 8 Only the base is shown. Figure 9 This is a top view of any memory cell in the first type of device region. Figure 10 (a) is Figure 9 Cross-sectional view along the AA direction. Figure 10 (b) is Figure 9 Cross-sectional view along the BB direction. Figure 11 This is a top view of any memory cell in the second type of device region. Figure 12 (a) is Figure 11 Cross-sectional view along the AA direction. Figure 12 (b) is Figure 11 A cross-sectional view along the BB direction.

[0031] The SRAM device includes: a substrate 121, including a substrate 101, and a protrusion on the substrate 101 along a first direction (e.g., ...). Figure 9 Multiple bottom fins 111 extending in the X direction (as shown in the middle X direction) are present. The substrate 121 includes a first type device region 101P for forming a first type SRAM device and a second type device region 101B for forming a second type SRAM device. The first type SRAM device has a maximum channel width. Both the first type device region 101P and the second type device region 101B include multiple memory cell regions S. Each memory cell region S includes a first sub-cell region S1 and a second sub-cell region S2 that are adjacent and centrally symmetrical. Sub-unit regions S2 each include a transmission gate transistor region PG, a pull-down transistor region PD, and a pull-up transistor region PU. The bottom fins 111 of the same transistor region in the first type of device region 101P and the second type of device region 101B have equal widths. A channel layer structure 251 is suspended above the bottom fins 111. The channel layer structure 251 includes one or more spaced channel layers 231 along the longitudinal direction. The channel layer structure 251 extends along the first direction. In the first type of device region 101P, the channel layers 231 extend along the second direction (e.g., ...). Figure 9 The sidewalls (as shown in the Y direction) and the sidewalls of the bottom fin 111 of the corresponding transistor region are in the longitudinal direction (as shown in the Y direction). Figure 10(As shown in the Z direction) The upper phase is flush. In the second type of device region 101B, in any one or two of the transmission gate transistor region PG, pull-down transistor region PD and pull-up transistor region PU, along the second direction, the sidewall of the channel layer 231 is recessed inward relative to the sidewall of the bottom fin 111 of the corresponding transistor region. The second direction is perpendicular to the first direction. The gate structure 501 is located on the substrate 121 and spans the plurality of channel layer structures 251 along the second direction. The gate structure 501 includes a gate dielectric layer 511 surrounding and covering the channel layer 231, and a gate electrode layer 521 surrounding and covering the gate dielectric layer 511.

[0032] In the SRAM device provided in this embodiment, during the formation of the SRAM device, a bottom fin 111 and a stacked structure including a channel layer 231 are typically formed in the same etching step. Then, along the second direction, a portion of the width of the channel layer 231 is removed to form the channel layer structure 251. Therefore, for the second type of SRAM device, the width of the bottom fin 111 in the same transistor region is consistent. That is to say, in this embodiment, for SRAM devices with different performance requirements, the same design layout can be used to form the stacked structure. Only the operating current requirements of each transistor region for different types of SRAM devices need to be considered. In any one or two of the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU, along the second direction, a portion of the width of the channel layer 231 is removed to form a channel layer 231 with a width smaller than the width of the bottom fin 111. This avoids separate layout design for different types of SRAM devices, saving design costs. Moreover, in the second type of SRAM devices, the width of the channel layer 231 is always smaller than the width of the bottom fin 111. Therefore, only the first type of SRAM device with the largest channel width needs to be verified for yield and reliability, simplifying the verification process and improving verification efficiency.

[0033] The substrate 121 provides the process operation basis for the formation of the SRAM device. The SRAM device includes a gate-all-around (GAA) transistor. The GAA transistor includes nanosheet FETs and nanowire FETs.

[0034] In this embodiment, the substrate 121 includes a substrate 101, and the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 101 may be a material suitable for process requirements or easy to integrate.

[0035] In this embodiment, the substrate 121 further includes a plurality of bottom fins 111 protruding from the substrate 101 and extending along a first direction. In this embodiment, the bottom fins 111 and the substrate 101 are integrally formed. In other embodiments, the bottom fins may also be semiconductor layers epitaxially grown on the substrate, thereby achieving precise control over the height of the bottom fins.

[0036] Accordingly, in this embodiment, the material of the bottom fin 111 is the same as the material of the substrate 101, and the material of the bottom fin 111 is silicon. In other embodiments, the material of the bottom fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the bottom fin may also be different from the material of the substrate.

[0037] In this embodiment, the bottom fins 111 of the same transistor region are of equal width in the first type of device region 101P and the second type of device region 101B.

[0038] That is, in the first type of device region 101P and the second type of device region 101B, the width of the bottom fin 111 in the transmission gate transistor region PG is equal, the width of the bottom fin 111 in the pull-down transistor region PD is equal, and the width of the bottom fin 111 in the pull-up transistor region PU is equal.

[0039] In this embodiment, the substrate 121 further includes an isolation layer 131, which covers the sidewall of the bottom fin 111. The isolation layer 131 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 131 is usually formed between NMOS transistors and PMOS transistors.

[0040] In this embodiment, the material of the isolation layer 131 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0041] In this embodiment, the substrate 121 includes a first type device region 101P for forming a first type SRAM device and a second type device region 101B for forming a second type SRAM device, wherein the first type SRAM device has a maximum channel width.

[0042] In this embodiment, the maximum channel width of the first type of SRAM device means that the channel width of each transistor in the first type of SRAM device is equal to the maximum value in the size specification of the corresponding transistor in the SRAM device.

[0043] Therefore, the first type of SRAM device has the maximum channel width, which is not limited to the fact that the channel width of each transistor in the first type of SRAM device is greater than the channel width of the corresponding transistor in the second type of SRAM device, but also includes cases where the channel width of a specific transistor is equal.

[0044] Since the first type of SRAM device has the maximum channel width, the stacked structure can be formed using the design layout of the first type of SRAM device for both the first type of SRAM device and the second type of SRAM device. It is only necessary to remove part of the width of the channel layer 231 along the second direction in any one or two of the transistor regions of the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU, according to the operating current requirements of each transistor region of the second type of SRAM device, to form a channel layer 231 with a width smaller than the width of the bottom fin 111, thereby forming the second type of SRAM device.

[0045] In this embodiment, the second type of device area 101B includes a first sub-type device area 101D, which is used to form a first sub-type SRAM device. The α ratio of the first sub-type SRAM device is greater than the α ratio of the first type of SRAM device.

[0046] The alpha ratio refers to the ratio of the operating current of the pull-up transistor region PU to that of the pull-down transistor region PD.

[0047] In this embodiment, both the first type of device region 101P and the second type of device region 101B include multiple memory cell regions S.

[0048] Specifically, in the first type of device region 101P and the second type of device region 101B, a plurality of memory cell regions S are arranged in a matrix along a first direction and a second direction. In the matrix arrangement of the plurality of memory cell regions S, the first direction is parallel to the column direction of the plurality of memory cell regions S, and the second direction is parallel to the row direction of the plurality of memory cell regions S.

[0049] In this embodiment, the storage cell region S includes a centrally symmetrical first sub-cell region S1 and a second sub-cell region S2. Both the first sub-cell region S1 and the second sub-cell region S2 include a transmission gate transistor region PG, a pull-down transistor region PD, and a pull-up transistor region PU. Figure 9 and Figure 11The diagram only shows the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU in the first sub-unit region S1. The second sub-unit region S2 is symmetrical to the first sub-unit region S1.

[0050] Specifically, the transmission gate transistor region PG and the pull-down transistor region PD are arranged adjacent to each other in the first direction, and the transmission gate transistor region PG and the pull-down transistor region PD are arranged adjacent to the pull-up transistor region PU in the second direction.

[0051] The transmission gate transistor region PG is used to form a transmission gate transistor, the pull-down transistor region PD is used to form a pull-down transistor, and the pull-up transistor region PU is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0052] The channel layer structure 251 includes one or more longitudinally spaced channel layers 231, which serve as channels for corresponding transistors. The longitudinal direction refers to the normal direction of the top surface of the substrate 121.

[0053] In this embodiment, the top, bottom and sidewalls of the channel layer 231 can all serve as channels, increasing the area in the channel layer 231 used as channels, thereby increasing the operating current of the SRAM device.

[0054] In this embodiment, the material of the channel layer 231 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel layer 231 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0055] refer to Figure 10 In the first type of device region 101P, the sidewall of the channel layer 231 along the second direction is flush with the sidewall of the bottom fin 111 of the corresponding transistor region in the longitudinal direction.

[0056] It should be noted that the corresponding transistor region refers to the transistor region where the channel layer 231 is located. For example, the sidewall of the channel layer 231 of the transmission gate transistor region PG is flush with the sidewall of the bottom fin 111 of the transmission gate transistor region PG in the longitudinal direction.

[0057] In this embodiment, for both the first type of SRAM device and the second type of SRAM device, the design layout of the first type of SRAM device can be used to form the stacked structure. Therefore, in the first type of device region 101P, it is not necessary to remove part of the width of the channel layer 231 along the second direction. Thus, in the first type of device region 101P, the sidewall of the channel layer 231 along the second direction is flush with the sidewall of the bottom fin 111 of the corresponding transistor region in the longitudinal direction.

[0058] Specifically, in the first type of device region 101P, along the second direction, the width of the bottom fin 111 in the pull-up transistor region PU is a first width, and the width of the bottom fin 111 in the pull-down transistor region PD and the transmission gate transistor region PG is equal and is a second width, which is twice the first width.

[0059] Therefore, in the first type of SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:2:2. In the semiconductor field, the first type of SRAM device is a commonly used SRAM device, and among the commonly used SRAM devices, the first type of SRAM device has a larger channel width. This is beneficial for forming a second type of SRAM device by removing part of the channel layer 231 of the first type of SRAM device, thereby facilitating the use of the design layout of the first type of SRAM device to form both the first type of SRAM device and the second type of SRAM device.

[0060] In this embodiment, in the second type of device region 101B, in any one or two of the transmission gate transistor region PG, pull-down transistor region PD and pull-up transistor region PU, along the second direction, the sidewall of the channel layer 231 is recessed inward relative to the sidewall of the bottom fin 111 of the corresponding transistor region, thereby enabling the formation of other types of SRAM devices.

[0061] It should be noted that the corresponding transistor region refers to the transistor region where the channel layer 231 is located. For example, along the second direction, the sidewall of the channel layer 231 of the transmission gate transistor region PG is recessed inward relative to the sidewall of the bottom fin 111 of the transmission gate transistor region PG.

[0062] It should also be noted that the sidewall of the channel layer 231 is recessed inward relative to the sidewall of the bottom fin 111 of the corresponding transistor region, which means that the width of the channel layer 231 is smaller than the width of the bottom fin 111.

[0063] Specifically, refer to Figure 12In the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-type device region 101D, along the second direction, the sidewall of the channel layer 231 is recessed inward relative to the sidewall of the bottom fin 111 of the corresponding transistor region.

[0064] In other words, in this embodiment, according to the operating current requirements of each transistor region of the first sub-type SRAM device, a portion of the width of the channel layer 231 is removed along the second direction in the transmission gate transistor region PG and the pull-down transistor region PD to form a channel layer 231 with a width smaller than the width of the bottom fin 111, thereby forming the first sub-type SRAM device.

[0065] Therefore, in this embodiment, by making the sidewall of the channel layer 231 recessed inward relative to the sidewall of the bottom fin 111 of the corresponding transistor region in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-type device region 101D, the effective width of the channel layer 231 is reduced, and the operating current of the transistor is reduced accordingly. This enables the formation of a first sub-type SRAM device with a smaller operating current. At the same time, by reducing the operating current of the pull-down transistor region PD, the α ratio of the first sub-type SRAM device is made larger, thereby enabling the first sub-type SRAM device to have good data retention stability.

[0066] Specifically, in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-type device region 101D, the width of the channel layer 231 is a first width.

[0067] Therefore, in the first sub-type SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:1. Thus, in the semiconductor field, the first sub-type SRAM device is also a commonly used SRAM device. Moreover, among the commonly used SRAM devices, the first sub-type SRAM device has better data retention stability, which is beneficial for the design layout using the first type of SRAM device. At the same time, it forms the first type of SRAM device and the first sub-type SRAM device commonly used in the semiconductor field.

[0068] The gate structure 501 is used to control the opening and closing of the channel of the SRAM device.

[0069] The gate dielectric layer 511 is used to isolate the gate electrode layer 521 from the channel layer 231.

[0070] The material of the gate dielectric layer 511 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0071] In this embodiment, the gate structure 501 is a metal gate structure. Therefore, the gate dielectric layer 511 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0072] It should be noted that the gate dielectric layer 511 may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 231. Specifically, the material of the gate oxide layer may be silicon oxide.

[0073] In this embodiment, the material of the gate electrode layer 521 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0074] Specifically, the gate electrode layer 521 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0075] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0076] Figures 13 to 15 This is a schematic diagram of another embodiment of the SRAM device of the present invention.

[0077] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that: the second type of device region includes a second sub-type device region, and in the transmission gate transistor region of the second sub-type device region, along the second direction, the sidewall of the channel layer is recessed inward relative to the bottom fin sidewall of the corresponding transistor region.

[0078] Reference Figures 13 to 15 For ease of illustration, Figure 13 Only the base is shown. Figure 14 This is a top view of any memory cell in the second type of device region. Figure 15 (a) is Figure 14 Cross-sectional view along the AA direction. Figure 15 (b) is Figure 14 A cross-sectional view along the BB direction shows that the second type of device region 103B includes a second sub-type device region 103V for forming a second sub-type SRAM device, wherein the β ratio of the second sub-type SRAM device is greater than the β ratio of the first type of SRAM device.

[0079] The beta ratio refers to the ratio of the operating current of the pull-down transistor region PD to the operating current of the transmission gate transistor region PG.

[0080] Specifically, refer to Figure 15 In the transmission gate transistor region PG of the second sub-type device region 103V, along the second direction, the sidewall of the channel layer 231 is recessed inward relative to the sidewall of the bottom fin 113 of the corresponding transistor region.

[0081] In other words, in this embodiment, during the formation of the SRAM device, according to the operating current requirements of each transistor region of the second sub-type SRAM device, a portion of the width of the channel layer 233 is removed along the second direction in the transmission gate transistor region PG to form a channel layer 233 with a width smaller than the width of the bottom fin 113, for forming the second sub-type SRAM device.

[0082] Therefore, in this embodiment, by making the sidewall of the channel layer 233 in the transmission gate transistor region PG of the second sub-type device region 103V recessed inward relative to the sidewall of the bottom fin 113 of the corresponding transistor region, the operating current of the transmission gate transistor is reduced. That is, the read current of the transmission gate transistor during read operation is reduced, which helps to reduce interference to the second sub-type SRAM device. This allows the second sub-type SRAM device to operate at a lower operating voltage. At the same time, by reducing the operating current of the transmission gate transistor region PG, the β ratio of the second sub-type SRAM device is made larger. Therefore, a second sub-type SRAM device with a larger static noise margin can be formed.

[0083] Specifically, in the transmission gate transistor region PG of the second sub-type device region 103V, the width of the channel layer 233 is a first width.

[0084] Therefore, in the second sub-type SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:2. Thus, in the semiconductor field, the second sub-type SRAM device is also a commonly used SRAM device. Moreover, among the commonly used SRAM devices, the second sub-type SRAM device has a larger static noise margin, which is beneficial for the design layout using the first type of SRAM device. At the same time, it forms the first type of SRAM device and the second sub-type SRAM device commonly used in the semiconductor field.

[0085] It should be noted that, in other embodiments, the second type of device area may also include a first sub-type device area and a second sub-type device area, which are used to form a first sub-type SRAM device and a second sub-type SRAM device, respectively, thereby adopting the design layout of the first type of SRAM device to simultaneously form the first type of SRAM device, the first sub-type SRAM device and the second sub-type SRAM device commonly used in the semiconductor field.

[0086] Figures 16 to 28 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming an SRAM device according to the present invention.

[0087] Reference Figures 16 to 18 For ease of illustration, Figure 16 Only the base is shown. Figure 17 This is a top view of any storage cell. Figure 18 (a) is Figure 17 Cross-sectional view along the AA direction. Figure 18 (b) is Figure 17 A cross-sectional view along the BB direction provides a substrate 120, including a first type device region 100P for forming a first type SRAM device and a second type device region 100B for forming a second type SRAM device. The first type SRAM device has a maximum channel width. Both the first type device region 100P and the second type device region 100B include a plurality of memory cell regions S. Each memory cell region S includes a first sub-cell region S1 and a second sub-cell region S2 that are adjacent and centrally symmetrical. Each first sub-cell region S1 and the second sub-cell region S2 includes a transmission gate transistor region PG, a pull-down transistor region PD, and a pull-up transistor region PU. The transmission gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU are formed on the substrate 120 along a first direction (e.g., Figure 17 A stacked structure 200 extending in the X direction (as shown in the middle X direction) includes one or more stacked channel stacks 210, each channel stack 210 including a first sacrificial layer 220 and a channel layer 230 located on the first sacrificial layer 220. The stacked structure 200 includes a channel region 200c along the first direction. The stacked structures 200 of each transistor region in the first type of device region 100P have a corresponding preset width, and the width of each stacked structure 200 in the second type of device region 100B is equal to the preset width of the corresponding transistor region in the first type of device region 100P.

[0088] The substrate 120 provides the process operation basis for the formation of the SRAM device. The SRAM device includes a fully enclosed gate transistor. The fully enclosed gate transistor includes nanosheet transistors and nanowire transistors.

[0089] In this embodiment, the substrate 120 includes a substrate 100, the material of which is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0090] In this embodiment, the substrate 120 further includes a plurality of bottom fins 110 protruding from the substrate 100 and extending along a first direction. In this embodiment, the bottom fins 110 and the substrate 100 are integrally formed. In other embodiments, the bottom fins may also be semiconductor layers epitaxially grown on the substrate, thereby achieving precise control over the height of the bottom fins.

[0091] Accordingly, in this embodiment, the material of the bottom fin 110 is the same as the material of the substrate 100, and the material of the bottom fin 110 is silicon. In other embodiments, the material of the bottom fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ionide, and the material of the bottom fin may also be different from the material of the substrate.

[0092] In this embodiment, the substrate 120 further includes an isolation layer 130, which covers the sidewall of the bottom fin 110. The isolation layer 130 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 130 is usually formed between NMOS transistors and PMOS transistors.

[0093] In this embodiment, the material of the isolation layer 130 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0094] In this embodiment, the substrate 120 includes a first type device region 100P for forming a first type SRAM device and a second type device region 100B for forming a second type SRAM device, wherein the first type SRAM device has a maximum channel width.

[0095] In this embodiment, the maximum channel width of the first type of SRAM device means that the channel width of each transistor in the first type of SRAM device is equal to the maximum value in the size specification of the corresponding transistor in the SRAM device.

[0096] Therefore, the first type of SRAM device has the maximum channel width, which is not limited to the fact that the channel width of each transistor in the first type of SRAM device is greater than the channel width of the corresponding transistor in the second type of SRAM device, but also includes cases where the channel width of a specific transistor is equal.

[0097] Since the first type of SRAM device has the maximum channel width, the stacked structure 200 can be formed using the design layout of the first type of SRAM device for both the first and second types of SRAM devices. Subsequently, it is only necessary to determine the operating current requirements of each transistor region for the second type of SRAM device within the second device region 100B, specifically within any one or two of the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU, along the second direction (e.g., ...). Figure 17 (As shown in the Y direction), by removing a portion of the width of the channel layer 230, the remaining width of the channel layer 230 can meet the requirements of the second type of SRAM device.

[0098] In this embodiment, the second type of device area 100B includes a first sub-type device area 100D, which is used to form a first sub-type SRAM device. The α ratio of the first sub-type SRAM device is greater than the α ratio of the first type of SRAM device.

[0099] In this embodiment, both the first type of device area 100P and the second type of device area 100B include multiple memory cell areas S.

[0100] Specifically, in the first type of device region 100P and the second type of device region 100B, a plurality of memory cell regions S are arranged in a matrix along a first direction and a second direction. In the matrix arrangement of the plurality of memory cell regions S, the first direction is parallel to the column direction of the plurality of memory cell regions S, and the second direction is parallel to the row direction of the plurality of memory cell regions S.

[0101] In this embodiment, the storage cell region S includes a centrally symmetrical first sub-cell region S1 and a second sub-cell region S2. Both the first sub-cell region S1 and the second sub-cell region S2 include a transmission gate transistor region PG, a pull-down transistor region PD, and a pull-up transistor region PU. Figure 17 The diagram only shows the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU in the first sub-unit region S1. The second sub-unit region S2 is symmetrical to the first sub-unit region S1.

[0102] Specifically, the transmission gate transistor region PG and the pull-down transistor region PD are arranged adjacent to each other in the first direction, and the transmission gate transistor region PG and the pull-down transistor region PD are arranged adjacent to the pull-up transistor region PU in the second direction.

[0103] The transmission gate transistor region PG is used to form a transmission gate transistor, the pull-down transistor region PD is used to form a pull-down transistor, and the pull-up transistor region PU is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0104] The channel layer 230 in the stacked structure 200 serves as the channel for the corresponding transistor. The first sacrificial layer 220 provides a process basis for the subsequent floating arrangement of the channel layer 230 and also occupies space for the subsequently formed gate structure. In subsequent processes, the first sacrificial layer 220 is removed, leaving the channel layer 230 floating. A gate structure is formed between the channel layer 230 and the substrate 120, and between adjacent channel layers 230, thereby causing the gate structure to surround and cover the channel layer 230.

[0105] In this embodiment, the top, bottom and sidewalls of the channel layer 230 can all serve as channels, increasing the area in the channel layer 230 used as channels, thereby increasing the operating current of the SRAM device.

[0106] refer to Figure 17 The stacked structure 200 includes a channel region 200c along the first direction. The channel layer 230 of the channel region 200c is used as a channel for an SRAM device.

[0107] In this embodiment, the location of the channel area 200c is indicated by a dashed line.

[0108] In this embodiment, the material of the channel layer 230 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0109] In this embodiment, the material of the first sacrificial layer 220 includes silicon germanide or silicon.

[0110] In this embodiment, the channel layer 230 is made of silicon, therefore, the first sacrificial layer 220 is made of silicon germanide.

[0111] The silicon germanide and silicon can form a large etching selectivity, which is beneficial when removing a portion of the width of the channel layer 230. The first sacrificial layer 220 has a good protective effect on the upper and lower surfaces of the channel layer 230, which is also beneficial for the subsequent removal of the first sacrificial layer 220 and reduces damage to the channel layer 230.

[0112] In other embodiments, a material with an etching selectivity that is suitable for the channel layer can be selected based on the material of the channel layer, so as to provide better protection for the channel layer and reduce damage to the channel layer when the first sacrificial layer is removed.

[0113] In this embodiment, the stacked structure 200 of each transistor region in the first type of device region 100P has a corresponding preset width, and the width of each stacked structure 200 in the second type of device region 100B is equal to the preset width of the corresponding transistor region in the first type of device region 100P.

[0114] In other words, in the first type of device region 100P and the second type of device region 100B, the width Ld of each stacked structure 200 in the pull-down transistor region PD is equal, the width Lg of each stacked structure 200 in the transmission gate transistor region PG is equal, and the width Lu of each stacked structure 200 in the pull-up transistor region PU is equal. Thus, the stacked structures 200 in the first type of device region 100P and the second type of device region 100B can all be formed using the same design layout. Moreover, with the width of the stacked structure 200 in the first type of device region 100P as the preset width, the design layout is the design layout for forming the first type of SRAM device.

[0115] Specifically, in the first type of device region 100P, along the second direction, the width of the stacked structure 200 in the pull-up transistor region PU is a first width, and the widths of the stacked structures 200 in the pull-down transistor region PD and the transmission gate transistor region PG are equal and are a second width, which is twice the first width.

[0116] Therefore, in the first type of SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:2:2. In the semiconductor field, the first type of SRAM device is a commonly used SRAM device, and among the commonly used SRAM devices, the first type of SRAM device has a larger channel width. This is beneficial for forming a second type of SRAM device by removing part of the channel layer 230 of the first type of SRAM device, thereby facilitating the use of the design layout of the first type of SRAM device to form both the first type of SRAM device and the second type of SRAM device.

[0117] refer to Figure 18 In the step of providing the substrate 120, a second sacrificial layer 240 covering the top of the stacked structure 200 is also formed on the stacked structure 200.

[0118] The second sacrificial layer 240 is used to protect the top surface of the topmost channel layer 230 in the stacked structure 200 when a portion of the width of the channel layer 230 is subsequently removed. The second sacrificial layer 240 is also used to occupy space for the gate structure to be formed subsequently.

[0119] In this embodiment, the material of the second sacrificial layer 240 is the same as that of the first sacrificial layer 220, which helps to simplify the formation process. Furthermore, since it is necessary to remove part of the second sacrificial layer 240 and the first sacrificial layer 220 later, it is beneficial to remove the second sacrificial layer 240 and the first sacrificial layer 220 in the same step, thus simplifying the removal process.

[0120] Specifically, the material of the second sacrificial layer 240 includes silicon germanide.

[0121] The silicon germanide and silicon can form a large etching selectivity, which is beneficial for the subsequent removal of a portion of the width of the channel layer 230. It also provides better protection for the top surface of the top channel layer 230 in the stacked structure 200, facilitates the removal of the second sacrificial layer 240, and reduces damage to the channel layer 230.

[0122] Reference Figure 19 and Figure 20 , Figure 19 For based on Figure 17 Top view, Figure 20 (a) is Figure 19 Cross-sectional view along the AA direction. Figure 20 (b) is Figure 19 A cross-sectional view along the BB direction. Before subsequent channel width adjustment processing, the forming method further includes: forming a pseudo-gate structure 300 spanning the stacked structure 200, the pseudo-gate structure 300 covering the sidewalls and top of the stacked structure 200 of the channel region 200c.

[0123] The pseudo-gate structure 300 is used to occupy space for the subsequent formation of the gate structure.

[0124] In this embodiment, the pseudo-gate structure 300 can be a single-layer structure or a multilayer structure, and the material of the pseudo-gate structure 300 includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the pseudo-gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0125] In this embodiment, the dummy gate structure 300 is a single-layer structure, and the material of the dummy gate structure 300 is amorphous silicon. Amorphous silicon does not have a crystal orientation; therefore, the etching rate uniformity and etching effect of amorphous silicon are better, thereby improving the subsequent removal effect of the dummy gate structure 300.

[0126] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the pseudo-gate structure 300 and the stacked structure 200. The material of the gate oxide layer may be silicon oxide.

[0127] Reference Figure 21 and Figure 22 , Figure 21 For based on Figure 19 Top view, Figure 22 (a) is Figure 21 Cross-sectional view along the AA direction. Figure 22 (b) is Figure 21 A cross-sectional view along the BB direction shows an interlayer dielectric layer 400 covering the sidewalls of the dummy gate structure 300, with the interlayer dielectric layer 400 exposed above the top of the dummy gate structure 300.

[0128] The interlayer dielectric layer 400 serves to isolate adjacent devices and also provides a process basis for the subsequent removal of the dummy gate structure 300 to form a gate opening.

[0129] The material of the interlayer dielectric layer 400 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0130] Continue to refer to Figure 21 and Figure 22 The pseudo-gate structure 300 is removed to form a gate opening 310 surrounded by the interlayer dielectric layer 400, and the gate opening 310 exposes the channel layer 230.

[0131] The gate opening 310 exposes the channel layer 230, preparing for the subsequent removal of a portion of the width of the channel layer 230. The gate opening 310 also provides space for the subsequent formation of the gate structure.

[0132] Reference Figure 23 and Figure 24 , Figure 23 For based on Figure 21 Top view of the first sub-category device area 100D, Figure 24 (a) is Figure 23 Cross-sectional view along the AA direction. Figure 24 (b) is Figure 23 In the cross-sectional view along the BB direction, the channel width is adjusted. In the second type of device region 100B, in any one or two of the transmission gate transistor region PG, pull-down transistor region PD and pull-up transistor region PU, a portion of the width of the channel layer 230 in the channel region 200c is removed along the second direction, where the second direction is perpendicular to the first direction.

[0133] For ease of illustration, Figure 23 The first sacrificial layer 220 and the second sacrificial layer 240 are not shown.

[0134] In the formation method provided by this embodiment of the invention, the width of each stacked structure 200 in the second type of device region 100B is equal to the preset width of the transistor corresponding to the first type of device region 100P. After forming the stacked structure 200, in the second type of device region 100B, in any one or two of the transistor regions of the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU, along the second direction, a portion of the width of the channel layer 230 in the channel region 200c is removed. Therefore, for different types of SRAM devices, the same design layout can be used to form the stacked structure 200, requiring only adjustments based on the operation of each transistor region of the second type of SRAM device. To meet current requirements, in any one or two of the transmission gate transistor region PG, pull-down transistor region PD, and pull-up transistor region PU, a portion of the width of the channel layer 230 in the channel region 200c is removed along the second direction to form channel layers 230 of different widths. This avoids separate layout design for different types of SRAM devices, saving design costs. Moreover, in the second type of device region 100B, there is a step of reducing the width of the channel layer 230 along the second direction. Therefore, after forming the SRAM device, only the yield and reliability verification of the first type of SRAM device with the largest channel width needs to be performed, simplifying the verification process and improving verification efficiency.

[0135] Moreover, in this embodiment, by removing a portion of the width of the channel layer 230 in the channel region 200c along the second direction, the width of the removed channel layer 230 can be flexibly selected, thereby more flexibly adapting to the performance requirements of various SRAM devices.

[0136] Specifically, a portion of the width of the channel layer 230 in the channel region 200c is removed through the gate opening 310.

[0137] In this embodiment, the sidewall of the gate opening 310 is typically also formed with a sidewall. Removing a portion of the channel layer 230 in the channel region 200c through the gate opening 310 has minimal impact on the channel layer 230 covered by the sidewall, which is beneficial for the growth of the source and drain doped regions. Furthermore, the gate opening 310 provides space for the formation of the gate structure. Removing a portion of the channel layer 230 using the gate opening 310 requires minimal modification to current processes and offers high process compatibility.

[0138] In this embodiment, the channel width adjustment process includes: in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-type device region 100D, along the second direction, removing a portion of the width of the channel layer 230 in the channel region 200c.

[0139] Therefore, in this embodiment, by removing a portion of the width of the channel layer 230 in the channel region 200c from the pull-down transistor region PD and the transmission gate transistor region PG in the first sub-type device region 100D, the effective width of the channel layer 230 is reduced, and the operating current of the transistor is correspondingly reduced. This allows the formation of a first sub-type SRAM device with a smaller operating current. At the same time, by reducing the operating current of the pull-down transistor region PD, the α ratio of the first sub-type SRAM device is made larger, thereby enabling the first sub-type SRAM device to have good data retention stability.

[0140] In this embodiment, a selective wet etching process is used to remove a portion of the width of the channel layer 230 in the channel region 200c. The selective wet etching process is an etching process in which the etching rate of the channel layer 230 is greater than the etching rate of the first sacrificial layer 220.

[0141] The selective wet etching process has a higher etching rate for the channel layer 230 than for the first sacrificial layer 220. Correspondingly, the selective wet etching process also has a higher etching rate for the channel layer 230 than for the second sacrificial layer 240. This allows the channel layer 230 to form a large etching selectivity with both the first sacrificial layer 220 and the second sacrificial layer 240. This is beneficial because when removing a portion of the width of the channel layer 230, the first sacrificial layer 220 and the second sacrificial layer 240 provide better protection for the upper and lower surfaces of the channel layer 230.

[0142] In this embodiment, the etching solution of the selective wet etching process includes a TMAH solution.

[0143] The TMAH solution has a higher etching rate for silicon and a lower etching rate for silicon germanide. In this embodiment, the channel layer 230 is made of silicon, and the first sacrificial layer 220 and the second sacrificial layer 240 are made of silicon germanide. Therefore, using the TMAH solution for selective wet etching makes it easier to remove a portion of the width of the channel layer 230, while reducing damage to the first sacrificial layer 220 and the second sacrificial layer 240, thus ensuring the protective effect of the first sacrificial layer 220 and the second sacrificial layer 240 on the upper and lower surfaces of the channel layer 230.

[0144] Specifically, the step of removing a portion of the width of the channel layer 230 in the channel region 200c along the second direction in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-device region 100D includes: forming a first mask layer 410 covering the pull-up transistor region PU in the first sub-device region 100D; and after forming the first mask layer 410, etching the channel layer 230 in the channel region 200c along the second direction in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-device region 100D.

[0145] The first mask layer 410 is used to protect the channel layer 230 in the pull-up transistor region PU when a portion of the width of the channel layer 230 in the pull-down transistor region PD and the transmission gate transistor region PG is removed.

[0146] It should be noted that the first mask layer 410 also covers the channel layer 230 of the first type of device region 100P, protecting the channel layer 230 of the first type of device region 100P from damage.

[0147] In this embodiment, the material of the first mask layer 410 includes photoresist, which is an easy-to-remove material, which is beneficial for the subsequent removal of the first mask layer 410 and also helps to reduce damage to other film layers when the first mask layer 410 is removed.

[0148] In this embodiment, after etching the channel layer 230 in the channel region 200c along the second direction in the pull-down transistor region PD and the transmission gate transistor region PG of the first sub-type device region 100D, the method further includes: removing the first mask layer 410.

[0149] In this embodiment, after the channel width adjustment process, the width of the remaining channel layer 230 in the channel region 200c is the first width in the pull-down transistor region PD and the transmission gate transistor region PG.

[0150] Therefore, in the first sub-type SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:1. Thus, in the semiconductor field, the first sub-type SRAM device is also a commonly used SRAM device. Moreover, among the commonly used SRAM devices, the first sub-type SRAM device has better data retention stability, which is beneficial for the design layout using the first type of SRAM device. At the same time, it forms the first type of SRAM device and the first sub-type SRAM device commonly used in the semiconductor field.

[0151] Reference Figures 25 to 28 , Figure 25 For based on Figure 21 Top view of the first type of device area 100P, Figure 26 (a) is Figure 25 Cross-sectional view along the AA direction. Figure 26 (b) is Figure 25 Cross-sectional view along the BB direction. Figure 27 For based on Figure 23 Top view of the first sub-category device area 100D, Figure 28 (a) is Figure 27 Cross-sectional view along the AA direction. Figure 28 (b) is Figure 27 A cross-sectional view along the BB direction, after removing a portion of the width of the channel layer 230 in the channel region 200c, removes the first sacrificial layer 220 in the channel region 200c.

[0152] The first sacrificial layer 220 is removed to provide space for the subsequent formation of the gate structure. At the same time, the surfaces of the channel layer 230 are exposed to prepare for the subsequent formation of the gate structure surrounding and covering the channel layer 230.

[0153] Specifically, the first sacrificial layer 220 in the channel region 200c is removed through the gate opening 310.

[0154] In this embodiment, wet etching is used to remove the first sacrificial layer 220. The wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which helps to reduce damage to the channel layer 230 during the removal of the first sacrificial layer 220.

[0155] In this embodiment, the step of removing the first sacrificial layer 220 in the channel region 200c further includes: removing the second sacrificial layer 240 in the channel region 200c.

[0156] The second sacrificial layer 240 of the channel region 200c is removed to expose the top surface of the top channel layer 230, in preparation for the subsequent formation of a gate structure surrounding and covering the channel layer 230.

[0157] In this embodiment, the second sacrificial layer 240 and the first sacrificial layer 220 are removed in the same step, simplifying the removal process.

[0158] Continue to refer to Figures 25 to 28 After removing the first sacrificial layer 220 in the channel region 200c, a gate structure 500 is formed in the channel region 200c that spans the channel layer 230. The gate structure 500 includes a gate dielectric layer 510 surrounding and covering the channel layer 230, and a gate electrode layer 520 surrounding and covering the gate dielectric layer 510.

[0159] Specifically, after removing the first sacrificial layer 220, the gate structure 500 is formed in the gate opening 310.

[0160] The gate structure 500 is used to control the opening and closing of the channel of the SRAM device.

[0161] The gate dielectric layer 510 is used to isolate the gate electrode layer 520 from the channel layer 230, and the gate electrode layer 520 from the substrate 120 of the channel region 200c.

[0162] The gate dielectric layer 510 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 510 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0163] It should be noted that the gate dielectric layer 510 may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 230. Specifically, the material of the gate oxide layer may be silicon oxide.

[0164] In this embodiment, the gate structure 500 is a metal gate structure. Therefore, the material of the gate electrode layer 520 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0165] Specifically, the gate electrode layer 520 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0166] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0167] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0168] Figures 29 to 30 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming an SRAM device according to the present invention.

[0169] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the pseudo-gate structure is formed after the channel width adjustment process.

[0170] Reference Figure 29 and Figure 30 , Figure 29 This is a top view of any memory cell area in the first sub-category device region. Figure 30 (a) is Figure 29 Cross-sectional view along the AA direction. Figure 30 (b) is Figure 29 In the cross-sectional view along the BB direction, after the channel width adjustment process is performed and before the first sacrificial layer 222 in the channel region 202c is subsequently removed, the method further includes: forming a pseudo-gate structure 302 that spans the stacked structure 202, the pseudo-gate structure 302 covering the sidewalls and top of the stacked structure 200 of the channel region 202c.

[0171] Specifically, after the formation of the stacked structure 202, the channel width adjustment process is performed. The channel width adjustment process is not limited to the channel layer 232 of the channel region 202c.

[0172] Correspondingly, when performing the channel width adjustment process, it is only necessary to adjust the formation position of the first mask layer to protect the areas that do not require channel width adjustment.

[0173] For a detailed description of the pseudo-gate structure 302, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0174] It should be noted that, Figure 29 and Figure 30 Only a schematic diagram of the first sub-type device region 102D is shown. The formation steps of the first type device region and the second type device region are the same.

[0175] Figures 31 to 33 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming an SRAM device according to the present invention.

[0176] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that: the second type of device region includes a second sub-type device region, and in the transmission gate transistor region of the second sub-type device region, a portion of the width of the channel layer in the channel region is removed along the second direction.

[0177] It should be noted that, as can be seen from the foregoing embodiments, the pseudo-gate structure can be formed before or after the channel width adjustment process. In this embodiment, the pseudo-gate structure is formed before the channel width adjustment process. In other embodiments, the pseudo-gate structure can also be formed after the channel width adjustment process.

[0178] Reference Figures 31 to 33 For ease of illustration, Figure 31 Only the base is shown. Figure 32 This is a top view of any memory cell area in the second sub-category device region. Figure 33 (a) is Figure 32 Cross-sectional view along the AA direction. Figure 33 (b) is Figure 32 A cross-sectional view along the BB direction shows that the second type of device region 104B includes a second sub-type device region 104V for forming a second sub-type SRAM device, wherein the β ratio of the second sub-type SRAM device is greater than the β ratio of the first type of SRAM device.

[0179] In this embodiment, the channel width adjustment process includes: in the transmission gate transistor region PG of the second sub-type device region 104V, along the second direction, removing a portion of the width of the channel layer 234 in the channel region 204c.

[0180] Therefore, in this embodiment, by removing a portion of the channel layer 234 in the channel region 204c from the transmission gate transistor region PG in the second sub-type device region 104V, the operating current of the transmission gate transistor is reduced. In other words, the read current of the transmission gate transistor during read operations is reduced, which helps to reduce interference to the second sub-type SRAM device. This allows the second sub-type SRAM device to operate at a lower operating voltage. At the same time, by reducing the operating current of the transmission gate transistor region PG, the β ratio of the second sub-type SRAM device is made larger, which enables the formation of a second sub-type SRAM device with a larger static noise margin.

[0181] Specifically, the step of removing a portion of the width of the channel layer 234 in the channel region 204c along the second direction in the transmission gate transistor region PG of the second sub-device region 104V includes: forming a second mask layer 414 covering the pull-up transistor region PU and the pull-down transistor region PD in the second sub-device region 104V; after forming the second mask layer 414, etching the channel layer 234 in the channel region 204c along the second direction in the transmission gate transistor region PG of the second sub-device region 104V exposed by the second mask layer 414.

[0182] The second mask layer 414 is used to protect the channel layer 234 in the pull-up transistor region PU and the pull-down transistor region PD when a portion of the width of the channel layer 234 in the transmission gate transistor region PG is removed.

[0183] In this embodiment, the material of the second mask layer 414 includes photoresist, which is an easy-to-remove material, which is beneficial for the subsequent removal of the second mask layer 414 and reduces damage to other film layers when the second mask layer 414 is removed.

[0184] It should be noted that the second mask layer 414 also covers the channel layer 234 of the first type of device region 104P, protecting the channel layer 234 of the first type of device region 104P from damage.

[0185] In this embodiment, after etching the channel layer 234 in the channel region 204c along the second direction in the transmission gate transistor region PG of the second sub-type device region 100V, the method further includes: removing the second mask layer 414.

[0186] Specifically, after the channel width adjustment process, in the transmission gate transistor region PG, the width of the remaining channel layer 234 in the channel region 204c is the first width.

[0187] Therefore, in the second sub-type SRAM device, the channel width ratio of the pull-up transistor region PU, the transmission gate transistor region PG, and the pull-down transistor region PD is 1:1:2. Thus, in the semiconductor field, the second sub-type SRAM device is also a commonly used SRAM device. Moreover, among the commonly used SRAM devices, the second sub-type SRAM device has a larger static noise margin, which is beneficial for the design layout using the first type of SRAM device. At the same time, it forms the first type of SRAM device and the second sub-type SRAM device commonly used in the semiconductor field.

[0188] It should be noted that, in other embodiments, the second type of device area may also include a first sub-type device area and a second sub-type device area, which are used to form a first sub-type SRAM device and a second sub-type SRAM device, respectively, thereby adopting the design layout of the first type of SRAM device to simultaneously form the first type of SRAM device, the first sub-type SRAM device and the second sub-type SRAM device commonly used in the semiconductor field.

[0189] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An SRAM device, characterized in that, include: The substrate includes a substrate and a plurality of bottom fins protruding from the substrate and extending along a first direction. The substrate includes a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device. The first type SRAM device has a maximum channel width. Both the first type device region and the second type device region include a plurality of memory cell regions. Each memory cell region includes a first sub-cell region and a second sub-cell region that are adjacent and centrally symmetrical. Both the first sub-cell region and the second sub-cell region include a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region. The bottom fins of the same transistor region in the first type device region and the second type device region have equal widths. A channel layer structure is suspended above the bottom fin. The channel layer structure includes one or more spaced channel layers along the longitudinal direction. The channel layer structure extends along the first direction. In the first type of device region, the sidewall of the channel layer along the second direction is flush with the sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction. In the second type of device region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, the sidewall of the channel layer is recessed inward relative to the sidewall of the bottom fin of the corresponding transistor region along the second direction. The second direction is perpendicular to the first direction. A gate structure located on the substrate and spanning a plurality of the channel layer structures along the second direction, the gate structure including a gate dielectric layer surrounding the channel layers and a gate electrode layer surrounding the gate dielectric layer.

2. The SRAM device as claimed in claim 1, characterized in that, In the first type of device region, along the second direction, the width of the bottom fin in the pull-up transistor region is a first width, and the width of the bottom fin in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, which is twice the first width.

3. The SRAM device as described in claim 1 or 2, characterized in that, The second type of device region includes one or both of a first sub-type device region for forming a first sub-type SRAM device and a second sub-type device region for forming a second sub-type SRAM device, wherein the α ratio of the first sub-type SRAM device is greater than the α ratio of the first type SRAM device, and the β ratio of the second sub-type SRAM device is greater than the β ratio of the first type SRAM device. In the pull-down transistor region and the transmission gate transistor region of the first sub-type device region, along the second direction, the sidewall of the channel layer is recessed inward relative to the bottom fin sidewall of the corresponding transistor region; In the transmission gate transistor region of the second sub-type device region, along the second direction, the sidewall of the channel layer is recessed inward relative to the bottom fin sidewall of the corresponding transistor region.

4. The SRAM device as described in claim 3, characterized in that, In the first type of SRAM device, the channel width ratio of the pull-up transistor region, the transmission gate transistor region and the pull-down transistor region is 1:2:2; In the first subclass of SRAM device, the channel width ratio of the pull-up transistor region, the transmission gate transistor region, and the pull-down transistor region is 1:1:

1.

5. The SRAM device as described in claim 4, characterized in that, In the first type of device region, along the second direction, the width of the bottom fin in the pull-up transistor region is a first width, and the width of the bottom fin in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, the second width being twice the first width; In the pull-down transistor region and transmission gate transistor region of the first sub-type device region, the width of the channel layer is a first width.

6. The SRAM device as claimed in claim 3, characterized in that, In the first type of SRAM device, the channel width ratio of the pull-up transistor region, the transmission gate transistor region and the pull-down transistor region is 1:2:2; In the second subclass of SRAM devices, the channel width ratio of the pull-up transistor region, the transmission gate transistor region, and the pull-down transistor region is 1:1:

2.

7. The SRAM device as claimed in claim 6, characterized in that, In the first type of device region, along the second direction, the width of the bottom fin in the pull-up transistor region is a first width, and the width of the bottom fin in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, the second width being twice the first width; In the transmission gate transistor region of the second sub-type device region, the width of the channel layer is a first width.

8. The SRAM device as claimed in claim 1, characterized in that, The channel layer material includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

9. The SRAM device as claimed in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

10. A method for forming an SRAM device, characterized in that, include: A substrate is provided, including a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device. The first type SRAM device has a maximum channel width. Both the first type device region and the second type device region include multiple memory cell regions. Each memory cell region includes adjacent and centrally symmetrical first and second sub-cell regions. Each first and second sub-cell region includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region. A stacked structure extending along a first direction is formed on the substrate of the transmission gate transistor region, the pull-down transistor region, and the pull-up transistor region. The stacked structure includes one or more stacked channel layers. The channel layer includes a first sacrificial layer and a channel layer located on the first sacrificial layer. The stacked structure includes a channel region along the first direction. The stacked structure of each transistor region in the first type device region has a corresponding preset width. The width of each stacked structure in the second type device region is equal to the preset width of the corresponding transistor region in the first type device region. A channel width adjustment process is performed. In the second type of device region, in any one or two of the transmission gate transistor region, pull-down transistor region, and pull-up transistor region, a portion of the width of the channel layer in the channel region is removed along the second direction, wherein the second direction is perpendicular to the first direction. After removing a portion of the width of the trench layer in the trench region, the first sacrificial layer in the trench region is removed; After removing the first sacrificial layer in the channel region, a gate structure spanning the channel layer is formed in the channel region. The gate structure includes a gate dielectric layer surrounding the channel layer and a gate electrode layer surrounding the gate dielectric layer.

11. The method for forming an SRAM device as described in claim 10, characterized in that, In the step of providing the substrate, in the first type of device region, along the second direction, the width of the stacked structure in the pull-up transistor region is a first width, and the width of the stacked structure in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, which is twice the first width.

12. The method for forming an SRAM device as described in claim 10 or 11, characterized in that, In the step of providing the substrate, the second type of device region includes a first sub-type device region for forming a first sub-type SRAM device, wherein the α ratio of the first sub-type SRAM device is greater than the α ratio of the first type of SRAM device. The channel width adjustment process includes: in the pull-down transistor region and the transmission gate transistor region of the first sub-type device region, along the second direction, removing a portion of the width of the channel layer in the channel region.

13. The method for forming an SRAM device as described in claim 12, characterized in that, In the step of providing the substrate, in the first type of device region, along the second direction, the width of the stacked structure in the pull-up transistor region is a first width, and the width of the stacked structure in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, the second width being twice the first width; After the channel width adjustment process, in the pull-down transistor region and the transmission gate transistor region, the width of the remaining channel layer in the channel region is the first width.

14. The method for forming an SRAM device as described in claim 12, characterized in that, In the pull-down transistor region and the transmission gate transistor region of the first sub-device region, the step of removing a portion of the width of the channel layer in the channel region along the second direction includes: forming a first mask layer covering the pull-up transistor region in the first sub-device region; After the first mask layer is formed, the channel layer in the channel region is etched along the second direction in the pull-down transistor region and the transmission gate transistor region of the first sub-type device region.

15. The method for forming an SRAM device as described in claim 10, characterized in that, In the step of providing the substrate, the second type of device region includes a second sub-type device region for forming a second sub-type SRAM device, wherein the β ratio of the second sub-type SRAM device is greater than the β ratio of the first type SRAM device. The channel width adjustment process includes: in the transmission gate transistor region of the second sub-type device region, along the second direction, removing a portion of the width of the channel layer in the channel region.

16. The method for forming an SRAM device as described in claim 15, characterized in that, In the step of providing the substrate, in the first type of device region, along the second direction, the width of the stacked structure in the pull-up transistor region is a first width, and the width of the stacked structure in the pull-down transistor region and the transmission gate transistor region is equal and is a second width, the second width being twice the first width; After the channel width adjustment process, in the transmission gate transistor region, the width of the remaining channel layer in the channel region is the first width.

17. The method for forming an SRAM device as described in claim 15, characterized in that, In the transmission gate transistor region of the second sub-type device region, the step of removing a portion of the width of the channel layer in the channel region along the second direction includes: forming a second mask layer covering the pull-up transistor region and the pull-down transistor region in the second sub-type device region; After forming the second mask layer, the channel layer in the channel region is etched along the second direction in the transmission gate transistor region of the second sub-type device region.

18. The method for forming an SRAM device as described in claim 10, characterized in that, Before performing the channel width adjustment process, the forming method further includes: forming a pseudo-gate structure that spans the stacked structure, the pseudo-gate structure covering the sidewalls and top of the stacked structure in the channel region; An interlayer dielectric layer is formed covering the sidewalls of the pseudo-gate structure, with the interlayer dielectric layer exposed at the top of the pseudo-gate structure; Remove the pseudo-gate structure to form a gate opening surrounded by the interlayer dielectric layer, the gate opening exposing the channel layer; The channel layer, representing a portion of the width of the channel region, is removed through the gate opening; After removing a portion of the width of the channel layer in the channel region, the first sacrificial layer in the channel region is removed through the gate opening; After removing the first sacrificial layer, the gate structure is formed in the gate opening.

19. The method for forming an SRAM device as described in claim 10, characterized in that, After performing the channel width adjustment process, and before removing the first sacrificial layer in the channel region, the method further includes: forming a pseudo-gate structure that spans the stacked structure, the pseudo-gate structure covering the sidewalls and top of the stacked structure in the channel region; An interlayer dielectric layer is formed covering the sidewalls of the pseudo-gate structure, with the interlayer dielectric layer exposed at the top of the pseudo-gate structure; Remove the pseudo-gate structure to form a gate opening surrounded by the interlayer dielectric layer, the gate opening exposing the first sacrificial layer; The first sacrificial layer in the channel region is removed through the gate opening; After removing the first sacrificial layer, the gate structure is formed in the gate opening.

20. The method for forming an SRAM device as described in claim 10, characterized in that, In the step of providing the substrate, a second sacrificial layer covering the top of the stacked structure is further formed on the stacked structure; The step of removing the first sacrificial layer in the trench region further includes: removing the second sacrificial layer in the trench region.

21. The method for forming an SRAM device as described in claim 10, characterized in that, In the step of removing a portion of the width of the channel layer in the channel region along the second direction, a selective wet etching process is used to remove a portion of the width of the channel layer in the channel region. The selective wet etching process is an etching process in which the etching rate of the channel layer is greater than the etching rate of the first sacrificial layer.

22. The method for forming an SRAM device as described in claim 21, characterized in that, The etching solution used in the selective wet etching process includes a TMAH solution.

23. The method for forming an SRAM device as described in claim 10, characterized in that, The material of the channel layer includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the first sacrificial layer includes silicon germanide or silicon.

Images