Display device and electronic equipment

Abstract

A display device with a small circuit area and low power consumption is provided. One embodiment of the present invention is a display device including an image signal line, an image data holding unit, a correction data holding unit, and a display element, wherein the correction data holding unit is electrically connected to the image signal line, the image signal line is electrically connected to the image data holding unit, and the image data holding unit is electrically connected to the display element. The image signal line has a function of holding first image data using parasitic capacitance, and the image data holding unit has a function of holding the first image data. The correction data holding unit has: a function of holding correction data; and a function of holding correction data in the correction data holding unit after the image data holding unit holds the first image data, thereby generating second image data having more grayscale than the first image data based on the first image data and the correction data.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, camera devices, storage devices, processors, electronic devices, systems, their driving methods, their manufacturing methods or their inspection methods can be cited. Background Art

[0003] In recent years, display devices included in mobile phones such as smartphones, tablet information terminals, notebook PCs (personal computers), portable game consoles, etc. have been improved in various aspects. For example, display devices are developed to improve resolution, improve color reproducibility, reduce drive circuits, or reduce power consumption. In addition, for example, Patent Document 1 discloses an invention of a source driver IC for a display device including a liquid crystal element using a multi-grayscale linear digital-to-analog conversion circuit in order to display a multi-grayscale image.

[0004] Another example is a technology of applying a transistor using an oxide semiconductor for a semiconductor thin film as a switching element included in a pixel circuit in a display device.

[0005] As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, in addition to single metal oxides such as indium oxide and zinc oxide, multinary metal oxides are also known. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot.

[0006] Through research on IGZO, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystal nor amorphous have been discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Non-patent documents 4 and 5 disclose an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure and also having tiny crystals.

[0007] It has been reported that a transistor using IGZO in an active layer has an extremely low off-state current (see non-patent document 6), and an LSI and a display device using this characteristic (see non-patent document 7 and non-patent document 8). In addition, patent document 2 discloses an invention in which a transistor including IGZO in an active layer is used in a pixel circuit of a display device.

[0008] [Prior technical literature]

[0009] [Patent Document]

[0010] [Patent Document 1] U.S. Patent No. 8462145

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2010-156963

[0012] [Non-patent literature]

[0013] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0014] [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0015] [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p. 151-154

[0016] [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022

[0017] [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164

[0018] [Non-patent document 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0019] [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217

[0020] [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0021] Technical problem to be solved by the invention

[0022] As conditions for displaying high-quality images, the display device is required to have, for example, high resolution, multiple grayscales, and a wide color gamut. For example, in a display device including a light-emitting element such as an organic EL (Electro Luminescence) element or a liquid crystal element such as a transmissive liquid crystal element or a reflective liquid crystal element, in order to realize a multi-grayscale image, it is necessary to appropriately design a source driver circuit.

[0023] In order to process multi-grayscale image data, it is necessary to improve the resolution of the digital-to-analog conversion circuit included in the source driver circuit. The digital-to-analog conversion circuit can output analog values ​​(voltages) more finely by improving its resolution. However, when designing a digital-to-analog conversion circuit with high resolution, the area of ​​the digital-to-analog conversion circuit increases.

[0024] One of the purposes of one embodiment of the present invention is to provide a display device capable of generating multi-grayscale image data. In addition, one of the purposes of one embodiment of the present invention is to provide a novel display device. In addition, one of the purposes of one embodiment of the present invention is to provide a novel electronic device including the above-mentioned display device.

[0025] Another object of one embodiment of the present invention is to provide a display device having a source driver circuit with a small circuit area. Another object of one embodiment of the present invention is to provide a display device having a source driver circuit with low power consumption.

[0026] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned in this section but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned in this section from the description of the specification or the drawings. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention does not need to achieve all of the above-mentioned purposes and other purposes.

[0027] Solutions to technical problems (1)

[0029] One embodiment of the present invention is a display device, including a first circuit, a second circuit and an image signal line, wherein the first circuit includes an image holding unit and a display element, the second circuit includes a correction data holding unit, the second circuit is electrically connected to the image signal line, the image signal line is electrically connected to the first circuit, the image data holding unit is electrically connected to the display element, the first circuit has a function of holding first image data in the image data holding unit, the second circuit has a function of holding correction data in the correction data holding unit and a function of correcting the first image data held in the image signal line and the image data holding unit into second image data based on the correction data, and the display element has a function of displaying an image corresponding to the second image data. (2)

[0031] In addition, one embodiment of the present invention is a display device having the structure of (1) above, wherein the second circuit includes first to third switches and a first capacitor, the first circuit includes a fourth switch and a second capacitor, the first terminal of the first switch is electrically connected to the first terminal of the first capacitor and an image signal line, the second terminal of the first switch is electrically connected to the first terminal of the second switch, a correction data holding unit is electrically connected to the second terminal of the second switch, the second terminal of the first capacitor and the first terminal of the third switch, the first terminal of the fourth switch is electrically connected to the image signal line, and the image data holding unit is electrically connected to the second terminal of the fourth switch and the second capacitor. (3)

[0033] In addition, one embodiment of the present invention is a display device having the structure of (2) above, wherein at least one of the first to fourth switches is a transistor including one of metal oxide and silicon in a channel formation region. (4)

[0035] In addition, one embodiment of the present invention is a display device having the structure of (2) or (3) above, which has first to fourth functions. The first function includes: a function of writing a first potential to a correction data holding unit by turning off the second switch and turning on the third switch; and a function of writing a second potential corresponding to the first image data to the image signal line and the image data holding unit by turning off the second switch and turning on both the first switch and the fourth switch. The second function includes: a function of putting the image signal line and the image data holding unit in an electrically floating state by turning off the first switch and turning on the fourth switch. The third function includes: a function of writing a third potential corresponding to the correction data to the correction data holding unit by turning off both the first switch and the third switch and turning on the second switch; and a function of changing the second potential held by the image signal line and the image data holding unit to a fourth potential corresponding to the second image data when the potential of the second terminal of the first capacitor changes from the first potential to the third potential. The fourth function includes: a function of driving the display element according to the fourth potential by turning off the fourth switch. (5)

[0037] In addition, one embodiment of the present invention is a display device having the structure of (4) above, wherein the second potential is a potential corresponding to a high bit of second image data, and the third potential is a potential corresponding to a low bit of the second image data. (6)

[0039] In addition, one embodiment of the present invention is a display device having any one of the structures (2) to (5) above, wherein the display element is a liquid crystal element, and a first terminal of the liquid crystal element is electrically connected to an image data storage unit. (7)

[0041] In addition, one embodiment of the present invention is a display device having any of the structures described in (2) to (5) above, wherein the display element is a light-emitting element and includes a driving circuit unit, the driving circuit unit includes a driving transistor, a gate of the driving transistor is electrically connected to an image data holding unit, and a first terminal of the driving transistor is electrically connected to a second terminal of a second capacitor and an input terminal of the light-emitting element. (8)

[0043] Another embodiment of the present invention is an electronic device including a display device having any one of the structures (1) to (7) described above, and a housing.

[0044] Effects of the Invention

[0045] According to one embodiment of the present invention, a display device capable of generating multi-grayscale image data can be provided. In addition, according to one embodiment of the present invention, a novel display device can be provided. In addition, according to one embodiment of the present invention, an electronic device including the above display device can be provided.

[0046] According to one embodiment of the present invention, a display device including a source driver circuit with a small circuit area can be provided. According to one embodiment of the present invention, a display device including a source driver circuit with low power consumption can be provided.

[0047] Note that the effects of one embodiment of the present invention are not limited to the above-mentioned effects. The effects listed above do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned in this section but will be described in the following description. Those skilled in the art can derive and appropriately extract the effects that are not mentioned in this section from the description of the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned effects and other effects. Therefore, one embodiment of the present invention sometimes does not have the effects listed above depending on the circumstances.

[0048] BRIEF DESCRIPTION OF THE DRAWINGS

[0049] [ Figure 1 ] is a block diagram showing an example of a display device.

[0050] [ Figure 2A and Figure 2B ] is a block diagram showing an example of a display device.

[0051] [ Figure 3 ] is a circuit diagram showing an example of a display device.

[0052] [ Fig.4A1 , Figure 4A2 , Figure 4B1 and Figure 4B2 ] is a circuit diagram showing an example of a pixel.

[0053] [ Figure 5A and Figure 5B ] is a circuit diagram showing an example of a circuit included in a display device.

[0054] [ Figure 6 ] is a circuit diagram showing an example of a display device.

[0055] [ Figure 7 ] is a timing diagram illustrating an example of the operation of a display device.

[0056] [ Fig. 8Aand Figure 8B ] is a top view showing an example of a display device.

[0057] [ Fig. 9A and Fig. 9B ] is a perspective view showing an example of a touch panel.

[0058] [ Fig.10 ] is a cross-sectional view showing an example of a display device.

[0059] [ Fig.11A1 , Fig.11A2 , Fig.11B1 , Fig.11B2 , Fig.11C1 and Fig.11C2 ] is a cross-sectional view showing a structural example of a transistor.

[0060] [ Fig.12A1 , Fig.12A2 , Fig.12A3 , Fig.12B1 , Fig.12B2 , Fig.12C1 and Fig.12C2 ] is a cross-sectional view showing a structural example of a transistor.

[0061] [ Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F ] is a perspective view showing an example of an electronic device.

[0062] [ Fig.14A and Fig. 14B ] is a perspective view showing an example of an electronic device.

[0063] [ Fig.15 ] is a cross-sectional view showing a structural example of a DOSRAM.

[0064] [ Fig.16 ] is a circuit diagram showing the display device described in the embodiment.

[0065] [ Fig.17 ] is shown Fig.16 FIG. 1 is a diagram showing a change in potential corresponding to image data caused by writing of a potential corresponding to correction data in a display device.

[0066] Modes for Carrying Out the Invention

[0067] In this specification, etc., metal oxide refers to the oxide of metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification function, a rectification function and a switching function, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor), referred to as OS. In addition, OS FET or OS transistor can be referred to as a transistor comprising a metal oxide or an oxide semiconductor.

[0068] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0069] (Implementation Method 1)

[0070] In this embodiment, a display device which is one embodiment of the present invention is described.

[0071] <Configuration Example 1 of Display Device>

[0072] First, a configuration example of a display device will be described. Figure 1 2 is a block diagram showing an example of a display device including a display element. The display device DD includes a display portion PA, a source driver circuit SD, and a gate driver circuit GD.

[0073] The display portion PA includes a plurality of pixels PIX. Figure 1 Only one of the plurality of pixels PIX included in the display portion PA is shown, and the other pixels PIX are omitted. In addition, the plurality of pixels PIX included in the display portion PA are preferably arranged in a matrix.

[0074] exist Figure 1In the display unit PA, the pixel PIX is electrically connected to the source driver circuit SD through the wiring SL used as an image signal line. In addition, the pixel PIX is electrically connected to the gate driver circuit GD through the wiring GL used as a selection signal line. Note that since the display unit PA includes a plurality of pixels PIX, the plurality of pixels PIX can be electrically connected to the wiring SL. Similarly, the plurality of pixels PIX can be electrically connected to the wiring GL. In addition, a plurality of wirings SL and a plurality of wirings GL can be provided according to the number of pixels PIX included in the display unit PA. Furthermore, according to the circuit structure of the pixel PIX, one pixel PIX can be electrically connected to a plurality of wirings SL or a plurality of wirings GL.

[0075] The pixel PIX may have a structure including more than one sub-pixel. For example, the pixel PIX may have the following structures: a structure including one sub-pixel (any color among red (R), green (G), blue (B), and white (W), etc.); a structure including three sub-pixels (three colors of red (R), green (G), and blue (B), etc.); or a structure including four sub-pixels (four colors of red (R), green (G), blue (B), and white (W), or four colors of red (R), green (G), blue (B), and yellow (Y), etc.). Note that the color elements applicable to the sub-pixels are not limited to the above combinations, and cyan (C) and magenta (M), etc. may also be combined as needed.

[0076] The source driver circuit SD has a function of generating image data to be input to the pixels PIX in the display portion PA and a function of transmitting the image data to the pixels PIX.

[0077] The source driver circuit SD may include, for example, a shift register SR, a latch circuit LAT, a level conversion circuit LVS, a digital-to-analog conversion circuit DAC, an amplifier circuit AMP, and a data bus wiring DB. Figure 1 In the embodiment, the output terminal of the shift register SR is electrically connected to the clock input terminal of the latch circuit LAT, the input terminal of the latch circuit LAT is electrically connected to the data bus wiring DB, the output terminal of the latch circuit LAT is electrically connected to the input terminal of the level conversion circuit LVS, the output terminal of the level conversion circuit LVS is electrically connected to the input terminal of the digital-to-analog conversion circuit DAC, the output terminal of the digital-to-analog conversion circuit DAC is electrically connected to the input terminal of the amplifier circuit AMP, and the output terminal of the amplifier circuit AMP is electrically connected to the display portion PA.

[0078] With respect to one wiring SL, Figure 1The latch circuit LAT, level conversion circuit LVS, digital analog conversion circuit DAC and amplifier circuit AMP shown in FIG. In other words, it is necessary to set a plurality of latch circuits LAT, a plurality of level conversion circuits LVS, a plurality of digital analog conversion circuits DAC and a plurality of amplifier circuits AMP according to the number of wirings SL. In this case, the shift register SR can send pulse signals to each clock input terminal of the plurality of latch circuits LAT in sequence.

[0079] The data bus wiring DB is a wiring for transmitting a digital signal including image data input to the display unit PA. The image data has grayscale, and the larger the grayscale, the smoother the change in color or brightness can be expressed, and a more natural image can be displayed on the display unit PA. However, the larger the grayscale, the larger the data volume of the image data, so a high-resolution digital-to-analog conversion circuit is required.

[0080] A digital signal including image data is input to an input terminal of the latch circuit LAT from the data bus wiring DB, and the latch circuit LAT performs one of an operation of holding the image data and an operation of outputting the held image data from an output terminal in response to a signal sent from the shift register SR.

[0081] The level conversion circuit LVS has the function of converting an input signal into an output signal having a larger or smaller amplitude voltage. Figure 1 In the embodiment, the level conversion circuit LVS has a function of converting the amplitude voltage of the digital signal including the image data sent from the latch circuit LAT into an amplitude voltage for the digital-to-analog conversion circuit DAC to operate appropriately.

[0082] The digital-to-analog converter circuit DAC has the function of converting an input digital signal including image data into an analog signal and outputting the analog signal from an output terminal. In particular, when displaying multi-grayscale image data on the display unit PA, the digital-to-analog converter circuit DAC needs to be a high-resolution digital-to-analog converter circuit.

[0083] The amplifier circuit AMP has a function of amplifying an analog signal input to an input terminal and outputting it to an output terminal. By providing the amplifier circuit AMP between the digital-to-analog conversion circuit DAC and the display unit PA, image data can be stably sent to the display unit PA. As the amplifier circuit AMP, a voltage follower circuit including an operational amplifier or the like can be applied. Note that, in the case of using a circuit having a differential input circuit as the amplifier circuit, the bias voltage of the differential input circuit is preferably infinitely close to 0V.

[0084] By performing the above-described operation, the source driver circuit SD can convert a digital signal including image data transmitted from the data bus wiring DB into an analog signal and transmit the signal to the display portion PA.

[0085] The gate driver circuit GD has a function of selecting a pixel PIX to which image data is input among a plurality of pixels PIX included in the display portion PA.

[0086] As a method of inputting image data to the display unit PA, for example, there is a method in which the gate driver circuit GD sends a selection signal to a plurality of pixels PIX electrically connected to a certain wiring GL, so that the writing switch elements of the image data contained in the plurality of pixels PIX are turned on, and then the image data is sent from the source driver circuit SD to the plurality of pixels PIX through the wiring SL to write the image data. Therefore, in this specification, the wiring GL can be replaced by a gate line, a selection signal line, etc., and the wiring SL can be replaced by a source line, a data line, an image signal line, etc.

[0087] Note that one embodiment of the present invention is not limited to Figure 1 As one embodiment of the present invention, the components of the display device DD are appropriately changed according to the design specifications, purpose, and other circumstances.

[0088] When displaying a multi-grayscale image on the display unit PA, the resolution of the digital-to-analog converter circuit DAC may be increased, but the digital-to-analog converter circuit DAC may be increased, so the circuit area of ​​the source driver circuit SD may be increased. When circuit elements such as transistors and capacitors included in the source driver circuit SD are reduced in size to reduce the circuit area of ​​the source driver circuit SD, the electrical characteristics of the circuit elements may be adversely affected by the influence of parasitic resistance or the influence of structural non-uniformity caused when manufacturing the circuit elements.

[0089] <Configuration Example 2 of Display Device>

[0090] A display device according to one embodiment of the present invention is constructed based on the above, and uses capacitive coupling to change the potential of the holding portion of the image data of the pixel PIX to a more accurate potential than the potential that the digital analog conversion circuit DAC can output. In other words, according to a display device according to one embodiment of the present invention, a potential with a higher resolution than the digital analog conversion circuit DAC can be supplied to the holding portion of the image data of the pixel PIX. Thus, since there is no need to improve the resolution of the digital analog conversion circuit, a digital analog conversion circuit with a low resolution can be used. Therefore, the circuit area of ​​the source driver circuit SD including the digital analog conversion circuit DAC can be reduced, and the power consumption of the source driver circuit SD can be reduced.

[0091] Figure 2A and Figure 2B A configuration example of a display device according to one embodiment of the present invention is shown.

[0092] Figure 2A The block diagram of exemplifies a display device including a liquid crystal element. The display device DD1 includes a display portion PA and circuits provided around the display portion PA.

[0093] Specifically, Figure 2A The display device DD1 shown in FIG. Figure 1 The display unit PA shown includes a correction data holding unit 104 in addition to the gate driver circuit GD and the source driver circuit SD. The pixel PIX in the display unit PA includes an image data holding unit 101 and a display element 103 .

[0094] An input terminal of the correction data holding unit 104 is electrically connected to an output terminal of the source driver circuit SD, and an output terminal of the correction data holding unit 104 is electrically connected to the wiring SL.

[0095] and Figure 1 The display unit PA shown in the figure is similar. Figure 2A The display portion PA shown includes a plurality of pixels PIX. Note that Figure 2A Only one of the plurality of pixels PIX included in the display portion PA is shown, and the other pixels PIX are omitted. In the pixel PIX included in the display portion PA, the image data holding portion 101 is electrically connected to the display element 103. In addition, the image data holding portion 101 is electrically connected to the wiring SL.

[0096] The image data holding section 101 has a function of holding image data sent from the source driver circuit SD via the correction data holding section 104 and the wiring SL. The image data holding section 101 may include a write switch element, a capacitor, and the like for holding image data.

[0097] Figure 2A The display element 103 in the pixel PIX shown has a function of controlling light emitted from the pixel PIX. The intensity of the light (which may be referred to as brightness, grayscale level, etc.) is determined based on the image data stored in the image data storage unit 101 .

[0098] As described above, a liquid crystal element can be used as the display element 103. Examples of the liquid crystal element include a transmissive liquid crystal element and a reflective liquid crystal element. In addition to the liquid crystal element, examples include an electrophoretic element, a display element using electronic powder fluid (registered trademark), and a display element using an electrowetting method. The case where a light-emitting element such as an inorganic EL element or an organic EL element is used as the display element 103 will be described later.

[0099] Figure 2A The wiring VA shown is electrically connected to the pixel PIX. The wiring VA may be, for example, a capacitor line for holding image data in the image data holding unit 101, a wiring for supplying a potential to one terminal of a liquid crystal element of the display element 103, etc. Therefore, there may be one or more wirings VA.

[0100] exist Figure 1 In the description of the display device DD, the wiring GL has the function of sending a selection signal in advance when writing image data to the pixel PIX, but can also have a control Figure 2A The function of switching the pixel PIX on and off between the wiring VA is provided. Thus, the wiring GL may be one or more. Thus, the application of voltage and / or the supply of current from the wiring VA can be temporarily stopped.

[0101] Figure 2B The block diagram shows an example of a display device including light-emitting elements such as organic EL elements and inorganic EL elements.

[0102] Specifically, Figure 2B The display device DD2 shown has a substantially similar structure to the pixel PIX of the display device DD1, but is different from the display device DD1 in that the pixel PIX in the display portion PA includes a driving circuit portion 102. Therefore, with respect to the display device DD2, only the portions that are different from the above-mentioned display device DD1 will be described, and the description of the portions that are the same as the display device DD1 will be omitted.

[0103] The driving circuit section 102 is electrically connected to the image data holding section 101 and the display element 103 .

[0104] The driving circuit unit 102 has a function of driving the display element 103 according to the image data held in the image data holding unit 101. For example, when a light-emitting element whose light-emitting brightness is determined by current, such as an organic EL element, is used as the display element 103, the driving circuit unit 102 may include a driving transistor for controlling the current. The driving transistor has a function of supplying a driving current to the display element 103.

[0105] As mentioned above, as Figure 2B The display element 103 in the pixel PIX shown may be, for example, a light emitting element. Examples of the light emitting element include inorganic EL elements and organic EL elements. In addition to the above, examples include Micro-LEDs.

[0106] and Figure 2A The wiring VA shown is similar, Figure 2BThe wiring VA is electrically connected to the pixel PIX. Here, the wiring VA may be a capacitor line for holding image data in the image data holding unit 101, a voltage supply line for driving the driving circuit unit 102, a wiring for supplying current to the light emitting element, etc. Figure 2A The wiring VA shown is similar, Figure 2B The wiring VA may be one or more wirings.

[0107] Next, the correction data holding unit 104 , the pixels PIX, and the wirings SL used as image signal lines will be described in detail. Figure 3 1 is a circuit diagram showing the parasitic capacitance and wiring resistance of the wiring SL, the circuit structure of the pixel PIX, and the circuit structure of the correction data holding unit 104. Figure 3 In order to show the connection relationship with the correction data holding unit 104, the source driver circuit SD is shown. In addition, in the pixel PIX, only the switch SWC and the capacitor Cs are shown as circuit elements, and the description of other circuit elements is omitted. Figure 3 The wiring SL electrically connected to the pixel PIX is shown, and the wiring (equivalent to the wiring SL) for sending the selection signal to the pixel PIX is omitted. Figure 1 as well as Figure 2A and Figure 2B GL shown in the figure), a wiring for supplying a predetermined potential to a specified node (equivalent to Figure 2A and Figure 2B The wiring VA shown in the figure) etc.

[0108] As mentioned above, in Figure 3 2 shows the parasitic capacitance and wiring resistance of the wiring SL. Specifically, the wiring SL includes a resistor Rp as wiring resistance and a capacitor Cp as parasitic capacitance in each pixel PIX. Figure 3 The display section PA shown includes N pixels PIX (N is an integer greater than or equal to 1) in one column, and the wiring SL includes N resistors Rp connected in series and N capacitors Cp connected in parallel. Figure 3 In the embodiment, one pixel PIX is electrically connected to an electrical connection point between a first terminal of a capacitor Cp and a first terminal of a resistor Rp.

[0109] exist Figure 3 In the display unit PA shown in FIG. 1 , a pixel PIX disposed in the i-th row (i is an integer greater than 1 and less than N) is represented as a pixel PIX[i]. Note that in this specification, unless otherwise specified, the address of each pixel PIX[1] to pixel PIX[N] may be omitted. Figure 3 Pixel PIX[1], pixel PIX[2], and pixel PIX[N] are shown, while other pixels PIX are omitted.

[0110] The pixel PIX includes a switch SWC and a capacitor Cs. The first terminal of the switch SWC is electrically connected to the first terminal of the capacitor Cs, and the second terminal of the switch SWC is electrically connected to the wiring SL. The second terminal of the capacitor Cs is electrically connected to the wiring VC. For example, the switch SWC is switched between the on state and the off state by a selection signal sent from the wiring GL or the like to the pixel PIX.

[0111] For example, the capacitor Cs can be Figure 2A and Figure 2B The image data holding unit 101 described above includes a capacitor for holding image data. For example, the wiring VC may be a wiring for supplying an appropriate potential to the second terminal of the capacitor Cs in order to hold the image data.

[0112] The wiring VP is electrically connected to the second terminal of the capacitor Cp used as a parasitic capacitance. As the wiring VP, for example, there can be used a wiring GL for transmitting a selection signal to the pixel PIX, a wiring VC, or the like.

[0113] The correction data holding unit 104 includes switches SW1 to SW3 and a capacitor Cd. The first terminal of the switch SW1 is electrically connected to the first terminal of the capacitor Cd and the wiring SL, and the second terminal of the switch SW1 is electrically connected to the first terminal of the switch SW2 and the source driver circuit SD. The first terminal of the switch SW3 is electrically connected to the second terminal of the capacitor Cd and the second terminal of the switch SW2, and the second terminal of the switch SW3 is electrically connected to the wiring VG.

[0114] Note that in this embodiment, an electrical connection point among the second terminal of the switch SW2 , the second terminal of the capacitor Cd, and the first terminal of the switch SW3 is represented as a node ND3 .

[0115] The correction data holding unit can write the correction data to the second terminal (node ​​ND3 ) of the capacitor Cd by turning on the switch SW2 .

[0116] The wiring VG is a wiring for resetting the correction data held in the correction data holding unit 104 , and may be a wiring for supplying a reference potential, for example.

[0117] 〈Pixel Circuit Configuration Example〉

[0118] Next, the Figures 1 to 3 An example of a circuit configuration of the pixel PIX shown will be described.

[0119] Fig.4A1 The pixel PIX shown includes a transistor Tr1, a capacitor C1, and a liquid crystal element LC. In addition, a wiring DL, a wiring GL, and a wiring VCOM are electrically connected to the pixel PIX.

[0120] The transistor Tr1 is used as a switching element. In particular, the transistor Tr1 is used as a transistor that electrically connects or disconnects the first terminal of the liquid crystal element LC from the wiring DL. In other words, the transistor Tr1 can be equivalent to Figure 3 The switch SWC in the pixel PIX is shown in FIG.

[0121] The wiring DL is a wiring for transmitting image data to the pixel PIX and is equivalent to Figures 1 to 3 The wiring GL is a selection signal line for the pixel PIX and is equivalent to Figure 1 as well as Figure 2A and Figure 2B The wiring GL shown is the wiring.

[0122] The wiring VCOM is used to supply a predetermined potential to the second terminal of the liquid crystal element LC. As the predetermined potential, for example, a reference potential, a low-level potential, or a potential lower than these can be used. In addition, the wiring VCOM can supply a common potential to the second terminal of the liquid crystal element LC included in each of the plurality of pixels PIX in the display unit PA.

[0123] A first terminal of the transistor Tr1 is electrically connected to a first terminal of the capacitor C1 , a second terminal of the transistor Tr1 is electrically connected to a wiring DL, and a gate of the transistor Tr1 is electrically connected to a wiring GL.

[0124] Note that in this embodiment, an electrical connection point among the first terminal of the transistor Tr1 , the first terminal of the capacitor C1 , and the first terminal of the liquid crystal element LC is represented as a node ND1 .

[0125] The second terminal of the liquid crystal element LC is electrically connected to the wiring VCOM. In addition, the second terminal of the capacitor C1 is electrically connected to the wiring VCOM.

[0126] The capacitor C1 has the function of maintaining the potential difference between the first terminal of the transistor Tr1 and the wiring VCOM. Figure 3 The capacitor Cs in the pixel PIX shown. In this case, Figure 3 The wiring VC shown can be equivalent to Fig.4A1 Note that the capacitor C1 only needs to have a function of maintaining the potential of the first terminal of the capacitor C1, so the second terminal of the capacitor C1 may be electrically connected to a wiring supplying a constant potential other than the wiring VCOM.

[0127] In addition, Fig.4A1 In the pixel PIX shown in FIG. 1 , the transistor Tr1 and the capacitor C1 may be equivalent to Figure 2AThe image data storage unit 101 of the pixel PIX shown in FIG. Fig.4A1 In the pixel PIX shown, the liquid crystal element LC can be equivalent to Figure 2A The display element 103 of the pixel PIX is shown.

[0128] exist Fig.4A1 In the pixel PIX shown, by maintaining a potential corresponding to image data at the node ND1, the liquid crystal molecules in the liquid crystal element LC are oriented between the first terminal and the second terminal of the liquid crystal element LC according to the voltage. The oriented liquid crystal molecules transmit light from the backlight unit in the display device, or reflect light entering from outside the display device by the reflective electrodes in the display device, so that the pixel PIX can emit light corresponding to the image data.

[0129] exist Fig.4A1 In the pixel PIX, the transistor Tr1 is preferably an OS transistor. In particular, the OS transistor is preferably an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium or tin) and zinc in the channel formation region. In addition, the oxide is described in detail in Embodiment 4. By using such an OS transistor as the transistor Tr1, the off-state current of the transistor can be made extremely small. In the case of maintaining data in the first terminal (node ​​ND1) of the capacitor C1, by using the OS transistor as the transistor Tr1, the damage of the data maintained in the node ND1 due to the off-state current can be prevented.

[0130] In addition, as the transistor Tr1, for example, a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) can be used. As silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used.

[0131] in addition, Fig.4A1 The transistor Tr1 shown may also include a back gate. Figure 4A2 The pixel PIX shown has a Fig.4A1 The transistor Tr1 included in the pixel PIX shown in the figure has a back gate structure. Figure 4A2 In the embodiment, the gate of transistor Tr1 is electrically connected to the back gate. A transistor whose gate is electrically connected to the back gate can increase the on-state current flowing through the transistor, so by using Figure 4A2 The structure of the pixel PIX shown can make the pixel PIX work faster. Note that Figure 4A2 The pixel PIX shown has a structure in which the gate and the back gate of the transistor Tr1 are connected, but may have a structure in which a potential is supplied to the back gate of the transistor Tr1 via another wiring.

[0132] In addition, the description and Fig.4A1 and Figure 4A2 Different can be applied to Figures 1 to 3 An example of a circuit structure of a pixel PIX is shown.

[0133] Figure 4B1 The pixel PIX shown includes transistors Tr2 to Tr4, a capacitor C2, and a light emitting element LD. In addition, the pixel PIX is electrically connected to wiring DL, wiring GL1, wiring AL, wiring VL, and wiring CAT.

[0134] The transistor Tr2 and the transistor Tr4 are used as switch elements. The writing of image data is performed by controlling the transistor Tr2, so the transistor Tr2 can be equivalent to Figure 3 The transistor Tr3 is used as a drive transistor for controlling the current flowing through the light emitting element LD. In addition, the structure described in Embodiment 3 can be applied to the transistor Tr2 and the transistor Tr4.

[0135] The wiring DL is a wiring for transmitting image data to the pixel PIX, and may be equivalent to Figures 1 to 3 Furthermore, the wiring GL1 is a selection signal line for the pixel PIX and can be equivalent to Figure 1 as well as Figure 2A and Figure 2B Wiring GL.

[0136] The wiring VL is a wiring for supplying a predetermined potential to a specific node in the pixel PIX. Furthermore, the wiring AL is a wiring for supplying a current flowing through the light emitting element LD. The wiring VL and the wiring AL may be equivalent to Figure 2A and Figure 2B The wiring VA shown.

[0137] The wiring CAT is used to supply a predetermined potential to the output terminal of the light emitting element LD. The predetermined potential may be, for example, a reference potential, a low-level potential, or a potential lower than these. Figure 2A and Figure 2B The wiring VA shown. In the plurality of pixels PIX in the display portion PA, the wiring CAT is preferably used as a wiring to which a common potential is supplied.

[0138] The first terminal of transistor Tr2 is electrically connected to the first terminal of capacitor C2 and the gate of transistor Tr3, the second terminal of transistor Tr2 is electrically connected to wiring DL, and the gate of transistor Tr2 is electrically connected to wiring GL1. The first terminal of transistor Tr3 is electrically connected to wiring AL, the second terminal of transistor Tr3 is electrically connected to the second terminal of capacitor C2, the first terminal of transistor Tr4, and the input terminal of liquid crystal element LD. The second terminal of transistor Tr4 is electrically connected to wiring VL, and the gate of transistor Tr4 is electrically connected to wiring GL1. The output terminal of light emitting element LD is electrically connected to wiring CAT.

[0139] Note that in this embodiment, an electrical connection point between the first terminal of the transistor Tr2 , the first terminal of the capacitor C2 , and the gate of the transistor Tr3 is represented as a node ND2 .

[0140] The capacitor C2 has the function of maintaining the potential difference between the second terminal and the gate of the transistor Tr3. Figure 3 The capacitor Cs in the pixel PIX is shown.

[0141] In addition, Figure 4B1 In the pixel PIX shown in FIG. 1 , the transistor Tr2 and the capacitor C2 may be equivalent to Figure 2B The image data storage unit 101 of the pixel PIX shown in FIG. Figure 4B1 In the pixel PIX shown in FIG. 1 , transistors Tr3 and Tr4 may be equivalent to Figure 2B The circuit elements included in the driving circuit unit 102 of the pixel PIX shown in FIG. Figure 4B1 In the pixel PIX shown, the light emitting element LD may be equivalent to Figure 2B The display element 103 of the pixel PIX is shown.

[0142] exist Figure 4B1 In the pixel PIX shown, by maintaining a potential corresponding to the image data at the node ND2, a current corresponding to the voltage between the gate and source of the transistor Tr3 as a driving transistor flows between the source and drain of the transistor Tr3. Since this current flows through the input terminal of the light emitting element LD, the light emitting element LD emits light. Thus, the pixel PIX can emit light corresponding to the image data.

[0143] exist Figure 4B1In the pixel PIX, at least one of the transistors Tr2 to Tr4 is preferably an OS transistor. In particular, the OS transistor is preferably an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium or tin) and zinc in the channel formation region. In addition, the oxide is described in detail in Embodiment 4. By adopting such an OS transistor as at least one of the transistors Tr2 to Tr4, the off-state current of the transistor adopting the OS transistor can be made extremely small. In the case where data is maintained in the first terminal (node ​​ND2) of the capacitor C2, by using the OS transistor as the transistor Tr2, the damage of the data maintained in the node ND2 due to the off-state current can be prevented. In addition, by adopting OS transistors as all the transistors Tr2 to Tr4, these transistors can be formed at the same time, so the manufacturing process of the display unit PA can sometimes be shortened. That is, since the production time of the display unit PA can be reduced, the number of production per unit time can be increased.

[0144] In addition, as at least one of the transistors Tr2 to Tr4, for example, a Si transistor including silicon in a channel formation region can be used. As silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used.

[0145] In addition, the channel formation regions of the transistors Tr2 to Tr4 are preferably made of the same material. In addition, depending on circumstances, some of the transistors Tr2 to Tr4 in the pixel PIX may be Si transistors and the other transistors may be OS transistors.

[0146] In addition, Figure 4B1 In the pixel PIX shown in FIG. 1 , a switching element may be provided at the input terminal of the light emitting element LD. Figure 4B2 In the pixel PIX shown, a transistor Tr5 serving as a switching element is provided between the electrical connection point of the second terminal of the transistor Tr3, the second terminal of the capacitor C2, and the first terminal of the transistor Tr4, and the light emitting element LD. In other words, the first terminal of the transistor Tr5 is electrically connected to the second terminal of the transistor Tr3, the second terminal of the capacitor C2, and the first terminal of the transistor Tr4, and the second terminal of the transistor Tr5 is electrically connected to the input terminal of the light emitting element LD. In addition, the gate of the transistor Tr5 is electrically connected to the wiring GL2 which is one of the selection signal lines.

[0147] In is Figure 4B1 In the case of the pixel PIX shown in FIG. 1 , in order to stop the light emission of the light emitting element LD, it is sufficient to stop the current from flowing through the input terminal of the light emitting element LD and at the same time reduce the potential applied to the wiring AL. In this case, a driver circuit for controlling the wiring AL needs to be separately provided, which may increase the manufacturing cost of the display device. Figure 4B2 In the case of the pixel PIX shown, a low level potential is applied to the wiring GL2 to turn off the transistor Tr5, thereby stopping the current supply to the light emitting element LD. In addition, by using the above-mentioned OS transistor as the transistor Tr5, the light emitting element LD can be prevented from emitting light due to the off-state current.

[0148] In addition, Figure 4B2 In the pixel PIX shown, transistor Tr5 can be equivalent to Figure 2B The driving circuit unit 102 of the pixel PIX shown in FIG.

[0149] <Circuit Configuration Example of Correction Data Holding Unit>

[0150] Next, the Figures 1 to 3 An example of the circuit configuration of the correction data storage unit 104 shown in FIG. 1 is described below.

[0151] Figure 5A The correction data storage unit 104 shown in FIG. Figure 3 The switches SW1 to SW3 of the correction data holding unit 104 shown in FIG. 1 are circuit structures of transistors SWT1 to SWT3, respectively. Figure 5A In order to show the connection relationship with the correction data holding unit 104, the display unit PA and the source driver circuit SD are shown.

[0152] The first terminal of the transistor SWT1 is electrically connected to the first terminal of the capacitor Cd and the wiring SL (wiring DL), the second terminal of the transistor SWT1 is electrically connected to the first terminal of the transistor SWT2 and the source driver circuit SD, and the gate of the transistor SWT1 is electrically connected to the wiring CRL1. The gate of the transistor SWT2 is electrically connected to the wiring CRL2. The first terminal of the transistor SWT3 is electrically connected to the second terminal of the capacitor Cd and the second terminal of the transistor SWT2, the second terminal of the transistor SWT3 is electrically connected to the wiring VG, and the gate of the transistor SWT3 is electrically connected to the wiring CRL1.

[0153] and Figure 3 Likewise, in Figure 5A and Figure 5B In FIG. 5 , an electrical connection point among the second terminal of the transistor SWT2 , the second terminal of the capacitor Cd, and the first terminal of the transistor SWT3 is referred to as a node ND3 .

[0154] Wiring CRL1 and wiring CRL2 are wirings used to switch the on state and off state of transistors SWT1 to SWT3. In particular, each gate of transistor SWT1 and transistor SWT3 is electrically connected to wiring CRL1, so by supplying a high level potential or a low level potential to wiring CRL1, the on state and off state of transistor SWT1 and transistor SWT3 can be switched at the same time. Note that it is not necessary to switch each on state and off state of transistor SWT1 and transistor SWT3 at the same time, and the on state and off state of transistor SWT1 and transistor SWT3 can also be switched independently. In this case, the correction data holding unit 104 only needs to have a structure in which each gate of transistor SWT1 and transistor SWT3 is electrically connected to different wirings.

[0155] It is preferable to use an OS transistor as at least one of the transistors SWT1 to SWT3. Since the OS transistor has a characteristic of extremely small off-state current, for example, by using an OS transistor as the transistor SWT2 and / or the transistor SWT3, it is possible to prevent the data held at the node ND3 from being destroyed due to the off-state current. In addition, by using an OS transistor as all of the transistors SWT1 to SWT3, these transistors can be formed at the same time, so that the manufacturing process of the display portion PA can sometimes be shortened.

[0156] in addition, Figure 5A At least one of the transistors SWT1 to SWT3 shown may be a transistor including a back gate. Figure 5B In the embodiment, transistors SWT1 to SWT3 are all transistors including back gates, and the gate of each transistor is electrically connected to the back gate. Since a transistor having a gate electrically connected to a back gate can increase the on-state current flowing through the transistor, by using Figure 5B The structure of the pixel PIX shown can make the pixel PIX work faster. Figure 5B The pixel PIX shown has a structure in which the gates of the transistors SWT1 to SWT3 are connected to the back gates, but may have a structure in which a potential is supplied to the back gate of each transistor via another wiring.

[0157] In addition, it is preferable to use a Si transistor as at least one of the transistors SWT1 to SWT3. In addition, some of the transistors SWT1 to SWT3 may be Si transistors and the other transistors may be OS transistors.

[0158] in addition, Figure 5A and Figure 5B Shown as Figure 3The switches SW1 to SW3 of the correction data holding unit 104 shown in the figure are circuit configuration examples using transistors SWT1 to SWT3, but Figure 3 The switches SW1 to SW3 of the correction data holding unit 104 shown may be switches formed of CMOS (Complementary MOS) circuits, such as analog switches.

[0159] Furthermore, when the correction data holding section 104 and the pixel PIX are formed over the same substrate, the transistors SWT1 to SWT3 and the channel formation regions of the transistors included in the pixel PIX are preferably formed of the same material.

[0160] In addition, when the correction data holding unit 104 and the channel forming regions of each transistor included in the source driver circuit SD are formed of the same material, the correction data holding unit 104 and the source driver circuit SD are preferably formed on the same semiconductor substrate. In addition, when the correction data holding unit 104 and the channel forming regions of each transistor included in the source driver circuit SD are formed of different materials from each other, it is preferable to adopt a stacked structure in which the source driver circuit SD is formed on a semiconductor substrate and the correction data holding unit 104 is formed above the source driver circuit SD. In this case, the transistors SWT1 to SWT3 of the correction data holding unit 104 are composed of OS transistors and the source driver circuit SD is composed of Si transistors. In addition, the correction data holding unit 104 and the source driver circuit SD may also adopt a structure in which a substrate in which the correction data holding unit 104 is formed is mounted on a semiconductor substrate in which the source driver circuit SD is formed. In addition, a structure in which the correction data holding unit 104 is included inside the source driver SD may also be adopted.

[0161] As a substrate on which the pixel PIX, the correction data holding unit 104, the source driver circuit SD, etc. are formed, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and other insulating substrates can be cited. As such a substrate, for example, a semiconductor substrate composed of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. In addition, as such a substrate, for example, an SOI (Silicon On Insulator) substrate including an insulating region in a semiconductor substrate can be cited. In addition, as such a substrate, for example, a conductive substrate such as a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited.

[0162] 〈〈Work Examples〉〉

[0163] Next, a working example of a display device according to one embodiment of the present invention will be described. Note that the display device used in this working example is Figure 6 The display device DD3 shown in FIG. The display device DD3 has a pixel PIX in the display device DD1. Fig.4A1 The pixel PIX shown in FIG. 1 and the wiring SL are Figure 3 The wiring SL shown in FIG. 1 is used, and the correction data holding unit 104 is Figure 5A The structure of the correction data storage unit 104 is shown. Figure 6 In the circuit, capacitor Cpa is used as Figure 3 The sum of the capacitors Cp of the parasitic capacitance of the wiring SL shown in FIG. 1 is expressed as Cpa=N×Cp when the number of pixels PIX electrically connected to the wiring SL is N. Figure 6 In the middle, omission indicates Figure 3 The wiring resistance of the wiring SL shown in FIG. Figure 6 In FIG. 1 , regarding the source driver circuit SD, only the amplifier circuit AMP is shown, and the circuits and elements electrically connected to the input terminals of the amplifier circuit are omitted.

[0164] Figure 7 : is a timing chart showing an operation example of the display device DD3. Figure 7 The timing chart shown in FIG. 1 shows the output voltages of the wiring GL, wiring VCOM, wiring CRL1, wiring CRL2, wiring VG, wiring DL, and the amplifier circuit at times T1 to T6 and in the vicinity thereof (at Figure 7 ), the potential changes of the node ND1 and the node ND3. Figure 7 The "high" in the description indicates a high level potential and the "low" indicates a low level potential. Figure 7 V GND Indicates the reference potential.

[0165] Note that from time T1 to time T6 and the times near it, the wiring VCOM and the wiring VG are always applied with V GND .

[0166] Note that in this working example, unless otherwise stated, the transistor Tr1, the transistor SWT1 to the transistor SWT3 sometimes operate in the linear region when they are turned on. That is, sometimes the gate voltage, source voltage, and drain voltage of the transistor Tr1, the transistor SWT1 to the transistor SWT3 are appropriately biased so that these transistors operate in the linear region. Figure 4B1 and Figure 4B2In the case of the pixel PIX shown, it is preferable that the transistors Tr2 and Tr4 are operated in the linear region and the transistor Tr3 is operated in the saturation region.

[0167] [Before time T1]

[0168] Before time T1, a low level potential is applied to the wiring GL. When the potential of the wiring GL is a low level potential, a low level potential is applied to the gate of the transistor Tr1, so the transistor Tr1 is turned off. In other words, the wiring DL and the node ND1 are in a non-conductive state.

[0169] A low level potential is applied to the wiring CRL1. When the potential of the wiring CRL1 is a low level potential, a low level potential is applied to each gate of the transistor SWT1 and the transistor SWT3, so that the transistor SWT1 and the transistor SWT3 are both in an off state. In other words, the source driver circuit SD and the display portion PA become non-conductive, and the node ND3 and the wiring VG also become non-conductive.

[0170] When a potential difference of a certain degree or more is generated between the first terminal (node ​​ND1) and the second terminal of the liquid crystal element LC, the liquid crystal molecules included in the liquid crystal element LC are oriented according to the potential difference. Since the oriented liquid crystal molecules allow light from the backlight unit included in the display device DD1 to pass through, the light is emitted from the pixel PIX. The intensity of the light is determined by the voltage applied between the first terminal (node ​​ND1) and the second terminal of the liquid crystal element LC, that is, the potential of the node ND1, and grayscale display can be performed by adjusting the potential. Note that in Figure 7 Before time T1 in the timing chart shown in FIG. 1 , a potential difference is generated between the first terminal (node ​​ND1) and the second terminal of the liquid crystal element LC to such an extent that light is not emitted from the pixel PIX, and the potential is set to V Ini1 In other words, Figure 7 In the timing diagram shown in FIG. 1 , the potential of the node ND1 is represented as V Ini1 . Note that V Ini1 It can also be equal to V GND or below V GND In this working example, V Ini1 Set to be greater than V GND But it is not high enough to explain the potential of light emitted from the pixel PIX.

[0171] Before time T1, the potential of wiring CRL2 changes from a high-level potential to a low-level potential. When the potential of wiring CRL2 is a high-level potential, a high-level potential is applied to the gate of transistor SWT2, so transistor SWT2 is in an on state. In other words, the source driver circuit SD and the node ND3 are in a conductive state. At this time, the potential output from the output terminal of the amplifier circuit AMP in the source driver circuit SD is applied to the node ND3. In addition, when the potential of wiring CRL2 becomes a low-level potential, transistor SWT2 is in an off state, so the source driver circuit SD and the node ND3 are not electrically connected.

[0172] In order to simply explain this working example, the potential of the node ND3 before time T1 is set to V Ini2 . Note that V Ini2 Can be equal to V GND or below V GND However, in this working example, V Ini2 Set higher than V GND The potential.

[0173] Before time T1, the potential of wiring DL is at an appropriate potential. Figure 7 It is assumed that the potential of wiring DL is higher than V GND The potential is shown graphically.

[0174] [Time T1]

[0175] At time T1, a high level potential is applied to the wiring GL. Therefore, from time T1 to time T2, a high level potential is applied to the gate of the transistor Tr1, and the transistor Tr1 is turned on. Thus, the wiring DL and the source driver circuit SD are turned on.

[0176] In addition, a high level potential is applied to wiring CRL1 at time T1. Therefore, from time T1 to time T2, a high level potential is applied to each gate of transistor SWT1 and transistor SWT3, and transistor SWT1 and transistor SWT3 are in a conductive state. Node ND3 and wiring VG are in a conductive state.

[0177] Here, it is assumed that at time T1, V is output as an analog signal from the output terminal of the amplifier circuit. data1 . V data1 The potential of the wiring DL is set to V data1 In addition, since the transistor Tr1 is in the on state, the potential of the node ND1 of the pixel PIX also becomes V data1 .

[0178] In addition, since the transistor SWT3 is in the on state, the potential of the wiring ND3 becomes V GND In addition, since the transistor SWT2 is in the off state, the potential V output from the output terminal of the amplifier circuit AMP is data1 Not applied to node ND3.

[0179] At this time, the voltage between the first terminal and the second terminal of the capacitor Cd becomes V data1 .

[0180] [Time T2]

[0181] At time T2, a low-level potential is applied to the wiring CRL1. Therefore, from time T2 to time T3, a low-level potential is applied to each gate of the transistor SWT1 and the transistor SWT3, and both the transistor SWT1 and the transistor SWT3 are in an off state.

[0182] When the transistor SWT1 is in the off state, the wiring DL and the source driver circuit SD are in a non-electrical conduction state. Therefore, the wiring DL and the node ND1 are in an electrically floating state. In addition, when the transistor SWT3 is in the off state, the node ND3 and the wiring VG are also in a non-electrical conduction state, so the node ND3 is also in an electrically floating state.

[0183] Furthermore, from time T2 to time T3, the potential V is outputted from the output terminal of the amplifier circuit AMP as an analog signal. data2 . With the potential V data1 Likewise, the potential V data2 It is also set to a potential that can be output by the digital-to-analog conversion circuit DAC included in the source driver circuit SD.

[0184] [Time T3]

[0185] At time T3, a high-level potential is applied to the wiring CRL2. Therefore, from time T3 to time T4, a high-level potential is applied to the gate of the transistor SWT2, and the transistor SWT2 is turned on.

[0186] At this time, since the transistor SWT2 is in the on state, the potential V outputted from the output terminal of the amplifier circuit AMP is applied to the node ND3. data2 In addition, since the transistor SWT3 is in the off state, the current does not flow from the source driver circuit SD to the wiring VG, and the potential of the node ND3 changes from V GND Rising to V data2 .

[0187] In addition, the wiring DL and the node ND1 are in an electrically floating state, and the change in the potential of the node ND3 causes the change in the potential of the wiring DL and the node ND1 due to the capacitive coupling of the capacitor Cd. Figure 7 In the timing diagram of FIG. 1 , the variation of each potential of the wiring DL and the node ND1 is represented by ΔV g , however, when the electrostatic capacitance value of capacitor Cd is set to C A The electrostatic capacitance value obtained by combining the capacitor Cpa, which is the parasitic capacitance of the wiring SL, and the capacitor C1 of the pixel PIX is represented by C B When ΔV g It can be estimated using the following formula (E1).

[0188] [Formula 1]

[0189]

[0190] Therefore, when the potential of the node ND1 is set to V ND1 When V ND1 .

[0191] [Formula 2]

[0192]

[0193] Note that regarding equation (E1) and equation (E2), the parasitic capacitance generated between the first terminal and the second terminal of the liquid crystal element LC is not considered. However, since the first terminal of the liquid crystal element LC and the first terminal of the capacitor C1 are electrically connected to each other, and the second terminal of the liquid crystal element LC and the second terminal of the capacitor C1 are each electrically connected to the wiring VCOM, it can be regarded as having a structure in which the liquid crystal element LC and the capacitor C1 are electrically connected in parallel. Therefore, the electrostatic capacitance value C in equation (E1) and equation (E2) can be B It is considered that the value takes the parasitic capacitance of the liquid crystal element into consideration.

[0194] [Time T4]

[0195] At time T4, a low-level potential is applied to the wiring GL. Therefore, from time T4 to time T5, a low-level potential is applied to the gate of the transistor Tr1, and the transistor Tr1 is in an off state.

[0196] When the transistor Tr1 is turned on, the wiring DL and the node ND1 are not in conduction. ND1 It is held by capacitor C1.

[0197] [Time T5]

[0198] At time T5, a low-level potential is applied to the wiring CRL2. Therefore, from time T5 to time T6, a low-level potential is applied to the gate of the transistor SWT2, and the transistor SWT2 is in an off state.

[0199] When the transistor SWT2 is in the off state, the source driver circuit SD and the node ND3 are in a non-conductive state. In addition, since the transistor SWT3 is in the off state, the node ND3 is in an electrically floating state. Thus, the potential of the node ND3 is maintained by the capacitor Cd.

[0200] [Time T6]

[0201] At time T6, a high-level potential is applied to the wiring CRL1. Therefore, after time T6, a high-level potential is applied to each gate of the transistor SWT1 and the transistor SWT3, so that both the transistor SWT1 and the transistor SWT3 are turned on.

[0202] Furthermore, at time T6, the potential V is output as an analog signal from the output terminal of the amplifier circuit AMP. AN . With V data1 and V data2 Likewise, V AN The potential is set to a potential that can be output by the digital-to-analog conversion circuit DAC included in the source driver circuit SD.

[0203] Since the transistor SWT1 is in the on state, the potential from the output terminal of the amplifier circuit AMP is applied to the wiring DL. As a result, the potential of the wiring DL becomes V AN .

[0204] In addition, since the transistor SWT3 is in the on state, the potential V GND .

[0205] Here, attention is paid to the liquid crystal element LC after time T4. V is applied between the first terminal and the second terminal of the liquid crystal element LC. ND1 =V data1 +ΔV g Therefore, after time T4, the liquid crystal molecules included in the liquid crystal element LC are adjusted according to the potential V ND1 Light is directed and emitted from the pixel PIX.

[0206] Note that the brightness of light emitted from the pixel PIX is determined according to a voltage applied between the first terminal and the second terminal of the liquid crystal element LC.

[0207] As mentioned above, by Figure 6 The display device DD3 shown in FIG. Figure 7The operation from time T1 to time T6 and times in the vicinity of the timing chart can supply a potential having a higher resolution than that of the digital-to-analog conversion circuit DAC to the image data holding portion (node ​​ND1) of the pixel PIX.

[0208] 〈〈Specific Examples〉〉

[0209] Here, an example is described in which image data having more grayscales than the image data output by the digital-to-analog conversion circuit DAC is displayed on the display portion PA of the display device DD3 through the above-mentioned operation example.

[0210] In this example, a 6-bit digital-to-analog conversion circuit is provided as the digital-to-analog conversion circuit DAC of the source driver circuit SD, and the electrostatic capacitance value C of the capacitor Cd included in the correction data holding unit 104 is set to A The electrostatic capacitance value C is obtained by synthesizing the capacitor Cpa as the parasitic capacitance of the wiring SL and the capacitor C1 of the pixel PIX. B The ratio is set to C A :C B =1:63.

[0211] By using a 6-bit digital-to-analog conversion circuit DAC as the digital-to-analog conversion circuit DAC, V written to the wiring DL and the node ND1 data1 The value can be expressed in binary from "000000" to "111111". Here, when the voltage value of "111111" is set to 6.3V, the V that the digital-to-analog converter circuit DAC can output is data1 Possible voltage values ​​are within the range of 0V to 6.3V with every 0.1V.

[0212] Thus, from time T1 to time T2 in the above-mentioned working example, a voltage V in the range of 0 V to 6.3 V can be written to the wiring DL and the node ND1. data1 .

[0213] Capacitor Cd's electrostatic capacitance value C A The electrostatic capacitance value C is obtained by synthesizing the capacitor Cpa as the parasitic capacitance of the wiring SL and the capacitor C1 of the pixel PIX. B The ratio is C A :C B =1:63, so equation (E1) becomes the following equation (E3).

[0214] [Formula 3]

[0215]

[0216] Here, for example, as output V data2The digital-to-analog conversion circuit uses the output V data1 The digital-to-analog conversion circuit DAC is the same circuit, V data2 Can be used with V data1 Similarly, the values ​​from "000000" to "111111" are obtained in binary. data2 The possible voltage value is also a voltage value ranging from 0V to 6.3V at intervals of 0.1V. That is, according to formula (E3), ΔV g The value can be set from 0 V to 6.3 / 64 V (= 0.0984375 V) at intervals of 0.1 / 64 V (= 0.0015625 V).

[0217] Therefore, between time T3 and time T4 of the above working example, according to equations (E2) and (E3), the potential of the node ND1 of the pixel PIX can take values ​​from 0 V to 6.3+6.3 / 64 V (=6.3984375 V) at intervals of 0.1 / 64 V (=0.0015625 V).

[0218] That is, in the display devices DD1 to DD3 of one embodiment of the present invention, by performing the above operation, a more precise voltage value that cannot be output by the 6-bit digital-to-analog conversion circuit DAC can be supplied to the node ND1 of the pixel PIX. In the above specific example, the digital-to-analog conversion circuit DAC outputs a potential every 0.1V, but a potential every 0.1 / 64V (=0.0015625V) can be written to the node ND1 of the pixel PIX. In other words, a potential (image data) having a higher resolution than the 6-bit digital-to-analog conversion circuit DAC can be written to the pixel PIX.

[0219] In the above specific example, the 6-bit digital-to-analog converter circuit DAC supplies V data1 The ΔV voltage supplied to the node ND1 by the capacitive coupling caused by the capacitor Cd of the correction data holding unit 104 corresponds to the upper 6 bits of the image data. g In other words, by using the display devices DD1 to DD3 of one embodiment of the present invention, the image data of the lower 6 bits are supplemented with the image data of the upper 6 bits supplied by the digital-to-analog conversion circuit DAC, and image data equivalent to 12 bits can be displayed on the display unit PA.

[0220] In the above operation example, between time T3 and time T4, a voltage higher than V is supplied to the node ND3 of the correction data storage unit 104 as correction data. GND potential, but can also be used as a correction data supply below V GNDIn other words, the ΔV applied to the node ND1 can be adjusted by the capacitive coupling of the capacitor Cd of the correction data holding unit 104. g Negative potential.

[0221] Note that the structure of the display device according to one embodiment of the present invention is not limited to Figures 1 to 3 , Figure 6 As one embodiment of the present invention, the components of the display device may be appropriately changed according to the design specifications, purpose, etc.

[0222] In addition, one structural example described in this embodiment mode may be combined with other structural examples. Figure 4A2 The same is true for PIX. Figure 4B1 and Figure 4B2 The pixel PIX shown may also include transistors Tr2 to Tr4 with back gates (not shown).

[0223] In addition, the operating method of the display device of one embodiment of the present invention is not limited to the above-mentioned working example or specific example. In the operating method, for example, the order of supplying potentials to elements, circuits, wirings, etc. or the value of the potentials can be appropriately changed. In addition, as described above, the structure of the display device of one embodiment of the present invention can be appropriately changed, and therefore, the operating method of the display device can also be changed according to the structure.

[0224] Note that this embodiment mode can be combined with other embodiment modes or examples described in this specification as appropriate.

[0225] (Implementation Method 2)

[0226] In this embodiment, a configuration example of a display device using a liquid crystal element is described. Note that in this embodiment, the description of the operation and function of supplying lower-bit image data to image data output from the source driver circuit SD described in Embodiment 1 is omitted.

[0227] Fig. 8A The display device shown in the figure includes a first substrate 4001 and a second substrate 4006. In this display device, a sealant 4005 is provided so as to surround a display portion 215 provided over the first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006.

[0228] The display portion 215 includes a pixel array including the pixels PIX described in Embodiment 1.

[0229] exist Fig. 8AIn the embodiment, the scanning line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a all include a plurality of integrated circuits 4042 provided on a printed circuit board 4041. The integrated circuit 4042 is formed of a single crystal semiconductor or a polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a have the function of the source driver circuit SD described in Embodiment 1. The scanning line driving circuit 221a has the function of the gate driver circuit GD described in Embodiment 1. The common line driving circuit 241a has the function of supplying a predetermined potential to the wiring VCOM described in Embodiment 1.

[0230] Various signals and potentials are supplied to the scanning line driving circuit 221 a , the common line driving circuit 241 a , the signal line driving circuit 231 a , and the signal line driving circuit 232 a via an FPC (Flexible printed circuit) 4018 .

[0231] The integrated circuit 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a has a function of supplying a selection signal to the display portion 215. The integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a has a function of supplying an image signal to the display portion 215. The integrated circuit 4042 is mounted in a region different from a region surrounded by the sealant 4005 on the first substrate 4001.

[0232] Note that there is no particular limitation on the connection method of the integrated circuit 4042, and a wire bonding method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like can be used.

[0233] Figure 8B An example in which the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a is mounted by a COG method is shown. Alternatively, by forming part or all of the driver circuit over the substrate 4001 on which the display portion 215 is formed, a system-on-panel can be formed.

[0234] Figure 8B The example in which the scanning line driver circuit 221a and the common line driver circuit 241a are formed over the substrate on which the display portion 215 is formed is shown. By forming the driver circuits at the same time as the pixel circuits in the display portion 215, the number of components can be reduced, thereby improving productivity.

[0235] In addition, Figure 8BIn the embodiment, a sealant 4005 is provided so as to surround the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a provided on the first substrate 4001. A second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Thus, the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0236] Although Figure 8B An example is shown in which a signal line driving circuit 231a and a signal line driving circuit 232a are separately formed and installed on the first substrate 4001, but one embodiment of the present invention is not limited to this structure, and a scanning line driving circuit may be separately formed and installed, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and installed.

[0237] In addition, a display device may include a panel in which a display element is sealed and a module in which an IC including a controller and the like is mounted on the panel.

[0238] The display unit and the scan line driver circuit provided on the first substrate include a plurality of transistors. As the transistors, OS transistors or Si transistors can be used.

[0239] The transistors included in the peripheral drive circuit and the transistors included in the pixel circuit of the display unit may have the same structure or different structures. The transistors included in the peripheral drive circuit may all have the same structure or a combination of two or more structures. Similarly, the transistors included in the pixel circuit may all have the same structure or a combination of two or more structures.

[0240] In addition, an input device 4200 (not shown. The input device 4200 will be described later) may be provided over the second substrate 4006 . Fig. 8A and Figure 8B The structure shown in which the input device 4200 is provided to the display device can be used as a touch panel.

[0241] The sensing element (also referred to as a sensor element) included in the touch panel of one embodiment of the present invention is not particularly limited, and various sensors capable of detecting the approach or contact of a detection object such as a finger or a stylus pen can be used as the sensing element.

[0242] For example, various types of sensors such as an electrostatic capacitance type, a resistance film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type can be used.

[0243] In this embodiment, a touch panel including an electrostatic capacitance type sensing element is taken as an example for description.

[0244] As the electrostatic capacitance type, there are surface type electrostatic capacitance type, projected type electrostatic capacitance type, etc. In addition, as the projected type electrostatic capacitance type, there are self capacitance type, mutual capacitance type, etc. It is preferable to use the mutual capacitance type because multi-point sensing can be performed simultaneously.

[0245] The touch panel of one embodiment of the present invention can have various structures, such as a structure in which a display device and a sensor element manufactured separately are bonded together, or a structure in which electrodes constituting a sensor element are provided on one or both of a substrate supporting a display element and a counter substrate.

[0246] Fig. 9A and Fig. 9B An example of a touch panel is shown. Fig. 9A is a perspective view of touch panel 4210. Fig. 9B 42 is a perspective schematic diagram of the input device 4200. Note that for the sake of clarity, only typical components are shown.

[0247] The touch panel 4210 has a structure in which a display device and a sensing element which are manufactured separately are bonded together.

[0248] The touch panel 4210 includes an input device 4200 and a display device which are overlapped.

[0249] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 may be electrically connected to the wiring 4237 or the wiring 4239. In addition, the electrode 4228 may be electrically connected to the wiring 4239. The FPC 4272b may be electrically connected to the plurality of wirings 4237 and the plurality of wirings 4238, respectively. The FPC 4272b may be provided with an IC 4273b.

[0250] A touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When the touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used in addition to an electrostatic capacitive touch sensor.

[0251] Fig.10 So Figure 8B A cross-sectional view of the portion shown by the dashed line N1 - N2 in FIG. Fig.10 The display device shown includes an electrode 4015, which is electrically connected to a terminal of an FPC 4018 via an anisotropic conductive layer 4019. Fig.10In the embodiment, the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112 , the insulating layer 4111 , and the insulating layer 4110 .

[0252] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source electrode and the drain electrode of the transistor 4010 and the transistor 4011 are formed using the same conductive layer.

[0253] In addition, the display portion 215 and the scan line driver circuit 221a provided over the first substrate 4001 include a plurality of transistors. Fig.10 , the transistor 4010 in the display portion 215 and the transistor 4011 in the scan line driver circuit 221a are illustrated. Fig.10 Although bottom-gate transistors are shown as the transistor 4010 and the transistor 4011, top-gate transistors may be used. Note that the transistor 4011 may be included in the gate driver circuit GD described in Embodiment 1.

[0254] exist Fig.10 In the embodiment, an insulating layer 4112 is provided over the transistor 4010 and the transistor 4011.

[0255] In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

[0256] in addition, Fig.10 The display device shown includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. The electrodes overlap each other with the insulating layer 4103 interposed therebetween. Note that as the capacitor 4020, for example, the capacitor C1 of the pixel PIX described in Embodiment 1 can be used.

[0257] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is set so as to hold charge for a predetermined period in consideration of leakage current of a transistor provided in the pixel portion, etc. The capacitance of the capacitor may be set in consideration of off-state current of the transistor, etc.

[0258] Fig.10 This is an example of a liquid crystal display device that uses a transmissive liquid crystal element as a display element. Fig.10In the embodiment, the liquid crystal element 4013 as a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 serving as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other via the liquid crystal layer 4008. The transistor 4010 provided in the display portion 215 is electrically connected to the liquid crystal element 4013. In other words, as the transistor 4010, for example, the transistor Tr1 described in Embodiment Mode 1 can be used, and as the liquid crystal element 4013, for example, the liquid crystal element LC of the pixel PIX described in Embodiment Mode 1 can be used.

[0259] As the first electrode layer 4030 and the second electrode layer 4031, a conductive material that allows visible light to pass is preferably used. As the conductive material, for example, a material containing one or more selected from indium (In), zinc (Zn) and tin (Sn) can be used. Specifically, indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, and zinc oxide containing gallium can be cited. In addition, a film containing graphene can be used. The film containing graphene can be formed by reducing a film containing graphene oxide formed on a film of an insulator or a conductor, for example.

[0260] As the liquid crystal element 4013, for example, a liquid crystal element using the FFS (Fringe Field Switching) mode can be used. In addition, generally speaking, as liquid crystal materials, there are positive liquid crystal materials whose dielectric anisotropy (Δε) is positive and negative liquid crystal materials whose anisotropy is negative. These two materials can be used as the liquid crystal element 4013 shown in this embodiment, and the most suitable liquid crystal material can be used according to the applied mode and design.

[0261] In the display device shown in this embodiment, it is preferred to use a negative liquid crystal material. In negative liquid crystals, the influence caused by the flexoelectric effect due to the polarization of liquid crystal molecules can be suppressed, and the polarity hardly affects the transmittance. Therefore, it is possible to suppress flickering (flicker) seen by the user of the display device. The flexoelectric effect refers to a phenomenon that is mainly caused by the shape of molecules and polarization occurs due to orientation distortion. In negative liquid crystal materials, orientation distortions such as flexural deformation or bending deformation are not easily generated.

[0262] Note that, although an element adopting the FFS mode is used as the liquid crystal element 4013 here, the present invention is not limited to this, and liquid crystal elements adopting various modes may be used. For example, a liquid crystal element adopting a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS (Vertical Alignment In-Plane-Switching) mode, a guest-host mode, or the like may be used.

[0263] In addition, a normally black liquid crystal display device, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode, may be used for the display device shown in this embodiment. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. may be used.

[0264] Liquid crystal elements are elements that use the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by the electric field (horizontal electric field, vertical electric field or tilted electric field) applied to the liquid crystal. As liquid crystals used in liquid crystal elements, thermotropic liquid crystals, low molecular liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal: polymer dispersed liquid crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials show cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc. depending on the conditions.

[0265] Although Fig.10An example of a display device having a liquid crystal element in a vertical electric field mode is shown, but a display device having a liquid crystal element in a horizontal electric field mode can also be applied to one mode of the present invention. In the case of a horizontal electric field mode, a liquid crystal presenting a blue phase without an alignment film can also be used. The blue phase is a type of liquid crystal phase, and refers to a phase that appears before the transition from the cholesteric phase to the homogeneous phase when the temperature of the cholesteric liquid crystal is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition in which more than 5wt% of a chiral agent is mixed is used for the liquid crystal layer 4008 to expand the temperature range. Since the liquid crystal composition containing a liquid crystal presenting a blue phase and a chiral agent has a fast response speed and is optically isotropic. In addition, the liquid crystal composition containing a liquid crystal presenting a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. In addition, since there is no need to set an alignment film and no friction treatment is required, electrostatic damage caused by the friction treatment can be prevented, and defects and damage to the liquid crystal display device in the manufacturing process can be reduced.

[0266] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer and is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may also be used.

[0267] In addition, as needed, optical components (optical substrates) such as black matrices (light shielding layers), coloring layers (color filters), polarization components, phase difference components, and anti-reflection components can be appropriately provided. For example, circular polarization using polarization substrates and phase difference substrates can also be used. In addition, backlight units or side light units can also be used as light sources. Micro-LEDs can also be used as the above-mentioned backlight units and side light units. In order to Fig.10 In the case of the display device shown, the following structure can be adopted. For example, a polarizing substrate is provided on the surface of the second substrate 4006 (the side opposite to the side where the coloring layer 4131 and the light-shielding layer 4132 are provided) and on the back side of the first substrate 4001 (the side opposite to the side where the insulating layer 4102 is provided), and a backlight unit (not shown) is provided on the back side of the first substrate 4001 through the polarizing substrate.

[0268] exist Fig.10 In the display device shown in FIG. 4 , a light shielding layer 4132 , a coloring layer 4131 , and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031 .

[0269] As materials that can be used for the light-shielding layer 4132, carbon black, titanium black, metals, metal oxides, or composite oxides containing a solid solution of multiple metal oxides can be cited. The light-shielding layer can also be a film containing a resin material or a thin film containing an inorganic material such as a metal. In addition, a laminated film containing a film of the material of the coloring layer 4131 can also be used for the light-shielding layer 4132. For example, a laminated structure can be used in which a film containing a material of the coloring layer 4131 for transmitting light of a certain color and a film containing a material of the coloring layer 4131 for transmitting light of other colors. By making the material of the coloring layer 4131 and the light-shielding layer 4132 the same, in addition to being able to use the same equipment, the process can also be simplified, so it is preferred.

[0270] Examples of materials that can be used for the coloring layer 4131 include metal materials, resin materials, and resin materials containing pigments or dyes. The light shielding layer and the coloring layer can be formed in the same manner as the above-mentioned layers. For example, an inkjet method can be used.

[0271] The insulating layer 4133 is preferably a protective layer having a planarization function. When the insulating layer 4133 has a planarization function, a flat insulating film can be formed on the formation surface of the coloring layer 4131 and the light shielding layer 4132 having different thicknesses. By planarizing the insulating layer 4133, the second electrode layer 4031 can be formed flat, thereby reducing unevenness in the thickness of the liquid crystal layer 4008. Examples of such an insulating layer 4133 include acrylic resins and the like.

[0272] in addition, Fig.10 The display device shown includes an insulating layer 4111 and an insulating layer 4102. Insulating layers that do not easily transmit impurity elements are used as the insulating layer 4111 and the insulating layer 4102. Since the transistor is sandwiched between the insulating layer 4111 and the insulating layer 4102, impurities from the outside can be prevented from entering the semiconductor layer.

[0273] In addition, although the configuration example of the display device is described in this embodiment, the circuit configuration and circuit elements can be appropriately changed according to the situation. For example, since the transistor 4011 is easily damaged by static electricity, etc., it is preferable to provide a protection circuit for protecting the drive circuit. In addition, the protection circuit is preferably configured using a nonlinear element.

[0274] Note that this embodiment mode can be combined with other embodiment modes or examples described in this specification as appropriate.

[0275] (Implementation method 3)

[0276] In this embodiment, a structure of a transistor which can be used for a semiconductor device or a display device which is one embodiment of the present invention is described.

[0277] The semiconductor device or display device of one embodiment of the present invention can be manufactured using various transistor types such as bottom-gate transistors and top-gate transistors. Therefore, the semiconductor layer material or transistor structure used can be easily replaced in a manner suitable for existing production lines.

[0278] [Bottom-gate transistor]

[0279] Fig.11A1 8 is a cross-sectional view of a channel protection transistor 810 which is a type of bottom-gate transistor. Fig.11A1 In the embodiment, the transistor 810 is formed over a substrate 771. In addition, the transistor 810 includes an electrode 746 on the substrate 771 via an insulating layer 772. In addition, a semiconductor layer 742 is included on the electrode 746 via an insulating layer 726. The electrode 746 may be used as a gate electrode, and the insulating layer 726 may be used as a gate insulating layer.

[0280] In addition, an insulating layer 741 is included on the channel formation region of the semiconductor layer 742. In addition, an electrode 744a and an electrode 744b are included on the insulating layer 726 in a manner of contacting a portion of the semiconductor layer 742. The electrode 744a can be used as one of a source electrode and a drain electrode. The electrode 744b is used as the other of the source electrode and the drain electrode. A portion of the electrode 744a and a portion of the electrode 744b are formed on the insulating layer 741.

[0281] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, the semiconductor layer 742 can be prevented from being exposed when the electrode 744a and the electrode 744b are formed. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrode 744a and the electrode 744b are formed. According to one embodiment of the present invention, a transistor with good electrical characteristics can be realized.

[0282] In addition, the transistor 810 includes an insulating layer 728 over the electrode 744 a , the electrode 744 b , and the insulating layer 741 , and includes an insulating layer 729 over the insulating layer 728 .

[0283] When an oxide semiconductor is used for the semiconductor layer 742, a material that can remove oxygen from a portion of the semiconductor layer 742 to generate oxygen vacancies is preferably used for at least the portion of the electrode 744a and the electrode 744b that is in contact with the semiconductor layer 742. The carrier concentration in the region where the oxygen vacancies are generated in the semiconductor layer 742 increases, and the region is converted to n-type and becomes an n-type region (sometimes referred to as n-type region). + region). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, an example of a material that can remove oxygen from the semiconductor layer 742 to generate an oxygen defect can be tungsten, titanium, or the like.

[0284] By forming the source region and the drain region in the semiconductor layer 742, the contact resistance between the electrode 744a and the electrode 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor such as field effect mobility and threshold voltage can be improved.

[0285] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of a transistor.

[0286] The insulating layer 729 is preferably formed using a material having a function of preventing impurities from being diffused into the transistor from the outside or reducing diffusion of impurities. Alternatively, the insulating layer 729 may be omitted as necessary.

[0287] Fig.11A2 The transistor 811 shown is different from the transistor 810 in that the transistor 811 includes an electrode 723 which can function as a back gate electrode over the insulating layer 729. The electrode 723 can be formed using the same material and method as the gate electrode 746.

[0288] Generally speaking, the back gate electrode is formed using a conductive layer and is arranged in a manner that the channel formation region of the semiconductor layer is sandwiched by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0289] The electrode 746 and the electrode 723 can both be used as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can all be used as gate insulating layers. Alternatively, the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0290] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 is a top gate transistor. In addition, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0291] By providing the electrode 746 and the electrode 723 across the semiconductor layer 742 and setting the potential of the electrode 746 and the electrode 723 to be the same, the region through which the carriers flow in the semiconductor layer 742 is further expanded in the thickness direction, so the amount of carrier movement increases. As a result, the on-state current of the transistor 811 increases, and the field effect mobility also increases.

[0292] Therefore, the transistor 811 is a transistor having a large on-state current relative to the occupied area. That is, the occupied area of ​​the transistor 811 can be reduced relative to the required on-state current. According to one embodiment of the present invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0293] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, they have a function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel formation region (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0294] In addition, by forming the back gate electrode using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side, thereby preventing light degradation of the semiconductor layer and preventing degradation of electrical characteristics such as threshold voltage drift of the transistor.

[0295] According to one embodiment of the present invention, a transistor with high reliability can be realized. In addition, a semiconductor device with high reliability can be realized.

[0296] Fig.11B1 A cross-sectional view of a channel protection transistor 820, which is one of the bottom-gate transistors, is shown. The transistor 820 has a structure substantially the same as the transistor 810, but the difference between the transistor 820 and the transistor 810 is that the insulating layer 741 covers the end of the semiconductor layer 742. In addition, in the opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. In addition, in the other openings formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 that overlaps the channel formation region can be used as a channel protection layer.

[0297] Fig.11B2 The transistor 821 shown is different from the transistor 820 in that the transistor 821 includes an electrode 723 on the insulating layer 729 that can be used as a back gate electrode.

[0298] By providing the insulating layer 741, the semiconductor layer 742 can be prevented from being exposed when the electrode 744a and the electrode 744b are formed. Therefore, the semiconductor layer 742 can be prevented from being thinned when the electrode 744a and the electrode 744b are formed.

[0299] In addition, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 of the transistor 820 and the transistor 821 are longer than those of the transistor 810 and the transistor 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided.

[0300] Fig.11C1 The transistor 825 shown is a channel-etched transistor which is one of the bottom-gate transistors. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0301] Fig.11C2 The transistor 826 shown is different from the transistor 825 in that the transistor 826 has an electrode 723 which can serve as a back gate electrode over the insulating layer 729 .

[0302] [Top-gate transistor]

[0303] Fig.12A1 The transistor 842 shown in the example is one of the top-gate transistors. The transistor 842 is different from the transistors 810, 811, 820, 821, 825, and 826 in that the electrodes 744a and 744b are formed after the insulating layer 729 is formed. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 through the openings formed in the insulating layers 728 and 729.

[0304] In addition, a portion of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the impurities 755 are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask. Fig.12A3As shown, an impurity region can be formed in a self-aligned manner in the semiconductor layer 742. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which the impurity 755 is introduced through the insulating layer 726 is lower than that of the region into which the impurity 755 is not introduced through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0305] Fig.12A2 The transistor 843 shown is different from the transistor 842 in that the transistor 843 includes an electrode 723. The transistor 843 includes an electrode 723 formed on a substrate 771. The electrode 723 has a region stacked with the semiconductor layer 742 via an insulating layer 772. The electrode 723 can function as a back gate electrode.

[0306] In addition, if Fig.12B1 The transistor 844 and Fig.12B2 As in the transistor 845 shown in FIG. 8 , the insulating layer 726 in the region not overlapping with the electrode 746 may be completely removed. Fig.12C1 The transistor 846 and Fig.12C2 As in the transistor 847 shown in the figure, the insulating layer 726 does not need to be removed.

[0307] In transistors 842 to 847, after forming electrode 746, impurity 755 may be introduced into semiconductor layer 742 using electrode 746 as a mask, thereby forming an impurity region in semiconductor layer 742 in a self-aligned manner. According to one embodiment of the present invention, a transistor with good electrical characteristics can be realized. In addition, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0308] Note that this embodiment mode can be combined with other embodiment modes or examples described in this specification as appropriate.

[0309] (Implementation 4)

[0310] In this embodiment, the structures of metal oxide CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) and CAAC-OS (c-axis Aligned Crystalline Oxide Semiconductor) that can be used for the OS transistor described in the above embodiment are described. Note that in this specification, etc., CAC represents an example of a function or material structure, and CAAC represents an example of a crystal structure.

[0311] 〈Composition of Metal Oxides〉

[0312] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (open / close function). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0313] CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated with a nanoparticle level. In addition, the conductive region and the insulating region are sometimes distributed unevenly in the material. In addition, sometimes the conductive region is observed to be fuzzy at its edge and connected with a cloud shape.

[0314] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0315] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with a narrow gap complements the component with a wide gap, and the carriers flow through the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on state of the transistor.

[0316] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0317] 〈Structure of Metal Oxides〉

[0318] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0319] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0320] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, the distortion sometimes has lattice arrangements such as pentagons and heptagons. In addition, no clear grain boundaries are observed near the distortion of CAAC-OS. That is, it can be seen that the formation of grain boundaries can be suppressed by distorting the lattice arrangement. This may be because CAAC-OS can tolerate distortions caused by the following reasons: low density of oxygen atoms in the ab plane direction or changes in the bonding distance between atoms due to substitution of metal elements.

[0321] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be expressed as an (In, M) layer.

[0322] CAAC-OS is an oxide semiconductor with high crystallinity. In addition, no clear grain boundaries are observed in CAAC-OS, so a decrease in electron mobility caused by grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (oxygen defects, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0323] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0324] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0325] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0326] <Transistor having an oxide semiconductor>

[0327] Here, a case where the above-mentioned oxide semiconductor is used for a transistor is described.

[0328] By using the above oxide semiconductor in a transistor, a transistor having high field effect mobility can be realized. In addition, a transistor having high reliability can be realized.

[0329] In addition, it is preferred to use an oxide semiconductor with a low carrier density for a transistor. When the carrier density of an oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density of an oxide semiconductor can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 and 1×10 -9 / cm 3 above.

[0330] In addition, since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0331] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region in an oxide semiconductor with a high trap state density may be unstable.

[0332] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0333] 〈Impurities〉

[0334] Here, the influence of each impurity in the oxide semiconductor is described.

[0335] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and near the interface of the oxide semiconductor (concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0336] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect energy level is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferred to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0337] When an oxide semiconductor contains nitrogen, electrons as carriers are generated, the carrier density increases, and the oxide semiconductor is easily converted to n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor is likely to have a normally-on characteristic. Therefore, it is preferred to reduce nitrogen in the oxide semiconductor as much as possible. For example, the nitrogen concentration in the oxide semiconductor measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0338] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, thereby sometimes forming an oxygen defect. When hydrogen enters the oxygen defect, electrons as carriers are sometimes generated. In addition, electrons as carriers are sometimes generated because part of the hydrogen is bonded to oxygen bonded to a metal atom. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration measured by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0339] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0340] This embodiment mode can be combined with other embodiment modes or examples as appropriate.

[0341] (Implementation method 5)

[0342] In this embodiment, a product example in which the semiconductor device or the display device described in the above embodiment is applied to electronic equipment is described.

[0343] 〈Notebook Personal Computer〉

[0344] A semiconductor device or a display device according to one embodiment of the present invention can be applied to a display included in an information terminal device. Fig.13A 14 shows a notebook personal computer which is one of the information terminal devices and includes a housing 5401 , a display portion 5402 , a keyboard 5403 , a pointing device 5404 , and the like.

[0345] 〈Smart Watch〉

[0346] A semiconductor device or a display device according to one embodiment of the present invention can be applied to a wearable terminal. Fig. 13B A smart watch is a type of wearable terminal, and the smart watch includes a frame 5901, a display unit 5902, an operation button 5903, a crown 5904, a strap 5905, and the like. In addition, a display device with the function of a position input device may be used for the display unit 5902. In addition, the function of the position input device may be added by providing a touch panel in the display device. Alternatively, the function of the position input device may be added by providing a photoelectric conversion element, also called a photoelectric sensor, in the pixel portion of the display device. In addition, as the operation button 5903, at least one of a power switch for starting the smart watch, a button for operating the software of the smart watch, a button for adjusting the volume, and a switch for turning on or off the display unit 5902 may be provided. In addition, in Fig. 13B The illustrated smartwatch shows two operation buttons 5903, but the number of operation buttons included in the smartwatch is not limited thereto. In addition, the crown 5904 is used as a crown for adjusting the time of the smartwatch. In addition, the crown 5904 can also be used as an input interface for operating the software of the smartwatch in addition to adjusting the time. In addition, Fig. 13B The smart watch shown has a structure including a crown 5904 , but is not limited to this and may also have a structure without a crown 5904 .

[0347] 〈Video Camera〉

[0348] A semiconductor device or a display device according to one embodiment of the present invention can be applied to a video camera. Fig. 13CThe video camera shown includes a first frame 5801, a second frame 5802, a display unit 5803, an operation key 5804, a lens 5805, and a connection unit 5806. The operation key 5804 and the lens 5805 are provided in the first frame 5801, and the display unit 5803 is provided in the second frame 5802. In addition, the first frame 5801 and the second frame 5802 are connected by the connection unit 5806, and the angle between the first frame 5801 and the second frame 5802 can be changed by the connection unit 5806. The image of the display unit 5803 can also be switched according to the angle between the first frame 5801 and the second frame 5802 formed by the connection unit 5806.

[0349] 〈Mobile Phone〉

[0350] A semiconductor device or a display device according to one embodiment of the present invention can be applied to a mobile phone. Fig.13D A mobile phone having the function of an information terminal is shown, and the mobile phone includes a frame 5501, a display portion 5502, a microphone 5503, a speaker 5504, and an operation button 5505. In addition, a display device with the function of a position input device can also be used for the display portion 5502. In addition, the function of the position input device can be added by providing a touch panel in the display device. Alternatively, the function of the position input device can be added by providing a photoelectric conversion element also called a photoelectric sensor in the pixel portion of the display device. In addition, as the operation button 5505, any one of a power switch for starting the mobile phone, a button for operating the software of the mobile phone, a button for adjusting the volume, and a switch for turning on or off the display portion 5502 can be provided.

[0351] In addition, Fig.13D The illustrated mobile phone shows two operation buttons 5505, but the number of operation buttons included in the mobile phone is not limited to this. Fig.13D The mobile phone shown may also include a light emitting device, which may be used as a flashlight or as an illumination.

[0352] 〈TV ​​equipment〉

[0353] The semiconductor device or display device according to one embodiment of the present invention can be applied to a television device. Fig.13E The television device shown includes a housing 9000, a display portion 9001, speakers 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, etc. A large display portion 9001 of, for example, 50 inches or more or 100 inches or more can be incorporated into the television device.

[0354] 〈Moving object〉

[0355] The semiconductor device or display device according to one embodiment of the present invention can be applied to the vicinity of a driver's seat of a vehicle as a moving object.

[0356] For example, Fig.13F It is a diagram showing the periphery of the front windshield in the interior of a vehicle. Fig.13F Display panel 5701, display panel 5702, display panel 5703 installed on the instrument panel, and display panel 5704 installed on the pillar are shown.

[0357] Display panels 5701 to 5703 can provide navigation information, speedometer, tachometer, driving distance, fuel level, gear status, air conditioning settings, and other information. In addition, the user can appropriately change the display content and layout displayed on the display panel to improve the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0358] By displaying the image captured by the camera unit installed on the vehicle body on the display panel 5704, the field of view (blind spot) blocked by the pillar can be supplemented. In other words, by displaying the image captured by the camera unit installed on the outside of the car, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can be used as a lighting device.

[0359] Electronic equipment for electronic advertising

[0360] A semiconductor device or a display device according to one embodiment of the present invention can be applied to a display for electronic advertisement. Fig.14A An example of a digital signage that can be hung on a wall is shown. Fig.14A The digital signage 6200 is shown hung on a wall 6201 .

[0361] 〈Foldable Tablet Information Terminal〉

[0362] The semiconductor device or display device according to one embodiment of the present invention can be applied to a tablet information terminal. Fig. 14B A tablet information terminal having a foldable structure is shown. Fig. 14B The information terminal shown includes a housing 5321a, a housing 5321b, a display portion 5322, and operation buttons 5323. In particular, the display portion 5322 includes a flexible substrate, and the substrate can realize a foldable structure.

[0363] In addition, the frame 5321a and the frame 5321b are connected by a hinge portion 5321c and can be folded in half by the hinge portion 5321c. In addition, the display portion 5322 is provided in the frame 5321a, the frame 5321b, and the hinge portion 5321c.

[0364] In addition, although not shown, FIG. 13A to FIG. 13C , Fig.13E , Fig.14A and Fig. 14B The electronic device shown may also have a structure including a microphone and a speaker. By adopting this structure, for example, a sound input function may be added to the electronic device.

[0365] In addition, although not shown in the figure, Fig.13A , Fig. 13B , Fig.13D , Fig.14A and Fig. 14B The electronic device shown may also have a structure including a camera.

[0366] In addition, although not shown in the figure, FIG. 13A to FIG. 13F , Fig.14A and Fig. 14B The electronic device shown may be provided with a sensor inside the frame (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared light, etc.). In particular, by providing a measuring device having a sensor for measuring inclination such as a gyro sensor or an acceleration sensor, it is possible to determine Fig.13D The orientation of the mobile phone shown (which direction the mobile phone is facing relative to the vertical direction) is determined, and the screen display of the display portion 5502 is automatically switched according to the orientation of the mobile phone.

[0367] In addition, although not shown in the figure, FIG. 13A to FIG. 13F , Fig.14A and Fig. 14B The electronic device shown may also include a device for obtaining biometric information such as fingerprints, veins, irises or voiceprints. By adopting this structure, an electronic device with a biometric recognition function can be realized.

[0368] FIG. 13A to FIG. 13F and Fig.14A The display unit of the electronic device shown in the figure can use a flexible substrate. Specifically, the display unit can also have a structure in which transistors, capacitors, and display elements are arranged on the flexible substrate. By using this structure, not only can the frame be realized as FIG. 13A to FIG. 13F and Fig.14A The electronic device has a flat surface as shown, and can realize Fig.13F An electronic device whose frame has a curved surface, such as the instrument panel and pillar shown.

[0369] As can be used FIG. 13A to FIG. 13F , Fig.14A and Fig. 14B The flexible substrate of the display part of the display part can be exemplified by the following materials that are translucent to visible light: polyethylene terephthalate resin (PET), polyethylene naphthalate resin (PEN), polyethersulfone resin (PES), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate resin, polyamide resin, polycycloolefin resin, polystyrene resin, polyamide-imide resin, polypropylene resin, polyester resin, polyvinyl halide resin, aromatic polyamide resin, epoxy resin, etc. In addition, a mixture or laminate of these materials can also be used.

[0370] Note that this embodiment mode can be combined with other embodiment modes or examples described in this specification as appropriate.

[0371] (Implementation 6)

[0372] In this embodiment, a semiconductor device that can be used in the electronic device described in the above embodiment is described. The semiconductor device described below can be used as a memory device.

[0373] In this embodiment, DOSRAM (registered trademark) is described as an example of a storage device using an oxide semiconductor. "DOSRAM" is derived from Dynamic Oxide Semiconductor Random Access Memory. DOSRAM refers to a storage device in which a storage cell is a 1T1C (one transistor and one capacitor) type cell and a write transistor is a transistor using an oxide semiconductor.

[0374] Reference Fig.15 The following describes an example of a stacked structure of the DOSRAM 1000. In the DOSRAM 1000, a sense amplifier section 1002 for reading data and a cell array section 1003 for storing data are stacked.

[0375] like Fig.15 As shown, the sense amplifier section 1002 is provided with a bit line BL, Si transistors Ta10 and Ta11. The Si transistors Ta10 and Ta11 include a semiconductor layer in a single crystal silicon wafer. The Si transistors Ta10 and Ta11 constitute a sense amplifier and are electrically connected to the bit line BL.

[0376] The cell array unit 1003 includes a plurality of memory cells 1001. The memory cell 1001 includes a transistor Tw1 and a capacitor C10. In the cell array unit 1003, two transistors Tw1 share a semiconductor layer. The semiconductor layer and the bit line BL are electrically connected via a conductor (not shown).

[0377] Fig.15The stacked structure shown can be used for various semiconductor devices formed by stacking a plurality of circuits including a transistor group.

[0378] Fig.15 The metal oxide, insulator, conductor, etc. in the film can be a single layer or a stacked layer. When manufacturing these layers, various film forming methods such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), chemical vapor deposition (CVD), atomic layer deposition (ALD) can be used. CVD methods include plasma CVD, thermal CVD, organometallic CVD, etc.

[0379] Here, the semiconductor layer of the transistor Tw1 is composed of a metal oxide (oxide semiconductor). Here, an example is shown in which the semiconductor layer is composed of three metal oxide layers. The semiconductor layer is preferably composed of a metal oxide containing In, Ga, and Zn.

[0380] Here, by adding an element that forms an oxygen defect or an element that bonds to an oxygen defect to the metal oxide, the carrier density of the metal oxide may be increased and the resistance may be reduced. For example, by selectively reducing the resistance of a semiconductor layer using a metal oxide, a source region or a drain region may be provided in the semiconductor layer.

[0381] In addition, as an element that makes the metal oxide low in resistance, boron or phosphorus is typical. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. can also be used. Typical examples of rare gas elements include helium, neon, argon, krypton and xenon. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.

[0382] In particular, boron and phosphorus are preferred because they can be produced using equipment in amorphous silicon or low-temperature polysilicon production lines. By switching to the equipment in such production lines, equipment investment can be reduced.

[0383] For example, a transistor including a semiconductor layer whose resistance is selectively reduced can be formed using a dummy gate. Specifically, a dummy gate is provided on the semiconductor layer, and the dummy gate is used as a mask to add an element that reduces the resistance of the semiconductor layer to the semiconductor layer. That is, the element is added to the region of the semiconductor layer that does not overlap with the dummy gate, thereby forming a region with reduced resistance. As a method for adding the element, the following can be used: an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc.

[0384] As the conductive material used for the conductor, there are the following materials: semiconductors represented by polycrystalline silicon doped with impurity elements such as phosphorus; silicides such as nickel silicide; metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; or metal nitrides containing the above metals as components (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride), etc. In addition, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide can also be used.

[0385] Insulating materials that can be used for insulators include aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In this specification, etc., oxynitride refers to a compound whose oxygen content is greater than nitrogen content, and oxynitride refers to a compound whose nitrogen content is greater than oxygen content.

[0386] Note that this embodiment mode can be combined with other embodiment modes or examples described in this specification as appropriate. Example

[0387] In order to confirm whether image data correction is appropriately performed in the operation of the display device described in Embodiment 1, calculation is performed using a circuit simulator. This calculation and its result will be described in this embodiment.

[0388] The software used in the calculation is SmartSpice (version 4.26.7.R) circuit simulator manufactured by SILVACO Co., Ltd. The calculation is performed using the circuit simulator, with the image data and the correction data as input data and the corrected image data as output data.

[0389] Fig.16 The circuit configuration used in the above calculation is shown. Fig.16 A source driver circuit SD, a correction data holding unit 104 and a display unit PA are shown.

[0390] exist Fig.16 The source driver circuit SD of FIG. 1 includes a digital-to-analog conversion circuit DAC and an operational amplifier OPA. The operational amplifier OPA is equivalent to Figure 1 The amplifier circuit AMP in the embodiment is a CMOS circuit composed of Si transistors.

[0391] The output terminal of the digital-to-analog conversion circuit DAC is electrically connected to the non-inverting input terminal of the operational amplifier OPA. In addition, the inverting input terminal of the operational amplifier OPA is electrically connected to the output terminal of the operational amplifier OPA, and the output terminal of the operational amplifier OPA is electrically connected to the second terminal of the switch SW1 and the first terminal of the switch SW2 of the correction data holding unit 104. In addition, due to the above connection structure, the operational amplifier OPA is used as a voltage follower circuit.

[0392] In addition, a high power input terminal of the operational amplifier OPA is electrically connected to the wiring VDL, and a low power input terminal of the operational amplifier OPA is electrically connected to the wiring VGL.

[0393] For the correction data storage unit 104, refer to the first embodiment. Figure 3 Description of the correction data holding unit 104.

[0394] In the first embodiment, the second terminal of the switch SW3 is electrically connected to the wiring VG. Fig.16 In the correction data holding unit 104, the second terminal of the switch SW3 is electrically connected to the wiring VGL via the DC power supply VD. In addition, the switches SW1 to SW3 all use analog switches (switches having a CMOS circuit structure) as switching elements.

[0395] exist Fig.16 , a resistor Rpa indicating resistance included in the wiring SL (wiring DL) in the display portion PA and a capacitor Cc obtained by combining the parasitic capacitance of the wiring SL (wiring DL) and the capacitance of the capacitor C1 of the pixel PIX are shown. The electrical connection point between the resistor Rpa and the capacitor Cc is a node ND.

[0396] Next, the calculation conditions are described. The capacitance of the capacitor Cd of the correction data holding unit 104 is set to 1 pF, and the capacitance of the capacitor Cc is set to 31 pF. According to the specific example of the first embodiment, this is equivalent to supplementing the voltage output from the digital-to-analog conversion circuit DAC with a voltage corresponding to the lower 5 bits.

[0397] In addition, the voltage of the DC power supply VD is set to 0.5V.

[0398] In addition, the value of the resistor Rpa is set to 10 kΩ.

[0399] The digital-to-analog conversion circuit DAC outputs a potential of 0.5V to 8.5V at every 0.25V.

[0400] In addition, since the operational amplifier OPA has a structure of a voltage follower circuit, the operational amplifier OPA needs to be a circuit that can operate appropriately within the potential range that the digital-to-analog conversion circuit DAC can output. Therefore, the potential supplied by the wiring VDL electrically connected to the high power input terminal of the operational amplifier OPA is set to 9V, and the potential supplied by the wiring VGL electrically connected to the low power input terminal of the operational amplifier OPA is set to a reference potential.

[0401] Fig.17 The graph of FIG. 1 shows the correction data output from the digital-to-analog conversion circuit DAC and the change in the potential of the node ND between the first period and the second period. Specifically, in Fig.17 In the figure, the vertical axis represents the potential V of the node ND. ND , the horizontal axis represents time. The first period and the second period correspond to the period between time T1 and time T2 and the period between time T2 and time T4 in the working example of the first embodiment, respectively. Specifically, time T1 is Fig.17 0 seconds (calculation start point), time T2 is 1.0×10 -5 seconds (the moment when writing of image data is completed).

[0402] In the first period, the switches SW1 and SW3 are turned on using the signal F1, and the switch SW2 is turned off using the signal F2. The digital-to-analog conversion circuit DAC outputs 4.0 V as a potential corresponding to image data, and this potential is written to the node ND.

[0403] During the second period, the switch SW1 and the switch SW3 are closed by the signal F1, and the switch SW2 is opened by the signal F2. The digital-to-analog conversion circuit DAC outputs a potential of 0.5V to 8.5V every 0.25V as correction data, and writes the output potential to the node ND3. By writing the potential corresponding to the correction data to the node ND3, the potential V ND In this embodiment, the potentials corresponding to the correction data, which are from 0.5 V to 8.5 V at intervals of 0.25 V, are respectively written as V0 to V 32 , Fig.17 Only the symbols V0 and V 10 、V 20 、V 30 、V 32 .

[0404] Here, consider the case where V0 (0.5V) is written to the node ND3 as correction data in the second period. The potential of the node ND3 is 0.5V in the first period, so even when the first period enters the second period, the potential of the node ND3 does not change, that is, it remains at 0.5V. Therefore, the potential VND There is no change due to capacitive coupling caused by capacitor Cd, and 4.0V is maintained.

[0405] Next, consider writing V into the node ND3 as correction data in the second period. 10 (3.0V). In the first period, the potential of the node ND3 is 0.5V, so when entering the second period, the potential of the node ND3 rises by 2.5V. Here, according to the formula (E2), the potential V ND The potential can be estimated to be 4+2.5 / 32V (=4.078125V), which is Fig.17 The results are roughly consistent.

[0406] Similarly, consider writing V 20 (5.5V), V 30 (8.0V), V 32 (8.5V). In the first period, the potential of the node ND3 is 0.5V, so when entering the second period, the potential of the node ND3 is written to V 20 (5.5V), V 30 (8.0V), V 32 (8.5V) rises by 5.0V, 7.5V, and 8.0V respectively. Here, according to formula (E2), the potential V ND The potential of can be estimated to be 4+5.0 / 32V (=4.15625V), 4+7.5 / 32V (=4.234375V), 4+8.0 / 32V (=4.25V) in each case, and Fig.17 The results are roughly consistent.

[0407] As described above, the digital-to-analog conversion circuit DAC outputs a potential at intervals of 0.25 V, and the correction data holding unit 104 can generate a potential whose intervals are smaller than 0.25 V.

[0408] In other words, by using a display device of one embodiment of the present invention, it is possible to generate image data having a higher resolution than the digital-to-analog conversion circuit DAC included in the source driver circuit SD using the correction data holding unit. In addition, by writing the image data to pixels included in the above-mentioned display device, the display unit of the above-mentioned display device can display a multi-grayscale image.

[0409] (Supplementary Notes Regarding the Descriptions in This Manual, etc.)

[0410] Hereinafter, notes will be added to each structure and description in the embodiment and examples described in this specification.

[0411] <Supplementary Notes on One Mode of the Present Invention Shown in the Embodiments and Examples>

[0412] The structure shown in each embodiment and example can be appropriately combined with the structure shown in other embodiment and example to constitute one mode of the present invention. In addition, when a plurality of structural examples are shown in one mode, the structural examples can be appropriately combined.

[0413] In addition, the content (or part thereof) described in a certain embodiment or example may be applied / combined / replaced with other content (or part thereof) described in that embodiment or example and at least one of the content (or part thereof) described in one or more other embodiments.

[0414] Note that the contents described in the embodiment modes or examples refer to the contents described in each embodiment mode or example using various drawings or the contents described in the articles described in the specification.

[0415] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment or example with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment or example, and at least one of the drawings (or parts thereof) shown in one or more other embodiments or examples.

[0416] A note on ordinal numbers

[0417] In this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion among constituent elements. Therefore, they are not added to limit the number of constituent elements. In addition, they are not added to limit the order of constituent elements. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments (or examples) of this specification, etc. may be attached with the ordinal number "second" in other embodiments (or examples) or claims. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments (or examples) of this specification, etc. may be omitted in other embodiments or claims.

[0418] <Supplementary Notes on the Description of the Drawings>

[0419] The implementation mode (or embodiment) is described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the implementation mode (or embodiment) can be implemented in a plurality of different forms, and its mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the implementation mode (or embodiment). Note that in the structure of the invention in the implementation mode (or the structure of the embodiment), the same figure mark is used in different drawings to represent the same part or the part with the same function, and repeated description is omitted.

[0420] In this specification, etc., for the sake of convenience, words and phrases such as "above" and "below" that indicate configuration are used to illustrate the positional relationship of constituent elements with reference to the accompanying drawings. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases that indicate configuration are not limited to the descriptions shown in this specification, etc., and the expressions can be appropriately changed according to the circumstances. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced by "an insulator located below the conductor".

[0421] In addition, the words "above" or "below" do not limit the positional relationship of the components to the situation where they are "directly above" or "directly below" and in direct contact. For example, when it is recorded as "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the situation where other components are included between insulating layer A and electrode B may also be included.

[0422] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not necessarily limited to the above dimensions. The drawings are for the sake of clarity and show arbitrary sizes, and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0423] In drawings such as perspective views, some components may be omitted for clarity.

[0424] In the drawings, the same reference numerals may be used to indicate the same components, components having the same functions, components made of the same material, components formed at the same time, etc., and repeated descriptions may be omitted.

[0425] 〈Supplementary Notes on Records That May Be Renamed〉

[0426] In this specification, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and the drain" (first electrode or first terminal), and the other of the source and the drain is referred to as "the other of the source and the drain" (second electrode or second terminal). This is because the source and the drain of the transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of the transistor may be appropriately renamed as source (drain) terminals, source (drain) electrodes, etc., depending on the circumstances. In addition, in this specification, the two terminals other than the gate are sometimes referred to as the first terminal and the second terminal or the third terminal and the fourth terminal. Note that in this specification, the channel formation region refers to a region where a channel is formed, and this region is formed by applying a potential to the gate, so that current can flow between the source and the drain.

[0427] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0428] In addition, in this specification, the words "electrode" or "wiring" do not limit the functions of the components. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed as one.

[0429] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference with the reference potential. For example, when the reference potential is the ground potential, voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0430] In this specification, etc., words such as "film" and "layer" can be interchanged depending on the situation or state. For example, "conductive layer" can be replaced with "conductive film" in some cases. In addition, "insulating film" can be replaced with "insulating layer" in some cases. In addition, other words can be used instead of words such as "film" and "layer" depending on the situation or state. For example, "conductive layer" or "conductive film" can be replaced with "conductive body" in some cases. In addition, for example, "insulating layer" or "insulating film" can be replaced with "insulator" in some cases.

[0431] In this specification, etc., depending on the situation or state, the words "wiring", "signal line" and "power line" can be interchanged with each other. For example, "wiring" can sometimes be converted to "signal line" etc. In addition, for example, "wiring" can sometimes be converted to "power line" etc. Vice versa, "signal line" or "power line" can sometimes be converted to "wiring". Sometimes "power line" etc. can be converted to "signal line" etc. Vice versa, "signal line" can sometimes be converted to "power line" etc. In addition, depending on the situation or state, the "potential" applied to the wiring can be converted to "signal" etc. Vice versa, "signal" etc. can sometimes be converted to "potential".

[0432] 〈Supplementary Notes on Definitions of Words and Phrases〉

[0433] The following describes the definitions of the terms and phrases mentioned in the above-mentioned implementation modes and examples.

[0434] 〈〈About Impurities in Semiconductors〉〉

[0435] Impurities of semiconductors are, for example, substances other than the main components constituting the semiconductor layer. For example, an element with a concentration lower than 0.1 atomic % is an impurity. Sometimes, due to the inclusion of impurities, for example, DOS (Density of States) is formed in the semiconductor, carrier mobility is reduced, or crystallinity is reduced. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, there are, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, for example, the mixing of impurities such as hydrogen sometimes leads to the generation of oxygen defects. In addition, when the semiconductor is a silicon layer, as impurities that change the characteristics of the semiconductor, there are, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0436] <<switch>>

[0437] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0438] For example, an electric switch or a mechanical switch may be used. In other words, the switch is not limited to a specific switch as long as it can control the current.

[0439] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors, etc.), or logic circuits combining these elements.

[0440] When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited. In addition, the "non-conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular restriction on the polarity (conductive type) of the transistor.

[0441] An example of a mechanical switch is a switch using MEMS (micro-electro-mechanical system) technology such as a digital micro-mirror device (DMD). This switch has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0442] <<connect>>

[0443] Note that in this specification, when it is stated that "X is connected to Y", it includes the following cases: X is electrically connected to Y; X is functionally connected to Y; and X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and includes connection relationships other than those shown in the drawings or the text.

[0444] X and Y used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0445] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) that can electrically connect X and Y may be connected between X and Y. In addition, the switch has a function of controlling on and off. In other words, whether or not current flows is controlled by placing the switch in a conducting state (on state) or a non-conducting state (off state).

[0446] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, γ (gamma) correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), a level converter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit capable of increasing signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0447] Furthermore, when it is explicitly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); a case where X and Y are functionally connected (in other words, a case where X and Y are functionally connected with another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween). In other words, when “electrically connected” is explicitly stated, it is the same as a case where only “connected” is explicitly stated.

[0448] Note that, for example, in the case where the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 (or not through Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 (or not through Z2) and in the case where the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0449] For example, it can be expressed as "X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y". Alternatively, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y". Alternatively, it can be expressed as "X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are sequentially arranged to be connected to each other". By specifying the connection order in the circuit structure using the same expression method as this example, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples and are not limited to the above expressions. Here, X, Y, Z1, and Z2 are objects (eg, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0450] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a portion of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0451] [Explanation of symbols]

[0452] DD: display device, DD1: display device, DD2: display device, DD3: display device, PA: display unit, GD: gate driver circuit, SD: source driver circuit, PIX: pixel, SR: shift register, LAT: latch circuit, LVS: level conversion circuit, DAC: digital analog conversion circuit, AMP: amplifier circuit, GL: wiring, GL1: wiring, GL2: wiring, SL: wiring, VA: wiring, VC: wiring, VP: wiring, VG: wiring, DL: wiring, AL: wiring, VL: wiring, VCOM: wiring, CAT: wiring, CRL1: wiring, CRL2: wiring, DB: data bus wiring, Rp: resistor, Cs: capacitor, Cp: ​​capacitor, Cpa: capacitor, Cd: capacitor, C1: capacitor, C2: capacitor, Tr1: transistor, Tr2: transistor, Tr3: transistor, Tr4: transistor, Tr5: transistor, SWT1: transistor, SWT2: transistor, SWT3: transistor, SWC: switch, SW1: switch, SW2: switch, SW3: switch, LC: liquid crystal element, LD: light emitting element, ND1: node, ND2: node, ND3: node, VDL: wiring, VGL: wiring, Rpa: resistor, Cc: capacitor, ND: node, BL: bit line, Ta10: Si transistor, Ta11: Si transistor, Tw1: transistor, C10: capacitor;101: image data holding unit, 102: drive circuit unit, 103: display element, 104: correction data holding unit, 215: display unit, 221a: scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving circuit, 241a: common line driving circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 755: impurity, 771: substrate, 772: insulating layer, 810: transistor, 811: transistor, 820: transistor, 821: transistor, 825: transistor, 826: transistor, 842: crystal body tube, 843: transistor, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 1000: DOSRAM, 1001: memory cell, 1002: read amplifier unit, 1003: cell array unit, 4001: first substrate, 4005: sealant, 4006: second substrate, 4010: transistor, 4011: transistor, 4013: liquid crystal element, 4014: wiring, 4015: electrode, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitor, 4021: electrode, 4030: first electrode layer, 4031: second electrode layer, 4032: insulating layer, 4033: insulating layer, 4 035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 5321a: frame, 5321b: frame, 5321c: hinge, 5322: display, 5323: operation button, 5401: frame, 5402: display, 5403: keyboard, 5404: pointing Device, 5501: housing, 5502: display unit, 5503: microphone, 5504: speaker, 5505: operation button, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5801: first housing, 5802: second housing, 5803: display unit, 5804: operation key, 5805: lens, 5806: connection unit, 5901: housing, 5902: display unit, 5903: operation button, 5904: crown, 5905: strap, 6200: digital sign, 6201: wall, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation key, 9006: connection terminal. ;

Claims

1. A display device, comprising: First Circuit; Second Circuit; as well as Image signal line, The first circuit includes an image data holding unit and a display element. The second circuit includes a correction data holding unit, The second circuit is electrically connected to the image signal line. The image signal line is electrically connected to the first circuit, The image data holding unit is electrically connected to the display element. The first circuit has a function of holding the first image data in the image data holding unit. The second circuit has: A function of holding correction data in the correction data holding unit; and A function of correcting the first image data held in the image signal line and the image data holding unit into second image data based on the correction data; The display element has a function of displaying an image corresponding to the second image data, The second circuit includes first to third switches and a first capacitor, The first terminal of the first switch is electrically connected to the first terminal of the first capacitor and the image signal line. The second terminal of the first switch is electrically connected to the first terminal of the second switch, Furthermore, the correction data holding unit is electrically connected to the second terminal of the second switch, the second terminal of the first capacitor, and the first terminal of the third switch.

2. The display device according to claim 1, The first circuit includes a fourth switch and a second capacitor, A first terminal of the fourth switch is electrically connected to the image signal line. Furthermore, the image data holding unit is electrically connected to the second terminal of the fourth switch and the second capacitor.

3. The display device according to claim 2, wherein at least one of the first to fourth switches is a transistor, And the transistor includes one of metal oxide and silicon in a channel formation region.

4. The display device according to claim 2, wherein the display device has first to fourth functions, The first function has: a function of writing a first potential to the correction data holding unit by turning the second switch off and the third switch on; and a function of writing a second potential corresponding to the first image data to the image signal line and the image data holding unit by turning the second switch off and turning the first switch and the fourth switch on; The second function has: a function of placing the first switch in a closed state and the fourth switch in an open state so as to place the image signal line and the image data holding unit in an electrically floating state, The third function has: a function of writing a third potential corresponding to the correction data into the correction data holding unit by placing both the first switch and the third switch in a closed state and placing the second switch in an open state; and When the potential of the second terminal of the first capacitor changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding unit changes to a fourth potential corresponding to the second image data. And the fourth function has: A function of turning off the fourth switch and driving the display element according to the fourth potential.

5. The display device according to claim 4, wherein the second potential is a potential corresponding to a high bit of the second image data, And the third potential is a potential corresponding to the lower bits of the second image data.

6. The display device according to claim 2, wherein the display element is a liquid crystal element, And the first terminal of the liquid crystal element is electrically connected to the image data holding unit.

7. The display device according to claim 2, Including the drive circuit part, The display element is a light emitting element, The driving circuit unit includes a driving transistor, The gate of the driving transistor is electrically connected to the image data holding unit. And the first terminal of the driving transistor is electrically connected to the second terminal of the second capacitor and the input terminal of the light emitting element.

8. An electronic device comprising: The display device according to any one of claims 1 to 7; as well as Frame.

Images