Electronic envelope detection circuit and corresponding demodulator

Abstract

Embodiments of the present disclosure relate to an electronic envelope detection circuit and a corresponding demodulator. The electronic envelope detection circuit includes an input signal detection circuit having at least one MOS transistor configured to receive a radio frequency input signal and deliver an internal signal based on the input signal. The bias point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit coupled to the input signal detection circuit is configured to deliver a low-frequency output signal based on the internal signal and further deliver a control signal based on the output signal. In operation, when the average power of the input signal increases, the value of the control signal decreases, and vice versa.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of French patent application No. 1900307 filed on January 14, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to electronic circuits, and in particular to electronic envelope detection circuits that can be incorporated into radio frequency demodulators for wireless communication applications. Background Art

[0004] Typically, the purpose of an electronic envelope detection circuit (or in other words an envelope detector) is to extract a low frequency signal from a carrier signal, such as an amplitude modulated radio frequency carrier signal.

[0005] Envelope detectors are often used in demodulators of the type modulated by amplitude shift keying (ASK).

[0006] This type of demodulator is capable of handling high data rates, such as on the order of several gigabytes per second, and can perform non-coherent demodulation while allowing for lower power consumption. These technical features are particularly advantageous for wireless communication applications such as short-range millimeter wave wireless links.

[0007] Conventional envelope detectors may, for example, be based on nonlinearities of electronics and may include an amplifier in a common-source configuration.

[0008] However, the amplifier of such an envelope detector requires a precise bias point to maximize the conversion gain and has a rather limited dynamic range.

[0009] This bias point is important so that the average power of the RF input signal to the envelope detector does not exceed the dynamic range of the envelope detector in order to extract low frequency signals with sufficient power without clipping.

[0010] In practice, it is difficult or impractical to configure such an exact bias point of the amplifier once and for all due to possible variations in the average power of the RF input signal of the envelope detector in the method used to manufacture the envelope detector or in the temperature near the envelope detector.

[0011] There are also some conventional technical solutions which propose a feedback circuit configured to adapt the change of the output signal of the envelope detector in direct current (DC) according to the average power of the RF input signal of the envelope detector.

[0012] However, such feedback circuits are often complex. In addition, the bias point of the envelope detector configured to receive the RF input signal is not variable and is often not suitable for the input signal due to the short channel effects of the transistors of the amplifier.

[0013] Therefore, the conversion gain (in other words, sensitivity) and the dynamic range of the envelope detector cannot be maximized. This usually leads to distortion of the output signal of the envelope detector during variations in the average power of the RF input signal.

[0014] Therefore, there is a need to provide a technical solution with low complexity, low energy consumption and low silicon footprint, making it possible to dynamically adapt the bias point and conversion gain of the envelope detector according to the average power of the input signal of the envelope detector so as to extend the dynamic range of the envelope detector. Summary of the invention

[0015] According to one aspect, an electronic envelope detection circuit is provided.

[0016] The electronic envelope detection circuit includes: an input signal detection circuit having at least one MOS transistor configured to receive a radio frequency input signal and to deliver an internal signal based on the input signal, a bias point of the at least one transistor being configured to be controlled by the input signal and a control signal; and a processing circuit coupled to the input signal detection circuit and configured to deliver a low frequency output signal based on the internal signal, and to deliver a control signal based on the output signal, such that when the average power of the input signal increases, the value of the control signal decreases, and vice versa.

[0017] Advantageously, such a circuit allows dynamically adjusting the bias point of at least one transistor of the input signal detection circuit according to changes in the average power of the input signal, so as to adapt the bias point of the at least one transistor to the average power of the RF input signal.

[0018] As a result, the conversion gain of the electronic envelope detection circuit is dynamically adapted to changes in the average power of the input signal.

[0019] In other words, when the average power of the input signal increases, the value of at least one control signal will decrease in order to compensate for the change in the average power of the input signal. Thus, the bias point is more or less adapted and is hardly affected by this change.

[0020] Therefore, the electronic envelope detection circuit can dynamically adapt to the change of the average power of the input signal, and the dynamic range of the electronic envelope detection circuit is extended.

[0021] According to one embodiment, an input signal detection circuit includes: a first N-type MOS transistor and a second N-type MOS transistor, the drains of the first N-type MOS transistor and the second N-type MOS transistor being commonly coupled to a processing circuit; and a transformer including: an input winding configured to receive an input signal; a first output winding coupled to the processing circuit and coupled to the gates of the first transistor and the second transistor; and a second output winding coupled to the sources of the first transistor and the second transistor, the first input winding being configured to receive a control signal.

[0022] Specifically, the first transformer and the second transformer form a mixer configured to receive an input signal on a gate and a source in order to multiply the input signal by itself and thus implement envelope detection by raising it to a second power. The gates of the first transistor and the second transistor are configured to be controlled by the input signal and by a control signal of the first output winding.

[0023] The first output winding may, for example, include a first center node located in the middle of the first output winding and configured to receive the control signal.

[0024] The second output winding may, for example, include a second center node located in the middle of the second output winding and coupled to ground.

[0025] The use of such a three-way transformer advantageously enables the application of RF input signals and control signals to the gates and sources of the first and second transistors to control the bias points of the first and second transistors and obtain higher conversion efficiency of the input signal detection circuit.

[0026] The number of turns of the first output winding may, for example, be greater than the number of turns of the input winding and greater than the number of turns of the second output winding, which advantageously makes it possible to increase the sensitivity of the input signal detection circuit.

[0027] According to another embodiment, an input signal detection circuit includes: an N-type MOS transistor, the drain of which is coupled to a processing circuit; and a transformer including: an input winding configured to receive an input signal and coupled between a source of the N-type MOS transistor and ground; and an output winding coupled between a gate of the N-type MOS transistor and the processing circuit and configured to receive a control signal.

[0028] This input signal detection circuit makes it possible to receive an input signal through a single input (single-ended mode).

[0029] According to yet another embodiment, the input signal detection circuit includes a first N-type MOS transistor and a second N-type MOS transistor, the drains of the first N-type MOS transistor and the second N-type MOS transistor are commonly coupled to the processing circuit, the sources of the first N-type MOS transistor and the second N-type MOS transistor are commonly coupled to the ground, and the gates of the first N-type MOS transistor and the second N-type MOS transistor are also configured to receive the input signal in a differential mode.

[0030] By way of indication and not limitation, the processing circuit may, for example, include a transimpedance amplifier configured to receive the internal signal.

[0031] The frequency of the RF input signal may be, for example, approximately 60 GHz.

[0032] According to another aspect, there is provided a demodulator comprising an electronic envelope detection circuit as defined above.

[0033] As a non-limiting example, the demodulator may be, for example, a demodulator of the type performing modulation by amplitude shift keying.

[0034] According to another aspect, there is provided a wireless radio frequency receiver comprising a demodulator as defined above.

[0035] According to a further aspect, there is provided a wireless communication device comprising a radio frequency receiver as defined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other advantages and characteristics of the present invention will become clear from a study of the detailed description of a purely non-limiting embodiment and of the accompanying drawings, in which:

[0037] Figure 1 schematically illustrates a wireless communication device,

[0038] Figure 2 A preferred embodiment of an electronic envelope detection circuit is schematically illustrated,

[0039] Figure 3A-3C schematically illustrates the results of a simulation of an electronic envelope detection circuit,

[0040] Figure 4 schematically illustrates the results of a simulation of an electronic envelope detection circuit,

[0041] Figure 5 schematically illustrates another embodiment of an electronic envelope detection circuit,

[0042] Figure 6 Another embodiment of an electronic envelope detection circuit is schematically illustrated. DETAILED DESCRIPTION

[0043] Figure 1A wireless communication device 1 is illustrated, which in this case is for example based on technology of a short-range millimetre wave wireless link.

[0044] The device 1 is configured to communicate wirelessly at a high rate (eg several gigabits per second) over a short range (eg approximately 10 centimeters) to replace data communication via cables of the Universal Serial Bus (USB) type, for example.

[0045] Without mechanical alignment constraints, the apparatus 1 may be advantageously used in industrial or consumer equipment that has a small size and / or is sealed.

[0046] The device 1 comprises a wireless radio receiver 2 having: an antenna 3, which receives a radio frequency transmission signal STR; a low noise amplifier 4, which is coupled to the antenna 3 and is configured to shape the radio frequency transmission signal STR so as to deliver a radio frequency input signal SER; and a demodulator 5 (in this case, for example, of the type modulated by amplitude shift keying (ASK), more particularly of the type modulated by on-off keying (OOK)) configured to deliver a baseband signal SBB based on the input signal SER.

[0047] The demodulator 5 comprises an electronic envelope detection circuit 6 and a baseband amplifier ABB.

[0048] The electronic envelope detection circuit 6 is configured to receive an input signal SER and is configured to deliver a low frequency output signal SSB to a baseband amplifier ABB.

[0049] The baseband amplifier is configured to subsequently amplify the low frequency output signal SSB so as to generate an output signal SBB.

[0050] For a more detailed description of a preferred exemplary embodiment of the electronic envelope detection circuit 6, refer to Figure 2 The electronic envelope detection circuit 6 includes an input signal detection circuit 7 and a processing circuit 8.

[0051] The input signal detection circuit 7 includes: a differential pair including a first N-type MOS transistor T1 and a second N-type MOS transistor T2, and a three-way transformer T3V coupled to the differential pair.

[0052] The transformer T3V includes: an input winding EE coupled between a reference voltage node (such as ground GND) and an input terminal BE configured to receive a radio frequency input signal SER; a first winding ES1 coupled between gates G1 and G2 of the first and second transistors T1 and T2; and a second output winding ES2 coupled between sources S1 and S2 of the first and second transistors T1 and T2.

[0053] It should be noted that the radio frequency input signal SER may also be applied differentially to the terminals of the input winding EE.

[0054] The first output winding ES1 comprises a first central node NM1 located in the middle of the first output winding ES1 and coupled to the processing circuit 8. The first central node NM1 is configured to receive a control signal SC delivered by the processing circuit 8.

[0055] The first output winding ES1 is configured to deliver a differential gate voltage to the gates G1 , G2 of the first and second transistors T1 , T2 based on the input signal SER and the control signal SC.

[0056] In other words, the bias points of the first and second transistors T1 , T2 are controlled by the input signal SER and the control signal SC.

[0057] As will be seen in more detail below, the control signal SC is a voltage signal configured to adjust the average power of the radio frequency input signal SER in common mode.

[0058] The second output winding ES2 includes a second center node NM2 located in the middle of the second output winding ES2 and coupled to a reference voltage node such as ground GND.

[0059] The second output winding ES2 is configured to deliver a differential source voltage to the sources S1 , S2 of the first and second transistors T1 , T2 based on the input signal SER.

[0060] It should be noted that the rotation directions of the input winding EE and the first output winding ES1 are the same, while the rotation direction of the second output winding ES2 is opposite to the rotation directions of the input winding EE and the first output winding ES1.

[0061] As a non-limiting example, the number of turns NSS1 of the first output winding ES1 is greater than the number of turns NSE of the input winding EE and greater than the number of turns NSS2 of the second output winding ES2 to increase the sensitivity of the input signal detection circuit 7 .

[0062] The input signal detection circuit 7 also includes an intermediate node NI coupled to the drains D1, D2 of the first and second transistors T1, T2, and the input signal detection circuit 7 is configured to output an internal current signal SI to the internal node NI, the internal current signal SI being a combination of the drain currents of the first and second transistors T1, T2.

[0063] The processing circuit 8 includes an output module 9 and a feedback module 10 .

[0064] The output module 9 comprises a transimpedance amplifier AT which is well known to those skilled in the art.

[0065] For example, in this case, the transimpedance amplifier AT includes a third N-type MOS transistor T3, a gate G3 of the third N-type MOS transistor T3 is coupled to the intermediate node NI, a source S3 of the third N-type MOS transistor T3 is coupled to a reference voltage node (such as ground GND), and a drain D3 of the third N-type MOS transistor T3 is coupled to the output terminal BS, and includes an output resistor RS coupled between the supply voltage VCC and the output terminal BS.

[0066] The size of the third transistor T3 is appropriately chosen so that it is adapted to the size of the first and second transistors T1 and T2 to ensure that the gate voltage VG3 of the third transistor T3 is adapted to operate the first and second transistors T1 and T2.

[0067] The drain current of the third transistor T3 is approximately proportional to the internal signal SI. The output module 9 is configured to convert the drain current into a low-frequency output voltage signal SSB at the output terminal BS by means of an output resistor RS.

[0068] In other words, the transimpedance amplifier AT is configured to deliver the low-frequency output voltage signal SSB to the output terminal BS based on the internal current signal SI.

[0069] The feedback module 10 includes: a fourth N-type MOS transistor T4, a gate G4 of the fourth N-type MOS transistor T4 is coupled to the output terminal BS, a drain D4 of the fourth N-type MOS transistor T4 is coupled to the power supply voltage VCC, and a source S4 of the fourth N-type MOS transistor T4 is coupled to the intermediate node NI via a feedback resistor RR; a control resistor RC coupled between the intermediate node NI and the first center node NM1; and a control capacitor CC coupled between the first center node NM1 and a reference voltage node (such as ground GND).

[0070] Reference now Figure 3A-3C , in order to schematically illustrate an example of a simulation of the operation of the electronic envelope detection circuit 6 .

[0071] Can be Figure 3A An example of the input voltage signal SER can be seen in . In this case, the frequency of the carrier of the input signal SER is, for example, 60 GHz, and the input signal SER is modulated with a 5 Gb / s bit stream under amplitude shift keying (ASK).

[0072] exist Figure 3B Schematically, the source voltages VS1 , VS2 of the first and second transistors T1 , T2 are shown.

[0073] Since the number of turns NSE of the input winding EE and the number of turns NSS2 of the second output winding ES2 are the same, and the direction of the input winding EE is opposite to that of the second output winding ES2, the amplitude of the source voltage VS2 of the second transistor T2 is substantially the same as the amplitude of the input signal SER, while the amplitude of the source voltage VS1 of the first transistor T1 is substantially opposite to the amplitude of the input signal SER.

[0074] In the same manner, since the number of turns NSS1 of the first output winding ES1 is greater than the number of turns of the input winding EE, and the direction of the input winding EE is the same as that of the first output winding ES1, the amplitude of the gate voltage VG1 of the first transistor T1 is greater than the amplitude of the input signal SER, and the amplitude of the gate voltage VG2 of the second transistor T2 is substantially opposite to that of the first transistor T1. Figure 3C Shown in.

[0075] It should also be noted that Figure 3C The value VSC of the control signal SC in corresponds to the average of the gate voltages VG1 , VG2 of the first and second transistors T1 , T2 .

[0076] When the average power of the input signal SER increases, the value of the internal signal SI and the average value of the low frequency output signal SSB will increase, and the value VSC of the control signal SC will decrease to reduce the bias point of the input signal detection circuit. As a result, the dynamic range of the input signal detection circuit is extended.

[0077] On the contrary, when the average power of the input signal SER decreases, the value of the internal signal SI and the value of the low frequency output signal SSB will also decrease, and the value VSC of the control signal SC will increase to compensate for the change in the average power of the input signal SER.

[0078] Reference now Figure 4 , in order to schematically illustrate another example of a simulation of the electronic envelope detection circuit 6 .

[0079] During the initial period Tini, since the value of the input signal SER is zero, the value of the output signal SSB is constant (DC value).

[0080] The average power of the input signal SER then increases to increase the value of the drain current of the first and second transistors T1, T2. Therefore, the value of the internal signal SI increases.

[0081] The output module 9 is configured to generate an output voltage signal SSB based on the internal signal SI.

[0082] Therefore, the value of the output signal SSB also increases to increase the value of the source current of the fourth transistor T4.

[0083] As an indication, the value of the output signal SSB is saturated in this case, since the amplitude of the input signal SER is already too large.

[0084] In this case, since the gain of the transimpedance amplifier is limited by, for example, the value of the feedback resistor RR and the size of the MOS transistor T4, as well as by the open-loop gain given by the third transistor T3 and the output resistor RS, the average gate voltage VG3 of the third transistor T3 and the value VSC of the control signal SC will therefore decrease, and will decrease accordingly more when the output BS of the output module 9 approaches saturation, the effect of which is to reduce the open-loop gain formed by the third transistor T3 and the output resistor RS.

[0085] As described above, the value VSC of the control signal SC corresponds to the average of the gate voltages VG1 , VG2 of the first and second transistors T1 , T2 .

[0086] A decrease in the value VSC of the control signal SC results in an average decrease in the gate voltages VG1 , VG2 of the first and second transistors T1 , T2 .

[0087] In other words, the bias point of the input signal detection circuit decreases as it follows the changes in the value VSC of the control signal SC.

[0088] Figure 4 Another example of a value VSC of the control signal SC is also shown if the electronic envelope detection circuit 6 operates without the feedback module 10 .

[0089] In this example, the range of variation of the output signal SSB is extended and the value of the output signal SSB oscillates around its DC value, which advantageously allows for better demodulation quality (particularly in order to generate a binary signal by comparing the output signal SSB with a threshold value close to its DC value) and advantageously allows for reduced distortion of the low-frequency output signal SSB. Such distortion may degrade the jitter of the demodulated binary signal.

[0090] As a variation, Figure 5 Another exemplary embodiment of the electronic envelope detection circuit 6 is illustrated.

[0091] As an indication, for example, the electronic envelope detection circuit 6 may have a configuration similar to Figure 2 The processing circuit 8 is the same as the processing circuit shown in FIG.

[0092] The input signal detection circuit 7 of the electronic envelope detection circuit 6 includes a fifth N-type MOS transistor T5, a drain D5 of the fifth N-type MOS transistor T5 is coupled to the intermediate node NI connected to the gate G3 of the third transistor T3, a source S5 of the fifth N-type MOS transistor T5 is coupled to a reference voltage node (such as ground) via an input winding EE of a two-way transformer T2V, and a gate G5 of the fifth N-type MOS transistor T5 is coupled to the feedback module 10 via an output winding ES of the transformer T2V.

[0093] The input signal detection circuit 7 receives the radio frequency input signal SER at the source S5 of the fifth transistor T5.

[0094] The direction of rotation of the input winding EE is opposite to that of the output winding ES. The number of turns NSE of the input winding EE is, for example, smaller than the number of turns NSS of the output winding ES to improve the sensitivity of the input signal detection circuit 7 .

[0095] As a result, the gate voltage VG5 of the fifth transistor T5 is controlled by the input signal SER.

[0096] The output winding ES is also configured to receive a control signal SC delivered by the processing circuit 8 .

[0097] In other words, the gate voltage VG5 of the fifth transistor T5 is also controlled by the control signal SC. Therefore, the bias point of the fifth transistor T5 is controlled by the input signal SER and the control signal SC.

[0098] When the average power of the input signal SER increases, the drain current of the fifth transistor T5 (in other words, the internal signal SI) also increases.

[0099] In that case, the processing circuit 8 is configured so as to increase the value of the output signal SSB and to decrease the value of the control signal SC in order to reduce the average of the gate voltage VG5 of the fifth transistor T5 .

[0100] Thus, the electronic envelope detection circuit 6 is able to adapt to changes in the average power of the input signal SER to dynamically modify the bias point and the conversion gain of the input signal detection circuit 7. Thus, the dynamic range of the circuit 6 is also extended.

[0101] Reference now Figure 6 , to illustrate another exemplary embodiment of the electronic envelope detection circuit 6 .

[0102] The processing circuit 8 is similar to Figure 2 and Figure 5 The processing circuit illustrated in FIG. 1 and the input signal detection circuit 7 include a sixth N-type MOS transistor T6 and a seventh N-type MOS transistor T7.

[0103] The drains of the sixth and seventh transistors T6 and T7 are commonly coupled to the intermediate node NI to deliver the internal signal SI to the intermediate node NI. The sources of the sixth and seventh transistors T6 and T7 are coupled to a reference voltage node (such as ground GND).

[0104] The gate G6 of the sixth transistor T6 is coupled to the intermediate node NI via the first control resistor RC1, and the gate G6 of the sixth transistor T6 is further coupled to the first input terminal BE1 via the first capacitor C1.

[0105] Likewise, the gate G7 of the seventh transistor T7 is coupled to the intermediate node N1 via the second control resistor RC2. The gate G7 of the seventh transistor T7 is also coupled to the second input terminal BE2 via the second capacitor C2.

[0106] The first and second control resistors RC1 , RC2 are identical, and the gates G6 , G7 of the sixth and seventh transistors T6 , T7 are configured to receive the same control signal SC.

[0107] The input signal detection circuit 7 is configured to receive the radio frequency input signal SER in a differential mode via the first and second capacitors C1 , C2 and the input terminals BE1 , BE2 .

[0108] If the average power of the input signal SER decreases, the internal signal SI also decreases.

[0109] The output module 9 is configured to convert the internal signal SI into an output signal SSB, and the value of the output signal SSB also decreases, which results in an increase in the gate voltage VG3 of the third transistor T3.

[0110] Therefore, the value of the control signal SC is increased to modify the bias point of the detection circuit 6 .

[0111] In the same way, an increase in the average power of the radio frequency input signal SER results in a decrease in the value of the control signal SC.

[0112] Therefore, an electronic envelope detection circuit is obtained, which enables the bias point and conversion gain of the circuit to dynamically adapt to the change of the average power of the input signal of the electronic envelope detection circuit to extend its dynamic range.

Claims

1. An electronic envelope detection circuit, comprising: An input signal detection circuit, the input signal detection circuit comprising: a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor having gates configured to receive a radio frequency input signal, wherein drains of the first MOS transistor and the second MOS transistor are commonly coupled to output an internal signal in response to the radio frequency input signal, wherein the first MOS transistor and the second MOS transistor have bias points, and wherein the bias points are controlled by the radio frequency input signal and a control signal; a processing circuit having an input configured to receive the internal signal and configured to generate a low frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low frequency output signal; wherein in response to an increase in the average power of the RF input signal, the value of the control signal decreases, and in response to a decrease in the average power of the RF input signal, the value of the control signal increases; and A transformer comprises: an input winding configured to receive the RF input signal; a first output winding coupled to receive the control signal and also coupled to gates of the first MOS transistor and the second MOS transistor; and a second output winding coupled to sources of the first MOS transistor and the second MOS transistor.

2. The circuit of claim 1 , wherein the first output winding includes a first center node located in the middle of the first output winding and configured to receive the control signal, and the second output winding includes a second center node located in the middle of the second output winding and coupled to a reference power supply node. 3 . The circuit of claim 1 , wherein the number of turns of the first output winding is greater than the number of turns of the input winding and greater than the number of turns of the second output winding.

4. The circuit of claim 1 , wherein the processing circuit comprises: an output transistor having a control terminal coupled to receive the internal signal and having a drain configured to output the low frequency output signal; as well as A resistor-capacitor circuit includes a resistor and a capacitor coupled in series between the control terminal and a reference power supply node, the resistor-capacitor circuit being configured to generate the control signal.

5. The circuit according to claim 4, further comprising: A feedback transistor has a control terminal configured to receive the low frequency output signal and has a drain coupled to the control terminal of the output transistor through a resistor circuit. 6 . The circuit of claim 1 , wherein the processing circuit comprises a transimpedance amplifier configured to receive the internal signal.

7. The circuit of claim 1, wherein the frequency of the RF input signal is approximately 60 GHz.

8. The circuit of claim 1, wherein the electronic envelope detection circuit is a component of a demodulator.

9. The circuit of claim 8, wherein the demodulator is of the type that modulates by amplitude shift keying.

10. The circuit of claim 8, wherein the demodulator is a component of a wireless radio frequency receiver.

11. The circuit of claim 10, wherein the wireless radio frequency receiver is a component of a wireless communication device.

12. An electronic envelope detection circuit, comprising: An input signal detection circuit, the input signal detection circuit comprising: a MOS transistor having a gate configured to receive a radio frequency input signal and a drain coupled to output an internal signal in response to the radio frequency input signal, wherein the MOS transistor has a bias point, and wherein the bias point is controlled by the radio frequency input signal and a control signal; a processing circuit having an input configured to receive the internal signal and configured to generate a low frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low frequency output signal; wherein in response to an increase in the average power of the RF input signal, the value of the control signal decreases, and in response to a decrease in the average power of the RF input signal, the value of the control signal increases; and The transformer comprises: an input winding configured to receive the RF input signal and coupled between the source of the MOS transistor and a reference voltage node; and an output winding coupled between the gate of the MOS transistor and the processing circuit and configured to receive the control signal.

13. The circuit of claim 12, wherein the processing circuit comprises: an output transistor having a control terminal coupled to receive the internal signal and having a drain configured to output the low frequency output signal; as well as A resistor-capacitor circuit includes a resistor and a capacitor coupled in series between the control terminal and a reference power supply node, the resistor-capacitor circuit being configured to generate the control signal.

14. The circuit of claim 13, further comprising a feedback transistor having a control terminal configured to receive the low frequency output signal and having a drain coupled to the control terminal of the output transistor through a resistor circuit.

15. The circuit of claim 12, wherein the processing circuit comprises a transimpedance amplifier configured to receive the internal signal.

16. The circuit of claim 12, wherein the frequency of the RF input signal is approximately 60 GHz.

17. The circuit of claim 12, wherein the electronic envelope detection circuit is a component of a demodulator.

18. The circuit of claim 17, wherein the demodulator is of the type that modulates by amplitude shift keying.

19. The circuit of claim 17, wherein the demodulator is a component of a wireless radio frequency receiver.

20. The circuit of claim 19, wherein the wireless radio frequency receiver is a component of a wireless communication device.

21. An electronic envelope detection circuit, comprising: An input signal detection circuit, the input signal detection circuit comprising: a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor having gates configured to receive a radio frequency input signal in a differential mode, wherein drains of the first MOS transistor and the second MOS transistor are commonly coupled to output an internal signal in response to the radio frequency input signal, wherein the first MOS transistor and the second MOS transistor have a bias point, wherein the bias point is controlled by the radio frequency input signal and a control signal, wherein sources of the first MOS transistor and the second MOS transistor are commonly coupled to a reference voltage node, and wherein gates of the first MOS transistor and the second MOS transistor are also coupled to receive the control signal; and a processing circuit having an input configured to receive the internal signal generated by the input signal detection circuit and configured to generate a low frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low frequency output signal; In response to an increase in the average power of the RF input signal, the value of the control signal decreases, and in response to a decrease in the average power of the RF input signal, the value of the control signal increases.

22. The circuit of claim 21 , wherein the processing circuit comprises: an output transistor having a control terminal coupled to receive the internal signal and having a drain configured to output the low frequency output signal; as well as A resistor circuit comprising: a first resistor coupled between the control terminal and the gate of the first MOS transistor to provide the control signal; and a second resistor coupled between the control terminal and the gate of the second MOS transistor to provide the control signal.

23. The circuit of claim 22, further comprising a feedback transistor having a control terminal configured to receive the low frequency output signal and having a drain coupled to the control terminal of the output transistor through a resistor circuit.

24. The circuit of claim 21, wherein the processing circuit comprises a transimpedance amplifier configured to receive the internal signal.

25. The circuit of claim 21, wherein the frequency of the RF input signal is approximately 60 GHz.

26. The circuit of claim 21, wherein the electronic envelope detection circuit is a component of a demodulator.

27. The circuit of claim 26, wherein the demodulator is of the type that modulates by amplitude shift keying.

28. The circuit of claim 26, wherein the demodulator is a component of a wireless radio frequency receiver.

29. The circuit of claim 28, wherein the wireless radio frequency receiver is a component of a wireless communication device.

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