Display device, display panel and printed circuit board

Abstract

The present disclosure provides a display device, a display panel, and a printed circuit board. The display device according to an embodiment includes: a display substrate including a display area and a pad area disposed around the display area; signal wirings disposed across the pad area and the display area on the display substrate; at least one wiring pad disposed on the pad area of the display substrate and including a pad pattern portion electrically connected to the signal wirings and a spaced pattern portion spaced apart from the pad pattern portion; and a printed circuit board attached to the pad area of the display substrate and including lead wirings connected to the wiring pads.

Description

Technical Field

[0001] The present disclosure relates to a display device, a display panel, and a printed circuit board. Background Art

[0002] A display device is a device that visually displays data. Such a display device includes a substrate divided into a display area and a non-display area. In the display area, a plurality of pixels are arranged on the substrate, and in the non-display area, a plurality of pads and the like are arranged on the substrate. A flexible film (COF Film) or the like on which a driving circuit or the like is mounted is bonded to the plurality of pads to transmit a driving signal to the pixels.

[0003] The flexible film includes a plurality of leads bonded to the plurality of pads, and each lead can be welded to a separately spaced pad. The welding can be achieved by an ultrasonic welding process.

[0004] However, in each display device manufacturing process, after the welding process, if an alignment error (Align miss) or a poorly mounted driving circuit occurs between the lead and the pad, the flexible film is separated from the plurality of pads. However, if there is damage on the plurality of pads that have been joined to the plurality of leads in the welding process, it may be difficult to reuse (Rework) the plurality of pads. Summary of the Invention

[0005] The problem to be solved by the present disclosure is to provide a display device including rework pads that can be re-separated after being joined to leads and have a reduced degree of damage.

[0006] The problems of the present disclosure are not limited to the above-mentioned technical problems, and those skilled in the art can clearly understand other technical problems not mentioned from the following description.

[0007] A display device according to an embodiment for solving the above problems includes: a display substrate including a display area and a pad area disposed around the display area; signal wirings disposed across the pad area and the display area on the display substrate; at least one wiring pad disposed on the pad area of the display substrate and including a pad pattern portion electrically connected to the signal wirings and a spaced pattern portion spaced apart from the pad pattern portion; and a printed circuit board attached to the pad area of the display substrate and including lead wirings connected to the wiring pads.

[0008] Optionally, it further includes a pad protection layer disposed in a space separated between the pad pattern portion and the spaced pattern portion.

[0009] It may be that the pad protection layer contains an organic insulating substance.

[0010] It may be that the separating pattern portion is arranged at a distance from the pad pattern portion along a first direction.

[0011] It may be that the first direction intersects with the direction from the end of the pad region toward the display region, and the width of the pad pattern portion in the first direction is larger than the width of the separating pattern portion in the first direction.

[0012] It may be that the wiring pad further includes a frame pattern portion in a square shape, and the frame pattern portion surrounds the pad pattern portion and the separating pattern portion on a plane.

[0013] It may be that the pad pattern portion, the separating pattern portion, and the frame pattern portion are arranged separately from each other, and the pad protection layer is integrally formed inside the frame pattern portion on a plane.

[0014] It may be that the frame pattern portion is physically connected to the pad pattern portion and the frame pattern portion is physically connected to the separating pattern portion respectively.

[0015] It may be that the pad protection layer includes a plurality of pad protection pattern portions separated from each other, and the plurality of pad protection pattern portions are arranged between the frame pattern portion and the separating pattern portion and between the separating pattern portion and the pad pattern portion.

[0016] It may be that the pad pattern portion has a line shape extending along a second direction intersecting with the first direction, and the shape of the separating pattern portion is the same as the shape of the pad pattern portion.

[0017] It may be that the second direction is the direction from the end of the pad region toward the display region.

[0018] It may be that the plurality of wiring pads include a first wiring pad and a second wiring pad arranged separately from each other, and the pad protection layer is also arranged between the first wiring pad and the second wiring pad.

[0019] It may be that a via hole layer is further included between the first wiring pad and the second wiring pad arranged on the display substrate, and the pad protection layer overlaps with the via hole layer.

[0020] It may be that the pad pattern portion and the separating pattern portion are directly connected to the lead wiring.

[0021] It may be that the pad pattern portion and the separating pattern portion are ultrasonically bonded to the lead wiring.

[0022] A display panel according to an embodiment for solving the above problem includes: a display substrate including a display area and a pad area disposed around the display area; signal wirings disposed across the pad area and the display area on the display substrate; and at least one wiring pad disposed on the pad area of the display substrate and including a pad pattern portion electrically connected to the signal wirings and a separation pattern portion separated from the pad pattern portion.

[0023] Optionally, it further includes a pad protection layer disposed in a space separating the pad pattern portion and the separation pattern portion.

[0024] Optionally, the pad protection layer includes an organic insulating material.

[0025] A printed circuit board according to an embodiment for solving the above problem includes: a base film; a plurality of lead wirings disposed on the base film and including a plurality of lead pattern portions separated from each other; and a plurality of insulating patterns disposed between the plurality of lead pattern portions.

[0026] Optionally, the plurality of insulating patterns are disposed between the plurality of lead wirings, and the insulating patterns contain an organic insulating material.

[0027] Details of other embodiments are included in the detailed description and the drawings.

[0028] Advantages of the Invention

[0029] According to an embodiment of the present disclosure, it is possible to provide a display device including a pad for rework that can be re-separated after wire bonding and has a reduced degree of damage.

[0030] The effects according to the present disclosure are not limited to the above examples, and more effects are included in this specification. Brief Description of the Drawings

[0031] Figure 1 is a plan layout view of a display device according to an embodiment.

[0032] Figure 2 is Figure 1 a cross-sectional view of the display device.

[0033] Figure 3A is a plan layout view of the pad area.

[0034] Figure 3B is a partial plan layout view of the printed circuit board.

[0035] Figure 4 is a schematic plan layout view of the pad area of the display panel and the printed circuit board attached to the pad area.

[0036] Figure 5 is an enlarged Figure 4 layout plan.

[0037] Figure 6 is a sectional view taken along Figure 5 line VI-VI' of

[0038] Figure 7 is a sectional view taken along Figure 5 line VII-VII' of

[0039] Figure 8 is a sectional view taken along Figure 5 line VIII-VIII' of

[0040] Figure 9 is a perspective view showing a situation where alignment errors occur between a plurality of leads of a printed circuit board and wiring pads of a display panel.

[0041] Figure 10 is a perspective view showing separation of a printed circuit board from wiring pads of a display panel.

[0042] Figure 11 is a sectional view showing a panel pad area of a display panel after separation of the printed circuit board.

[0043] Figure 12 is a sectional view showing separation of a pad protective layer and residues on the pad protective layer.

[0044] Figure 13 is a sectional view showing a panel pad area after separation of a pad protective layer and residues on the pad protective layer.

[0045] Figure 14 is a sectional view showing bonding of leads of a printed circuit board after separation of a pad protective layer and residues on the pad protective layer.

[0046] Figure 15 is a layout plan of a printed circuit board according to another embodiment.

[0047] Figure 16 is Figure 15 a sectional view of bonding of a printed circuit board and wiring pads of

[0048] Figure 17 is a layout plan of a panel pad area according to another embodiment.

[0049] Figure 18 is a sectional view taken along Figure 17 line XVIII-XVIII' of

[0050] Figure 19It is a plan view of a panel pad area according to another embodiment.

[0051] Figure 20 It is a plan view of a printed circuit board according to another embodiment.

[0052] Figure 21 It is a plan view of a panel pad area according to another embodiment.

[0053] Figure 22 It is a plan view of a display device according to another embodiment.

[0054] Figure 23 It is a cross-sectional view of a display device according to another embodiment.

[0055] Description of Reference Numerals

[0056] 100: Display panel

[0057] 200: Lower panel pad

[0058] 300: Printed circuit board

[0059] 500: Main circuit board Detailed Description of the Embodiment

[0060] The advantages and features of the present disclosure and the methods for realizing them will become clear with reference to the embodiments described in detail later in connection with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in different forms. That is, the present disclosure is defined by the scope of the claimed rights. Figure One

[0061] When an element or layer is described as "on" or "above" another element or layer, it includes not only the case where it is directly on the other element or layer but also all cases where there are other layers or other elements in between. On the contrary, when an element is described as "directly on" or "right above", it means that there are no other elements or layers in between.

[0062] Throughout the specification, the same reference numerals are used for the same or similar parts.

[0063] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0064] Figure 1 Figure 2 It is a plan view of a display device according to an embodiment, Figure 2 is Figure 1 a cross-sectional view of the display device, and for the sake of convenience of explanation, the ultrasonic device 700 is shown simultaneously in Figure 2 and Figure 3A andFigure 3B is a plan view of a pad region and a partial plan view of a printed circuit board, Figure 4 is a schematic plan view of a pad region of a display panel and a printed circuit board attached to the pad region.

[0065] The display device 1, as a device for displaying dynamic images or still images, can be used not only as portable electronic devices such as mobile phones, smartphones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs), but also as display screens for various products such as televisions, laptop computers, monitors, billboards, and the Internet of Things.

[0066] Referring to Figures 1 to 4 , the display device 1 may include a display panel 100 for displaying images, a printed circuit board 300 connected to the display panel 100, and a main circuit board 500 connected to the printed circuit board 300.

[0067] The display panel 100 may, for example, be an organic light-emitting display panel. In the following embodiments, the case where an organic light-emitting display panel is applied as the display panel 100 is illustrated, but it is not limited thereto, and other types of display panels such as liquid crystal displays (LCDs), quantum dot organic light-emitting display panels (QD-OLEDs), quantum dot liquid crystal displays (QD-LCDs), quantum nano-emissive display panels (QNEDs), and micro LEDs may also be applied.

[0068] The display panel 100 includes: a display area DA including a plurality of pixel areas; and a non-display area NA disposed around the display area DA. The display area DA may be in the shape of a rectangle with a vertical angle or a rectangle with a rounded corner in a plane. The display area DA may have a short side and a long side. The short side of the display area DA may be a side extending in the first direction DR1. The long side of the display area DA may be a side extending in the second direction DR2. However, the planar shape of the display area DA is not limited to a rectangle and may have a circular, elliptical, or other various shapes. The non-display area NA may be disposed adjacent to two short sides and two long sides of the display area DA. In this case, the non-display area NA may surround all sides of the display area DA to form a border of the display area DA. However, it is not limited thereto, and the non-display area NA may also be disposed adjacent to only two short sides or two long sides of the display area DA.

[0069] The non-display area NA of the display panel 100 further includes a panel pad area P_PA. The panel pad area P_PA can be arranged, for example, around one short side of the display area DA, but is not limited thereto, and can be arranged around two short sides of the display area DA or around two short sides and two long sides of the display area DA.

[0070] The printed circuit board 300 can include a printed base film 310 and a driving integrated circuit 390 arranged on the printed base film 310. The printed base film 310 can be composed of an insulating material.

[0071] The printed circuit board 300 can include: a first circuit area CA1, attached to the panel pad area P_PA of the display panel 100 on one side; a second circuit area CA2, arranged on one side of the first circuit area CA1 in the second direction DR2; and a third circuit area CA3, arranged on one side of the second circuit area CA2 in the second direction DR2 and attached to the main circuit board 500. The driving integrated circuit 390 can be arranged on one surface of the second circuit area CA2 of the printed circuit board 300. The driving integrated circuit 390 can be, for example, a data driving integrated circuit, and a chip on film (COF) method implemented by a data driving chip can be applied.

[0072] The main circuit board 500 can include a circuit pad area attached to the third circuit area CA3 of the printed circuit board 300. A plurality of circuit pads can be arranged in the circuit pad area of the main circuit board 500 to be connected to the lead wirings arranged in the third circuit area CA3 of the printed circuit board 300.

[0073] Refer to Figure 2 , the display device 1 further includes a panel underpad 200 arranged below the display panel 100. The panel underpad 200 can be attached to the back surface of the display panel 100. The panel underpad 200 includes at least one functional layer. The functional layer can be a layer that performs functions such as heat dissipation, electromagnetic wave shielding, grounding, buffering, strength reinforcement, support, and / or digitization functions. The functional layer can be a pad layer composed of pads, a film layer composed of films, a thin film layer, a coating layer, a panel, a flat plate, etc. One functional layer can be composed of a single layer, but can also be composed of multiple stacked thin films or coating layers. The functional layer can be, for example, a support substrate, a heat dissipation layer, an electromagnetic wave shielding layer, an impact absorption layer, a digitizer, etc.

[0074] The printed circuit board 300 can be bent downward in the third direction DR3 as Figure 2 shown. The other side of the printed circuit board 300 and the main circuit board 500 can be located below the panel underpad 200. The lower surface of the panel underpad 200 can be combined with the main circuit board 500 through a bonding layer, but is not limited thereto.

[0075] The display panel 100 may include a display substrate 101, a plurality of conductive layers, a plurality of insulating layers insulating the conductive layers, and an organic EL layer, etc.

[0076] The display substrate 101 is disposed across the entire display area DA and the non-display area NA. The display substrate 101 can function to support a plurality of components disposed above. In one embodiment, the display substrate 101 may be a rigid substrate including a rigid material such as soda lime glass, quartz, etc. However, it is not limited thereto, and the display substrate 101 may be a flexible substrate including a flexible material such as polyimide (PI).

[0077] The buffer layer 102 may be disposed on the display substrate 101. The buffer layer 102 can prevent the penetration of moisture and oxygen from the outside through the display substrate 101. The buffer layer 102 may include silicon nitride (SiN x ) film, silicon oxide (SiO2) film, and silicon oxynitride (SiO x N y ) film.

[0078] A semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 constitutes the channel of the thin film transistor. The semiconductor layer 105 may be disposed in each pixel of the display area DA, or may be disposed in the non-display area NA as the case may be. The semiconductor layer 105 may include a source region / drain region and an active region. The semiconductor layer 105 may include polysilicon.

[0079] A first insulating layer 111 may be disposed on the semiconductor layer 105. The first insulating layer 111 may be disposed across the entire surface of the display substrate 101. The first insulating layer 111 may be a gate insulating film having a gate insulating function. The first insulating layer 111 may include a silicon compound, a metal oxide, etc. For example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination with each other.

[0080] On the first insulating layer 111, a first conductive layer 120 may be disposed. The first conductive layer 120 may include a gate electrode GE of a thin film transistor TFT, a first electrode CE1 of a holding capacitor (Cst), and a gate signal line GSL. The gate signal line GSL may be disposed to pass through the display area DA and the panel pad area P_PA. The first conductive layer 120 may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu). The first conductive layer 120 may be a single-layer film or a stacked film composed of the above-exemplified substances.

[0081] On the first conductive layer 120, second insulating layers 112a and 112b may be disposed. The second insulating layers 112a and 112b can insulate the first conductive layer 120 and the second conductive layer 130. It may be that the second insulating layer 112a is generally disposed in the display area DA, and the second insulating layer 112b is generally disposed in the panel pad area P_PA. The second insulating layers 112a and 112b may be selected from the exemplified substances of the first insulating layer 111. In the panel pad area P_PA, the second insulating layer 112b may include a plurality of contact holes CNT that locally expose the gate signal line GSL. In Figure 2 it is exemplified that the second insulating layer 112b includes two contact holes CNT, but it is not limited thereto, and it may also include one or more than three contact holes CNT.

[0082] On the second insulating layers 112a and 112b, a second conductive layer 130 may be disposed. The second conductive layer 130 may include a second electrode CE2 of the holding capacitor Cst. The material of the second conductive layer 130 may be selected from the exemplified substances of the above first conductive layer 120. The first electrode CE1 of the holding capacitor Cst and the second electrode CE2 of the holding capacitor Cst may form a capacitor through the second insulating layers 112a and 112b.

[0083] On the second conductive layer 130, a third insulating layer 113 may be disposed. The third insulating layer 113 may include at least one of the exemplified substances of the above first insulating layer 111. In several embodiments, the third insulating layer 113 may be composed of an organic insulating material. The organic insulating material may be selected from the exemplified substances of the first via layer VIA1 described later.

[0084] On the third insulating layer 113, a third conductive layer 140 may be disposed. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high-potential voltage electrode ELVDDE, and a wiring pad PAD. The third conductive layer 140 may include at least any one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 140 may be a single-layer film composed of the substances exemplified above. However, this is not limited thereto, and the third conductive layer 140 may be a laminated film. For example, the third conductive layer 140 may be formed of a laminated structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc. In one embodiment, the third conductive layer 140 may be composed of Ti / Al / Ti.

[0085] The wiring pad PAD of the third conductive layer 140 may be overlapped and disposed with the gate signal line GSL of the first conductive layer 120 in the thickness direction and electrically connected to the gate signal line GSL through the contact hole CNT of the second insulating layer 112b.

[0086] On the third conductive layer 140, a first via layer VIA1 may be disposed. The first via layer VIA1 may contain an organic insulating material. The organic insulating material may include at least any one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0087] On the other hand, the upper structure of the third insulating layer 113 and the third conductive layer 140 may be removed or omitted from a part of the area of the wiring pad PAD on the panel pad area P_PA. Therefore, the omitted or removed structure may expose the wiring pad PAD disposed in the panel pad area P_PA.

[0088] The printed circuit board 300 further includes a lead wiring LE on one side of the first circuit region CA1 of the printed base film 310, and a circuit lead wiring C_LE on one side of the third circuit region CA3. The lead wiring LE is connected to a wiring pad PAD. In one embodiment, the lead wiring LE may be directly connected to the upper surface of the exposed wiring pad PAD. For example, the lead wiring LE may be ultrasonically welded to the wiring pad PAD.

[0089] On the other hand, the ultrasonic welding may be performed by an ultrasonic device 700. The ultrasonic device 700 may include a vibration generating unit 710, a vibration unit 720 connected to the vibration generating unit 710, a pressing unit 730 for increasing the amplitude of the vibration unit 720, and a vibration transmitting unit 740 connected to the vibration unit 720.

[0090] The vibration generating unit 710 can convert electrical energy into vibration energy. The vibration unit 720 is capable of vibrating with the vibration energy converted in the vibration generating unit 710. The vibration unit 720 may vibrate with a certain vibration direction and a predetermined amplitude. The vibration unit 720 may increase the amplitude in a direction parallel to the vibration direction through the pressing unit 730 connected to the vibration unit 720. The vibration transmitting unit 740 can transmit the vibration of the vibration unit 720 to the ultrasonic welding object. The support unit 750 fixes the upper and lower surfaces of the vibration unit 720, thereby being able to suppress the vibration unit 720 and the vibration transmitting unit 740 from moving up and down due to the vibration.

[0091] In one embodiment, the ultrasonic device 700 contacts the other side of the printed circuit board 300 and maintains a certain pressing state downward, so that the vibration transmitting unit 740 effectively transmits the vibration to the printed circuit board 300. At this time, as Figure 2 shown, the vibration transmitting unit 740 of the ultrasonic device 700 can overlap with the entire area of the printed circuit board 300 arranged below and perform ultrasonic welding.

[0092] The ultrasonic device 700 can vibrate along a predetermined vibration direction and cause the lead wiring LE to vibrate along the vibration direction. However, in this case, although the wiring pad PAD may vibrate weakly along the vibration direction due to the vibration transmitted through the lead wiring LE, the amplitude of its vibration may be weak. Therefore, the amplitude of the vibration transmitting unit 740 in the vibration direction can be regarded as substantially the same as the distance that the lead wiring LE moves along the vibration direction on the wiring pad PAD. In one embodiment, the vibration direction may be the second direction DR2. That is, the vibration direction may be the direction in which the long sides of the wiring pad PAD and the lead wiring LE extend.

[0093] If ultrasonic vibration is applied to the lead wiring LE on one side of the wiring pad PAD, a predetermined frictional force may be generated at the interface between one side of the wiring pad PAD and one side of the lead wiring LE, and frictional heat is generated due to the frictional force. If the frictional heat is sufficient to melt the substances constituting the wiring pad PAD and the lead wiring LE, the pad melting region PADb adjacent to the lead wiring LE of the wiring pad PAD and the lead melting region LEb adjacent to the wiring pad PAD of the lead wiring LE can be melted. That is, the wiring pad PAD may include a pad non-melting region PADa and a pad melting region PADb. In addition, the lead wiring LE may include a lead non-melting region LEa and a lead melting region LEb.

[0094] The pad non-melting region PADa may be a region that only contains the substances included in the wiring pad PAD. The lead non-melting region LEa may be a region that only contains the substances included in the lead wiring LE.

[0095] The pad melting region PADb may be a region where the substances included in the lead wiring LE are diffused and mixed with the substances of the wiring pad PAD and the lead wiring LE. The lead melting region LEb may be a region where the substances included in the wiring pad PAD are diffused and mixed with the substances of the lead wiring LE and the wiring pad PAD.

[0096] In the pad melting region PADb and the lead melting region LEb, the wiring pad PAD and the lead wiring LE can be combined through solidification. The interface between the wiring pad PAD and the lead wiring LE, that is, the interface between the pad melting region PADb and the lead melting region LEb, may have a non-flat shape.

[0097] For example, the lead wiring LE may include a metallic substance. The lead wiring LE may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). In the illustrated embodiment, the lead wiring LE may be formed of copper (Cu) and gold (Au). That is, the lead wiring LE may be composed of copper (Cu) disposed on the printed base film 310 and gold (Au) disposed on the copper (Cu). In this case, the copper (Cu) directly disposed on the printed base film 310 may not be directly connected to the wiring pad PAD, but is not limited thereto, and may be directly connected to a part of the wiring pad PAD. Further, the gold (Au) disposed on the copper (Cu) may be directly connected to the wiring pad PAD. In this case, the pad melting region PADb may be a region in which the Ti / Al / Ti of the wiring pad PAD, the gold (Au) and / or copper (Cu) of the lead wiring LE are mixed, and the lead melting region LEb may be a region in which the substances contained in the wiring pad PAD are diffused and the gold (Au) and / or copper (Cu) of the lead wiring LE and the Ti / Al / Ti of the wiring pad PAD are mixed.

[0098] On the other hand, if an alignment error occurs between the wiring pad PAD in the panel pad region P_PA and the lead wiring LE of the printed circuit board 300 or a defect occurs in the driving integrated circuit 390 that transmits a signal to the lead wiring LE after ultrasonic bonding between them, the plurality of lead wirings LE of the printed circuit board 300 may be separated from the plurality of wiring pads PAD in the panel pad region P_PA. However, in this case, if the plurality of wiring pads PAD that have been bonded to the plurality of lead wirings LE in the ultrasonic welding process are damaged, it may be difficult to rework the plurality of wiring pads PAD. Generally, the substance of the lead wiring LE may be stronger than the substance of the wiring pad PAD. In the illustrated embodiment, the gold (Au) of the lead wiring LE directly connected to the wiring pad PAD may be stronger than the aluminum (Al) contained in the wiring pad PAD. Therefore, if the plurality of lead wirings LE are separated from the plurality of wiring pads PAD after ultrasonic welding between the plurality of lead wirings LE and the plurality of wiring pads PAD, the wiring pads PAD may be partially damaged due to the lead wiring LE that is stronger than the constituent substance of the wiring pad PAD.

[0099] To this end, the wiring pad PAD may include a plurality of pattern portions arranged at intervals from each other, and a pad protection layer may be disposed between the plurality of pattern portions ( Figure 5("600"). The pad protection layer 600 can reduce the damage to the wiring pad PAD caused by the lead wiring LE. In addition, through the separation process of the pad protection layer 600, it is possible to easily remove the residue of the lead wiring LE remaining after the separation of the lead wiring LE. A detailed description thereof will be given later.

[0100] On the first via layer VIA1, a fourth conductive layer 150 may be arranged. The fourth conductive layer 150 may include a data line DL, a connection electrode CNE, and a high-potential voltage wiring ELVDDL. The data line DL may be electrically connected to the source electrode SE of the thin film transistor TFT through a contact hole penetrating the first via layer VIA1. The connection electrode CNE may be electrically connected to the drain electrode DE of the thin film transistor TFT through a contact hole penetrating the first via layer VIA1. The high-potential voltage wiring ELVDDL may be electrically connected to the high-potential voltage electrode ELVDDE through a contact hole penetrating the first via layer VIA1. The fourth conductive layer 150 may contain a material selected from the exemplified materials of the third conductive layer 140.

[0101] On the fourth conductive layer 150, a second via layer VIA2 is arranged. The second via layer VIA2 may contain at least one of the exemplified materials of the above-mentioned first via layer VIA1.

[0102] On the second via layer VIA2, an anode electrode ANO is arranged. The anode electrode ANO may be electrically connected to the connection electrode CNE through a contact hole penetrating the second via layer VIA2.

[0103] On the anode electrode ANO, a touch pad layer BANK may be arranged. The touch pad layer BANK may include contact holes exposing the anode electrode ANO. The touch pad layer BANK may be composed of an organic insulating material or an inorganic insulating material. For example, the touch pad layer BANK may be composed of at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, a polyacrylic resin, etc.

[0104] An organic layer EL may be arranged on the anode electrode ANO and within the opening of the touch pad layer BANK. A cathode electrode CAT is arranged on the organic layer EL and the touch pad layer BANK. The cathode electrode CAT may be a common electrode arranged across multiple pixels.

[0105] A thin film encapsulation layer 170 is arranged on the cathode electrode CAT. The thin film encapsulation layer 170 may cover the organic light-emitting element OLED. The thin film encapsulation layer 170 may be a laminated film in which an inorganic film and an organic film are alternately laminated. For example, the thin film encapsulation layer 170 may include a first encapsulation inorganic film 171, an encapsulation organic film 172, and a second encapsulation inorganic film 173 laminated in sequence.

[0106] On the other hand, in the panel pad region P_PA, the stacked structure and shape of the gate signal line GSL and the wiring pad PAD can be deformed.

[0107] For example, in several embodiments, the gate signal line GSL may include multiple patterns, and the wiring pad PAD disposed on the gate signal line GSL reflects the steps of the gate signal line GSL pattern and has surface irregularities.

[0108] In several embodiments, an auxiliary pad of the second conductive layer 130 may also be disposed between the gate signal line GSL and the wiring pad PAD. In this case, the planar dimension of the auxiliary pad may be smaller than the planar dimension of the wiring pad PAD. The wiring pad PAD, the auxiliary pad, and the gate signal line GSL may overlap and be electrically connected in the thickness direction.

[0109] In addition, in several embodiments, the gate signal line GSL may also be composed of the second conductive layer 130, and the wiring pad PAD may also be composed of the fourth conductive layer 150.

[0110] Referring to Figure 3A and Figure 3B , there may be multiple wiring pads PAD, and the multiple wiring pads PAD are arranged along the first direction DR1. The multiple wiring pads PAD may include, for example, a power pad, a data pad, and a panel dummy pad. The first direction DR1 may be a direction from the end of the panel pad region P_PA toward the display region DA. The second direction DR2 may be a direction intersecting the first direction DR1.

[0111] In addition, there may be multiple lead wirings LE disposed in the first circuit region CA1, and they may be arranged along the first direction DR1. The multiple lead wirings LE may include a power lead wiring, a data lead wiring, and a dummy lead.

[0112] Referring to Figure 4 , the multiple wiring pads PAD may be connected to the multiple lead wirings LE. For example, the wiring pad PAD may be directly connected to the lead wiring LE by ultrasonic welding. The first circuit region CA1 that is inverted 180° is attached to the panel pad region P_PA of Figure 4 along the thickness direction Figure 3A and Figure 3B .

[0113] Hereinafter, the specific shape of the above-mentioned wiring pad PAD and the pad protection layer 600 between the multiple pattern portions disposed on the wiring pad PAD will be described.

[0114] Figure 5 is an enlarged Figure 4 planar layout diagram, Figure 6 is along Figure 5A cross-sectional view taken along the VI-VI' line, Figure 7 is a cross-sectional view taken along Figure 5 the VII-VII' line, Figure 8 is a cross-sectional view taken along Figure 5 the VIII-VIII' line. Figures 5 to 8 Fig. shows a state in which the pad protection layer 600 is arranged between a plurality of pattern portions of the wiring pad PAD and is neatly arranged and attached to the printed circuit board 300 on the panel pad area P_PA.

[0115] Referring to Figures 5 to 8 , the gate signal line GSL can be arranged from the display area DA to the panel pad area P_PA and has a shape in which the width increases in the first direction DR1 in a region overlapping the wiring pad PAD of the panel pad area P_PA.

[0116] The first via layer VIA1 arranged on the third conductive layer 140 can be arranged around the wiring pad PAD. The first via layer VIA1 can be arranged between adjacent wiring pads PAD. As Figures 6 to 8 shown, the first via layer VIA1 can be arranged to partially overlap the wiring pad PAD. That is, the first via layer VIA1 can be arranged to partially overlap the leftmost, rightmost, uppermost, and lowermost regions on the plane of the wiring pad PAD.

[0117] One wiring pad PAD can include a plurality of pattern portions PT1, PT2, PT3 arranged at intervals from each other. The first pad pattern portion PT1 of the wiring pad PAD can surround the second pad pattern portion PT2 and the third pad pattern portion PT3 on the plane. The first pad pattern portion PT1 can be separated from the second pad pattern portion PT2 and the third pad pattern portion PT3. The first pad pattern portion PT1 can be a rectangular frame shape above the plane, but is not limited thereto, and other shapes can also be applied. When the first pad pattern portion PT1 is applied as a rectangular frame shape above the plane, the first pad pattern portion PT1 can include a short side extending in the first direction DR1 and a long side extending in the second direction DR2, but is not limited thereto. The first pad pattern portion PT1 can be a frame pattern portion surrounding the second pad pattern portion PT2 and the third pad pattern portion PT3.

[0118] The second pad pattern portion PT2 of the wiring pad PAD can be separated from the first pad pattern portion PT1 and the third pad pattern portion PT3 of the wiring pad PAD. The second pad pattern portion PT2 can be disposed between the first pad pattern portion PT1 and the third pad pattern portion PT3. The second pad pattern portion PT2 can partially overlap with the gate signal line GSL disposed therebelow, but is not limited thereto. Different from the third pad pattern portion PT3 described later, the second pad pattern portion PT2 may not be directly connected to the gate signal line GSL disposed therebelow. That is, the second insulating layer 112b disposed in the panel pad region P_PA can be disposed to overlap with the second pad pattern portion PT2, and the contact hole CNT of the second insulating layer 112b may not be disposed below the second pad pattern portion PT2. However, the second pad pattern portion PT2 can be connected to the lead wiring LE described later, so as to be electrically connected to the gate signal line GSL through the third pad pattern portion PT3 connected to the lead wiring LE.

[0119] The second pad pattern portion PT2 of the wiring pad PAD can dispose the third pad pattern portion PT3 therebetween and be separated from each other. The second pad pattern portion PT2 can be a separating pattern portion separated from the third pad pattern portion PT3. In Figure 5 it is shown that there are two second pad pattern portions PT2 disposed with the third pad pattern portion PT3 therebetween, but is not limited thereto, and the second pad pattern portion PT2 can be one or more than three.

[0120] The second pad pattern portion PT2 of the wiring pad PAD can be in a line shape extending in one direction. For example, the second pad pattern portion PT2 can have a line shape extending in the second direction DR2. In several embodiments, the second pad pattern portion PT2 can extend in the second direction DR2 and have a shape including at least one bent portion, for example, a bent portion bent in the first direction DR1. For example, the second pad pattern portion PT2 can extend in a zigzag shape along the second direction DR2, but is not limited thereto.

[0121] The third pad pattern portion PT3 of the wiring pad PAD can be disposed between adjacent second pad pattern portions PT2. The third pad pattern portion PT3 can be separated from the first pad pattern portion PT1 and the second pad pattern portion PT2 as described above.

[0122] The third pad pattern portion PT3 can be disposed to overlap with the gate signal line GSL therebelow. Through a plurality of contact holes CNT of the second insulating layer 112b below the third pad pattern portion PT3, it can be electrically connected to the gate signal line GSL.

[0123] The third pad pattern portion PT3 may have a shape that is substantially the same as or similar to the shape of the second pad pattern portion PT2 described above. That is, the third pad pattern portion PT3 of the wiring pad PAD may be in the shape of a line extending in one direction. For example, the third pad pattern portion PT3 may have a shape of a line extending in the second direction DR2. In several embodiments, the third pad pattern portion PT3 may extend in the second direction DR2 and have a shape including at least one bent portion, for example, a bent portion bent in the first direction DR1. For example, the third pad pattern portion PT3 may extend with a zigzag shape in the second direction DR2, but is not limited thereto. In Figure 5 FIG. shows one third pad pattern portion PT3 extending in one direction, but is not limited thereto, and there may be two or more third pad pattern portions PT3.

[0124] In the illustrated embodiment, the width W1 of the first direction DR1 on the plane of the third pad pattern portion PT3 may be larger than the width W2 of the first direction DR1 on the plane of the second pad pattern portion PT2. As described above, the third pad pattern portion PT3 may be electrically connected to the underlying gate signal line GSL. Thereafter, when the lead wirings LE of the printed circuit board 300 are respectively connected to the second pad pattern portion PT2 and the third pad pattern portion PT3, as described above, the third pad pattern portion PT3 functions to electrically connect the signal applied from the lead wirings LE of the printed circuit board 300 to the gate signal line GSL. Since the width W1 of the third pad pattern portion PT3 is larger than the width W2 of the second pad pattern portion PT2, an increase in the overall resistance of the wiring pad PAD can be prevented.

[0125] The pad protection layer 600 may be disposed between the plurality of pattern portions PT1, PT2, and PT3 of one wiring pad PAD as described above. That is, the pad protection layer 600 may be disposed between the first pad pattern portion PT1 and the second pad pattern portion PT2, between the first pad pattern portion PT1 and the third pad pattern portion PT3, and between the second pad pattern portion PT2 and the third pad pattern portion PT3. The pad protection layer 600 may be provided as a film including a plurality of patterns, but is not limited thereto.

[0126] As described above, when an alignment error (Align miss) occurs between the wiring pad PAD and the lead wiring LE of the printed circuit board 300 after ultrasonic bonding, or when the driving integrated circuit 390 that transmits a signal to the lead wiring LE malfunctions and the lead wiring LE of the printed circuit board 300 is separated from the wiring pad PAD in the panel pad area P_PA, since the constituent material of the lead wiring LE is stronger than the constituent material of the wiring pad PAD, the wiring pad PAD may be damaged by the lead wiring LE.

[0127] The pad protective layer 600 can reduce the damage to the wiring pad PAD caused by the lead wiring LE during ultrasonic bonding between the lead wiring LE and the wiring pad PAD. That is, during the ultrasonic bonding process, the lead wiring LE is in direct contact not only with the wiring pad PAD but also with the adjacent pad protective layer 600. The pad protective layer 600 can be composed of a material that can relieve a part of the physical pressure of the lead wiring LE. For example, the pad protective layer 600 can include an organic insulating material. In one embodiment, the pad protective layer 600 can be composed of polyimide (PI).

[0128] In addition, the pad protective layer 600 can also be in surface contact with the upper lead wiring LE during the ultrasonic process. That is, the function of the upper lead wiring LE is that during the ultrasonic process, it is in contact not only with the wiring pad PAD but also with the pad protective layer 600, maintaining an appropriate bonding depth between the lead wiring LE and the wiring pad PAD to partially prevent the lead wiring LE from penetrating deeply downward and bonding to the wiring pad PAD. Thus, even after separating multiple lead wirings LE from multiple wiring pads PAD after the ultrasonic process, the degree of damage to the multiple wiring pads PAD caused by the multiple lead wirings LE can be reduced.

[0129] The pad protective layer 600 can be arranged in the separated space between the pattern portions PT1, PT2, PT3 of the wiring pad PAD. That is, the pad protective layer 600 can include: a first protection pattern portion 610 and a second protection pattern portion 620, arranged between the first pad pattern portion PT1 and the second pad pattern portion PT2 and the third pad pattern portion PT3 of the wiring pad PAD and extending along the first direction DR1; and a third protection pattern portion 630, arranged between the first pad pattern portion PT1 and the second pad pattern portion PT2 and between the second pad pattern portion PT2 and the third pad pattern portion PT3 and connected to the first protection pattern portion 610 and the second protection pattern portion 620.

[0130] The first protection pattern portion 610 can be arranged closer to the display area DA than the second protection pattern portion 620. That is, the first protection pattern portion 610 can be arranged between the upper short side of the first pad pattern portion PT1 and the adjacent second pad pattern portion PT2 and the third pad pattern portion PT3, and the second protection pattern portion 620 can be arranged between the lower short side of the first pad pattern portion PT1 and the adjacent second pad pattern portion PT2 and the third pad pattern portion PT3.

[0131] In Figure 5 it is shown that the number of the third protection pattern portions 630 is four, but it is not limited thereto. The number of the third protection pattern portions 630 can be one to three, or can be five or more.

[0132] The first protection pattern portion 610 and the second protection pattern portion 620 may be in a line shape extending along the first direction DR1, and the third protection pattern portion 630 may vary according to the planar shape of the adjacent pad pattern portions PT1, PT2, and PT3. In Figure 5 it is shown that the third protection pattern portion 630 is in a line shape extending along the second direction DR2. In several embodiments, the third protection pattern portion 630 may extend along the second direction DR2 and include at least one bent portion. For example, the third protection pattern portion 630 may be in a zigzag shape extending along the second direction DR2.

[0133] The pad protection layer 600 may be formed integrally on a plane. That is, as described above, the third protection pattern portion 630 may physically connect the first protection pattern portion 610 and the second protection pattern portion 620 disposed on the upper side and the lower side.

[0134] The wiring pad PAD and the pad protection layer 600 may include irregularities on the surface. The convex portion of the wiring pad PAD and the pad protection layer 600 may be a region overlapping the second insulating layer 112b in the thickness direction, and the concave portion of the wiring pad PAD and the pad protection layer 600 may be a region not overlapping the second insulating layer 112b in the thickness direction.

[0135] Moreover, in the region where the wiring pad PAD and the pad protection layer 600 overlap the second insulating layer 112b in the thickness direction, the region overlapping the lower gate signal line GSL may protrude more upward, for example, in the third direction DR3, than the region not overlapping the lower gate signal line GSL.

[0136] A printed circuit board 300 including a lead wiring LE may be disposed on the wiring pad PAD and the pad protection layer 600. The lead wiring LE may be in contact with at least a part of the wiring pad PAD and the pad protection layer 600. That is, referring to Figures 6 to 8 , the lead wiring LE may be in contact with the second pad pattern portion PT2 and the third pad pattern portion PT3 of the wiring pad PAD, and in contact with at least a part of the first protection pattern portion 610, the second protection pattern portion 620, and the third protection pattern portion 630 of the pad protection layer 600. The lead wiring LE in contact with the wiring pad PAD may be electrically connected by ultrasonic welding. However, different from the illustrated example, the lead wiring LE may also be connected to the first pad pattern portion PT1 of the wiring pad PAD and may be in full contact with the first protection pattern portion 610 to the third protection pattern portion 630 of the pad protection layer 600, but is not limited thereto.

[0137] Hereinafter, a display device according to another embodiment will be described. In the following embodiments, the same structural components as those in the embodiments already described are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0138] In this embodiment, a case where the lead wiring LE of the printed circuit board 300 is separated from the wiring pad PAD in the panel pad region P_PA due to an alignment error between the lead wiring LE and the wiring pad PAD and / or a defect in the driving integrated circuit 390 or the like is described. Hereinafter, a case where an alignment error (Align miss) occurs between the wiring pad PAD and the lead wiring LE will be described as an example.

[0139] Figure 9 is a perspective view showing a case where alignment errors occur between a plurality of leads of a printed circuit board and wiring pads of a display panel, Figure 10 is a perspective view showing the separation of the printed circuit board from the wiring pads of the display panel, Figure 11 is a cross-sectional view showing the panel pad region of the display panel after the printed circuit board is separated, Figure 12 is a cross-sectional view showing the separation of the pad protective layer and the residue on the pad protective layer, Figure 13 is a cross-sectional view showing the panel pad region after the pad protective layer and the residue on the pad protective layer are separated.

[0140] Referring to Figures 9 to 13 , the panel pad region P_PA may further include a lead contact region CTA. The lead contact region CTA means the contact region between the wiring pad PAD in the panel pad region P_PA and the lead wiring LE on the pad protective layer 600. In Figure 11 , the lead contact region CTA is illustrated as overlapping with the third pad pattern portion PT3a, the second pad pattern portion PT2a, the first pad pattern portion PT1a, the third protection pattern portion 630 disposed between the third pad pattern portion PT3a and the second pad pattern portion PT2a, and the third protection pattern portion 630 disposed between the second pad pattern portion PT2a and the first pad pattern portion PT1a.

[0141] In the lead contact region CTA, the wiring pad PADa may have a cross-sectional shape that is locally recessed downward. In contrast, unlike the wiring pad PADa, the pad protective layer 600 may not substantially deform in shape.

[0142] The region recessed due to the lead contact between the wiring pad PADa and the pad protective layer 600 is hereinafter defined as the pad damage region DMA. In Figure 11 , the pad damage region DMA may overlap with the region where the third pad pattern portion PT3a, the second pad pattern portion PT2a, and the first pad pattern portion PT1a that are substantially in contact with the leads of the wiring pad PADa are disposed.

[0143] In the case of this embodiment, the pad protection layer 600 is disposed between a plurality of separated pattern portions of the wiring pad PADa. Therefore, when the lead wiring LE is separated from the panel pad region P_PA of the display panel 100 and the display panel 100 is reused, the degree of damage to the wiring pad PADa in the pad damage area DMA can be reduced.

[0144] Furthermore, in the lead contact area CTA, residues RES of the lead wiring LE may remain on the wiring pad PADa and the pad protection layer 600. Figure 11 shows the residues RES integrally disposed on the wiring pad PADa and the pad protection layer 600, but is not limited thereto, and may be locally separated and disposed on the wiring pad PADa and the pad protection layer 600.

[0145] Refer to Figure 12 , after ultrasonic welding, the pad protection layer 600 is peeled off from the panel pad region P_PA. Figure 12 shows the separated pad protection layer 600 in the cross-sectional shape, but actually as Figure 5 shows, the pad protection layer 600 is integrally formed on one wiring pad PADa.

[0146] As Figure 12 shows, during the process of peeling off the pad protection layer 600, the residues RES of the lead wiring LE remaining on the pad protection layer 600 and the wiring pad PADa can be removed together with the pad protection layer 600. Thus, even if ultrasonic welding is re-executed on the display panel 100, the efficiency of ultrasonic welding can be prevented from being reduced due to the residues RES of the separated lead wiring LE.

[0147] Figure 14 is a cross-sectional view of joining the leads of the printed circuit board after separating the pad protection layer and the residues on the pad protection layer. Figure 14 shows the printed circuit board 300 disposed in the Figure 13 panel pad region P_PA.

[0148] Refer to Figure 14 , the printed circuit board 300 including the lead wiring LE is connected to the wiring pad PADa_1 and does not include the pad protection layer 600, which is different from the display device 1 according to Figure 6 .

[0149] More specifically, the lead wiring LE can be connected to the wiring pad PADa_1. A groove can be formed in the wiring pad PADa_1 in a downward direction from the pad damage area DMA. The lead wiring LE can be ultrasonically welded in direct connection with the wiring pad PADa_1 including the groove formed in the pad damage area DMA. The groove of the wiring pad PADa_1 can be arranged in the pad damage area DMA of the wiring pad PADa_1. In the panel pad area P_PA according to the present embodiment, a pad protection layer can be not arranged between the plurality of pad pattern portions PT1a_1, PT2a_1, PT3a_1 of the wiring pad PADa_1.

[0150] In Figure 14 In the pad damage areas DMA of the respective pad pattern portions PT1a_1, PT2a_1, PT3a_1, the respective pad pattern portions PT1a_1, PT2a_1, PT3a_1 may not be in direct contact with the upper lead wiring LE, but not limited thereto. In the pad damage areas DMA of the respective pad pattern portions PT1a_1, PT2a_1, PT3a_1, the respective pad pattern portions PT1a_1, PT2a_1, PT3a_1 may also be in partial contact with the upper lead wiring LE for ultrasonic welding.

[0151] Figure 15 is a plan layout diagram of a printed circuit board according to another embodiment, Figure 16 is Figure 15 a cross-sectional view of the printed circuit board of

[0152] Referring to Figure 15 , in the printed circuit board 300_1 according to the present embodiment, a lead wiring LE_1 is included, and the lead wiring LE_1 includes a plurality of pattern portions L_PT1, L_PT2, which is different from the printed circuit board 300 according to Figure 3A and Figure 3B in this regard.

[0153] More specifically, the printed circuit board 300_1 according to the present embodiment can include a lead wiring LE_1, and the lead wiring LE_1 includes a plurality of pattern portions L_PT1, L_PT2 arranged apart from each other. That is, the lead wiring LE_1 can include a second lead pattern portion L_PT2 electrically connected to the driving integrated circuit and extending along the second direction DR2 and a first lead pattern portion L_PT1 electrically separated from the driving integrated circuit and extending along the second direction DR2.

[0154] In Figure 15In the example, the second lead pattern portion L_PT2 is one, but it is not limited thereto. The second lead pattern portion L_PT2 may be two or more. An example is given where the first lead pattern portion L_PT1 places the second lead pattern portion L_PT2 in the middle and arranges two on each side respectively, but it is not limited thereto. The first lead pattern portion L_PT1 may also arrange one or more than three on each side of the second lead pattern portion L_PT2.

[0155] Moreover, the printed circuit board 300_1 may further include a lead protection layer 600_1 disposed between the plurality of pattern portions L_PT1, L_PT2 of the lead wiring LE_1. The lead protection layer 600_1 may be formed of a substance substantially the same as the constituent substance of the pad protection layer 600 described in one embodiment.

[0156] The lead protection layer 600_1 may include a first lead protection pattern portion 601_1 disposed between the plurality of pattern portions L_PT1, L_PT2 spaced apart from each other and a second lead protection pattern portion 602_1 surrounding the lead wiring LE_1 in a plane. The second lead protection pattern portion 602_1 may be disposed to extend between adjacent lead wirings LE_1. That is, the lead protection layer 600_1 may include a plurality of lead protection pattern portions 601_1, 602_1 integrally formed with each other.

[0157] Refer to Figure 16 , at least a part of the plurality of pattern portions L_PT1, L_PT2 of the lead wiring LE_1 and the lead protection layer 600_1 disposed between the plurality of pattern portions L_PT1, L_PT2 may be in direct contact with the underlying wiring pad PAD_1. That is, the second lead pattern portion L_PT2 of the lead wiring LE_1 may be directly connected to the underlying wiring pad PAD_1. In Figure 16 it is shown that the second lead pattern portion L_PT2 is in direct contact with the wiring pad PAD_1 in a region where only the gate signal line GSL having the underlying wiring pad PAD_1 and the wiring pad PAD_1 are arranged and the second insulating layer 112b is not arranged, but it is not limited thereto. The second lead pattern portion L_PT2 may not be in contact with the wiring pad PAD_1 in a region where only the gate signal line GSL having the underlying wiring pad PAD_1 and the wiring pad PAD_1 are arranged and the second insulating layer 112b is not arranged.

[0158] Furthermore, the first lead pattern portion L_TP1 disposed with the second lead pattern portion L_PT2 in the middle and spaced apart may be directly connected to the underlying wiring pad PAD_1. In Figure 16In the first lead pattern portion L_TP1 shown, the first lead pattern portion L_TP1 that places the first lead pattern portions L_TP1 adjacent to each other in the plane in the middle and is spaced apart from the second lead pattern portion L_PT2 does not contact the underlying wiring pad PAD_1. However, this is not limited thereto, and the first lead pattern portion L_TP1 that places the first lead pattern portions L_TP1 adjacent to each other in the plane in the middle and is spaced apart from the second lead pattern portion L_PT2 may also be directly connected to the underlying wiring pad PAD_1.

[0159] Moreover, the first lead protection pattern portion 601_1 disposed between the second lead pattern portion L_PT2 and the first lead pattern portion L_TP1 may be in direct contact with the underlying wiring pad PAD_1, and the second lead protection pattern portion 602_1 may be disposed at a distance from the underlying wiring pad PAD_1 in the thickness direction. In Figure 16 it is shown that the first lead protection pattern portion 601_1 disposed between adjacent first lead pattern portions L_TP1 does not contact the underlying wiring pad PAD_1. However, this is not limited thereto, and the first lead protection pattern portion 601_1 disposed between adjacent first lead pattern portions L_TP1 may also contact the underlying wiring pad PAD_1.

[0160] In several embodiments, the lead protection layer 600_1 may not include the second lead protection pattern portion 602_1 and may only include the first lead protection pattern portion 601_1 disposed between the plurality of lead pattern portions L_PT1 and L_PT2 of the lead wiring LE_1. In this case, the lead protection layer 600_1 may have a shape that is not integrally formed and is spaced apart from each other with the plurality of lead pattern portions L_PT1 and L_PT2 in the middle.

[0161] Moreover, in several embodiments, the lead protection layer 600_1 may not be integrally formed and the planar shape of the lead wiring LE_1 may be substantially the same as the planar shape of the wiring pad PAD described in Figure 5 That is, the lead wiring LE_1 may further include a third lead pattern portion that surrounds the lead pattern portions L_PT1 and L_PT2 in the plane, and the lead protection layer 600_1 may be surrounded by the third lead pattern portion.

[0162] In the case of this embodiment, the lead protection layer 600_1 is also disposed between the plurality of spaced pattern portions of the lead wiring LE_1. Therefore, when the display panel 100 is reused after separating the lead wiring LE_1 from the panel pad region P_PA of the display panel 100, damage to the wiring pad PAD_1 can be reduced.

[0163] Figure 17 is a plan layout diagram of a panel pad region according to another embodiment.Figure 18 is a sectional view taken along line XVIII-XVIII' of Figure 17 .

[0164] Referring to Figure 17 and Figure 18 , the wiring pad PAD_2 according to the present embodiment is substantially the same in planar shape as the lead wiring LE_1 described in Figure 15 , which is different from the wiring pad PAD according to an embodiment in this regard.

[0165] More specifically, different from the wiring pad PAD of Figure 5 , the wiring pad PAD_2 may not include the first pad pattern portion PT1. That is, the wiring pad PAD_2 may include a second pad pattern portion PT2_1 that is the same as the second pad pattern portion PT2 described in Figure 5 and a third pad pattern portion PT3_1 that is the same as the third pad pattern portion PT3 described in Figure 5 .

[0166] The pad protection layer 600_2 disposed between the plurality of pad pattern portions PT2_1, PT3_1 of the wiring pad PAD_2 may be substantially the same in planar shape as the lead protection layer 600_1 disposed between the plurality of lead pattern portions L_PT1, L_PT2 of the lead wiring LE_1 described in Figure 15 . That is, the pad protection layer 600_2 may include: a first pad protection pattern portion 601_2 disposed between the third pad pattern portion PT3_1 and the adjacent second pad pattern portion PT2_1 and between the adjacent second pad pattern portions PT2_1; and a second pad protection pattern portion 602_2 that wraps around the entire first pad pattern portion PT1_1 and the second pad pattern portion PT2_1 in a plane and is disposed between the adjacent wiring pads PAD_2.

[0167] Figure 19 is a plan layout diagram of a panel pad region according to still another embodiment.

[0168] Referring to Figure 19 , the wiring pad PAD_3 according to the present embodiment is different from the wiring pad PAD according to an embodiment in the planar shapes of the second pad pattern portion PT2_2 and the third pad pattern portion PT3_2.

[0169] More specifically, the second pad pattern portion PT2_2 and the third pad pattern portion PT3_2 of the wiring pad PAD_3 according to the present embodiment may each have a line shape extending along the first direction DR1. In Figure 19Illustrated in the example below, the third pad pattern portion PT3_2 electrically connected to the lower gate signal line GSL is disposed between adjacent second pad pattern portions PT2_2, but is not limited thereto.

[0170] The pad protection layer 600_3 according to the present embodiment may include a first protection pattern portion 610_1 and a second protection pattern portion 620_1 disposed between a second pad pattern portion PT2_2 and a third pad pattern portion PT3_2 adjacent to a long side edge of the first pad pattern portion PT1 of the wiring pad PAD_3, and may include a third protection pattern portion 630_1 disposed between second pad pattern portions PT2_2 adjacent to a short side edge of the first pad pattern portion PT1. The third protection pattern portion 630_1 may also be disposed between adjacent second pad pattern portions PT2_2 and third pad pattern portion PT3_2.

[0171] In the case of this embodiment as well, by disposing the pad protection layer 600_3 between a plurality of separated pattern portions of the wiring pad PAD_3, when the display panel 100_2 is reused after separating the lead wiring LE from the panel pad region P_PA of the display panel 100_2, it is possible to reduce the area of the wiring pad PAD_3 that is substantially damaged in the pad damage region.

[0172] Moreover, when the display panel 100_2 is reused, during the process of peeling off the pad protection layer 600_3, the residue of the lead wiring remaining on the pad protection layer 600_3 and the wiring pad PAD_3 is removed together with the pad protection layer 600_3. Therefore, even if ultrasonic welding is performed again on the display panel 100_2, it is possible to prevent the efficiency of ultrasonic welding from being reduced due to the residue of the separated lead wiring.

[0173] Figure 20 It is a plan layout diagram of a printed circuit board according to another embodiment.

[0174] Refer to Figure 20 , in the printed circuit board 300_2 according to the present embodiment, the lead wiring LE_2 has a smaller area than the lead wiring LE according to an embodiment, which is different from an embodiment in this regard.

[0175] More specifically described, in the printed circuit board 300_2 according to the present embodiment, as Figure 20 shown, the lead wiring LE_2 is formed with an area that is substantially half the area of the lead wiring LE according to an embodiment.

[0176] In the case of this embodiment as well, by reducing the area of the lead wiring LE_2, when the lead wiring LE_2 is separated from the wiring pad region of the display panel and the display panel is reused, it is possible to reduce the damage to the wiring pad.

[0177] Figure 21 It is a plan view of a panel pad region according to another embodiment.

[0178] Referring to Figure 21 , the wiring pad PAD_4 according to the present embodiment is integrally formed, which is different from the wiring pad PAD according to an embodiment in this regard.

[0179] More specifically, the second pad pattern portion PT2_3 and the third pad pattern portion PT3_3 of the wiring pad PAD_4 according to the present embodiment can be physically connected to the first pad pattern portion PT1.

[0180] In addition, the pad protection layer 600_4 according to the present embodiment can be disposed between the adjacent first pad pattern portion PT1 and the second pad pattern portion PT2_3, and between the second pad pattern portion PT2_3 and the third pad pattern portion PT3_3. The pad protection layer 600_4 can separate the second pad pattern portion PT2_3 and the third pad pattern portion PT3_3 by placing them in the middle.

[0181] In the case of the present embodiment, by disposing the pad protection layer 600_4 between the plurality of separated pattern portions of the wiring pad PAD_4, when the display panel 100_3 is reused after separating the lead wiring LE from the panel pad region P_PA of the display panel 100_3, the area of the wiring pad PAD_4 that is substantially damaged in the pad damage region can be reduced.

[0182] Moreover, when the display panel 100_3 is reused, during the process of peeling off the pad protection layer 600_4, the residues of the lead wiring remaining on the pad protection layer 600_4 and the wiring pad PAD_4 are removed together with the pad protection layer 600_4. Therefore, even if ultrasonic welding is performed on the display panel 100_3 again, the efficiency of ultrasonic welding can be prevented from being reduced due to the residues of the separated lead wiring.

[0183] Figure 22 It is a plan view of a display device according to another embodiment. Figure 23 It is a cross-sectional view of a display device according to another embodiment.

[0184] Referring to Figure 22 and Figure 23 , the display panel 100_4 of the display device 2 according to the present embodiment may further include a bending region BA.

[0185] The display substrate of the display panel 100_4 can be made of an insulating material such as a polymer resin. Examples of such polymer materials include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The display substrate 101 can be a flexible substrate capable of bending, folding, rolling, etc. An example of the material constituting the flexible substrate is polyimide (PI), but it is not limited thereto.

[0186] The bending region BA can be arranged between the array of a plurality of pixels and the panel pad region P_PA_1. The bending region BA can be located in the non-display region NA. The display panel 100_4 can be bent in one direction with the bending line, which is the reference line arranged in the bending region BA, as the center. The bending line can be a straight line parallel to the lower (or upper) edge of the display panel 100_4. As Figure 23 shown, the bending region BA of the display panel 100_4 can be bent downward in the third direction DR3.

[0187] However, it is not limited thereto, and the display region DA and the panel pad region P_PA_1 can be connected to each other without the bending region BA. That is, the display panel 100_4 can be flat as a whole with the display region DA and the non-display region NA without the bending region BA.

[0188] In the panel pad region P_PA_1, a plurality of wiring pads PAD described in Figure 5 are arranged. A driving integrated circuit 900 can be attached to the plurality of wiring pads PAD.

[0189] In this embodiment, the driving integrated circuit 900 can be applicable to chip on plastic (COP) or chip on glass (COG). The driving integrated circuit 900 can include a plurality of protrusions connected to a plurality of wiring pads PAD. The protrusions can be formed of one or more of gold (Au), nickel (Ni), and tin (Sn).

[0190] In this embodiment, the protrusions of the driving integrated circuit 900 can be coupled to the respective wiring pads PAD in a manner of being directly connected without being separated by other layers or structures. The direct coupling of the protrusions of the driving integrated circuit 900 and the respective wiring pads PAD can be completed by ultrasonic welding.

[0191] As mentioned above, although the description has been centered around the embodiments of the present disclosure, this is merely illustrative and does not limit the present disclosure. Those with ordinary knowledge in the field to which the present disclosure pertains should know that various deformations and applications not exemplified above can be made without exceeding the essential features of the embodiments of the present disclosure. For example, each component specifically shown in the embodiments of the present disclosure can be deformed and implemented. Moreover, the differences related to such deformations and applications should be interpreted as being included within the scope of the present disclosure.

Claims

1. A display device, wherein, Comprising: A display substrate, including a display area and a pad area disposed around the display area; Signal wirings, disposed across the pad area and the display area on the display substrate; At least one wiring pad, disposed on the pad area of the display substrate, and including a pad pattern portion electrically connected to the signal wirings and a spaced pattern portion spaced apart from the pad pattern portion; And A printed circuit board, attached to the pad area of the display substrate, and including lead wirings connected to the wiring pads, The spaced pattern portion is insulated from the signal wirings, The spaced pattern portion overlaps the signal wirings in a plane, The display device further includes a pad protection layer, which is disposed in the spaced space between the pad pattern portion and the spaced pattern portion.

2. The display device according to claim 1, wherein, The pad protection layer contains an organic insulating material.

3. The display device according to claim 1, wherein, The spaced pattern portion is disposed spaced apart from the pad pattern portion along a first direction.

4. The display device according to claim 3, wherein, The first direction intersects the direction from the end of the pad area toward the display area, The width of the pad pattern portion in the first direction is larger than the width of the spaced pattern portion in the first direction.

5. The display device according to claim 3, wherein, The wiring pad further includes a frame pattern portion in a square shape, which surrounds the pad pattern portion and the spaced pattern portion in a plane.

6. The display device according to claim 5, wherein, The pad pattern portion, the spaced pattern portion, and the frame pattern portion are disposed separately from each other, The pad protection layer is integrally formed inside the frame pattern portion in a plane.

7. The display device according to claim 5, wherein, The frame pattern portion is physically connected to the pad pattern portion and the spaced pattern portion respectively.

8. A display panel, wherein, Comprising: A display substrate, including a display area and a pad area disposed around the display area; Signal wirings, disposed across the pad area and the display area on the display substrate; And At least one wiring pad, disposed on the pad area of the display substrate, and including a pad pattern portion electrically connected to the signal wirings and a spaced pattern portion spaced apart from the pad pattern portion, The spaced pattern portion is insulated from the signal wirings, The spaced pattern portion overlaps the signal wirings in a plane, The display panel further includes a pad protection layer, which is disposed in the spaced space between the pad pattern portion and the spaced pattern portion.

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