LED chip with improved external quantum efficiency and preparation method thereof

Abstract

The present invention provides an LED chip with improved external quantum efficiency. It includes a DBR layer, a substrate, a buffer layer, a first semiconductor layer, an active layer, a second semiconductor layer, a transparent conductive layer, an N-type electrode and a P-type electrode. Both the N-type electrode and the P-type electrode are aluminum-based reflective electrodes. The aluminum metal layer of the P-type electrode is directly in contact with the transparent conductive layer to improve the reflectivity of the interface between the reflective electrode and the semiconductor. The present invention also provides a method for preparing an LED chip with improved external quantum efficiency. It includes growing a complete LED structure epitaxial wafer on a substrate and etching to form a semiconductor structure with a stepped slope; then making a current blocking layer and a transparent conductive layer including an AZO layer; preparing a P-type electrode, an N-type electrode and a passivation layer, and then back-plating a DBR layer; and preparing the wafer into an LED chip device. The present invention adopts an aluminum-based reflective electrode, eliminates the insertion layer metal between the P-type electrode and the transparent conductive layer, improves the luminous efficiency of the LED chip, and improves the external quantum efficiency of the LED chip.

Description

Technical Field

[0001] The invention relates to the technical field of LED chip manufacturing, and in particular to an LED chip with improved external quantum efficiency and a preparation method thereof. Background Art

[0002] Since the breakthrough of p-gallium nitride (p-GaN) in 1992, GaN-based light-emitting diode (LED) technology has made rapid progress. The internal quantum efficiency of LED chips has been greatly improved to more than 80%, but the external quantum efficiency is still very low.

[0003] In order to improve the external quantum efficiency of LEDs, people have developed many process technologies, one of which is the use of reflective electrodes. The principle of reflective electrode technology is that the electrode metal is opaque in the visible light range, and the traditional LED chip has two electrodes installed on the same side, both on the light-emitting surface of the LED chip, so the electrode metal blocks the light emitted by the active area, affecting the light extraction, thereby affecting the external quantum efficiency of the LED. Therefore, in order to extract the light from the active area under the electrode as much as possible, people use reflective electrodes to improve the reflectivity of the interface between the electrode and the semiconductor, and reflect the light irradiated from the active area back, so that it is extracted after multiple reflections between the electrode and the back of the LED chip.

[0004] The most widely used reflective electrode is aluminum-based, but the adhesion between the aluminum metal and the transparent conductive layer indium tin oxide (ITO) is very poor, causing the electrode to fall off during the subsequent packaging wire bonding. Therefore, in order to improve the adhesion between the aluminum reflective electrode and ITO, a layer of insertion layer metal must be added between aluminum and ITO, generally a metal with good adhesion to semiconductors and ITO such as chromium, nickel, and titanium. Because of the presence of the insertion layer, the reflectivity of the reflective electrode will decrease. This creates a contradiction that both reflectivity and adhesion cannot be achieved at the same time. In practice, the reflectivity of the evaporated pure aluminum layer in the blue light band (455nm) is 80% to 85%, but because of the presence of the insertion layer, the reflectivity of the electrode in the actual application of LED chip electrodes is only 70% to 75%. Thinning the insertion layer can improve the reflectivity of the electrode, but the adhesion between the electrode and ITO drops sharply, resulting in a high risk of electrode falling off (electrode falling off is a fatal defect in the downstream packaging wire bonding).

[0005] In summary, there is an urgent need for an LED chip with improved external quantum efficiency and a preparation method thereof to solve the problems existing in the prior art. Summary of the invention

[0006] The present invention aims to provide an LED chip with improved external quantum efficiency and a preparation method thereof, so as to solve the problem of improving the reflectivity of a reflective electrode while ensuring the adhesion between the electrode and a transparent conductive layer.

[0007] To achieve the above object, the present invention provides an LED chip with improved external quantum efficiency, comprising:

[0008] DBR layer;

[0009] a substrate located on the DBR layer;

[0010] a buffer layer located on the substrate;

[0011] a first semiconductor layer located on the buffer layer;

[0012] an active layer located on the first semiconductor layer;

[0013] a second semiconductor layer located on the active layer;

[0014] a transparent conductive layer located on the second semiconductor layer;

[0015] It also includes an N-type electrode that contacts and is electrically conductive with the first semiconductor layer, and a P-type electrode that contacts and is electrically conductive with the second semiconductor layer, wherein both the N-type electrode and the P-type electrode are aluminum-based reflective electrodes, and the aluminum metal layer of the P-type electrode is directly in contact with the transparent conductive layer to improve the reflectivity of the interface between the reflective electrode and the semiconductor.

[0016] Preferably, the transparent conductive layer includes an AZO layer for contacting the aluminum metal layer in the P-type electrode, so as to improve the adhesion between the P-type electrode and the transparent conductive layer.

[0017] Preferably, the AZO layer has uniform grains, and the grain size is 30-50 nm, so as to improve the adhesion between the P-type electrode and the transparent conductive layer.

[0018] Preferably, a current blocking layer is provided between the second semiconductor layer and the transparent conductive layer to improve the luminous efficiency of the LED chip.

[0019] Preferably, a step slope is provided between the first semiconductor layer and the second semiconductor layer in the vertical direction; the step slope includes a plane and a slope; the slope extends from the second semiconductor layer to the first semiconductor layer and intersects with the plane, and the plane is horizontally arranged on the first semiconductor layer for installing an N-type electrode.

[0020] Preferably, an LED chip with improved external quantum efficiency further comprises a passivation layer covering the top of the LED chip.

[0021] The present invention also provides a method for preparing an LED chip with improved external quantum efficiency, comprising the following steps:

[0022] Step 1: growing a complete LED structure epitaxial wafer on a substrate, wherein the LED structure epitaxial wafer comprises a buffer layer, a first semiconductor layer, an active layer and a second semiconductor layer;

[0023] Step 2: etching a portion of the first semiconductor layer, the active layer and the second semiconductor layer from the LED structure epitaxial wafer to form a semiconductor structure with a stepped slope;

[0024] Step 3: forming a current blocking layer on the upper surface of the second semiconductor layer;

[0025] Step 4: depositing a transparent conductive layer on the basis of the device obtained in step 3, the transparent conductive layer including an AZO layer, and annealing the layer; then removing the transparent conductive layer on the step slope and at the center of the conductive portion between the P-type electrode and the second semiconductor layer;

[0026] Step 5: Prepare the P-type electrode, N-type electrode and passivation layer of the LED chip, and then back-plate the DBR layer; finally, prepare the wafer into an LED chip device.

[0027] Preferably, in step 4, the AZO layer is prepared by electron beam evaporation or metal organic chemical vapor deposition.

[0028] Preferably, when the AZO layer is prepared by electron beam evaporation in step 4, zinc oxide is firstly evaporated by electron beam, and then the aluminum layer is evaporated by electron beam, and then aluminum-doped zinc oxide is obtained by annealing; wherein the temperature of electron beam evaporation of zinc oxide is 250-300°C, and the coating rate is The target material is fine-grained ZnO particles or ingot-shaped ZnO, the plating pot revolution speed is 30-60r / min, and the plating pot rotation speed is 60-100r / min.

[0029] Preferably, when the AZO layer is prepared by metal organic chemical vapor deposition in step 4, the atomic doping ratio of aluminum is 5E18-1E20, and then the layer is transferred to the target wafer by thin film transfer.

[0030] The application of the technical solution of the present invention has the following beneficial effects:

[0031] (1) In the present invention, by adopting an aluminum-based reflective electrode, the intercalated metal layer between the P-type electrode and the transparent conductive layer is eliminated, so that the aluminum metal layer of the P-type electrode directly reflects the light emitted by the active layer, and the reflectivity can reach 85%. The light is taken out after multiple reflections between the aluminum metal layer and the DBR layer, thereby improving the luminous efficiency of the LED chip, thereby improving the external quantum efficiency of the LED chip.

[0032] (2) In the present invention, by providing an AZO transparent conductive layer, while ensuring that the adhesion between the transparent conductive layer and the aluminum metal layer of the P-type electrode meets the standard, there is no need to add a metal insertion layer, thereby ensuring the reflectivity of the aluminum metal layer and solving the contradiction that both reflectivity and adhesion cannot be achieved at the same time.

[0033] (3) In the present invention, a current blocking layer is provided between the second semiconductor layer and the transparent conductive layer to improve the luminous efficiency of the LED chip; the ITO layer in the transparent conductive layer is in direct contact with the second semiconductor layer (P-type nitride semiconductor layer), thereby ensuring low ohmic contact between the transparent conductive layer and the P-type nitride semiconductor layer, thereby ensuring that the device has a lower voltage under a certain driving current.

[0034] (4) In the present invention, a step slope is provided between the first semiconductor layer and the second semiconductor layer in the vertical direction for mounting an N-type electrode so that the N-type electrode is in direct contact and conduction with the N-type nitride semiconductor layer.

[0035] (5) In the present invention, conventional processes are used to manufacture LED structure epitaxial wafers and step slopes, and the process operation is simple and easy to implement.

[0036] (6) In the present invention, when preparing the AZO layer, zinc oxide is first evaporated by electron beam, and then the aluminum layer is evaporated by electron beam, and then annealing is performed to obtain aluminum-doped zinc oxide; wherein the temperature of electron beam evaporation of zinc oxide is 250-300°C, and the coating rate is The film thickness is 20-200nm, the target material can be fine-grained ZnO particles or ingot ZnO, the plating pot revolution rate is 30-60r / min, the plating pot rotation rate is 60-100r / min, and the film layer plated under the above conditions is observed under a scanning electron microscope. The particles are uniform and the grain size is between 30-50nm, so that the adhesion test thrust between the electrode and the transparent conductive layer meets the packaging welding wire standard.

[0037] In addition to the above-described objects, features and advantages, the present invention has other objects, features and advantages. The present invention will be further described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0039] Figure 1 is a schematic structural diagram of an LED chip for improving external quantum efficiency in Example 1;

[0040] Figure 2 is a diagram of the semiconductor structure after etching in Example 1;

[0041] Figure 3 is a top view of an LED chip with improved external quantum efficiency in Example 1;

[0042] Figure 4 is a schematic diagram of the cross-sectional structure of the P-type electrode lead of the LED chip device in Example 1;

[0043] Figure 5 is a flow chart of the preparation of the LED chip in Example 1;

[0044] Figure 6 is a scanning electron microscope image of the AZO layer in Example 1;

[0045] Figure 7 is a scanning electron microscope image 1 of the AZO layer in Comparative Example 1;

[0046] Figure 8 is the second scanning electron microscope image of the AZO layer in Comparative Example 1;

[0047] Fig. 9 is a scanning electron microscope image of the AZO layer in Comparative Example 2;

[0048] Fig.10 is the IV curve of the LED device in Example 1 and the comparative device;

[0049] Fig.11 IL curves of the LED device in Example 1 and the comparative device;

[0050] Among them, 1. DBR layer, 2. substrate, 3. buffer layer, 4. first semiconductor layer, 5. active layer, 6. second semiconductor layer, 7. transparent conductive layer, 7.1. AZO layer, 7.2. ITO layer, 8. N-type electrode, 8.1. N-type electrode pad, 8.2. N-type electrode lead, 9. P-type electrode, 9.1. P-type electrode pad, 9.2. P-type electrode lead, 10. current blocking layer, 11. step slope, 11.1. plane, 11.2. slope, 12. passivation layer. DETAILED DESCRIPTION

[0051] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0052] Embodiment 1:

[0053] See also Figures 1 to 11 , an LED chip with improved external quantum efficiency and a preparation method thereof, this embodiment is applied to improve the external quantum efficiency of the LED chip.

[0054] An LED chip with improved external quantum efficiency, see Figure 1 , from bottom to top include:

[0055] DBR layer 1, in this embodiment, the DBR material is an alternating structure of silicon dioxide (SiO2) and titanium dioxide (TiO2), the refractive index of the two materials are between 1.45 and 1.52 and 2.45 and 2.55 respectively, the thickness of each layer is determined by optical software simulation, and a distributed Bragg reflector (DBR) is formed, and its reflectivity is greater than 95% in the visible light wavelength range (380 to 800 nm);

[0056] A substrate 2 located on the DBR layer 1. In this embodiment, the substrate 2 is a sapphire substrate (PSS substrate);

[0057] A buffer layer 3 located on the substrate 2;

[0058] a first semiconductor layer 4 located on the buffer layer 3; in this embodiment, the first semiconductor layer 4 is an N-type nitride semiconductor layer;

[0059] an active layer 5 located on the first semiconductor layer 4;

[0060] A second semiconductor layer 6 located on the active layer 5. In this embodiment, the second semiconductor layer 6 is a P-type nitride semiconductor layer;

[0061] a transparent conductive layer 7 located on the second semiconductor layer 6;

[0062] It also includes an N-type electrode 8 that contacts with the first semiconductor layer 4 and is electrically conductive, and a P-type electrode 9 that contacts with the second semiconductor layer 6 and is electrically conductive, wherein the N-type electrode 8 and the P-type electrode 9 are both aluminum-based reflective electrodes, and the aluminum metal layer of the P-type electrode 9 directly contacts the upper surface of the transparent conductive layer 7, thereby eliminating the insertion layer metal between the P-type electrode 9 and the transparent conductive layer 7; the aluminum metal layer of the N-type electrode 8 contacts the first semiconductor layer 4, and reflects the light irradiated from the active layer 5 back through the aluminum metal layer, so that the light is taken out after multiple reflections between the aluminum metal layer of the electrode and the DBR layer 1 to improve the reflectivity of the interface between the reflective electrode and the semiconductor, thereby improving the external quantum efficiency of the LED device.

[0063] The transparent conductive layer 7 includes an AZO layer 7.1 (aluminum-doped zinc oxide) for contacting the aluminum metal layer of the P-type electrode 9 to improve the adhesion between the P-type electrode 9 and the transparent conductive layer 7 to prevent the electrode from falling off when packaging the electrode; in this embodiment, see Figure 1The transparent conductive layer 7 also includes an ITO layer 7.2. The ITO layer 7.2 is located between the AZO layer 7.1 and the second semiconductor layer 6. The ITO layer 7.2 is in direct contact with the upper surface of the second semiconductor layer 6 (P-type nitride semiconductor layer), thereby ensuring low ohmic contact between the transparent conductive layer 7 and the P-type nitride semiconductor layer, thereby ensuring that the device has a lower voltage under a certain driving current, and at the same time can effectively increase the light-emitting area.

[0064] See also Figure 6 The grain size of the AZO layer 7.1 is 30nm-50nm, which is used to improve the adhesion between the P-type electrode 9 and the transparent conductive layer 7. The adhesion effect is mainly characterized by the thrust after wire bonding at the LED chip manufacturing end. A wire with a wire diameter of 0.9mil and a composition of 96% Ag4% Au is used for wire bonding. The diameter of the solder ball after wire bonding is 55-62um, and the height of the solder ball is 10-16um (the solder ball is located on the pad). A thrust machine is used to push the solder ball and the thrust is recorded.

[0065] Ten LED chip samples with uniform grains of AZO layer 7.1 and a grain size of 30nm to 50nm were selected for thrust test, and the thrust results were as follows: 42, 38, 44, 46, 40, 43, 43, 39, 40, 42, in g, which all meet the inspection standard of electrode package wire thrust greater than 30g.

[0066] Ten LED chip samples with uneven grains of AZO layer 7.1 or blocky shape were selected for thrust test. The adhesion thrust results between AZO layer 7.1 and the aluminum metal layer of the aluminum-based reflective electrode were poor. The experimental results are as follows: 22, 26, 24, 28, 33, 25, 31, 30, 26, 24, the unit is g, and the qualified rate is only 30%.

[0067] In the experiment, if the deposited AZO layer 7.1 grains appear in clusters, the electrode adhesion is worse, and the electrode will fall off when pushing the solder ball, that is, the electrode pad metal and the semiconductor are completely detached. 10 LED chip samples in this state were selected for the same thrust verification experiment, and the experimental results were: 12, 15, 10, 8, 22, 18, 15, 23, 16, 20, in g. The experiment verified that when the grain size of the AZO layer is 30-50nm, the adhesion between the AZO layer 7.1 and the aluminum metal layer of the P-type electrode 9 is good, which meets the packaging wire bonding standard.

[0068] See also Figure 1 A current blocking layer 10 is provided between the second semiconductor layer 6 and the transparent conductive layer 7 to improve the luminous efficiency of the LED chip.

[0069] See also Figure 2A step slope 11 is provided between the first semiconductor layer 4 and the second semiconductor layer 6 along the vertical direction; the step slope 11 includes a plane 11.1 and a slope 11.2; the slope 11.2 extends from the second semiconductor layer 6 to the first semiconductor layer 4 and intersects with the plane 11.1, and the plane 11.1 is horizontally arranged on the first semiconductor layer 4 for installing the N-type electrode 8.

[0070] The top of the LED chip is covered with a passivation layer 12. Both the current blocking layer 10 and the passivation layer 12 are made of insulating materials, and the insulating material is one or more of silicon dioxide (SiO2), silicon oxynitride (SiON) and silicon nitride (SiN).

[0071] See also Figure 3 The N-type electrode 8 includes an N-type electrode pad 8.1 and an N-type electrode lead 8.2, both of which are located on the first semiconductor layer 4, and the N-type electrode 8 has good adhesion to the N-type nitride semiconductor layer; the P-type electrode 9 includes a P-type electrode pad 9.1 and a P-type electrode lead 9.2, and the bottom end of the P-type electrode pad 9.1 passes through the transparent conductive layer 7 and the through hole on the current blocking layer 10 to communicate with the second semiconductor layer 6; see Figure 4 A current blocking layer 10 and a transparent conductive layer 7 are provided between the P-type electrode lead 9.2 and the second semiconductor layer 6 from bottom to top. The luminous active layer 5 is located below the second semiconductor layer 6. The metal pads and motor leads of the electrode are opaque in the visible light wavelength range (i.e., the electrode pads and electrode leads are light-shielded). Therefore, a current blocking layer 10 is provided below the P-type electrode lead 9.2 to prevent current from directly passing through the active layer 5 below the P-type electrode lead 9.2 (because even if current directly passes through the active layer 5 below the P-type electrode lead 9.2, most of the light emitted by the active layer is blocked by the P-type electrode lead 9.2 and cannot be emitted to the outside of the LED chip). This indirectly increases the current density of other light-emitting areas outside the P-type electrode lead 9.2, thereby improving the brightness.

[0072] A method for preparing an LED chip with improved external quantum efficiency, the preparation process is as follows Figure 5 As shown, the specific steps are as follows:

[0073] Step 1: growing a complete LED structure epitaxial wafer on a substrate 2 according to a conventional metal organic chemical vapor deposition (MOCVD) process, including a buffer layer 3, a first semiconductor layer 4, an active layer 5 and a second semiconductor layer 6;

[0074] Step 2: Clean the LED structure epitaxial wafer obtained in step 1, use a photoresist as a masking layer, and use ICP (inductively coupled plasma etching) to etch away part of the first semiconductor layer 4, the active layer 5, and the second semiconductor layer 6 to form a semiconductor structure with a step slope 11, wherein the etching gas is BCl3 (boron trichloride), Cl2 (chlorine) or Ar (argon);

[0075] Step 3: A current blocking layer 10 is formed on the upper surface of the second semiconductor layer 6 by plasma enhanced chemical vapor deposition (PECVD). In this embodiment, the insulating material used in the current blocking layer 10 is SiO2, the deposition power is 30-500W, the pressure is 500-1500mTorr, the temperature is 150-300°C, the N2O is 50-1500sccm, the N2 is 50-1500sccm, and the 5% SiH4 / N2 is 50-1500sccm;

[0076] Step 4: Depositing a transparent conductive layer 7 on the basis of the device obtained in step 3. In this embodiment, the transparent conductive layer 7 includes an ITO layer 7.2 and an AZO layer 7.1 arranged from bottom to top; the ITO layer 7.2 is prepared by magnetron sputtering, the thickness of the ITO layer 7.2 is 20 to 200 nm, the sputtering temperature is room temperature, and the sputtering power is 20 to 300 W; the preparation of the AZO layer 7.1 can be carried out by electron beam evaporation or metal organic chemical vapor deposition;

[0077] When the AZO layer 7.1 is prepared by electron beam evaporation, zinc oxide is firstly evaporated by electron beam, and then the aluminum layer is evaporated by electron beam, and then the aluminum-doped zinc oxide is obtained by annealing; wherein, the temperature of the electron beam evaporation of zinc oxide is 250-300°C, and the coating rate is The film thickness is 20-200nm. The target material can be fine-grained ZnO particles or ingot ZnO. The plating pot revolution rate is 30-60r / min and the plating pot rotation rate is 60-100r / min. Under normal temperature conditions, the electron beam evaporates metal aluminum and the coating thickness is The obtained semi-finished product is annealed in a rapid annealing furnace (RTA) at an annealing temperature of 400-800°C, an annealing time of 1-20 min, and a heating rate of 10-50°C / s. In this embodiment, the selected electron beam evaporation zinc oxide deposition temperature is 275°C, the plating pot rotation speed is 60r / min, and the plating pot rotation speed is 30r / min. Under this combination of process parameters, the obtained AZO layer 7.1 has uniform grains and a grain size between 30nm and 50nm. The electrode thrust test meets the requirements, and the brightness of the LED chip is improved.

[0078] When the AZO layer 7.1 is prepared by metal organic chemical vapor deposition, the atomic doping ratio of aluminum is 5E18 to 1E20, and then it is transferred to the target wafer by thin film transfer;

[0079] The semi-finished product is subjected to photolithography, wet etching, degumming and cleaning, and spin drying to remove the transparent conductive layer 7 and the metal aluminum layer on the step slope 11, and at the same time remove the AZO layer 7.1, the ITO layer 7.2 and the current blocking layer 10 at the center of the P-type electrode pad 9.1 of the P-type electrode 9, so that the conductive end of the P-type electrode pad 9.1 extending downward is in contact with the second semiconductor layer 6 for conduction;

[0080] Step 5: Prepare the P-type electrode 9, N-type electrode 8 and passivation layer 12 of the LED chip through conventional processes, and then back-plate the DBR layer 1; finally, prepare the wafer into an LED chip device:

[0081] The semi-finished product obtained after step 4 is subjected to negative photolithography, electrode evaporation, stripping, degumming cleaning, spin drying and other steps to prepare a P-type electrode 9 and an N-type electrode 8, wherein the first layer of metal of the electrode structure is pure aluminum (i.e., the reflective surface metal of the electrode), the electrode metal thickness is 0.8-4um, and the electrode metal includes a metal sandwich structure such as Al, Ti, Pt, Au, etc., the thickness of the Al layer is 20-300nm, the thickness of the Ti layer is 10-200nm, the thickness of the Pt layer is 10-200nm, and the thickness of the Au layer is 400-3000nm;

[0082] The insulating passivation layer 12 is deposited by PECVD, wherein the material of the passivation layer 12 is SiO2, the thickness is 500-3000nm, the deposition power is 30-500W, the pressure is 500-1500mTorr, the temperature is 150-300°C, the N2O is 50-1500sccm, the N2 is 50-1500sccm, and the 5% SiH4 / N2 is 50-1500sccm; then the passivation layer 12 on the P-type electrode 9 and the N-type electrode 8 is removed by positive photolithography, wet etching, degumming and cleaning, etc., wherein the wet etching adopts a BOE solution of HF:NH3F=1:9;

[0083] Finally, the substrate 2 of the semi-finished product is thinned by grinding, then polished with a polishing liquid, the DBR layer 1 is plated on the back, and then cut by an invisible cutting method to split the chip to obtain a discrete LED chip device.

[0084] The LED chip prepared in this embodiment has a double-layer transparent conductive layer, the electrode reflectivity is as high as 85%, the electrode adhesion is qualified, and the adhesion test thrust is more than 38g after the 9mil96% Ag wire is used for wire bonding (pushing the solder ball), which meets the inspection standard that the package wire bonding thrust is greater than 30g. Fig.10As shown in FIG. 1 , compared with the comparative device (the reflective electrode of the comparative device is provided with an insertion layer metal for adhering to the transparent conductive layer), the brightness of the embodiment is increased by 3.76% at 60 mA, while the voltage is only 0.019 V higher, and at a large current, the voltage is more advantageous and lower than the comparative device; Fig.11 As shown, the light efficiency of the LED chip of the present application is higher than that of the comparative device at the same current.

[0085] Embodiment 2:

[0086] The difference between Example 2 and Example 1 is that the selected electron beam evaporation zinc oxide deposition temperature is 250°C, and the rest is the same as Example 1. Under this combination of process parameters, the obtained AZO layer 7.1 has uniform grains and a grain size between 30nm and 50nm. The thrust test meets the requirements and the brightness of the LED chip is improved.

[0087] Embodiment 3:

[0088] The difference between Example 3 and Example 1 is that the selected electron beam evaporation zinc oxide deposition temperature is 300°C, the plating pot rotation speed is 60r / min, and the others are the same as Example 1. Under this combination of process parameters, the obtained AZO layer 7.1 has uniform grains, and the grain size is between 30nm and 50nm. After the electrode is plated, the pad shows slight black spots, which affects the appearance but does not affect the welding wire. The thrust test meets the requirements and the brightness of the LED chip is improved.

[0089] Comparative Example 1:

[0090] The difference between Comparative Example 1 and Example 1 is that the selected electron beam evaporation zinc oxide deposition temperature is 220°C, the plating pot rotation speed is 40r / min, and the plating pot rotation speed is 20r / min. Under this combination of process parameters, the obtained AZO layer 7.1 has uneven grains and the grains are clustered. The thrust test does not meet the requirements. The brightness of the LED chip is slightly improved, but the electrode is prone to falling off.

[0091] Comparative Example 2:

[0092] The difference between Comparative Example 2 and Example 1 is that the selected electron beam evaporation zinc oxide deposition temperature is 330°C, the plating pot rotation speed is 40r / min, and the plating pot rotation speed is 60r / min. Under this combination of process parameters, the obtained AZO layer 7.1 grains are uneven, local unidirectional growth grains appear, the thrust test does not meet the requirements, and the pads show serious black spots after the electrodes are plated, which affects the appearance and the packaging welding wires. The brightness improvement effect is not obvious, and the LED chip voltage is high.

[0093] The test results of Examples 1 to 3 and Comparative Examples 1 to 2 using the method of the present application are compared, as shown in Table 1:

[0094] Table 1:

[0095]

[0096]

[0097] According to the experimental verification in Table 1, when the AZO layer 7.1 is prepared by the method of the present application (Example 1 to Example 3), the film layer plated under the above process conditions is observed under a scanning electron microscope, and the particles are uniform and the grain size is between 30-50nm. Figure 6 As shown, at this time, the adhesion effect between the contact surface of the AZO layer 7.1 and the aluminum metal layer of the P-type electrode pad 9.1 is good;

[0098] If the deposition temperature is too low (below 250°C) and the plating pot rotation speed is too slow, the uniformity of the surface morphology of the deposited film layer will be very poor. Figure 7 As shown, the adhesion between the AZO layer 7.1 and the aluminum metal layer of the P-type electrode 9 cannot be guaranteed at this time; if the rotation rate of the plating pot is lower than 60r / min, and the deposition temperature is lower than 250°C, the deposited film layer may even appear in clusters under the SEM observation, as shown in FIG. Figure 8 As shown, the adhesion between the AZO layer 7.1 and the aluminum metal layer of the P-type electrode 9 cannot be guaranteed at this time.

[0099] If the deposition temperature is too high (over 300°C), the evaporator will work in the extreme temperature zone, which is not conducive to process energy saving and protecting the life of the machine. More importantly, many black spots will appear on the surface of the film after deposition. Under the scanning electron microscope, it can be seen that the grains grow in a single direction locally, resulting in crystal columns. Fig. 9 shown.

[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An LED chip with improved external quantum efficiency, characterized in that: The LED chip for improving external quantum efficiency comprises: DBR layer (1); A substrate (2) located on the DBR layer (1); A buffer layer (3) located on the substrate (2); A first semiconductor layer (4) located on the buffer layer (3); An active layer (5) located on the first semiconductor layer (4); A second semiconductor layer (6) located on the active layer (5); a transparent conductive layer (7) located on the second semiconductor layer (6); It also includes an N-type electrode (8) in contact with and electrically connected to the first semiconductor layer (4) and a P-type electrode (9) in contact with and electrically connected to the second semiconductor layer (6), wherein the N-type electrode (8) and the P-type electrode (9) are both aluminum-based reflective electrodes, and the aluminum metal layer of the P-type electrode (9) is directly in contact with the transparent conductive layer (7) to improve the reflectivity of the interface between the reflective electrode and the semiconductor; The transparent conductive layer (7) comprises an AZO layer (7.1) for contacting the aluminum metal layer in the P-type electrode (9) so as to improve the adhesion between the P-type electrode (9) and the transparent conductive layer (7); The AZO layer (7.1) has uniform grains with a grain size of 30-50 nm, so as to improve the adhesion between the P-type electrode (9) and the transparent conductive layer (7); A current blocking layer (10) is provided between the second semiconductor layer (6) and the transparent conductive layer (7) to improve the luminous efficiency of the LED chip.

2. The LED chip for improving external quantum efficiency according to claim 1, characterized in that: A step slope (11) is provided between the first semiconductor layer (4) and the second semiconductor layer (6) in a vertical direction; the step slope (11) comprises a plane (11.1) and a slope (11.2); the slope (11.2) extends from the second semiconductor layer (6) to the first semiconductor layer (4) and intersects with the plane (11.1); the plane (11.1) is horizontally provided on the first semiconductor layer (4) for mounting an N-type electrode (8).

3. The LED chip with improved external quantum efficiency according to claim 1, characterized in that: Also included is a passivation layer (12) covering the top of the LED chip.

4. A method for preparing an LED chip with improved external quantum efficiency, characterized in that: The following steps are involved: Step 1: growing a complete LED structure epitaxial wafer on a substrate (2), wherein the LED structure epitaxial wafer comprises a buffer layer (3), a first semiconductor layer (4), an active layer (5) and a second semiconductor layer (6); Step 2: etching away a portion of the first semiconductor layer (4), the active layer (5) and the second semiconductor layer (6) from the LED structure epitaxial wafer to form a semiconductor structure having a stepped slope (11); Step 3: forming a current blocking layer (10) on the upper surface of the second semiconductor layer (6); Step 4: Depositing a transparent conductive layer (7) on the basis of the device obtained in step 3, wherein the transparent conductive layer (7) comprises an AZO layer (7.1), wherein the AZO layer ( 7.1) has uniform grains with a grain size of 30-50 nm, which is used to improve the adhesion between the P-type electrode (9) and the transparent conductive layer (7), and annealing is performed; then the transparent conductive layer (7) on the step slope (11) and the center of the conductive portion between the P-type electrode (9) and the second semiconductor layer (6) is removed; Step 5: Prepare the P-type electrode (9), N-type electrode (8) and passivation layer (12) of the LED chip, and then back-plate the DBR layer (1); finally, prepare the wafer into an LED chip device.

5. The method for preparing an LED chip with improved external quantum efficiency according to claim 4, characterized in that: In the step 4, the AZO layer (7.1) is prepared by electron beam evaporation or metal organic chemical vapor deposition.

6. The method for preparing an LED chip with improved external quantum efficiency according to claim 5, characterized in that: When the AZO layer (7.1) is prepared by electron beam evaporation in step 4, zinc oxide is first evaporated by electron beam, and then the aluminum layer is evaporated by electron beam, and then aluminum-doped zinc oxide is obtained by annealing; wherein the temperature of electron beam evaporation of zinc oxide is 250-300°C, the coating rate is 0.5-3Å / s, the target material is fine-grained ZnO particles or ingot ZnO, the plating pot revolution rate is 30-60r / min, and the plating pot rotation rate is 60-100r / min.

7. The method for preparing an LED chip with improved external quantum efficiency according to claim 5, characterized in that: When the AZO layer (7.1) is prepared by metal organic chemical vapor deposition in step 4, the atomic doping ratio of aluminum is 5E18-1E20, and then it is transferred to the target wafer by thin film transfer.

Images