A circuit and method for realizing low temperature drift and low power consumption of on-chip clock

Abstract

The present invention relates to a circuit for realizing low temperature drift and low power consumption of an on-chip clock, characterized in that it comprises: a charge-discharge control circuit module, a comparator A1, a hysteresis comparator A2, an output control circuit module and a clock shutdown control circuit module; the charge-discharge control circuit module is respectively connected to the negative input terminal of the comparator A1, the clock shutdown control circuit module and the positive input terminal of the hysteresis comparator A2; the output control circuit module is respectively connected to the positive input terminal of the comparator A1, the clock shutdown control circuit module and the output terminal of the hysteresis comparator A2; the output terminal of the comparator A1 is respectively connected to the negative input terminal of the hysteresis comparator A2 and a capacitor C; the comparator A1 and the hysteresis comparator A2 are respectively connected to a first tail current source and a second tail current source. The output period of the present invention is not affected by the power supply voltage and temperature, thereby realizing high precision and low temperature drift of the oscillation signal; the introduced clock shutdown circuit can be shut down according to system requirements, effectively reducing power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of on-chip clocks of integrated circuits, and in particular relates to a circuit and a method for realizing low temperature drift and low power consumption of an on-chip clock. Background Art

[0002] With the development of semiconductor technology and electronic technology, digital-analog hybrid electronic systems are becoming more and more integrated, low-power and highly stable. As an important part of electronic systems, the performance of clock circuits directly affects the performance of the system. Therefore, it is of great practical significance to achieve low power consumption, low temperature drift, high precision and other performance of clock circuits.

[0003] The existing oscillator circuits are mainly ring oscillator circuits and relaxation oscillators based on comparator for benchmark comparison. The ring oscillator is composed of an odd number of inverters connected end to end. In order to reduce the frequency, an RC circuit is added; the period of this implementation method mainly depends on the size of RC. When the frequency is small, the area becomes larger, which is not conducive to integration. At the same time, the feedback amount of the loop is single and is easily affected by power supply noise. In a wide voltage range, the frequency offset is large. The relaxation oscillator based on comparator for benchmark comparison has a stable comparison amount and a stable output clock waveform, but the bandgap reference voltage source contains transistors, so the circuit scale is large. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a circuit for realizing low temperature drift and low power consumption of an on-chip clock, wherein the output period is not affected by power supply voltage and temperature, and high precision and low temperature drift of an oscillation signal are realized.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A circuit for realizing low temperature drift and low power consumption of an on-chip clock comprises: a charge-discharge control circuit module, a comparator A1, a hysteresis comparator A2, an output control circuit module and a clock shutdown control circuit module; the charge-discharge control circuit module is respectively connected to the negative input end of the comparator A1, the clock shutdown control circuit module and the positive input end of the hysteresis comparator A2; the output control circuit module is respectively connected to the positive input end of the comparator A1, the clock shutdown control circuit module and the output end of the hysteresis comparator A2; the output end of the comparator A1 is respectively connected to the negative input end of the hysteresis comparator A2 and a capacitor C; the comparator A1 and the hysteresis comparator A2 are respectively connected to a first tail current source and a second tail current source.

[0007] Furthermore, the charge and discharge control circuit includes a first resistor R1, a first capacitor C1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and an NMOS transistor NMb; one end of the first resistor R1 is connected to a power supply, and the other end is connected to the first capacitor C1; the other end of the first capacitor C1 is grounded; the common end of the first resistor R1 and the first capacitor C is recorded as a node V R The gate of the first NMOS tube NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to V R The source is connected to the drain of the second NMOS tube NM2; the gate of the second NMOS tube NM2 is connected to the gate of the NMOS tube NMb, and the source is grounded; the gate of the third NMOS tube NM3 is connected to the gate of the second NMOS tube NM2, and the drain is connected to V R , the source is grounded; the drain current of the NMOS tube NMb is connected to I b .

[0008] Furthermore, the output control circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first inverter INV1 and a second inverter INV2; the gate of the first PMOS transistor PM1 is connected to the negative output terminal V of the hysteresis comparator A2. ON , the source is connected to the power supply, and the drain is connected to the drain of the fourth NMOS tube NM4; the gate of the fourth NMOS tube NM4 is connected to the clock shutdown control signal PD, and the source is grounded; the drain of the fifth NMOS tube NM5 is connected to the drain of NM4, the gate and the drain are connected, and the source is grounded; the gate of the sixth NMOS tube NM6 is connected to the gate of NM5, the source is grounded, and the drain is connected to the drain of the second PMOS tube PM2; the gate of the second PMOS tube PM2 is connected to the positive output terminal V of the hysteresis comparator A2 OP , the source is connected to the power supply, and the drain is connected to the input terminal V of the first inverter INV1 O1； The output terminal V of the first inverter INV1 O2 The input terminal of the second inverter INV2 is connected to the output terminal of INV2 to output the clock signal CLK.

[0009] Further, the clock shutdown control circuit includes a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, and a reference current source Ibias; the clock shutdown control signal PD of the third inverter INV3 is output and connected to the gate of the seventh NMOS tube NM7; the drain of the seventh NMOS tube NM7 is connected to Ibias, and the source is connected to the drain of the eighth NMOS tube NM8; the source of the eighth NMOS tube NM8 is grounded, and the gate is connected to the clock shutdown control signal PD; the gate of the ninth NMOS tube NM9 is connected to the drain of the eighth NMOS tube NM8, and the drain is connected to Ibias. bias The gate of the tenth NMOS tube NM10 is connected to the drain of NM4, and the drain is connected to I b , the source is grounded.

[0010] Furthermore, in the charge and discharge control circuit, the resistor R1 is composed of two resistors with positive and negative temperature coefficients connected in series, and the proportional coefficient is based on To determine, is the temperature coefficient.

[0011] Furthermore, the capacitor C is a poly capacitor with a low temperature coefficient.

[0012] A control method for a circuit that realizes low temperature drift and low power consumption of an on-chip clock comprises the following steps:

[0013] Step S1: When the system power is turned on, the node voltage V C Less than the node voltage V R , the hysteresis comparator A2 outputs a low level in the positive direction, PM1 is turned off, PM2 is turned on, and the node V O1 is high level, V O2 is low level, comparator A1 outputs high level, charging capacitor C, and the charging current is the tail current source nI of A1. b , while the low level signal V O2 Turn off NM2, the branch current I1 = 0, the voltage drop on the resistor R1 decreases, and the node voltage V R Rise to ;

[0014] Step S2: Capacitor C continues to charge. When the voltage V C Slightly larger than V R1 When the hysteresis comparator A2 outputs V OP Flipping from low level to high level, PM1 is turned on, PM2 is turned off, and node V O1 is low level, V O2 is high level, comparator A1 outputs low level, capacitor C discharges, and the charging current is the tail current source nIb of A1. At the same time, the high level signal VO2 When NM2 is turned on, branch current I1 passes through, the voltage drop on resistor R1 increases, and the node voltage VR drops to ;

[0015] Step S3: The capacitor C continues to discharge. When the voltage V C Slightly smaller than V R2 When the hysteresis comparator A2 outputs V OP Flip from high level to low level;

[0016] Step S4: Repeat steps S2-S3 cyclically to form a square wave oscillation output CLK.

[0017] Furthermore, the circuit is also provided with a shutdown control signal PD. When PD is at a high level, NM4 is turned on, the gate voltages of NM5 and NM6 are at a low level, NM5 and NM6 are turned off, and no current flows through the output control branch.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention introduces a charge and discharge control circuit, which uses a reference current to change the charge and discharge threshold voltage. The output cycle is not affected by the power supply voltage and temperature, thereby achieving high precision and low temperature drift of the oscillation signal.

[0020] 2. The present invention introduces a shutdown control circuit, that is, the system control signal PD controls the clock generation circuit to shut down. When the system is finished working, the clock generation circuit is shut down, thereby reducing the static power consumption of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the principle of the on-chip clock generation circuit of the present invention;

[0022] Figure 2 The figure is a schematic diagram of the principle of a microprocessor power supply monitoring circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] This embodiment takes the stability of the portable microprocessor system as the improvement object of this embodiment, and its preferred device is a power supply monitoring system. Figure 2The power supply monitoring circuit includes: a voltage divider circuit, a reference voltage source, a comparator, a clock generation circuit and a delay module; wherein the voltage divider circuit is used to generate a reset threshold voltage that is proportional to the input voltage; the reference voltage source is used to generate a reference voltage that is independent of the power supply voltage and temperature; the comparator is used to compare the voltage after voltage division with the reference voltage, and when the threshold voltage is reached, it outputs a high level, which is inverted and used together with the on-chip reset signal to control the enable end of the delay module, thereby generating a reset signal with a certain delay; the clock generation circuit is used to generate a clock signal of the delay unit; the delay module is used for timing (the timing time t can be determined by setting the number n of D flip-flops, t=2 n ×T clk ).

[0025] like Figure 1 As shown, in this embodiment, a circuit for realizing low temperature drift and low power consumption of an on-chip clock circuit includes a charge and discharge control circuit, a comparator A1, a hysteresis comparator A2, an output control circuit and a clock shutdown control circuit.

[0026] The charge and discharge control circuit is used to control the charge and discharge voltage threshold of capacitor C; the comparator A1 is used to distinguish the high and low potentials of the output signal and control the capacitor C to provide the charge and discharge process; the hysteresis comparator A2 is used to compare the voltage of capacitor C with the reference potential V R For comparison, the output signal is flipped and controlled; the output control circuit is used to control the high and low levels of the output signal; the clock shutdown control circuit is used to shut down the clock under system requirements to achieve low power consumption.

[0027] In this embodiment, the charge and discharge control circuit includes: a first resistor R1, a first capacitor C1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and an NMOS transistor NMb; one end of the first resistor R1 is connected to the power supply, one end is connected to the first capacitor C1, the other end of C1 is grounded, and the common end of the two is recorded as a node V R The gate of the first NMOS tube NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to V R The source is connected to the drain of the second NMOS tube NM2, the gate of NM2 is connected to the gate of NMb, and the source is grounded; the gate of the third NMOS tube NM3 is connected to the gate of NM2, and the drain is connected to V R , the source is grounded; the drain current of the NMOS tube NMb is controlled by the I b Mirror image, the value is consistent with I b ;

[0028] The output control circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first inverter INV1 and a second inverter INV2; the gate of the first PMOS transistor PM1 is connected to the negative output terminal V of the hysteresis comparator A2. ON , the source is connected to the power supply, and the drain is connected to the drain of the fourth NMOS tube NM4; the gate of the fourth NMOS tube NM4 is connected to the clock shutdown control signal PD, and the source is grounded; the drain of the fifth NMOS tube NM5 is connected to the drain of NM4, the gate and the drain are connected, and the source is grounded; the gate of the sixth NMOS tube NM6 is connected to the gate of NM5, the source is grounded, and the drain is connected to the drain of the second PMOS tube PM2; the gate of the second PMOS tube PM2 is connected to the positive output terminal V of the hysteresis comparator A2 OP , the source is connected to the power supply, and the drain is connected to the input terminal V of the first inverter INV1 O1 The output terminal V of the first inverter INV1 O2 The input terminal of the second inverter INV2 is connected to the output terminal of INV2, and the output terminal of INV2 is the clock signal CLK.

[0029] The clock shutdown control circuit comprises: a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, and a reference current source Ibias; the input terminal of INV3 is connected to the shutdown signal PD, the output terminal is connected to the gate of NM7, the drain of NM7 is connected to Ibias, the source is connected to the drain of NM8, the source of NM8 is grounded, and the gate is connected to PD; the gate of NM9 is connected to the drain of NM8, the drain is connected to Ibias, and the gate of NM9 is connected to the drain of NM8. bias , the source is grounded, the gate of NM10 is connected to the drain of NM4, and the drain is connected to I b , the source is grounded.

[0030] The positive input terminal of comparator A1 is connected to the input terminal V O1 , the negative input terminal is connected to the output terminal V of INV1 O2 , the output terminal V of INV1 O2 The output of A1 is connected to the capacitor C and the negative input terminal V of comparator A2. C , the positive input terminal of A2 is connected to the output terminal V of the charge and discharge control circuit R The tail current sources of comparator A1 and hysteresis comparator A2 are nI b and mI b , I b The reference current source I bias A mirror image is generated, where n and m are proportional coefficients.

[0031] Preferably, in this embodiment, the capacitor C is a poly capacitor with a low temperature coefficient.

[0032] Preferably, in the present embodiment, in the charge and discharge control circuit, the resistor R1 is composed of two resistors with positive and negative temperature coefficients connected in series, and the proportional coefficient is based on To determine, is the temperature coefficient, which can be found in the model file of the process library; determines V R The two currents I1 and I2 of the node voltage are obtained by mirroring Ib with a certain proportional coefficient.

[0033] Preferably, in this embodiment, a shutdown control signal PD is introduced into the output control circuit. When PD is at a high level, NM4 is turned on, the gate voltages of NM5 and NM6 are at a low level, NM5 and NM6 are turned off, and no current flows through the output control branch, thereby reducing static power consumption.

[0034] In this embodiment, a control method for a circuit to achieve low temperature drift and low power consumption of an on-chip clock is specifically as follows:

[0035] When the power supply is turned on, the node voltage V C Less than the node voltage V R , the hysteresis comparator A2 outputs a low level in the positive direction, PM1 is turned off, PM2 is turned on, and the node V O1 is high level, V O2 is low level, comparator A1 outputs high level, charging capacitor C, and the charging current is the tail current source nI of A1. b , while the low level signal V O2 Turn off NM2, the branch current I1 = 0, the voltage drop on the resistor R1 decreases, and the node voltage V R Rise to ;

[0036] Capacitor C is continuously charged. When the voltage V C Slightly larger than V R1 When the hysteresis comparator A2 outputs V OP Flipping from low level to high level, PM1 is turned on, PM2 is turned off, and node V O1 is low level, V O2 is high level, comparator A1 outputs low level, capacitor C discharges, and the charging current is the tail current source nIb of A1. At the same time, the high level signal V O2 When NM2 is turned on, branch current I1 passes through, the voltage drop on resistor R1 increases, and the node voltage VR drops to ;

[0037] Capacitor C continues to discharge. When the voltage V C Slightly smaller than VR2 When the hysteresis comparator A2 outputs V OP It flips from high level to low level, and repeats like this, forming a square wave oscillation output CLK.

[0038] In this embodiment, the capacitor C is at a voltage V R1 and V R2 Periodic charging and discharging are performed between ; The voltage change on the capacitor ,Depend on have to , where I is the tail current source of comparator A1, and I2 is I bias The mirror current of the clock circuit is calculated by the ratio of the two, and the temperature influence is eliminated. From the formula, it can be seen that the output signal CLK of the clock circuit is basically not affected by the power supply voltage, and the capacitor C with a low temperature coefficient and the resistor R1 with positive and negative temperature complementarity both ensure the low temperature drift characteristics of the circuit.

[0039] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A circuit for realizing low temperature drift and low power consumption of an on-chip clock, characterized in that: include: Charge and discharge control circuit module, comparator A1, hysteresis comparator A2, output control circuit module and clock shutdown control circuit module; The charge and discharge control circuit module is connected to the negative input terminal of the comparator A1, the clock shutdown control circuit module and the positive input terminal of the hysteresis comparator A2 respectively; the output control circuit module is connected to the positive input terminal of the comparator A1, the clock shutdown control circuit module and the output terminal of the hysteresis comparator A2 respectively; the output terminal of the comparator A1 is connected to the negative input terminal of the hysteresis comparator A2 and the capacitor C respectively; the comparator A1 and the hysteresis comparator A2 are connected to the first tail current source and the second tail current source respectively; The charge and discharge control circuit includes a first resistor R1, a first capacitor C1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and an NMOS transistor NMb; one end of the first resistor R1 is connected to a power supply, and the other end is connected to the first capacitor C1; the other end of the first capacitor C1 is grounded; the common end of the first resistor R1 and the first capacitor C is recorded as a node V R The gate of the first NMOS tube NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to V R The source is connected to the drain of the second NMOS tube NM2; the gate of the second NMOS tube NM2 is connected to the gate of the NMOS tube NMb, and the source is grounded; the gate of the third NMOS tube NM3 is connected to the gate of the second NMOS tube NM2, and the drain is connected to V R , the source is grounded; the drain current of the NMOS tube NMb is connected to I b ; The output control circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first inverter INV1 and a second inverter INV2; the gate of the first PMOS transistor PM1 is connected to the negative output terminal V of the hysteresis comparator A2. ON , the source is connected to the power supply, and the drain is connected to the drain of the fourth NMOS tube NM4; the gate of the fourth NMOS tube NM4 is connected to the clock shutdown control signal PD, and the source is grounded; the drain of the fifth NMOS tube NM5 is connected to the drain of NM4, the gate and the drain are connected, and the source is grounded; the gate of the sixth NMOS tube NM6 is connected to the gate of NM5, the source is grounded, and the drain is connected to the drain of the second PMOS tube PM2; the gate of the second PMOS tube PM2 is connected to the positive output terminal V of the hysteresis comparator A2 OP , the source is connected to the power supply, and the drain is connected to the input terminal V of the first inverter INV1 O1； The output terminal V of the first inverter INV1 O2 The input terminal of the second inverter INV2 is connected, and the output terminal of INV2 outputs the clock signal CLK; The clock shutdown control circuit includes a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, and a reference current source Ibias; the clock shutdown control signal PD of the third inverter INV3 is outputted to the gate of the seventh NMOS tube NM7; the drain of the seventh NMOS tube NM7 is connected to Ibias, and the source is connected to the drain of the eighth NMOS tube NM8; the source of the eighth NMOS tube NM8 is grounded, and the gate is connected to the clock shutdown control signal PD; the gate of the ninth NMOS tube NM9 is connected to the drain of the eighth NMOS tube NM8, and the drain is connected to Ibias. bias The gate of the tenth NMOS tube NM10 is connected to the drain of NM4, and the drain is connected to I b , the source is grounded.

2. The circuit for realizing low temperature drift and low power consumption of an on-chip clock according to claim 1, characterized in that: In the charge and discharge control circuit, the resistor R1 is composed of two resistors with positive and negative temperature coefficients connected in series, and its proportional coefficient is determined according to αR11+βR12=0, where α and β are temperature coefficients.

3. The circuit for realizing low temperature drift and low power consumption of an on-chip clock according to claim 1, characterized in that: The capacitor C is a poly capacitor with a low temperature coefficient.

4. A control method for a circuit that realizes low temperature drift and low power consumption of an on-chip clock, characterized in that: The method is implemented by using the circuit for realizing low temperature drift and low power consumption of the on-chip clock as described in any one of claims 1 to 3, and comprises the following steps: Step S1: When the system power is turned on, the node voltage V C Less than the node voltage V R , the hysteresis comparator A2 outputs a low level in the positive direction, PM1 is turned off, PM2 is turned on, and the node V O1 is high level, V O2 is low level, comparator A1 outputs high level, charging capacitor C, and the charging current is the tail current source nI of A1. b , while the low level signal V O2 Turn off NM2, branch current I1=0, voltage drop on resistor R1 decreases, node voltage V R Rising to V R1 =V CC -I2×R1; Step S2: Capacitor C continues to charge. When the voltage V C Slightly larger than V R1 When the hysteresis comparator A2 outputs V OP Flipping from low level to high level, PM1 is turned on, PM2 is turned off, and node V O1 is low level, V O2 is high level, comparator A1 outputs low level, capacitor C discharges, and the charging current is the tail current source nI of A1 b , while the high level signal V O2 When NM2 is turned on, branch current I1 passes through, the voltage drop on resistor R1 increases, and the node voltage V R Drop to V R2 =V CC -(I1+I2)×R1; Step S3: The capacitor C continues to discharge. When the voltage V C Slightly smaller than V R2 When the hysteresis comparator A2 outputs V OP Flip from high level to low level; Step S4: Repeat steps S2-S3 cyclically to form a square wave oscillation output CLK.

5. The control method for realizing a circuit with low temperature drift and low power consumption of an on-chip clock according to claim 4, characterized in that: The circuit is also provided with a shutdown control signal PD. When PD is at a high level, NM4 is turned on, the gate voltages of NM5 and NM6 are at a low level, NM5 and NM6 are turned off, and no current flows through the output control branch.

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