Method for preparing rewiring layer and semiconductor structure

Abstract

The present invention provides a method for preparing a redistribution layer and a semiconductor structure. The semiconductor structure includes a substrate and a redistribution layer located on the upper surface of the substrate. The redistribution layer includes a dielectric layer, and the dielectric layer includes trenches penetrating through the dielectric layer; a metal seed layer, the metal seed layer covering the upper surface of the dielectric layer and the bottom and side walls of the trenches; a first metal layer, the first metal layer filling the trenches; a second metal layer, the second metal layer covering the first metal layer, and the width of the second metal layer being greater than the width of the first metal layer, and covering the metal seed layer located on the upper surface of the dielectric layer. The present invention prepares the first metal layer by conformal electroplating to shorten the process cycle and reduce the process cost; by the first metal layer filling the trenches, the flatness of the redistribution layer can be improved, and grooves are avoided from being generated in the formed redistribution layer, thereby being beneficial to subsequent manufacturing processes, reducing the process risk of multi-layer stacking, and further reducing the process difficulty and cost.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and relates to a method for preparing a redistribution layer and a semiconductor structure. Background Art

[0002] As the functions of integrated circuits become more powerful, their performance and integration level become higher, and with the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products and accounts for an increasingly large proportion of the value of the entire electronic system. At the same time, as the feature size of integrated circuits reaches the nanometer level and transistors develop towards higher density and higher clock frequencies, packaging also develops towards higher density.

[0003] Due to advantages such as miniaturization, low cost, high integration, better performance, and higher energy efficiency, wafer-level packaging (WLP) technology has become an important packaging method for high-demand electronic devices such as mobile / wireless networks and is one of the most promising packaging technologies at present.

[0004] The redistribution layer (RDL) generally includes a dielectric layer and a metal layer; it can re-layout the solder pad areas of the chip so that the new solder pad areas meet the requirements for the minimum pitch of solder balls and are arranged in an array. In the existing WLP process, the manufacturing part of the RDL is the more complex and expensive part of the entire WLP process. Generally, according to requirements, there is often a large thickness difference between the RDL dielectric layer and the through-connection plug metal layer above and below. For example, in the RDL, the thickness of the PI (photosensitive polyimide) dielectric layer is about 10 μm, while the designed thickness of the Cu metal layer may be designed to be about 1.0 μm.

[0005] In the prior art, for a high I / O chip packaging structure, since it is often necessary for the RDL to have multiple metal layers to obtain more power supply tracks within a limited form factor and packaging size, it is often necessary to form a stacked RDL. Due to the large thickness difference between the RDL dielectric layer and the metal layer, the thickness difference between the RDL dielectric layer and the metal layer will also be superimposed during the process of forming a stacked RDL, thus increasing the difficulty of the process for preparing the stacked RDL. Moreover, in the finally formed RDL product, relatively deep grooves will be formed in the RDL. For example, when forming a 3-layer stacked RDL, grooves with a depth of about 27 μm or deeper will be formed in the RDL. The existence of these relatively deep grooves poses a great challenge to subsequent processes, such as preparing a dielectric layer on the RDL, coating photoresist, exposure, development, and V-IC (metal soldering) processes.

[0006] Therefore, providing a new method for preparing a redistribution layer and a semiconductor structure to improve the planarization of the redistribution layer has become an urgent problem to be solved in this field. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a method for preparing a redistribution layer and a semiconductor structure, which are used to solve the problems in the prior art that the process for preparing RDL is complex, time-consuming, and costly, and a series of process problems brought about by the relatively deep grooves in the prepared RDL.

[0008] To achieve the above object and other related objects, the present invention provides a method for preparing a redistribution layer, including the following steps:

[0009] Provide a substrate, and form a dielectric layer on the upper surface of the substrate;

[0010] Pattern the dielectric layer to form a trench penetrating the dielectric layer;

[0011] Form a metal seed layer, and the metal seed layer covers the upper surface of the dielectric layer and the bottom and side walls of the trench;

[0012] Form a first mask layer, and pattern the first mask layer to form a first window in the first mask layer, so that the first mask layer covers the metal seed layer on the dielectric layer and exposes the metal seed layer on the bottom and side walls of the trench through the first window;

[0013] Based on the first window, form a first metal layer, and the first metal layer fills the trench;

[0014] Remove the first mask layer;

[0015] Form a second mask layer, and pattern the second mask layer to form a second window in the second mask layer, and expose the first metal layer through the second window, and the width of the second window is greater than the width of the first window;

[0016] Based on the second window, form a second metal layer, and the second metal layer covers the first metal layer;

[0017] Remove the second mask layer and the metal seed layer under the second mask layer to form the redistribution layer on the substrate.

[0018] Optionally, the method for forming the first metal layer includes one or a combination of conformal plating and electroless plating.

[0019] Optionally, multiple layers of the rewiring layer are included on the substrate.

[0020] Optionally, the first metal layer and the metal seed layer located on the dielectric layer are at the same horizontal plane.

[0021] Optionally, the thickness range of the dielectric layer includes 5 μm to 30 μm; the thickness range of the second metal layer includes 0.5 μm to 5 μm.

[0022] Optionally, the cross-sectional morphology formed by the second metal layer and the first metal layer includes a T-shaped morphology.

[0023] Optionally, the width range of the first metal layer includes 20 μm to 150 μm; the width range of the second metal layer includes 5 μm to 500 μm.

[0024] Optionally, the first metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer; the second metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer.

[0025] Optionally, the first metal layer and the second metal layer are made of the same material.

[0026] Optionally, the dielectric layer includes one or a combination of a photosensitive polyimide (PI) polymer film, a polybenzoxazole (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

[0027] The present invention further provides a semiconductor structure, which includes:

[0028] A substrate;

[0029] A rewiring layer located on the upper surface of the substrate; wherein, the rewiring layer includes:

[0030] A dielectric layer including a trench penetrating through the dielectric layer;

[0031] A metal seed layer covering the upper surface of the dielectric layer and the bottom and side walls of the trench;

[0032] A first metal layer filling the trench;

[0033] A second metal layer, which covers the first metal layer, and the width of the second metal layer is greater than that of the first metal layer, and the second metal layer covers the metal seed layer located on the upper surface of the dielectric layer.

[0034] Optionally, multiple layers of the rewiring layer are included on the substrate.

[0035] Optionally, the first metal layer and the metal seed layer located on the dielectric layer are on the same horizontal plane.

[0036] Optionally, the thickness range of the dielectric layer includes 5μm to 30μm; the thickness range of the second metal layer includes 0.5μm to 5μm.

[0037] Optionally, the cross-sectional morphology formed by the second metal layer and the first metal layer includes a T-shaped morphology.

[0038] Optionally, the width range of the first metal layer includes 20μm to 150μm; the width range of the second metal layer includes 5μm to 500μm.

[0039] Optionally, the first metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer; the second metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer.

[0040] Optionally, the first metal layer and the second metal layer are made of the same material.

[0041] Optionally, the dielectric layer includes one or a combination of a photosensitive polyimide (PI) polymer film, a polybenzoxazole (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

[0042] As described above, the method for preparing the rewiring layer and the semiconductor structure of the present invention use the conformal electroplating method to prepare the first metal layer, which can separately control and optimize the filling speed and filling uniformity of the first metal layer, fill the trenches to control their flatness; the conformal electroplating method can use low-cost electroplating solutions used in traditional middle and back-end processes, so the process cost can be reduced; through the first metal layer that fills the trenches, the flatness of the rewiring layer can be improved, avoiding the generation of grooves in the formed rewiring layer, which is beneficial to subsequent manufacturing processes, reduces the process risk of multi-layer stacking, and further reduces the process difficulty and cost. Description of the Drawings

[0043] Figure 1 Shown is a schematic flow chart of the method for preparing the rewiring layer in the first embodiment.

[0044] Figures 2 to 7a Shown are schematic structural diagrams presented by each step of the method for preparing the rewiring layer in the first embodiment, where Figure 7a Also shown is a schematic structural diagram of the semiconductor structure in the second embodiment.

[0045] Figure 7b Shown is a schematic structural diagram of the semiconductor structure with two rewiring layers in the first and second embodiments.

[0046] Element reference numeral description

[0047] 101 Substrate

[0048] 201 Dielectric layer

[0049] 202 Trench

[0050] 301 Metal seed layer

[0051] 401 First mask layer

[0052] 402 First window

[0053] 501 First metal layer

[0054] 601 Second mask layer

[0055] 602 Second window

[0056] 701 Second metal layer Detailed implementation manners

[0057] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] Please refer to Figures 1 to 7b . It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0059] First embodiment

[0060] AsFigure 1 , this embodiment provides a method for fabricating a redistribution layer, comprising the following steps:

[0061] Provide a substrate, and form a dielectric layer on the upper surface of the substrate;

[0062] Pattern the dielectric layer to form trenches penetrating the dielectric layer in the dielectric layer;

[0063] Form a metal seed layer, and the metal seed layer covers the upper surface of the dielectric layer and the bottom and side walls of the trenches;

[0064] Form a first mask layer, and pattern the first mask layer to form a first window in the first mask layer, such that the first mask layer covers the metal seed layer on the dielectric layer and exposes the metal seed layer on the bottom and side walls of the trenches through the first window;

[0065] Based on the first window, form a first metal layer, and the first metal layer fills the trenches;

[0066] Remove the first mask layer;

[0067] Form a second mask layer, and pattern the second mask layer to form a second window in the second mask layer, and expose the first metal layer through the second window, and the width of the second window is greater than the width of the first window;

[0068] Based on the second window, form a second metal layer, and the second metal layer covers the first metal layer;

[0069] Remove the second mask layer and the metal seed layer under the second mask layer to form the redistribution layer on the substrate.

[0070] By separately controlling and optimizing the filling speed and filling uniformity of the first metal layer, the present invention can fill the trenches, improve the flatness of the redistribution layer, avoid generating grooves in the formed redistribution layer, thereby facilitating subsequent process steps, reducing process difficulty and cost.

[0071] Specifically, refer to Figures 2 to 7a , which shows a schematic structural diagram of each step of forming the redistribution layer.

[0072] As shown in Figure 2, First, a substrate 101 is provided. The substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, which can be selected according to needs and is not limited here. A dielectric layer 201 is formed on the upper surface of the substrate 101. The dielectric layer 201 includes one or a combination of a photosensitive polyimide (PI) polymer film, a polybenzoxazole (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The dielectric layer 201 is patterned to form a trench 202 penetrating the dielectric layer 201. The morphology of the trench 202 is not limited here and may include an opening. Among them, the method of patterning the dielectric layer 201 can adopt a conventional etching method, which is not limited here. A metal seed layer 301 is formed on the upper surface of the dielectric layer 201 and in the trench 202. The metal seed layer 301 covers the upper surface of the dielectric layer 201 and the bottom and side walls of the trench 202. The material of the metal seed layer 301 includes one or a combination of titanium metal and copper metal, but is not limited thereto. The method of preparing the metal seed layer 301 includes one of evaporation plating, electroplating, and sputtering, which can be selected according to needs. (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The dielectric layer 201 is patterned to form a trench 202 penetrating the dielectric layer 201. The morphology of the trench 202 is not limited here and may include an opening. Among them, the method of patterning the dielectric layer 201 can adopt a conventional etching method, which is not limited here. A metal seed layer 301 is formed on the upper surface of the dielectric layer 201 and in the trench 202. The metal seed layer 301 covers the upper surface of the dielectric layer 201 and the bottom and side walls of the trench 202. The material of the metal seed layer 301 includes one or a combination of titanium metal and copper metal, but is not limited thereto. The method of preparing the metal seed layer 301 includes one of evaporation plating, electroplating, and sputtering, which can be selected according to needs.

[0073] As Figure 3 , a first mask layer 401 is formed and patterned to form a first window 402 in the first mask layer 401, so that the first mask layer 401 covers the metal seed layer 301 on the dielectric layer 201 and exposes the metal seed layer 301 on the bottom and side walls of the trench 202 through the first window 402.

[0074] Specifically, the first mask layer 401 serves as a mask for forming the first metal layer 501 later. Its material includes photoresist, but is not limited thereto. As long as the material of the first mask layer 401 can meet the pattern making and can be removed later. In this embodiment, a relatively common photoresist is used as the first mask layer 401. The method of patterning the first mask layer 401 can adopt a conventional patterning method, which is not limited here.

[0075] As Figure 4 , based on the first window 402, the first metal layer 501 is formed, and the first metal layer 501 fills the trench 202.

[0076] As a further embodiment of this embodiment, the method of forming the first metal layer 501 includes one or a combination of conformal plating and electroless plating.

[0077] Specifically, when forming the first metal layer 501, based on the first window 402 and the metal seed layer 301 located in the trench 202, the first metal layer 501 can be formed by electroplating, where the electroplating method includes conformal electroplating. The first metal layer 501 can also be prepared by electroless plating. In this embodiment, the conformal electroplating method with fewer additives in the electroplating solution, lower plating solution cost, and lower maintenance cost of the plating solution is used to prepare the first metal layer 501. For example, the electroplating solution can use traditional low-cost electroplating chemicals in the middle and later processes, which can reduce the process cost compared with TSV electroplating chemicals. The filling speed and filling uniformity of the first metal layer 501 can be separately controlled and optimized, thereby improving the operation convenience.

[0078] As a further embodiment of this embodiment, the first metal layer 501 includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer. In this embodiment, the relatively common copper metal layer is used, but it is not limited thereto.

[0079] As a further embodiment of this embodiment, the first metal layer 501 and the metal seed layer 301 located on the dielectric layer 201 are on the same horizontal plane.

[0080] Specifically, when the first metal layer 501 and the metal seed layer 301 located on the dielectric layer 201 are on the same horizontal plane, it can provide a horizontal plane for the subsequent formation of the second metal layer 701, thereby reducing the process difficulty and further improving the flatness of the subsequent formed rewiring layer.

[0081] Such as Figure 5 , remove the first mask layer 401, form a second mask layer 601, and pattern the second mask layer 601 to form a second window 602 in the second mask layer 601, and expose the first metal layer 501 through the second window 602, and the width of the second window 602 is greater than the width of the first window 402.

[0082] Specifically, the second mask layer 601 serves as a mask for the subsequent formation of the second metal layer 701, and its material includes photoresist, but it is not limited thereto. As long as the material of the second mask layer 601 can meet the pattern making and can be removed subsequently. In this embodiment, the relatively common photoresist is used as the second mask layer 601, and the method of patterning the second mask layer 601 can adopt conventional patterning methods, which are not limited here.

[0083] Such as Figure 6, based on the second window 602, the second metal layer 701 is formed. The second metal layer 701 covers the first metal layer 501, and the width of the second metal layer 701 is greater than the width of the first metal layer 501.

[0084] Specifically, the method of forming the second metal layer 701 may include one or a combination of conformal electroplating and electroless plating. When forming the second metal layer 701, based on the second window 602, the first metal layer 501 located in the trench 202, and the metal seed 301 located on a partial upper surface of the dielectric layer 201, electroplating may be used to form the second metal layer 701, where the filling speed and filling uniformity of the second metal layer 701 can be individually adjusted.

[0085] As a further embodiment of this embodiment, the second metal layer 701 includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer. In this embodiment, a commonly used copper metal layer is employed, but it is not limited thereto.

[0086] As a further embodiment of this embodiment, the first metal layer 501 and the second metal layer 701 are made of the same material.

[0087] Specifically, when the first metal layer 501 and the second metal layer 701 are made of the same material, the bonding force between the materials can be enhanced, and phenomena such as interface delamination and cracking caused by physical and chemical properties of the materials such as thermal expansion can be avoided. In this embodiment, both the first metal layer 501 and the second metal layer 701 are made of a copper metal layer, but it is not limited thereto.

[0088] As a further embodiment of this embodiment, the thickness range of the dielectric layer 201 includes 5 μm to 30 μm; the thickness range of the second metal layer 701 includes 0.5 μm to 5 μm.

[0089] Specifically, the thickness ranges of the dielectric layer 201 and the second metal layer 701 can be set according to specific process requirements. In this embodiment, the thicknesses of the dielectric layer 201 and the second metal layer 701 both adopt relatively common specifications, that is, the thickness of the dielectric layer 201 can be 10 μm, and the thickness of the second metal layer 701 can be 1.0 μm, but it is not limited thereto.

[0090] Such as Figure 7a, the second mask layer 601 and the metal seed layer 301 located below the second mask layer 601 are removed to form the redistribution layer on the substrate 101. After preparing the redistribution layer, the step of removing the substrate 101 may also be included, which is not limited herein.

[0091] As a further embodiment of this embodiment, multiple layers of the redistribution layer are included on the substrate 101.

[0092] Specifically, since the first metal layer 501 fills the trench 202, a redistribution layer without grooves can be prepared, thereby reducing the process difficulty of subsequently preparing stacked redistribution layers and reducing the process risk of multi-layer stacking. Therefore, multiple layers of the redistribution layer can be prepared on the substrate 101. For example Figure 7b , in this embodiment, a semiconductor structure including 2 layers of the redistribution layer is illustrated, but it is not limited thereto. After forming the redistribution layer in contact with the substrate 101, using the redistribution layer as the substrate, the above steps of forming the redistribution layer are continued to be repeated to form 2 layers of the redistribution layer arranged in a stack. The specific number of layers of the redistribution layer arranged in a stack can be selected as needed, such as 3 layers, 5 layers, etc., which is not limited herein. Through the redistribution layer arranged in a stack, more power supply tracks can be further obtained under limited external shape and package size.

[0093] As a further embodiment of this embodiment, the width range of the first metal layer 501 includes 20 μm to 150 μm; the width range of the second metal layer 701 includes 5 μm to 500 μm.

[0094] Specifically, the width of the second metal layer 701 is greater than the width of the first metal layer 501 to facilitate expanding the effective area of the metal layer of the redistribution layer and further increasing the number of power supply tracks under limited external shape and package size. The width range of the first metal layer 501 and the width range of the second metal layer 701 can be selected as needed. For example, the width of the first metal layer 501 can be 60 μm, and the width of the second metal layer 701 can be 80 μm, etc.

[0095] As a further embodiment of this embodiment, the cross-sectional morphology formed by the second metal layer 701 and the first metal layer 501 includes a T-shaped morphology.

[0096] Specifically, it is preferred that the cross-sectional morphology formed by the second metal layer 701 and the first metal layer 501 is an axisymmetric T-shaped morphology. When the cross-sectional morphology formed by the second metal layer 701 and the first metal layer 501 is an axisymmetric T-shaped morphology, the effective area of the metal layer in the redistribution layer can be further expanded under limited external shapes and packaging dimensions, so as to reduce the packaging size.

[0097] Embodiment 2

[0098] Such as Figure 7a , this embodiment provides a semiconductor structure, which includes: a substrate 101 and a redistribution layer, and the redistribution layer is located on the upper surface of the substrate 101. Among them, the redistribution layer includes: a dielectric layer 201, and the dielectric layer 201 includes a trench 202 penetrating through the dielectric layer 201; a metal seed layer 301, and the metal seed layer 301 covers the upper surface of the dielectric layer 201 and the bottom and side walls of the trench 202; a first metal layer 501, and the first metal layer 501 fills the trench 202; a second metal layer 701, and the second metal layer 701 covers the first metal layer 501, and the width of the second metal layer 701 is greater than the width of the first metal layer 501, and covers the metal seed layer 301 located on the upper surface of the dielectric layer 201.

[0099] In this embodiment, through the first metal layer 501 that fills the trench 202, the flatness of the redistribution layer can be improved, and grooves are avoided from being generated in the formed redistribution layer, which is beneficial to subsequent manufacturing processes and reduces the process difficulty and cost.

[0100] Specifically, Figure 7b It also shows a semiconductor structure including 2 layers of the redistribution layer.

[0101] The preparation method of the redistribution layer in this embodiment can adopt the preparation method of the redistribution layer in Embodiment 1, but is not limited thereto. The morphologies, materials of the substrate 101, the dielectric layer 201, the metal seed layer 301, the first metal layer 501 and the second metal layer 701 in the redistribution layer, and the structure of the redistribution layer can be the same as those in Embodiment 1, and will not be elaborated here.

[0102] In summary, for the method for preparing a rewiring layer and a semiconductor structure according to the present invention, the first metal layer is prepared by conformal electroplating, and the filling rate and filling uniformity of the first metal layer can be separately controlled and optimized to fill the trench to control its flatness; the conformal electroplating method can use low-cost electroplating solutions used in the traditional middle and back-end processes, so the process cost can be reduced; the flatness of the rewiring layer can be improved by the first metal layer that fills the trench, avoiding the generation of grooves in the formed rewiring layer, which is beneficial to subsequent manufacturing processes and reduces the process risk of multi-layer stacking, further reducing the process difficulty and cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0103] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a rewiring layer, characterized in that, The method includes the following steps: Provide a substrate and form a dielectric layer on the upper surface of the substrate; Pattern the dielectric layer to form a trench penetrating the dielectric layer in the dielectric layer; Form a metal seed layer, and the metal seed layer covers the upper surface of the dielectric layer and the bottom and side walls of the trench; Form a first mask layer and pattern the first mask layer to form a first window in the first mask layer, so that the first mask layer covers the metal seed layer on the dielectric layer and exposes the metal seed layer on the bottom and side walls of the trench through the first window; Based on the first window, form a first metal layer, and the first metal layer fills the trench; Remove the first mask layer; Form a second mask layer and pattern the second mask layer to form a second window in the second mask layer, and expose the first metal layer and the metal seed layer on a part of the upper surface of the dielectric layer through the second window, and the width of the second window is greater than the width of the first window; Based on the second window, form a second metal layer, the second metal layer covers the first metal layer, and the cross-sectional morphology formed by the second metal layer and the first metal layer is a T-shaped morphology, and the first metal layer and the second metal layer are made of the same material; Remove the second mask layer and the metal seed layer under the second mask layer to form the redistribution layer on the substrate.

2. The method for preparing a rewiring layer according to claim 1, characterized in that: The method for forming the first metal layer includes one or a combination of conformal plating and electroless plating.

3. The method for preparing a rewiring layer according to claim 1, wherein: There are multiple redistribution layers on the substrate.

4. The method for preparing a rewiring layer according to claim 1, wherein: The first metal layer and the metal seed layer on the dielectric layer are at the same horizontal plane.

5. The method for preparing a rewiring layer according to claim 1, wherein: The thickness range of the dielectric layer includes 5μm to 30μm; the thickness range of the second metal layer includes 0.5μm to 5μm.

6. The method for preparing a rewiring layer according to claim 1, wherein: The width range of the first metal layer includes 20μm to 150μm; the width range of the second metal layer includes 5μm to 500μm.

7. The method for preparing a rewiring layer according to claim 1, characterized in that: The first metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer; the second metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer.

8. The method for preparing a rewiring layer according to claim 1, wherein: The dielectric layer includes one or a combination of a photosensitive polyimide (PI) polymer film, a polybenzoxazole (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

9. A semiconductor structure is prepared by using the method for preparing a rewiring layer according to any one of claims 1 to 8, and is characterized in that, The semiconductor structure includes: A substrate; A redistribution layer located on the upper surface of the substrate; wherein, the redistribution layer includes: A dielectric layer, and the dielectric layer includes a trench penetrating the dielectric layer; A metal seed layer, and the metal seed layer covers the upper surface of the dielectric layer and the bottom and side walls of the trench; A first metal layer, and the first metal layer fills the trench; A second metal layer, the second metal layer covering the first metal layer, and the width of the second metal layer being greater than the width of the first metal layer, and covering the metal seed layer located on the upper surface of the dielectric layer, the cross-sectional morphology formed by the first metal layer and the second metal layer being a T-shaped morphology, and the first metal layer and the second metal layer having the same material.

10. The semiconductor structure according to claim 9, wherein: Multiple such rewiring layers are included on the substrate.

11. The semiconductor structure according to claim 9, wherein: The first metal layer and the metal seed layer located on the dielectric layer are at the same horizontal plane.

12. The semiconductor structure according to claim 9, wherein: The thickness range of the dielectric layer includes 5 μm to 30 μm; the thickness range of the second metal layer includes 0.5 μm to 5 μm.

13. The semiconductor structure according to claim 9, wherein: The width range of the first metal layer includes 20 μm to 150 μm; the width range of the second metal layer includes 5 μm to 500 μm.

14. The semiconductor structure according to claim 9, wherein: The first metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer; the second metal layer includes one or a combination of a copper metal layer, an aluminum metal layer, a silver metal layer, a chromium metal layer, a titanium metal layer, a tantalum metal layer, a molybdenum metal layer, and a neodymium metal layer.

15. The semiconductor structure according to claim 9, wherein: The dielectric layer includes one or a combination of a photosensitive polyimide (PI) polymer film, a polybenzoxazole (PBO) polymer film, a benzocyclobutene (BCB) polymer film, an epoxy resin (EMC), silica gel, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

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