An intelligent remote control unit IRIG-B code output board for a substation and its usage method

Abstract

The present invention discloses an IRIG-B code output board for a substation intelligent remote terminal unit and its usage method, which includes an FPGA module, a PCIe interface circuit, an optical fiber output circuit, and an RS-485 interface circuit. The PCIe interface circuit, the optical fiber output circuit, and the RS-485 interface circuit are all connected to the FPGA module. The PCIe board based on the FPGA chip of the present invention has a simple structure, does not affect the appearance and overall structure of the tester, and is convenient to use. The delay compensation algorithm based on the ping-pong principle eliminates the time error between the synchronization board and the test, improves the accuracy of the output synchronization signal to the 1ms level, and provides an accurate time reference for the automatic test of the remote terminal unit.

Description

Technical Field

[0001] The present invention relates to an IRIG-B code output board of a substation intelligent remote terminal unit and a using method thereof, and belongs to the technical field of intelligent remote terminal unit test systems. Background Art

[0002] With the rapid development of the power industry, large-scale construction of power dispatching automation systems has been carried out, and they have gradually occupied a more important position. The remote terminal unit is a very important link connecting the master station and the substation system. All data collected by substation equipment needs to be uploaded to the master station through the remote terminal unit for the master station to analyze and use. Also, the operation commands of the master station for substation equipment are sent to substation automation equipment through the remote terminal unit.

[0003] Under the background of the secondary integration construction of the Southern Power Grid, it is necessary to build a panoramic data center in the master station to integrate data from various specialties. Substations need to achieve unified data acquisition, processing, storage, transmission, etc. Therefore, intelligent remote terminal units have been vigorously promoted and applied. In principle, intelligent remote terminal units need to be redundantly configured for substations above 35 kV, and the Southern Power Grid requires that all 500 kV substations be equipped with intelligent remote terminal units.

[0004] Aiming at the problem that there are few means for functional and performance testing of intelligent remote terminal units during commissioning and maintenance, and testing depends on on-site devices, a platform-based, interface, and script testing method is studied. Relying on the test platform, modern computer technology is used to complete the development of the test system, and the functions and performance of intelligent remote terminal units are automatically tested.

[0005] For the automatic testing of intelligent remote test machines, it is necessary to ensure the time synchronization between the remote terminal unit and the tester. The tester simulates the remote control command sent by the remote master station to the remote terminal unit. The remote terminal unit needs to record the remote control command and the time, and the time accuracy requirement is at the 1 ms level.

[0006] Since the current tester based on a Windows industrial computer only supports the SNTP technology for time synchronization of the remote terminal unit, and the SNTP time synchronization technology can only provide a time synchronization accuracy of 1 - 50 ms, in some scenarios, it cannot meet the time accuracy requirements for the automatic testing of intelligent remote terminal units.

[0007] The tester can also achieve time synchronization between the tester and the intelligent remote terminal unit by cooperating with an external clock synchronization device. However, this solution makes the test system more complex, with more operation procedures and not easy to carry. At the same time, it also increases the hardware cost of the entire test system. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide an IRIG-B code output board of a substation intelligent remote terminal unit and a using method thereof to solve the problems existing in the prior art.

[0009] The technical solution adopted by the present invention is as follows: An IRIG-B code output board for a substation intelligent remote terminal unit, which includes an FPGA module, a PCIe interface circuit, an optical fiber output circuit, and an RS-485 interface circuit. The PCIe interface circuit, the optical fiber output circuit, and the RS-485 interface circuit are all connected to the FPGA module.

[0010] Preferably, the above-mentioned FPGA module includes an FPGA chip, a power supply circuit, and a crystal oscillator circuit. The power supply circuit and the crystal oscillator circuit are connected to the FPGA chip.

[0011] Preferably, the above-mentioned PCIe interface circuit is an X4 interface circuit that supports the PCIe 4.0 specification and is the hardware interface between the board and the tester main board.

[0012] Preferably, the above-mentioned optical fiber output interface circuit includes a drive circuit and an optical fiber transmission module. The drive circuit connects the IRIG-B code signal to the optical fiber transmission module, and the optical fiber transmission module is used to output an optical signal with a wavelength of 820 nm.

[0013] Preferably, the above-mentioned RS-485 output interface circuit includes an isolation circuit and an RS-485 interface circuit. After the isolation circuit isolates the IRIG-B code signal with an insulation voltage of 2 kV, it outputs to the RS-485 interface circuit.

[0014] Preferably, the above-mentioned FPGA module is provided with a time processing module and a B code encoding module. The time processing module is connected to the B code encoding module. The time processing module is connected to the PCIe interface circuit, and the B code encoding module is connected to the optical fiber output circuit and the RS-485 interface circuit.

[0015] A method for using an IRIG-B code output board of a substation intelligent remote terminal unit, and the method is as follows: When performing a closed-loop automated test on the remote terminal unit, the board works in the PCIe slot of the industrial control computer main board. The time processing module obtains the tester time through the PCIe interface and performs delay compensation, and outputs the IRIG-B code to synchronize the measured remote terminal unit.

[0016] Preferably, the above-mentioned time processing module performs data interaction with the tester through the PCIe interface, obtains the tester time, calculates the PCIe interaction delay through the ping-pong principle and performs delay compensation, and writes the compensated time into the time information buffer.

[0017] Preferably, the above time processing module initiates a request to read time information from the tester host through a PCIe memory read operation at time T1. After receiving the request message, the tester host records the current time T2. The tester host writes the T2 time into the response message and sends the response message at time T3. The time processing module receives the response message at time T4. The time processing module calculates the PCIe communication delay time Td = ((T4 - T1) - (T3 - T2)) / 2. The time processing module takes the average of the communication delay data obtained from multiple calculations and uses T4 + Td as the current time of the board card, which is then written into the time information buffer.

[0018] Preferably, the above IRIG-B encoding module calculates the whole second moment based on the time information read from the time information buffer and encodes it in the IRIG-B format, which is then output through the optical fiber output interface circuit and the RS-485 interface circuit.

[0019] The beneficial effects of the present invention are as follows compared with the prior art:

[0020] 1. In the tester based on a Windows industrial control computer, the present invention expands a PCIe board card to output an IRIG-B code time synchronization signal. At the same time, an FPGA module is used to increase the delay compensation for the PCIe communication between the board card and the tester, greatly improving the time synchronization accuracy between the tester and the remote device under test, which can reach the 1ms level.

[0021] 2. The present invention uses an expanded PCIe board card that can be directly inserted into the PCIe slot of the industrial control computer for testing, so it does not affect the appearance of the tester. All time synchronization configurations can be automatically completed by the tester software, with simple operation, no need for additional wiring, and greatly saving the cost of the test system.

[0022] 3. The present invention can output multiple optical fiber synchronization signals and RS-485 synchronization signals, which can provide synchronization signals for multiple intelligent remote devices at the same time. Description of the Drawings

[0023] Figure 1 It is a functional block diagram of an IRIG-B code output board card for an intelligent remote device automation tester in a substation.

[0024] Figure 2 It is a schematic diagram for calculating the PCIe communication delay of the FPGA time processing module.

[0025] Figure 3 It is the state machine of the IRIG-B encoding module. Detailed Embodiments

[0026] The present invention will be further introduced below in conjunction with the accompanying drawings and specific embodiments.

[0027] Embodiment 1: As Figures 1 - 3 shown, an IRIG-B code output board for a substation intelligent remote terminal unit includes an FPGA module, a PCIe interface circuit, an optical fiber output circuit, and an RS-485 interface circuit. The PCIe interface circuit, the optical fiber output circuit, and the RS-485 interface circuit are all connected to the FPGA module.

[0028] Preferably, the above FPGA module includes an FPGA chip with the model number EP4CGX75CF23C8, a power supply circuit, and a crystal oscillator circuit. The power supply circuit and the crystal oscillator circuit are connected to the FPGA chip.

[0029] Preferably, the above PCIe interface circuit is an X4 interface circuit that supports the PCIe 4.0 specification and is the hardware interface between the board and the tester main board.

[0030] Preferably, the above optical fiber output interface circuit includes a driving circuit and an optical fiber transmitting module. The driving circuit connects the IRIG-B code signal to the optical fiber transmitting module, and the optical fiber transmitting module is used to output an optical signal with a wavelength of 820 nm.

[0031] Preferably, the above RS-485 output interface circuit includes an isolation circuit and an RS-485 interface circuit. After the isolation circuit isolates the IRIG-B code signal with an insulation voltage of 2 kV, it outputs the signal to the RS-485 interface circuit.

[0032] Preferably, the above FPGA module is provided with a time processing module and a B code encoding module. The time processing module is connected to the B code encoding module. The time processing module is connected to the PCIe interface circuit, and the B code encoding module is connected to the optical fiber output circuit and the RS-485 interface circuit.

[0033] The time processing module includes three functions: PCIe message processing, PCIe communication delay calculation, and time information buffer. It performs data interaction with the automated test software through the PCIe interface to obtain the tester time, calculates the PCIe interaction delay through the ping-pong principle and performs delay compensation, and writes the compensated time into the time information buffer.

[0034] As Figure 2 shown, the time processing module initiates a request to read time information from the tester host through a PCIe memory read operation at time T1; the tester host records the current time T2 after receiving the request message; the tester host writes the T2 time into the response message; the tester host sends the response message at time T3; the time processing module receives the response message at time T4.

[0035] The time processing module calculates the PCIe communication delay Td = ((T4 - T1) - (T3 - T2)) / 2.

[0036] The time processing module takes the average value of the communication delay data obtained from multiple calculations to reduce the random error of the system.

[0037] The time processing module uses T4+Td as the current time of the board and writes it into the time information buffer.

[0038] The IRIG-B encoding module includes the functions of calculating the whole second and sending the IRIG-B code. The IRIG-B encoding module reads the time information stored in the time information buffer and updates the current millisecond value. When the millisecond counter reaches 990, which is the whole second, it starts the following steps: Figure 3 The IRIG-B code encoding state machine is shown.

[0039] Example 2: Figures 1 - 3 As shown, a method for using an IRIG-B code output board for an intelligent telemotor in a substation is as follows: when performing closed-loop automated testing on the telemotor, the board operates in a PCIe slot on an industrial computer motherboard. The time processing module obtains the tester time through the PCIe interface, performs delay compensation, and outputs the IRIG-B code to synchronize the telemotor under test.

[0040] Preferably, the time processing module exchanges data with the tester through the PCIe interface, obtains the tester time, calculates the PCIe interaction delay and performs delay compensation through the ping-pong principle, and writes the compensated time into the time information buffer.

[0041] Preferably, the above-mentioned time processing module initiates a read time information request to the tester host through a PCIe memory read operation at time T1. After receiving the request information, the tester host records the current time T2. The tester host writes the T2 time into the response message. The tester host sends a response message at time T3. The time processing module receives the response message at time T4. The time processing module calculates the PCIe communication delay time Td=((T4-T1)-(T3-T2)) / 2. The time processing module takes the average of the communication delay data obtained by multiple calculations, and uses T4+Td as the current time of the board, and writes it into the time information buffer.

[0042] Preferably, the IRIG-B encoding module calculates the whole second based on the time information read from the time information buffer area, encodes it in IRIG-B format, and outputs it through the optical fiber output interface circuit and the RS-485 interface circuit.

[0043] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A method for using an IRIG-B code output board of a substation intelligent remote terminal unit, characterized in that The board card includes an FPGA module, a PCIe interface circuit, an optical fiber output interface circuit, and an RS-485 interface circuit. The PCIe interface circuit, the optical fiber output interface circuit, and the RS-485 interface circuit are all connected to the FPGA module; The FPGA module is provided with a time processing module and a B-code encoding module. The time processing module is connected to the B-code encoding module. The time processing module is connected to the PCIe interface circuit, and the B-code encoding module is connected to the optical fiber output interface circuit and the RS-485 interface circuit. The method is as follows: When performing a closed-loop automation test on the remote terminal unit, the board card works in the PCIe slot of the industrial computer motherboard. The time processing module obtains the tester time through the PCIe interface and performs delay compensation, and outputs the IRIG-B code to synchronize the measured remote terminal unit. The time processing module calculates and compensates the delay according to the following ping-pong principle: At time T1, a request for reading time information is sent to the tester host through a PCIe memory read operation. After receiving the request information, the tester host records the current time T2. The tester host writes the T2 time into the response message. The tester host sends the response message at time T3. The time processing module receives the response message at time T4. The time processing module calculates the PCIe communication delay time Td = ((T4 - T1) - (T3 - T2)) / 2. The time processing module takes the average value of the communication delay data obtained from multiple calculations, and uses T4 + Td as the current time of the board card and writes it into the time information buffer. The IRIG-B encoding module updates the current millisecond value according to the time information in the read time information buffer to calculate the whole second moment, and encodes it in the IRIG-B format and outputs it through the optical fiber output interface circuit and the RS-485 interface circuit.

2. The usage method of an IRIG-B code output board of a substation intelligent remote terminal unit according to claim 1, characterized in that: The FPGA module includes an FPGA chip, a power supply circuit, and a crystal oscillator circuit. The power supply circuit and the crystal oscillator circuit are connected to the FPGA chip.

3. The usage method of an IRIG-B code output board of a substation intelligent remote terminal unit according to claim 1, characterized in that: The PCIe interface circuit is an X4 interface circuit that supports the PCIe 4.0 specification and is the hardware interface between the board card and the tester motherboard.

4. The usage method of an IRIG-B code output board of a substation intelligent remote terminal unit according to claim 1, characterized in that: The optical fiber output interface circuit includes a driving circuit and an optical fiber transmitting module. The driving circuit connects the IRIG-B code signal to the optical fiber transmitting module, and the optical fiber transmitting module is used to output an optical signal with a wavelength of 820 nm.

5. The usage method of an IRIG-B code output board of a substation intelligent remote terminal unit according to claim 1, characterized in that: The RS-485 output interface circuit includes an isolation circuit and an RS-485 interface circuit. The isolation circuit isolates the IRIG-B code signal with an insulation voltage of 2 KV and then outputs it to the RS-485 interface circuit.

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