A dual-gate structure pixel circuit and manufacturing method

Abstract

A dual-gate structure pixel circuit includes a gate layer, the gate layer is patterned into a first gate layer and a second gate layer, a gate insulating layer and a first semiconductor layer are arranged above the first gate layer, a gate insulating layer and a second semiconductor layer are arranged above the second gate layer, a barrier layer is also arranged above the first semiconductor layer and the second semiconductor layer, a first via hole is also arranged above the first semiconductor, the first via hole penetrates the barrier layer to expose the first semiconductor layer; a second through hole and a third through hole are arranged above the second gate layer, the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer, the above technical solution forms a dual-gate structure TFT by patterning the SD layer and the second top gate portion at the same time, this design has higher current and device stability, and avoids uneven luminous brightness of OLED devices due to threshold voltage drift.

Description

Technical Field

[0001] The present invention relates to a design scheme of a pixel circuit, and in particular to a circuit structure and a manufacturing method of a TFT capable of providing a dual-gate driving structure. Background Art

[0002] At present, amorphous metal oxide semiconductors are developing rapidly. Among them, amorphous InGaZnO (IGZO) has become an ideal material for TFT preparation due to its simple preparation process and excellent optoelectronic properties. The TFT prepared with it has the characteristics of high mobility and high switching ratio, and has the potential to replace a-Si. Compared with a-Si TFT, the carrier mobility of IGZO-TFT can reach 10-30cm2 / V·S, which greatly improves the charging and discharging efficiency and response speed of TFT to pixel electrodes. More importantly, the IGZO process has good compatibility with the existing a-Si production line, and has a lower investment cost than low-temperature polycrystalline silicon (LTPS), which has a more complex production process and higher equipment investment.

[0003] Active matrix organic light emitting diode AMOLED is considered to be the next generation mainstream display technology due to its advantages such as high response, high contrast and low power consumption. AMOLED is a current driven device. Taking the common 2T1C as an example, the pixel circuit is composed of a switching TFT, a driving TFT and a capacitor. Among them, the switching TFT mainly controls the data input signal, and the driving TFT mainly provides current for the OLED. However, this TFT technology inevitably has abnormal conditions such as threshold voltage drift and uneven threshold voltage, which seriously affects the final OLED display quality.

[0004] In order to solve abnormal phenomena such as threshold voltage drift, multiple TFTs or multiple control signal lines are designed to compensate for the TFTs. Although such a design has played the expected role, the complex circuit architecture and control timing have greatly increased the difficulty of implementing peripheral driving. Summary of the invention

[0005] Therefore, it is necessary to provide a new TFT structure design to reduce the offset and thus solve the problem of unstable light emission in the existing circuit.

[0006] To achieve the above-mentioned purpose, the inventor provides a dual-gate structure pixel circuit, including a gate layer, the gate layer is patterned into a first gate layer and a second gate layer, a gate insulating layer and a first semiconductor layer are arranged above the first gate layer, a gate insulating layer and a second semiconductor layer are arranged above the second gate layer, a barrier layer is also arranged above the first semiconductor layer and the second semiconductor layer, a first via is also arranged above the first semiconductor, the first via penetrates the barrier layer to expose the first semiconductor layer; a second through hole and a third through hole are arranged above the second gate layer, the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer, the barrier layer also includes an electrode metal layer, the electrode metal layer is patterned to include a first conductive portion connected to the first semiconductor layer through the first via hole and connected to the second gate layer through the second through hole, and a second top gate portion is arranged above the barrier layer on the second semiconductor layer and extends to connect to the second gate layer through the third through hole.

[0007] Specifically, a first through hole is provided above the first gate layer, and the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer;

[0008] The electrode metal layer is further patterned to include a first top gate portion disposed above the barrier layer on the first semiconductor layer and extending to pass through the first through hole to connect with the first gate layer.

[0009] A method for manufacturing a dual-gate structure pixel circuit comprises the following steps:

[0010] A patterned gate layer, wherein the gate layer is patterned into a first gate layer and a second gate layer;

[0011] forming a gate insulating layer on the gate layer, and then patterning a semiconductor layer on the gate insulating layer, wherein the semiconductor layer includes a first semiconductor layer disposed above the first gate layer, and a second semiconductor layer disposed above the second gate layer;

[0012] Forming a barrier layer above the first semiconductor layer and the second semiconductor layer, and etching a first via hole in the barrier layer above the first semiconductor, wherein the first via hole penetrates the barrier layer to expose the first semiconductor layer; etching a second through hole and a third through hole in the gate insulating layer and the barrier layer above the second gate layer, wherein the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer;

[0013] An electrode metal layer is formed on the barrier layer and patterned, wherein the electrode metal layer is patterned to include a first conductive portion connected to the first semiconductor layer through a first via hole and to the second gate layer through a second through hole, and a second top gate portion arranged above the barrier layer on the second semiconductor layer and extending to connect to the second gate layer through a third through hole.

[0014] Specifically, a first through hole is provided above the first gate layer, and the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer;

[0015] The electrode metal layer is further patterned to include a first top gate portion disposed above the barrier layer on the first semiconductor layer and extending to pass through the first through hole to connect with the first gate layer.

[0016] Different from the prior art, the above technical solution forms a dual-gate TFT by patterning the SD layer and a second top gate portion at the same time. This design has higher current and device stability, and avoids uneven brightness of the OLED device due to threshold voltage drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a dual-gate structure pixel circuit according to a specific implementation method;

[0018] Figure 2 A schematic diagram of a BCE type dual-gate structure pixel circuit according to a specific implementation method;

[0019] Figure 3 This is a schematic diagram of an ES-type dual-gate structure pixel circuit described in a specific implementation manner;

[0020] Figure 4 It is a schematic diagram of projection in a direction perpendicular to the substrate according to a specific implementation method;

[0021] Figure 5 Schematic diagram of an equivalent circuit described in a specific implementation manner. DETAILED DESCRIPTION

[0022] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0023] See also Figure 1, a dual-gate structure pixel circuit is shown in stages, including a gate layer GE, which is patterned into a first gate layer GE1 and a second gate layer GE2, as shown in the figure. Then after stages ② and ③, we can see that a gate insulating layer GI and a first semiconductor layer SE1 are arranged above the first gate layer, and a gate insulating layer GI and a second semiconductor layer SE2 are arranged above the second gate layer. In the fourth stage, a barrier layer ES is also arranged above the first semiconductor layer SE1 and the second semiconductor layer SE2, and a first via hole DC4 is also arranged at the barrier layer above the first semiconductor, and the first via hole penetrates the barrier layer to expose the first semiconductor layer; at the same time, we can see that a second through hole DC2 and a third through hole DC3 are arranged above the second gate layer on the right side, and the second through hole and the third through hole are both arranged to penetrate the gate insulating layer and the barrier layer to expose the second gate layer. In the fifth stage, we can see that the barrier layer also includes an electrode metal layer SD, and the electrode metal layer is patterned to include a first conductive portion SD3 connected to the first semiconductor layer through the first through hole DC4 and connected to the second gate layer through the second through hole DC2, and a second top gate portion SD2 arranged above the barrier layer on the second semiconductor layer and extending to the second gate layer through the third through hole. Through the above scheme, we design a second top gate portion on the driving TFT where the second gate layer is located, so that the driving TFT works in a dual-gate structure, and the dual-gate structure TFT has better anti-drift characteristics, so that the pixel circuit can better display stably. In other aspects, by sharing the photomask between the top gate and the SD metal layer, the overlap between the top gate and the SD metal layer can be avoided compared to the traditional double gate, eliminating the parasitic capacitance between the top gate and the SD metal layer. Excessive parasitic capacitance will cause a considerable resistance and capacitance load (RC Loading) in the signal transmission process of TFT applied to the driving circuit of the liquid crystal panel, resulting in a decrease in the display quality of the display.

[0024] Others Figure 2 , Figure 3 The embodiment shown also shows that the same dual-gate structure effect can be achieved by different patterning methods, which is the same as the previous embodiment ① to ③. For the specific TFT structure Figure 2 and Figure 3 From the fourth to sixth stages, it was made into BCE type and ES type respectively. Figure 2 and Figure 3 The left half shows the projection in the direction perpendicular to the substrate, and the cross-section direction is AB. The difference is Figure 2 , 3 The embodiments do not adopt Figure 1 The technical solution of setting a first top gate portion on the first semiconductor layer is shown in . Figure 1As shown, a first through hole DC1 is arranged above the first gate layer, and the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer; the electrode metal layer is also patterned to include a first top gate portion SD1 arranged above the barrier layer on the first semiconductor layer and extending to the first through hole DC1 to connect with the first gate layer.

[0025] Figure 4 yes Figure 1 The embodiment shown is a view in a direction perpendicular to the substrate, with the reference section plane being A(A')-B. The connection method between the circuit and the external circuit is also given. In addition to the above structure, the second semiconductor layer is also connected to the capacitor CS through an electrode patterned on the SD layer. Specifically, the top gate and the bottom gate of the switch T1 are connected to the scan through DC1. When the scan signal is turned on, the top gate also acts on T1 to form a dual-gate structure T1. The top gate of the driving TFT (T2) is connected to the bottom gate through DC3. Even when the scan signal is turned off, the voltage maintained by the storage capacitor CS can also turn on the top gate to form a dual-gate structure T2, thereby achieving stable performance of the TFT device.

[0026] Figure 5 Also showed Figure 1 and Figure 2 , 3 It can be seen that the difference lies in whether the first TFT is a double-gate structure.

[0027] For IGZOTFT devices, the dual-gate structure TFT itself has better electrical stability and stronger gate control capability than the traditional single-gate structure TFT device, and the dual-gate structure TFT device is characterized by higher electron mobility and high stability of gate bias and light. In the above invention, Example 1 gives examples of dual-gate structure switching TFT and driving TFT, aiming to improve the charging capacity of the switching TFT to the storage capacitor and the driving TFT to provide a more stable output current. The biggest difference between Example 2 and Example 3 and Example 1 is that the switching TFT is a single-gate structure, but the driving TFT is still a dual-gate structure. The design idea is to consider that the driving TFT has higher requirements for Vth offset stability than the switching TFT. Therefore, without increasing the process conditions, the switching TFT can be designed as a single-gate structure of BCE and ES type respectively. On the other hand, because the driving TFT is the most direct factor affecting the stability of the OLED current, it is best to keep the driving TFT as a dual-gate structure, and the reverse is not very meaningful.

[0028] Similarly, the above embodiments only use the 2T1C circuit as the most basic to illustrate how to more easily achieve the desired dual-gate structure in terms of process and design. The main purpose is to use a dual-gate structure for the driving TFT to control the stability of the current passing through the OLED. Based on the switching TFT and the driving TFT, more complex circuits (such as 7T1C) can be developed, and not only can a compensation circuit be added, but the design concept of the present invention can also be used to further control the positive and negative drift of the driving TFT Vth to achieve current stability.

[0029] Furthermore, in Figure 1 In the embodiment shown, the inventor also provides a method for manufacturing a dual-gate structure pixel circuit, comprising the following steps:

[0030] ①GE process: patterned gate layer GE, the gate layer is patterned into a first gate layer and a second gate layer; the material can be selected from composite materials such as Mo, Al, and Ti.

[0031] ②GI process: forming a gate insulating layer GI on the gate layer.

[0032] ③SE process: patterning a semiconductor layer SE on the gate insulating layer, wherein the SE may be IGZO. The semiconductor layer includes a first semiconductor layer disposed above the first gate layer, and a second semiconductor layer disposed above the second gate layer;

[0033] ④ES process: forming a barrier layer ES above the first semiconductor layer and the second semiconductor layer, and etching a first via hole in the barrier layer above the first semiconductor, wherein the first via hole penetrates the barrier layer to expose the first semiconductor layer; etching a second through hole and a third through hole in the gate insulating layer and the barrier layer above the second gate layer, wherein the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer;

[0034] ⑤SD process: An electrode metal layer SD is formed on the barrier layer and patterned. The material can be a composite material such as Mo, Al, Ti, etc. The electrode metal layer is patterned to include a first conductive portion connected to the first semiconductor layer through a first via hole and to the second gate layer through a second through hole, and a second top gate portion arranged above the barrier layer on the second semiconductor layer and extending to the second gate layer through a third through hole.

[0035] ⑥PV process: Finally, an insulating layer PV is formed. The material of PV and ES can be silicon oxide.

[0036] The method may further specifically include the steps of providing a first through hole above the first gate layer, wherein the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer;

[0037] The electrode metal layer is further patterned to include a first top gate portion disposed above the barrier layer on the first semiconductor layer and extending to pass through the first through hole to connect with the first gate layer.

[0038] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A dual-gate pixel circuit, It is characterized in that The invention comprises a gate layer, wherein the gate layer is patterned into a first gate layer and a second gate layer, wherein a gate insulating layer and a first semiconductor layer are arranged above the first gate layer, a gate insulating layer and a second semiconductor layer are arranged above the second gate layer, a barrier layer is also arranged above the first semiconductor layer and the second semiconductor layer, a first via hole is also arranged above the first semiconductor, the first via hole penetrates the barrier layer to expose the first semiconductor layer; a second through hole and a third through hole are arranged above the second gate layer, the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer, the barrier layer also comprises an electrode metal layer, the electrode metal layer is patterned to include a first conductive portion connected to the first semiconductor layer through the first via hole and connected to the second gate layer through the second through hole, and a second top gate portion is arranged above the barrier layer on the second semiconductor layer and extends to connect to the second gate layer through the third through hole.

2. The dual-gate structure pixel circuit according to claim 1, It is characterized in that A first through hole is disposed above the first gate layer, and the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer; The electrode metal layer is further patterned to include a first top gate portion disposed above the barrier layer on the first semiconductor layer and extending to pass through the first through hole to connect with the first gate layer.

3. A method for manufacturing a dual-gate pixel circuit, It is characterized in that The following steps are included: A patterned gate layer, wherein the gate layer is patterned into a first gate layer and a second gate layer; forming a gate insulating layer on the gate layer, and then patterning a semiconductor layer on the gate insulating layer, wherein the semiconductor layer includes a first semiconductor layer disposed above the first gate layer, and a second semiconductor layer disposed above the second gate layer; Forming a barrier layer above the first semiconductor layer and the second semiconductor layer, and etching a first via hole in the barrier layer above the first semiconductor, wherein the first via hole penetrates the barrier layer to expose the first semiconductor layer; etching a second through hole and a third through hole in the gate insulating layer and the barrier layer above the second gate layer, wherein the second through hole and the third through hole both penetrate the gate insulating layer and the barrier layer to expose the second gate layer; An electrode metal layer is formed on the barrier layer and patterned, wherein the electrode metal layer is patterned to include a first conductive portion connected to the first semiconductor layer through a first via hole and to the second gate layer through a second through hole, and a second top gate portion arranged above the barrier layer on the second semiconductor layer and extending to connect to the second gate layer through a third through hole.

4. The method for manufacturing a dual-gate pixel circuit according to claim 3, It is characterized in that A first through hole is disposed above the first gate layer, and the first through hole penetrates the gate insulating layer and the barrier layer to expose the first gate layer; The electrode metal layer is further patterned to include a first top gate portion disposed above the barrier layer on the first semiconductor layer and extending to pass through the first through hole to connect with the first gate layer.

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