Storage device

Abstract

A storage device includes an address generator that generates a first physical address and a second physical address different from the first physical address. A first nonvolatile memory includes the first physical address, and a second nonvolatile memory includes the second physical address. An attack detection circuit detects whether the first nonvolatile memory and the second nonvolatile memory are under attack. The attack detection circuit receives first data from the first nonvolatile memory and second data from the second nonvolatile memory, compares the first data and the second data, and determines whether the first nonvolatile memory and the second nonvolatile memory are under attack based on the comparison result of the first and second data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0018418 filed on February 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a storage device and system, and more particularly to a storage device and system having an enhanced security function for preventing data from being leaked to the outside or preventing program code from being altered. Background Art

[0004] As technology develops, storage devices and systems are used in various fields. However, data requiring high security, such as personal information, needs to be stored in storage devices with enhanced security functions.

[0005] Secure storage devices (such as smart cards) can handle data requiring security, such as cryptographic keys, sensitive data, and sensitive code. However, errors may occur in this data due to external attacks or problems with the secure storage device. For example, data stored in a secure storage device may be leaked through fault attacks that repeatedly inject errors using lasers or X-rays, or by altering program code, potentially causing significant problems. Summary of the Invention

[0006] Aspects of the present disclosure provide a storage device with enhanced security functionality.

[0007] Aspects of the present disclosure also provide a storage system with enhanced security capabilities.

[0008] According to some aspects of the present disclosure, a storage device includes: an address generator that generates a first physical address and a second physical address different from the first physical address; a first non-volatile memory that includes the first physical address; a second non-volatile memory that includes the second physical address; and an attack detection circuit that detects whether the first non-volatile memory and the second non-volatile memory are under attack. The attack detection circuit receives first data from the first non-volatile memory and second data from the second non-volatile memory, compares the first data and the second data, and determines whether the first non-volatile memory and the second non-volatile memory are under attack based on the comparison result of the first data and the second data.

[0009] According to some aspects of the present disclosure, a storage device includes a first non-volatile memory and a second non-volatile memory. A processor receives an identifier, first data associated with the identifier, and a write request for the first data. The processor generates a first logical address using the identifier. An address generator generates a first physical address corresponding to the first logical address and a second physical address corresponding to the first logical address and different from the first physical address. In response to the write request for the first data, the processor stores the first data at the first physical address in the first non-volatile memory and stores the first data at the second physical address in the second non-volatile memory.

[0010] According to some aspects of the present disclosure, a storage device includes: (1) a first non-volatile memory in which first data is stored at a first physical address corresponding to a first identifier, and (2) a second non-volatile memory in which second data different from the first data is stored at a second physical address corresponding to the first identifier and different from the first physical address. An attack detection circuit detects whether the first non-volatile memory and the second non-volatile memory are under attack. A processor receives a read request for data corresponding to the first identifier. In response to the read request, the processor accesses the first physical address of the first non-volatile memory to read third data associated with the first data, and accesses the second physical address of the second non-volatile memory to read fourth data associated with the second data. The attack detection circuit receives the third data and the fourth data, and determines whether the first non-volatile memory and the second non-volatile memory are under attack based on the third data and the fourth data.

[0011] According to some aspects of the present disclosure, a storage system includes a host and a storage device. The storage device includes a first non-volatile memory and a second non-volatile memory. In response to a data read request received from the host, the storage device compares first data stored at a first physical address of the first non-volatile memory with second data stored at a second physical address of the second non-volatile memory. The storage device determines whether the first non-volatile memory and the second non-volatile memory are under attack based on the comparison result of the first and second data. The first and second physical addresses are different from each other.

[0012] According to one aspect of the present disclosure, a storage device includes a nonvolatile memory that stores data, and a nonvolatile memory controller that controls read, write, and erase operations of the nonvolatile memory. In response to receiving a read request and an address identifier from a host external to the storage device, a processor instructs the nonvolatile memory controller to determine whether first data stored at a first physical address of the nonvolatile memory associated with the address identifier corresponds to second data stored at a second physical address of the nonvolatile memory associated with the address identifier. In response to determining that the first data does not correspond to the second data, the processor refuses to provide information represented by each of the first and second data to the host. The first physical address is different from and does not overlap with the second physical address.

[0013] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0015] Figure 1 is an exemplary diagram for explaining a storage system according to some embodiments.

[0016] Figure 2 is an exemplary diagram for explaining a storage device according to some embodiments.

[0017] Figure 3 is an exemplary diagram illustrating a processor according to some embodiments.

[0018] Figure 4 and Figure 5 is an exemplary diagram for illustrating an address generator according to some embodiments.

[0019] Figure 6 is an exemplary diagram for illustrating an attack detection circuit according to some embodiments.

[0020] Figure 7 and Figure 8 is an exemplary diagram illustrating a write operation of a memory system and a memory device according to some embodiments.

[0021] Figures 9 to 12 is an exemplary diagram for explaining a read operation of a memory system and a memory device according to some embodiments.

[0022] Figure 13 is an exemplary diagram for explaining a storage device according to some embodiments.

[0023] Figure 14 is an exemplary diagram for explaining a write operation of a memory system and a memory device according to some embodiments.

[0024] Figure 15 is an exemplary diagram for explaining a read operation of a memory system and a memory device according to some embodiments. DETAILED DESCRIPTION

[0025] Figure 1 is an exemplary diagram for explaining a storage system according to some embodiments.

[0026] Reference Figure 1 , a storage system according to some embodiments may include a host 200 and a storage device 100. The storage system according to some embodiments may be implemented as a personal computer (PC), a workstation, a data center, an Internet data center (IDC), a storage area network (SAN), a network attached storage (NAS), or a mobile computing device, but the embodiments are not limited thereto.

[0027] The mobile computing device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital camcorder, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, a credit card system, a radio frequency identification (RFID) device, an e-book device, etc., but the embodiments are not limited thereto.

[0028] The host 200 can be connected to the storage device 100. The host 200 can request the storage device 100 to process data. For example, the host 200 can request the storage device 100 to perform a read operation, a write operation, an erase operation, or an update operation of the data. The storage device 100 can perform an operation corresponding to the request of the host 200, and data can be exchanged between the host 200 and the storage device 100. For example, when data needs to be written in the storage device 100, the host 200 can provide the data to be written and an identifier associated with the data to be written together with a data write request to the storage device 100. The storage device 100 can determine the location to write the data based on the identifier and can store the data at that location. In another example, when data stored in the storage device 100 needs to be read, the host 200 provides the identifier associated with the data to be read together with the data read request to the storage device 100. The storage device 100 can respond to the data read request of the host 200 by the following steps: (1) determining the storage location of the data to be read based on the received identifier; (2) reading the data from the location; and (3) providing the data to the host 200. Figure 2 .

[0029] Figure 2 is an exemplary diagram for explaining a storage device according to some embodiments.

[0030] Reference Figure 2 According to some embodiments, a storage device 100 may include a host interface (I / F) 110, a processor 120, a buffer memory 130, an address generator 140, a non-volatile memory (NVM) controller 150, a first non-volatile memory (NVM_1) 160_1, a second non-volatile memory (NVM_2) 160_2, and an attack detection circuit 170.

[0031] The host interface 110 may include a protocol for performing data exchange between the host 200 and the storage device 100. For example, the host interface 110 may communicate with the host 200 through at least one of wireless protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-E (PCI-express) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, a non-volatile memory express (NVMe) protocol, an integrated drive electronics (IDE) protocol, and a radio frequency identification (RFID) protocol. However, embodiments are not limited thereto, and the host interface 110 may communicate with the host 200 using various protocols other than the above-mentioned protocols. In other words, the host interface 110 may perform a function of providing a path through which data, requests, or responses are exchanged between the host 200 and the storage device 100.

[0032] The processor 120 may execute a program code for controlling the storage device 100. For example, the processor 120 may execute a program code for performing a data write operation or a data read operation according to a request from the host 200.

[0033] The processor 120 according to some embodiments may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microprocessor unit (MPU), etc., but the embodiment is not limited thereto. For additional description of the processor 120, refer to Figure 3 .

[0034] Figure 3 is an exemplary diagram illustrating a processor according to some embodiments.

[0035] Reference Figure 3 The processor 120 may include an identifier conversion module 122 , a data protection module 124 , and a command (CMD) control module 126 .

[0036] The identifier conversion module 122 may generate a first logical address LA using the identifier received from the host 200. According to some embodiments, when the identifier includes logical address information, the identifier conversion module 122 may output the logical address information included in the identifier as the first logical address LA. According to some other embodiments, when the identifier does not include logical address information, the identifier conversion module 122 may output a predetermined logical address corresponding to the identifier as the first logical address LA.

[0037] For example, if the identifier received from the host 200 includes the logical address "0001," the identifier conversion module 122 may output "0001" as the first logical address LA. In another example, if the identifier received from the host 200 indicates "password," the identifier conversion module 122 may output "0010," a predetermined logical address corresponding to "password," as the first logical address LA. Although the logical address has been described as 4-bit data, this is merely an exemplary description, and embodiments are not limited thereto. The logical address may be implemented in various sizes, such as 16 bits, 64 bits, and 256 bits.

[0038] Data protection module 124 may perform data protection operations for first non-volatile memory 160_1 and second non-volatile memory 160_2. According to some embodiments, when an attack detection signal (ADS) is generated from attack detection circuit 170, data protection module 124 may perform data protection operations for first non-volatile memory 160_1 and second non-volatile memory 160_2. Data protection operations by data protection module 124 may include preventing external leakage of data by deleting first data Data_1 and second data Data_2 stored in first non-volatile memory 160_1 and second non-volatile memory 160_2, or preventing external leakage of data by not responding to a data read request from host 200.

[0039] The command control module 126 may provide a data processing command to the nonvolatile memory controller 150 in response to an external request. For example, the command control module 126 may provide a data write command to the nonvolatile memory controller 150 in response to a data write request from the host 200. In another example, the command control module 126 may provide a data read command to the nonvolatile memory controller 150 in response to a data read request from the host 200. However, embodiments are not limited to the above operations, and the command control module 126 may provide commands for performing various operations (e.g., background operations, erase operations, etc.) to the nonvolatile memory controller 150.

[0040] Refer again Figure 2, the buffer memory 130 can be a memory for temporarily storing data. For example, the processor 120 can temporarily store data received from the host 200 in the buffer memory 130 in response to a data write request from the host 200. In another example, the processor 120 can temporarily store data read from the first non-volatile memory 160_1 and the second non-volatile memory 160_2 in the buffer memory 130 in response to a data read request from the host 200. According to some embodiments, the buffer memory 130 can be implemented as a static random access memory (SRAM), a fast SRAM and / or a dynamic RAM (DRAM), etc., but the embodiment is not limited thereto. In some drawings, the buffer memory 130 is shown as being implemented as an independent component, but the embodiment is not limited thereto. For example, the buffer memory 130 may also be included in the processor 120 and may also be included in the non-volatile memory controller 150.

[0041] The address generator 140 may generate a first physical address PA_1 and a second physical address PA_2 using the first logical address LA generated by the processor 120. Hereinafter, for ease of description, the physical address of the first nonvolatile memory 160_1 is defined as the first physical address PA_1, and the physical address of the second nonvolatile memory 160_2 is defined as the second physical address PA_2. The physical location of the first physical address PA_1 and the physical location of the second physical address PA_2 are different from each other. In other words, the first physical address PA_1 and the second physical address PA_2 are different physical addresses from each other. An exemplary illustration of the address generator 140 is shown with reference to FIG. Figure 4 and Figure 5 .

[0042] Figure 4 and Figure 5 is an exemplary diagram for illustrating an address generator according to some embodiments.

[0043] First, refer to Figure 4 According to some embodiments, the address generator 140 may include a first lookup table 141 and a second lookup table 142. The first lookup table 141 may be associated with the first non-volatile memory 160_1. In other words, the first lookup table 141 may include a correspondence between the first logical address LA and the first physical address PA_1 of the first non-volatile memory 160_1. Similarly, the second lookup table 142 may be associated with the second non-volatile memory 160_2. In other words, the second lookup table 142 may include a correspondence between the first logical address LA and the second physical address PA_2 of the second non-volatile memory 160_2.

[0044] According to some embodiments, the first logical address LA and the first physical address PA_1 may be randomly matched, and the first logical address LA and the second physical address PA_2 may be randomly matched. For example, the address generator 140 generates a random number to generate the first physical address PA_1 and the second physical address PA_2, and each of the first physical address PA_1 and the second physical address PA_2 may be matched with the first logical address LA to generate the first lookup table 141 and the second lookup table 142.

[0045] According to some embodiments, processor 120 may convert a received identifier into a first logical address LA and provide the first logical address LA to address generator 140. Address generator 140 may use the received first logical address LA, first lookup table 141, and second lookup table 142 to generate first physical address PA_1 and second physical address PA_2. For example, when processor 120 receives LA#0 as the first logical address LA, address generator 140 may determine first physical address PA_1 of first non-volatile memory 160_1 as PA#35 by referring to first lookup table 141. Furthermore, when processor 120 receives LA#0 as the first logical address LA, address generator 140 may determine second physical address PA_2 of second non-volatile memory 160_2 as PA#5 by referring to second lookup table 142. However, it should be understood that this description is merely an example and embodiments are not limited thereto. As can be seen in the above example, first physical address PA_1 and second physical address PA_2 are different addresses.

[0046] Reference Figure 5 According to some embodiments, the address generator 140 may include a first address operator 143 and a second address operator 144. The first address operator 143 may receive a first logical address LA and a predetermined first physical address generation code PAC_1. Similarly, the second address operator 144 may receive a first logical address LA and a predetermined second physical address generation code PAC_2. The first physical address generation code PAC_1 and the second physical address generation code PAC_2 may be different from each other.

[0047] For example, it will be assumed that the address generator 140 receives the first logical address LA (i.e., "1111") from the processor 120. In this case, the description will be made assuming that the first physical address generation code PAC_1 is "0010" and the second physical address generation code PAC_2 is "0011." Furthermore, the first address operator 143 and the second address operator 144 will be assumed to be XOR operators. These examples are for ease of description and can be implemented in various ways by a person skilled in the art.

[0048] "1111," the first logical address LA, may be input to the first address operator 143. At this time, the first address operator 143 performs an XOR operation on "1111" and "0010," the predetermined first physical address generation code PAC_1. The output of the first address operator 143 may be "1101." That is, the first physical address PA_1 generated by the address generator 140 may be "1101." Similarly, "1111," the first logical address LA, may also be input to the second address operator 144. At this time, the second address operator 144 performs an XOR operation on "1111" and "0011," the predetermined second physical address generation code PAC_2. The output of the second address operator 144 may be "1100." That is, the second physical address PA_2 generated by the address generator 140 may be "1100." As described above, the first physical address PA_1 and the second physical address PA_2 generated by the address generator 140 may be different from each other.

[0049] Refer again Figure 2 The nonvolatile memory controller 150 may be configured to provide an interface between the first nonvolatile memory 160_1, the second nonvolatile memory 160_2, the host interface 110, the processor 120, the buffer memory 130, and the address generator 140. Furthermore, the nonvolatile memory controller 150 may be configured to drive firmware for controlling the first nonvolatile memory 160_1 and the second nonvolatile memory 160_2. For example, the nonvolatile memory controller 150 may provide a chip enable signal, a write enable signal, a read enable signal, and the like to the first nonvolatile memory 160_1 and the second nonvolatile memory 160_2. The nonvolatile memory controller 150 may control data input to and output from the first nonvolatile memory 160_1 and the second nonvolatile memory 160_2 in accordance with various commands (e.g., write commands, read commands, etc.) from the processor 120. Even though the drawings show that the processor 120 and the non-volatile memory controller 150 are separated from each other, the embodiment is not limited thereto. For example, in some other embodiments, the non-volatile memory controller 150 may be omitted, and the processor 120 may perform the operations of the non-volatile memory controller 150 described above.

[0050] First data Data_1 may be stored at a first physical address PA_1 of first nonvolatile memory 160_1. Furthermore, second data Data_2 may be stored at a second physical address PA_2 of second nonvolatile memory 160_2. The first data Data_1 and the second data Data_2 may be provided to attack detection circuit 170 under the control of nonvolatile memory controller 150.

[0051] The first nonvolatile memory 160_1 and the second nonvolatile memory 160_2 may be the same type of nonvolatile memory, or may be different types of nonvolatile memory. The first nonvolatile memory 160_1 and the second nonvolatile memory 160_2 may include flash memory, resistive RAM (RRAM), phase change memory (PRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), spin injection magnetization reversal memory (Spin STT-RAM), etc., but the embodiment is not limited to these examples.

[0052] Although the first non-volatile memory 160_1 and the second non-volatile memory 160_2 are shown as being separated from each other in some figures, embodiments are not limited thereto. According to some embodiments, the first non-volatile memory 160_1 and the second non-volatile memory 160_2 may represent different regions of the same memory. For example, the first non-volatile memory 160_1 may be a single-level cell (SLC) region of a flash memory, and the second non-volatile memory 160_2 may be a multi-level cell (MLC) region of the same flash memory. A person of ordinary skill in the art may use various methods and strategies to appropriately implement the first non-volatile memory 160_1 and the second non-volatile memory 160_2.

[0053] In addition, although the memory device 100 according to some embodiments has been illustrated as including two nonvolatile memories, examples are not limited thereto. For example, the memory device 100 according to some embodiments may include three or more nonvolatile memories.

[0054] Although not shown in the drawings, the nonvolatile memory controller 150, the first nonvolatile memory 160_1 and / or the second nonvolatile memory 160_2 according to some embodiments may be mounted using packages such as package-on-package technology (POP), ball grid array (BGA), chip scale package (CSP), plastic chip carrier with leads (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in chip form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP) and wafer-level processing stack package (WSP), but the embodiments are not limited thereto.

[0055] The nonvolatile memory controller 150, the first nonvolatile memory 160_1, and the second nonvolatile memory 160_2 may be integrated into a single semiconductor device. For example, the nonvolatile memory controller 150, the first nonvolatile memory 160_1, and the second nonvolatile memory 160_2 may be integrated into a single semiconductor device to form a memory card. For example, the nonvolatile memory controller 150, the first nonvolatile memory 160_1, and the second nonvolatile memory 160_2 may be integrated into a single semiconductor device to form a memory card, such as a PC card (PCMCIA, Personal Computer Memory Card International Association), a flash memory card (CF), a smart media card (SM, SMC), a smart card, a memory stick, a multimedia card (MMC, RS-MMC, and MMCmicro), an SD card (SD, miniSD, microSD, and SDHC), and a universal flash memory (UFS).

[0056] The attack detection circuit 170 can use the first data Data_1 received from the first non-volatile memory 160_1 and the second data Data_2 received from the second non-volatile memory 160_2 to detect whether the first non-volatile memory 160_1 and the second non-volatile memory 160_2 are attacked. The attack detection circuit 170 can generate an attack detected signal (ADS) or an attack not detected signal (ANDS) based on the detection result. Figure 6 .

[0057] Figure 6 is an exemplary diagram for illustrating an attack detection circuit according to some embodiments.

[0058] Reference Figure 6, the attack detection circuit 170 may include a comparator 171. The first nonvolatile memory 160_1 may provide the first data Data_1 stored at the first physical address PA_1 to the comparator 171 of the attack detection circuit 170. Similarly, the second nonvolatile memory 160_2 may provide the second data Data_2 stored at the second physical address PA_2 to the comparator 171 of the attack detection circuit 170.

[0059] The comparator 171 compares the received first data Data_1 with the second data Data_2 and may generate one of an attack detected signal (ADS) and an attack not detected signal (ANDS) based on the comparison result. According to some embodiments, if the first data Data_1 and the second data Data_2 are different from each other, the comparator 171 may generate an attack detected signal (ADS). On the other hand, if the first data Data_1 and the second data Data_2 are the same, the comparator 171 may generate an attack not detected signal (ANDS). The comparator 171 may be implemented using, for example, an XOR operator or an XNOR operator, but embodiments are not limited thereto. That is, according to some embodiments, the attack detection circuit 170 may use the first data Data_1 received from the first non-volatile memory 160_1 and the second data Data_2 received from the second non-volatile memory 160_2 to determine whether the first non-volatile memory 160_1 and the second non-volatile memory 160_2 have been attacked.

[0060] Refer again Figure 2 , the attack detection circuit 170 may generate one of an attack detected signal (ADS) and an attack not detected signal (ANDS) and provide it to the non-volatile memory controller 150. The non-volatile memory controller 150 may output data to the processor 120 or transmit an attack detection alarm to the processor 120 according to the signal received from the attack detection circuit 170. The processor 120 may perform a data protection operation upon receiving the attack detection alarm.

[0061] According to some embodiments, the storage device 100 may be a storage device with enhanced security features. For example, the storage device 100 may be a credit card in which the first non-volatile memory 160_1 and the second non-volatile memory 160_2 are implemented as a smart card with a very important security feature. However, embodiments are not limited thereto, and according to some embodiments, the storage device 100 may be used in a host server, for example, where security features are determined to be important. A person skilled in the art of the present disclosure may implement the storage device 100 described in some embodiments to improve security features in various fields and achieve its purpose.

[0062] Although the storage device 100 according to some embodiments is shown as having the host interface 110, the processor 120, the buffer memory 130, the address generator 140, and the non-volatile memory controller 150 interconnected with each other through a bus, this is only for exemplary description, and the connection relationship between the components is not limited to these examples. For example, it is a matter of course that the processor 120 and the address generator 140 can be directly connected, or the attack detection circuit 170 and the processor 120 can be directly connected. A person skilled in the art of the present disclosure can implement some embodiments of the present disclosure by changing the connection relationship as needed. In the following, Figures 7 to 12 Specific operations of a storage system and a storage device according to some embodiments are described.

[0063] Figure 7 and Figure 8 FIG1 is an exemplary diagram illustrating a write operation of a storage system and a storage device according to some embodiments. For the sake of convenience, the same or similar contents as those described above will be omitted or briefly described.

[0064] Reference Figure 7 and Figure 8 , the processor 120 may receive a data write request, data to be written, and an identifier associated with the data to be written from the host 200 (S710). As previously mentioned, the identifier may include or may not include a logical address.

[0065] The processor 120 may convert the received identifier into a first logical address LA (S720). For example, the identifier conversion module 122 of the processor 120 may generate the first logical address LA based on the identifier received from the host 200. The first logical address LA generated by the processor 120 may be provided to the address generator 140.

[0066] The address generator 140 may generate a first physical address PA_1 and a second physical address PA_2 using the received first logical address LA ( S730 ).

[0067] For example, if the address generator 140 utilizes the first lookup table 141 and the second lookup table 142, the address generator 140 may generate a random number to generate the first physical address PA_1 and the second physical address PA_2. Subsequently, the address generator 140 may match the received first logical address LA with the generated first physical address PA_1 to generate the first lookup table 141. Similarly, the address generator 140 may match the received first logical address LA with the generated second physical address PA_2 to generate the second lookup table 142.

[0068] For example, if the address generator 140 utilizes a first physical address generation code PAC_1 and a second physical address generation code PAC_2, the address generator 140 may provide the first logical address LA and the first physical address generation code PAC_1 to the first address operator 143 to generate the first physical address PA_1. Similarly, the address generator 140 may provide the first logical address LA and the second physical address generation code PAC_2 to the second address operator 144 to generate the second physical address PA_2. As described above, the first physical address PA_1 and the second physical address PA_2 have physically different locations.

[0069] According to some embodiments, the first physical address PA_1 and the second physical address PA_2 generated by the address generator 140 may be provided to the processor 120 again. However, the embodiment is not limited thereto. For example, the first physical address PA_1 and the second physical address PA_2 may not be provided to the processor 120, but may be provided to the non-volatile memory controller 150.

[0070] The processor 120 may provide the data to be written, the first physical address PA_1 and the second physical address PA_2, and a write command Write CMD to the nonvolatile memory controller 150. The nonvolatile memory controller 150 may store the data to be written as first data Data_1 at the first physical address PA_1 of the first nonvolatile memory 160_1. In addition, the nonvolatile memory controller 150 may store the data to be written as second data Data_2 at the second physical address PA_2 of the second nonvolatile memory 160_2 (S740).

[0071] According to some embodiments, since the data to be written can be stored as first data Data_1 and second data Data_2 in first non-volatile memory 160_1 and second non-volatile memory 160_2, respectively, in principle, the first data Data_1 and second data Data_2 can be identical to each other. That is, in principle, the first data Data_1 stored at the first physical address PA_1 of first non-volatile memory 160_1 can be identical to the second data Data_2 stored at the second physical address PA_2 of second non-volatile memory 160_2. In other words, according to some embodiments, data with the same content can be stored at different physical addresses of the non-volatile memory.

[0072] Figures 9 to 12 FIG1 is an exemplary diagram for explaining a read operation of a storage system and a storage device according to some embodiments. For the sake of convenience, the same or similar contents as those described above will be omitted or briefly described.

[0073] Reference Figures 9 to 12 , the processor 120 may receive a data read request and an identifier associated with data to be read from the host 200 ( S910 ).

[0074] The processor 120 may convert the received identifier into a first logical address LA (S920). For example, the identifier conversion module 122 of the processor 120 may generate the first logical address LA based on the identifier received from the host 200. The first logical address LA generated by the processor 120 may be provided to the address generator 140.

[0075] The address generator 140 may generate a first physical address PA_1 and a second physical address PA_2 using the received first logical address LA ( S930 ).

[0076] For example, if the address generator 140 utilizes the first and second lookup tables 141 and 142 , the address generator 140 may generate the first and second physical addresses PA_1 and PA_2 matching the first logical address LA by referring to the first and second lookup tables 141 and 142 .

[0077] For example, if the address generator 140 uses the first physical address generation code PAC_1 and the second physical address generation code PAC_2, the address generator 140 may provide the first logical address LA and the first physical address generation code PAC_1 to the first address operator 143 to generate the first physical address PA_1. Similarly, the address generator 140 may provide the first logical address LA and the second physical address generation code PAC_2 to the second address operator 144 to generate the second physical address PA_2. As described above, the first physical address PA_1 and the second physical address PA_2 have different physical addresses from each other.

[0078] According to some embodiments, the first and second physical addresses PA_1 and PA_2 generated by the address generator 140 may be provided again to the processor 120. However, embodiments are not limited thereto, and the first and second physical addresses PA_1 and PA_2 may be provided directly to the nonvolatile memory controller 150 without passing through the processor 120.

[0079] The processor 120 may provide the first and second physical addresses PA_1 and PA_2, along with a read command Read CMD, to the nonvolatile memory controller 150. The nonvolatile memory controller 150 may access the first physical address PA_1 of the first nonvolatile memory 160_1 to read the first data Data_1. Similarly, the nonvolatile memory controller 150 may access the second physical address PA_2 of the second nonvolatile memory 160_2 to read the second data Data_2.

[0080] The read first data Data_1 and second data Data_2 may be provided to the attack detection circuit 170. The attack detection circuit 170 may compare the provided first data Data_1 with the provided second data Data_2 (S940).

[0081] If the first data Data_1 and the second data Data_2 provided by the attack detection circuit 170 are different from each other (S950, No), the attack detection circuit 170 may generate an attack detection signal (ADS) (S960). The attack detection circuit 170 may provide the generated attack detection signal (ADS) to the non-volatile memory controller 150. However, the embodiment is not limited thereto, for example, the attack detection signal (ADS) may be provided directly to the processor 120. If the non-volatile memory controller 150 receives the attack detection signal (ADS), the non-volatile memory controller 150 may generate an attack detection alarm and provide it to the processor 120. The processor 120 may perform a data protection operation upon receiving the attack detection alarm (S970). In other words, if the attack detection signal (ADS) is generated in the attack detection circuit 170, the processor 120 may perform a data protection operation (S970).

[0082] According to some embodiments, the data protection operation (S970) may be an operation for preventing the first data Data_1 stored in the first non-volatile memory 160_1 and the second data Data_2 stored in the second non-volatile memory 160_2 from leaking to the outside. For example, the data protection operation (S970) may include deleting the first data Data_1 stored at the first physical address PA_1 of the first non-volatile memory 160_1 and deleting the second data Data_2 stored at the second physical address PA_2 of the second non-volatile memory 160_2. In another example, the data protection operation may include an operation in which the processor 120 does not respond to a data read request from the host 200.

[0083] If the first data Data_1 and the second data Data_2 provided by the attack detection circuit 170 are identical (S950, Yes), the attack detection circuit 170 may generate an attack not detected signal (ANDS) (S980). The generated attack not detected signal (ANDS) is provided to the non-volatile memory controller 150, and the non-volatile memory controller 150 may access one of the first physical address PA_1 of the first non-volatile memory 160_1 and the second physical address PA_2 of the second non-volatile memory 160_2 to output one of the first data Data_1 and the second data Data_2. In other words, if the attack detection circuit 170 generates the attack not detected signal (ANDS), one of the first data Data_1 and the second data Data_2 may be provided to the processor 120 (S990).

[0084] When the attack not detected signal (ANDS) is generated, the nonvolatile memory controller 150 may determine which of the first data Data_1 or the second data Data_2 to provide to the processor 120 according to various situations and policies. For example, if the first nonvolatile memory 160_1 has a faster response speed than the second nonvolatile memory 160_2, the nonvolatile memory controller 150 may provide the first data Data_1 to the processor 120 when the attack not detected signal (ANDS) is received. In another example, if the first nonvolatile memory 160_1 is a single-level cell region of a flash memory and the second nonvolatile memory 160_2 is a multi-level cell region of the flash memory, the nonvolatile memory controller 150 may provide the first data Data_1 to the processor 120 when the attack not detected signal (ANDS) is received. However, these descriptions are merely illustrative, and embodiments are not limited thereto.

[0085] An attacker may launch a physical attack on first non-volatile memory 160_1 and / or second non-volatile memory 160_2 to obtain desired data or change program code. For example, an attacker may irradiate first non-volatile memory 160_1 and / or second non-volatile memory 160_2 with a laser beam. When a physical attack is launched on first non-volatile memory 160_1 and / or second non-volatile memory 160_2, first data Data_1 and / or second data Data_2 stored in first non-volatile memory 160_1 and / or second non-volatile memory 160_2 may be partially altered. For example, if first data Data_1 is an "encrypted password," a physical attack on first non-volatile memory 160_1 may cause the first data Data_1 to become an "unencrypted password." In another example, in the case where the first data Data_1 is a program code of “blocking connection when external connection is found”, the first data Data_1 may become a program code of “providing data if external connection is found” through a physical attack on the first nonvolatile memory 160_1 .

[0086] According to some embodiments, the same data (e.g., the data to be written described above) is stored at each of the first physical address PA_1 of first non-volatile memory 160_1 and the second physical address PA_2 of second non-volatile memory 160_2. Therefore, even if an attacker attacks first non-volatile memory 160_1 to obtain desired data or change program code, the attack is not applied to second non-volatile memory 160_2. Therefore, even if the first data Data_1 is changed by the attacker, the second data Data_2 is unchanged and an attack detection signal (ADS) is generated, thereby preventing data leakage or program code changes.

[0087] Let's assume an attacker attacks both first non-volatile memory 160_1 and second non-volatile memory 160_2 simultaneously. According to some embodiments, because first physical address PA_1 and second physical address PA_2 are different, only one of first data Data_1 and second data Data_2 may be affected by the attack. Ultimately, because only one of first data Data_1 and second data Data_2 is altered (i.e., processor 120 performs a data protection operation), the attacker may be unable to obtain desired data or alter program code.

[0088] Depending on the type of attack (for example, depending on the size of the laser beam), there may be a situation where both the first data Data_1 and the second data Data_2 are affected by the attack. However, even in this case, since the first physical address PA_1 and the second physical address PA_2 are different from each other, each of the first data Data_1 and the second data Data_2 may be affected differently by the attack. For example, the first data Data_1 may be completely changed by the attack, while the second data Data_2 may be only partially changed by the attack. Therefore, even when both the first data Data_1 and the second data Data_2 are changed, since the first data Data_1 and the second data Data_2 are different from each other, an attack detection signal (ADS) is generated, and ultimately the attacker may not be able to obtain the desired data or change the program code. That is, even if the attacker attacks the first non-volatile memory 160_1 and the second non-volatile memory 160_2 at the same time, the leakage of data and the change of program code can still be prevented.

[0089] Figure 13 is an exemplary diagram for explaining a storage device according to some embodiments. Figure 14 is an exemplary diagram for explaining a write operation of a memory system and a memory device according to some embodiments. Figure 15 FIG1 is an exemplary diagram for explaining a read operation of a storage system and a storage device according to some embodiments. For the sake of convenience, similar or repeated contents of the above contents will be omitted or briefly described.

[0090] Reference Figure 1 and Figure 13 According to some embodiments, a storage device 100 may include a host interface (I / F) 110, a processor 120, a buffer memory 130, an address generator 140, a non-volatile memory (NVM) controller 150, a first non-volatile memory (NVM_1) 160_1, a second non-volatile memory (NVM_2) 160_2, an attack detection circuit 170, a first error correction circuit 180_1, and a second error correction circuit 180_2.

[0091] The first error correction circuit 180_1 can be connected to the first non-volatile memory 160_1, and the second error correction circuit 180_2 can be connected to the second non-volatile memory 160_2. Although the first error correction circuit 180_1 and the second error correction circuit 180_2 are shown in the drawings as being separate from the non-volatile memory controller 150, embodiments are not limited thereto. For example, the first error correction circuit 180_1 and the second error correction circuit 180_2 can be included in the non-volatile memory controller 150. Furthermore, although the first error correction circuit 180_1 and the second error correction circuit 180_2 are shown in the drawings as separate components, embodiments are not limited thereto. For example, the first error correction circuit 180_1 and the second error correction circuit 180_2 can be implemented as a single error correction circuit.

[0092] The first error correction circuit 180_1 can be used to detect whether data stored in the first non-volatile memory 160_1 contains errors. Furthermore, when data is stored in the first non-volatile memory 160_1 (i.e., when data is written), the first error correction circuit 180_1 can generate a first error correction code (ECC_1) for error detection. Similarly, the second error correction circuit 180_2 can be used to detect whether data stored in the second non-volatile memory 160_2 contains errors. Furthermore, when data is stored in the second non-volatile memory 160_2, the second error correction circuit 180_2 can generate a second error correction code (ECC_2) for error detection. For example, the first error correction code (ECC_1) and the second error correction code (ECC_2) can be parity bits, Hamming codes, etc., but embodiments are not limited thereto.

[0093] First non-volatile memory 160_1 can store first data Data_1 and a first error correction code ECC_1 generated by first error correction circuit 180_1. In some embodiments, the area storing first data Data_1 can be different from the area storing first error correction code ECC_1, but embodiments are not limited thereto. Similarly, second non-volatile memory 160_2 can store second data Data_2 and a second error correction code ECC_2 generated by second error correction circuit 180_2.

[0094] Reference Figure 1 、 Figure 13 and Figure 14 , the processor 120 may receive data to be written and an identifier associated with the data to be written, and a data write request from the host 200 ( S1410 ).

[0095] The processor 120 may generate a first logical address LA from the received identifier ( S1420 ).

[0096] The generated first logical address LA is provided to the address generator 140 , and the address generator 140 may generate a first physical address PA_1 and a second physical address PA_2 using the first logical address LA ( S1430 ).

[0097] The first physical address PA_1 and the second physical address PA_2 are again provided to the processor 120 , and the processor 120 may provide the data to be written, the first physical address PA_1 and the second physical address PA_2 , and the data write command together to the nonvolatile memory controller 150 .

[0098] The data to be written is provided to the first error correction circuit 180_1 and the second error correction circuit 180_2, and the first error correction circuit 180_1 and the second error correction circuit 180_2 can respectively generate a first error correction code ECC_1 and a second error correction code ECC_2 using the data to be written (S1435). According to some embodiments, the first error correction code ECC_1 and the second error correction code ECC_2 can be the same as each other.

[0099] The nonvolatile memory controller 150 stores the data to be written as first data Data_1 at the first physical address PA_1 of the first nonvolatile memory 160_1 and may store the generated first error correction code ECC_1 in a specific area of ​​the first nonvolatile memory 160_1. In addition, the nonvolatile memory controller 150 stores the data to be written as second data Data_2 at the second physical address PA_2 of the second nonvolatile memory 160_2 and may store the generated second error correction code ECC_2 in the specific area of ​​the second nonvolatile memory 160_2 (S1440).

[0100] Refer again Figure 1 、 Figure 13 and Figure 15 , the processor 120 receives an identifier associated with data to be read and a data read request from the host 200 ( S1510 ).

[0101] The processor 120 converts the received identifier into a first logical address LA ( S1520 ), the first logical address LA is provided to the address generator 140 , and may generate a first physical address PA_1 and a second physical address PA_2 ( S1530 ).

[0102] The first physical address PA_1 and the second physical address PA_2 may be provided to the processor 120. The processor 120 may provide the first physical address PA_1 and the second physical address PA_2 along with a read command to the non-volatile memory controller 150. The non-volatile memory controller 150 reads the first data Data_1 stored at the first physical address PA_1 of the first non-volatile memory 160_1 and may provide it to the first error correction circuit 180_1. Furthermore, the non-volatile memory controller 150 also reads the first error correction code ECC_1 from the first non-volatile memory 160_1 and may provide it to the first error correction circuit 180_1. Similarly, the non-volatile memory controller 150 reads the second data Data_2 stored at the second physical address PA_2 of the second non-volatile memory 160_2 and may provide it to the second error correction circuit 180_2. In addition, the nonvolatile memory controller 150 also reads the second error correction code ECC_2 from the second nonvolatile memory 160_2 and may provide it to the second error correction circuit 180_2.

[0103] The first error correction circuit 180_1 can use the first error correction code ECC_1 and the first data Data_1 to detect and correct errors in the first data Data_1. Similarly, the second error correction circuit 180_2 can use the second error correction code ECC_2 and the second data Data_2 to detect and correct errors in the second data Data_2 (S1535). For ease of description, the error-corrected first data Data_1 and the error-corrected second data Data_2 are defined as third data Data_3 and fourth data Data_4, respectively. The third data Data_3 and the fourth data Data_4 can be provided to the attack detection circuit 170. The attack detection circuit 170 can receive the third data Data_3 and the fourth data Data_4 and compare them (S1540).

[0104] If the third data Data_3 and the fourth data Data_4 are different from each other (S1550, No), the attack detection circuit 170 generates an attack detection signal (ADS) (S1560) and may provide it to the non-volatile memory controller 150. The non-volatile memory controller 150 may provide an attack detection alert to the processor 120 upon receiving the attack detection signal (ADS). The processor 120 may perform a data protection operation upon receiving the attack detection alert (S1570). In other words, when the attack detection signal (ADS) is generated, the processor 120 may perform a data protection operation.

[0105] If the third data Data_3 and the fourth data Data_4 are identical to each other (S1550, Yes), the attack detection circuit 170 generates an attack not detected signal (ANDS) (S1580) and may provide it to the non-volatile memory controller 150. Upon receiving the attack not detected signal (ANDS), the non-volatile memory controller 150 may provide one of the third data Data_3 and the fourth data Data_4 to the processor 120 (S1590). The processor 120 receives one of the third data Data_3 and the fourth data Data_4 and provides it to the host 200, thereby responding to the data read request from the host 200. In other words, when the attack not detected signal (ANDS) is generated, the processor 120 may provide one of the third data Data_3 and the fourth data Data_4 to the outside.

[0106] According to some embodiments, even if the first data Data_1 and / or the second data Data_2 are altered by an attacker, the data can be restored to the original data through the first error correction circuit 180_1 and the second error correction circuit 180_2. If the data is restored, the attacker ultimately does not receive the desired data. There are cases where the first error correction circuit 180_1 and the second error correction circuit 180_2 may be unable to restore the data. However, in this case, since the first data Data_1 and the second data Data_2 are different from each other as described above, and the processor 120 performs a data protection operation, data leakage and program code alteration can be prevented.

[0107] According to some embodiments, if the first data Data_1 stored in the first non-volatile memory 160_1 and the second data Data_2 stored in the second non-volatile memory 160_2 are different from each other, the processor 120 may perform a data protection operation. However, depending on the situation, the first data Data_1 and / or the second data Data_2 may be changed due to reasons other than an attacker's attack. Even in this case, the processor 120 may perform a data protection operation, but this may not be the intended operation. Therefore, according to some embodiments, the storage device 100 further includes a first error correction circuit 180_1 and a second error correction circuit 180_2 to effectively prevent attacks from attackers and prevent the execution of unintended data protection operations.

[0108] As is conventional in the art, embodiments can be described and illustrated according to the blocks that perform one or more functions described. These blocks, referred to herein as units or modules, are physically implemented by analog circuits and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, storage circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, and the like, and can optionally be driven by firmware and / or software. The circuit can be, for example, embodied in one or more semiconductor chips, or embodied on substrate supports such as printed circuit boards. The circuits constituting the blocks can be implemented by dedicated hardware or by a processor (for example, one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware that performs certain functions of the block and a processor that performs other functions of the block. Without departing from the scope of this disclosure, each block of the embodiment can be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of this disclosure, the blocks of the embodiment can be physically combined into more complex blocks. One aspect of the embodiment can be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0109] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed preferred embodiments of the present disclosure are intended to be general and descriptive only and not for the purpose of limitation.

Claims

1. A storage device comprising: an address generator, the address generator generating a first physical address and a second physical address different from the first physical address; a first non-volatile memory, the first non-volatile memory comprising the first physical address; a second non-volatile memory, the second non-volatile memory comprising the second physical address; a first error correction circuit connected to the first nonvolatile memory; a second error correction circuit connected to the second nonvolatile memory; as well as an attack detection circuit, wherein the attack detection circuit detects whether the first non-volatile memory and the second non-volatile memory are attacked, The first non-volatile memory and the second non-volatile memory include a first error correction code and a second error correction code, respectively. the first error correction circuit generates first data using the data stored in the first physical address and the first error correction code, the second error correction circuit generates second data using the data stored in the second physical address and the second error correction code, The attack detection circuit receives the first data from the first non-volatile memory, The attack detection circuit receives the second data from the second non-volatile memory, The attack detection circuit compares the first data and the second data with each other, and The attack detection circuit determines whether the first non-volatile memory and the second non-volatile memory are attacked according to a comparison result of the first data and the second data.

2. The storage device according to claim 1, wherein: When the first data and the second data are different from each other, the attack detection circuit determines that the first nonvolatile memory and the second nonvolatile memory are attacked, and When the first data and the second data are identical to each other, the attack detection circuit determines that the first nonvolatile memory and the second nonvolatile memory are not attacked.

3. The storage device according to claim 1, further comprising: A processor that performs data protection operations, wherein The attack detection circuit generates an attack detection signal when the first data and the second data are different from each other.

4. The storage device according to claim 3, wherein: When the attack detection signal is generated, the processor performs the data protection operation, and The data protection operation includes deleting data stored at the first physical address and deleting data stored at the second physical address.

5. The storage device according to claim 3, wherein: When the attack detection signal is generated, the processor performs the data protection operation, and The data protection operation includes not responding to an external data read request.

6. The storage device according to claim 1, further comprising: A processor that receives a first identifier and a read request for the first identifier, wherein: The processor converts the first identifier into a first logical address and provides the first logical address to the address generator.

7. The storage device according to claim 6, wherein: The address generator operates the first logical address and a first physical address generation code to generate the first physical address, and The address generator operates the first logical address and the second physical address generation code to generate the second physical address.

8. The storage device according to claim 6, wherein: The address generator generates the first physical address using the first logical address and a first lookup table, and The address generator generates the second physical address using the first logical address and a second lookup table.

9. The storage device according to claim 1, further comprising: A processor, the processor receiving a data read request, wherein: When the first data and the second data are identical to each other, the attack detection circuit generates an attack not detected signal, and When the attack-not-detected signal is generated, the processor outputs one of the first data and the second data.

10. The storage device according to claim 9, wherein: The first non-volatile memory is a single-level cell area of ​​a flash memory, The second nonvolatile memory is a multi-level cell region of a flash memory, and When the attack-not-detected signal is generated, the processor outputs the first data.

11. The storage device according to claim 1 , further comprising: a processor that receives a second identifier, third data associated with the second identifier, and a write request for the third data, wherein: The address generator generates a third physical address and a fourth physical address different from the third physical address from the second identifier, and In response to a write request for the third data: The processor stores the third data at the third physical address of the first non-volatile memory, and The processor stores the third data at the fourth physical address of the second nonvolatile memory.

12. A storage device comprising: a first nonvolatile memory and a second nonvolatile memory; a processor that receives an identifier, first data associated with the identifier, and a write request for the first data, and generates a first logical address using the identifier; an address generator configured to generate a first physical address corresponding to the first logical address and a second physical address corresponding to the first logical address and different from the first physical address; a first error correction circuit connected to the first nonvolatile memory, the first error correction circuit generating a first error correction code for correcting errors of the first data using the first data; as well as a second error correction circuit connected to the second nonvolatile memory, the second error correction circuit generating a second error correction code for correcting errors in the first data using the first data, Wherein: in response to a write request for the first data: The processor stores the first data at the first physical address of the first non-volatile memory, and The processor stores the first data at the second physical address of the second non-volatile memory.

13. The storage device according to claim 12, wherein: The address generator generates a random number to generate the first physical address and the second physical address, The address generator generates a first lookup table by matching the first logical address with the first physical address, and The address generator generates a second lookup table by matching the first logical address with the second physical address.

14. The storage device according to claim 12, wherein: The address generator operates the first logical address and a first physical address generation code to generate the first physical address, and The address generator operates the first logical address and the second physical address generation code to generate the second physical address.

15. The storage device according to claim 12, wherein The identifier does not include information about the first physical address and the second physical address.

16. The storage device according to claim 12, wherein: The first nonvolatile memory and the second nonvolatile memory are separated from each other.

17. A storage device comprising: a first non-volatile memory in which first data is stored at a first physical address corresponding to the first identifier; a second nonvolatile memory, in which second data different from the first data is stored at a second physical address corresponding to the first identifier and different from the first physical address; a first error correction circuit connected to the first nonvolatile memory; a second error correction circuit connected to the second nonvolatile memory; an attack detection circuit, configured to detect whether the first non-volatile memory and the second non-volatile memory are attacked; as well as a processor that receives a read request for data corresponding to the first identifier, The first non-volatile memory and the second non-volatile memory include a first error correction code and a second error correction code, respectively. In response to the read request: the processor accessing the first physical address of the first nonvolatile memory to read third data associated with the first data, the third data being generated by the first error correction circuit using the first data and the first error correction code, The processor accesses the second physical address of the second nonvolatile memory to read fourth data associated with the second data, the fourth data being generated by the second error correction circuit using the second data and the second error correction code, and The attack detection circuit receives the third data and the fourth data and determines whether the first nonvolatile memory and the second nonvolatile memory are attacked based on the third data and the fourth data.

18. The storage device according to claim 17, wherein: In response to the read request: The first nonvolatile memory provides the first data as the third data to the attack detection circuit, and The second nonvolatile memory provides the second data as the fourth data to the attack detection circuit, The attack detection circuit generates an attack detected signal, and When the attack detection signal is generated, the processor performs a data protection operation of the first nonvolatile memory and the second nonvolatile memory.

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