Method for forming semiconductor device and structure thereof

Abstract

The present invention is entitled "Methods of Forming Semiconductor Devices and Structures Thereof." In one embodiment, a differential buffer may include a first input stage that alternately compares a non-inverting portion of an input signal with a non-inverting portion of an output and with an inverting portion of the output. Another embodiment of the differential buffer may also include a second input stage that alternately compares an inverting portion of the input signal with an inverting portion of the output signal and a non-inverting portion of the output signal. Other embodiments of the differential buffer may include a feedback chopping switch that transmits the non-inverting portion and the inverting portion of the output signal to the first input stage and the second input stage.

Description

[0001] Priority claim to an existing provisional application

[0002] This application claims priority to provisional application No. 62 / 806,524, filed on February 15, 2019, entitled “Chopping Technique to Reduce Kick-Back Disturbance,” which has docket number ONS3314L01US and co-inventors Daniels et al., and is hereby incorporated by reference into this application. Background Art

[0003] The present invention relates generally to electronic devices and, more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices.

[0004] The semiconductor industry has historically utilized various methods and structures to create circuits for measuring various types of input signals. Some applications utilize chopper-stabilized amplifiers as part of their systems to improve measurement accuracy. Some chopper-stabilized amplifiers can cause variations in the input signal, often resulting in a circuit delay of a certain period to allow the input signal to stabilize. In some applications, chopping must be performed at a relatively low frequency to avoid loss of measurement accuracy.

[0005] Accordingly, it is desirable to have a circuit or method that improves the accuracy of measuring a signal, reduces the delay of signal measurement, or reduces interference with an input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 schematically shows an example of an embodiment of a part of a system according to the invention;

[0007] Figure 2 schematically shows an example of an embodiment of a portion of a differential buffer according to the present invention;

[0008] Figure 3 Schematically shows the Figure 2 An example of an embodiment of a portion of a differential buffer having another operating state;

[0009] Figure 4 schematically illustrates an example of part of an embodiment of a differential amplifier according to the present invention; and

[0010] Figure 5 The invention includes Figure 1 or Figure 2 An enlarged plan view of a differential buffer semiconductor device.

[0011] For clarity and simplicity of illustration, the elements in the figures are not necessarily drawn to scale, some elements may be exaggerated for schematic illustration, and unless otherwise specified, the same reference numerals in different figures indicate the same elements. In addition, for simplicity of description, descriptions and details of well-known steps and elements may be omitted. As used herein, a current-carrying element or current-carrying electrode means an element of a device that carries current through the device, such as the source or drain of a MOS transistor or the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, while a control element or control electrode means an element of a device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. In addition, one current-carrying element may carry current through the device in one direction, such as carrying current into the device, while a second current-carrying element may carry current through the device in the opposite direction, such as carrying current out of the device. Although the device may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, it will be understood by those skilled in the art that complementary devices according to the present invention are also possible. Those skilled in the art understand that conductivity type refers to the mechanism by which conduction occurs, such as conduction by holes or electrons. Thus, conductivity type does not refer to doping concentration but rather to doping type, such as P-type or N-type. Those skilled in the art will understand that the terms "during," "simultaneously," and "when" used herein in connection with circuit operation do not necessarily mean that an action occurs immediately after the initiating action, but rather that there may be some small but reasonable delay, such as various propagation delays, between the initial action and the reaction triggered. Additionally, the term "simultaneously" means that an action occurs at least for a period of time during the duration of the initiating action. The use of the words "approximately" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor variations that prevent the value or position from being exactly as stated. It is recognized in the art that deviations of up to at least ten percent (10%) (and for some elements, including semiconductor doping concentrations, up to twenty percent (20%)) are reasonable deviations from the ideal goal of being exactly as stated. When used with respect to signal states, the term "active" means the valid state of a signal, while the term "inactive" means the inactive state of a signal. The actual voltage value or logic state (such as "1" or "0") of the signal depends on whether positive logic or negative logic is used. Thus, if positive logic is used, a high voltage or high logic may be active, and if negative logic is used, a low voltage or low logic may be active; whereas if positive logic is used, a low voltage or low state may be inactive, and if negative logic is used, a high voltage or high logic may be inactive. In this document, the positive logic convention is used, but those skilled in the art understand that the negative logic convention may also be used.The terms "first", "second", "third", etc. in the claims and / or detailed description (as used in part of an element name) are used to distinguish between similar elements and do not necessarily describe an order in time, space, level or in any other manner. It should be understood that the terms so used are interchangeable where appropriate, and that the embodiments described herein are capable of operating in other orders than those described or illustrated herein. Reference to "one embodiment" means that the particular features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, but in some cases, may refer to the same embodiment. In addition, as will be apparent to one of ordinary skill in the art, in one or more embodiments, the specific features, structures or characteristics may be combined in any suitable manner.

[0012] The embodiments to be illustrated and described hereinafter may have embodiments and / or may be practiced in the absence of any element not specifically disclosed herein. DETAILED DESCRIPTION

[0013] Figure 1 An example of a portion of an embodiment of a measurement system 10 including a measurement channel 18 is schematically shown. System 10 receives a signal to be measured from a signal transmitting device 11. System 10 includes input 13 and input 14 configured to receive a differential input signal from device 11. For example, input 13 can be configured to receive the non-inverting portion of the differential input signal, and input 14 can be configured to receive the inverting portion of the differential input signal. Channel 18 can have an embodiment configured to receive the differential input signal and measure its value.

[0014] Channel 18 may have an embodiment that includes a low-pass filter 20, a differential buffer 30, an analog-to-digital conversion circuit 31, and other circuitry (OC) 32 that facilitates forming an output signal at output 16 that represents a measured characteristic of a differential input signal received between input 13 and input 14. For example, output 16 may have a digital signal having a certain number of bits representing a numerical value.

[0015] An embodiment of filter 20 may include a non-inverting portion of filter 20, which may include resistor 22 and capacitor 21, and an inverting portion of filter 20, which may include resistor 23 and capacitor 24. An embodiment of filter 20 may have a cutoff frequency established by the combined values ​​of resistor 22 and capacitor 21, and the combined values ​​of resistor 23 and capacitor 24. Filter 20 may have other embodiments, such as a cascade of RC filters that may form a higher-order passive filter.

[0016] Figure 2 An example of a portion of an embodiment of a differential buffer 35 is schematically shown, which may have a Figure 1 Buffer 35 includes a non-inverting input 26 configured to receive the non-inverting portion (INp) of the differential input signal from filter 20, and also includes an inverting input 27 configured to receive the inverting portion (INn) of the differential input signal from filter 20.

[0017] Buffer 35 includes an input stage or circuit 50, an input stage or circuit 58, and an output stage or circuit 64. Circuit 50 and circuit 58 can each have an embodiment that can be formed as a differential input amplifier, and output stage 64 can have an embodiment that can be formed as an output amplifier. For example, circuit 50, circuit 58, and circuit 64 can have a differential pair embodiment. Buffer 35 can also include a feedback chopping switch or switch 36, a positive input chopping switch or switch 44, and a negative input chopping switch or switch 52. Adding circuit or adder 61 and adding circuit or adder 62 can also be included in the embodiment of buffer 35. Buffer 35 is configured to form a differential output signal that includes a non-inverting output signal (OTp) at a non-inverting output 65 and also includes an inverting output signal (OTn) at an inverting output 66. Buffer 35 is configured such that the DC gain of the signal from inputs 26 and 27 to outputs 65 and 66 is substantially unity. In some embodiments, buffer 35 may have unity gain for frequencies less than the bandwidth of buffer 35 .

[0018] Buffer 35 may also have an embodiment that includes a common-mode adjustment circuit 70 for adjusting the common-mode portion of the output signal formed by buffer 35. Circuit 70 includes an input stage or input circuit 71, an input stage or input circuit 72, an adding circuit or adder 73, another adding circuit or adder 74, and a subtracting circuit or subtractor 75. Input stage 71 and input stage 72 may have an embodiment that may be formed as differential input amplifiers similar to circuits 50 and 58.

[0019] Switches 36, 44, and 52 are formed as differential chopping switches, each receiving a differential signal and alternately applying portions of the differential signal to different differential outputs of the switch. Thus, each of switches 36, 44, and 52 comprises an active or selector switch. Switch 36 comprises selector switches 39-42, switch 44 comprises selector switches 45-48, and switch 52 comprises selector switches 53-56. The sequence of alternately applying portions of the received differential signal to different outputs of the switches is described herein as different operating states or phases. One embodiment of buffer 35 is configured to operate in two operating states or phases, referred to herein as Phase I and Phase II. Buffer 35 is configured to selectively enable and disable corresponding selector switches, thereby routing the input signal to different outputs for each of the Phase I and Phase II conditions. Those skilled in the art will recognize that the enabled and disabled states of the selector switches are controlled so that the selector switches operate in non-overlapping enabled states. Thus, there may be a short non-overlapping interval between the Phase I state and the Phase II state (and another short non-overlapping interval between Phase II and Phase I) during which all of the select switches may be disabled or open. Those skilled in the art will appreciate that each of Phase I and Phase II may have time intervals during which certain select switches are enabled or closed and other switches are disabled or open, these time intervals not including the non-overlapping intervals. The frequency at which the circuit changes between Phase I and Phase II (or vice versa) is often referred to as the chopping frequency.

[0020] Figure 2 shows the condition of the selector switch in phase 1 operation or phase 1, and Figure 3 The condition of the selector switch in phase II operation or phase II is shown.

[0021] As will be seen further below, switch 36 is configured to receive the non-inverting output signal (OTp) as a first feedback signal and the inverting output signal (OTn) as a second feedback signal from circuit 64, and selectively transmit one of these feedback signals to circuit 50 via switch 44, and transmit a different one of these feedback signals to circuit 58 via switch 52. Furthermore, as will be seen further below, the embodiment of buffer 35 is formed such that, during both Phase I and Phase II, circuit 50 receives the non-inverting portion (INp) of the input signal from input 26, and circuit 58 receives the inverting portion (INn) of the input signal from input 27. Moreover, as will be further seen below, the embodiment of buffer 35 is formed so that, during phase I, circuit 50 receives any first of the non-inverting output (OTp) signal or the inverting output (OTn) signal from circuit 64, and circuit 58 receives the opposite of the non-inverting or inverting output signals from circuit 64; and during phase II, circuit 50 receives the opposite of the non-inverting or inverting output signal, and circuit 58 receives the first of the non-inverting output signal or the inverting output signal from circuit 64.

[0022] See the example of the embodiment of Phase I. Figure 2 , buffer 35 is configured to selectively enable circuit 44 to pass the non-inverting input (INp) signal from input 26 to the non-inverting input of circuit 50. For example, buffer 35 can be configured to selectively enable switch 45 and disable switch 46 to facilitate this transfer. Circuit 36 ​​is also selectively enabled to pass the non-inverting output signal (OTp) of amplifier 64 to circuit 44, and circuit 44 is selectively enabled to pass the non-inverting output (OTp) signal to the inverting input of circuit 50. Thus, switch 39 is selectively enabled and switch 40 is selectively disabled, and switch 47 is selectively enabled and switch 48 is selectively disabled to facilitate transfer to the inverting input of circuit 50.

[0023] Buffer 35 is also configured to selectively enable circuit 52 to pass the inverted input signal (INn) from input 27 to the inverting input of circuit 58. Thus, switch 55 is selectively enabled by buffer 35 and switch 56 is selectively disabled by buffer 35 to facilitate this transfer. Furthermore, circuit 36 ​​is selectively enabled to pass the inverted output (OTn) signal to circuit 52, and circuit 52 is selectively enabled to pass the inverted output (OTn) signal to the non-inverting input of circuit 58. Thus, switch 41 is selectively enabled and switch 42 is selectively disabled, and switch 53 is selectively enabled and switch 54 is selectively disabled to facilitate transfer to the non-inverting input of circuit 58.

[0024] Circuit 50 receives a non-inverting input signal (INp) and a non-inverting output signal (OTp) and forms a differential output signal 51. Circuit 58 receives an inverting input signal (INn) and an inverting output signal (OTn) and forms a differential output signal 59. Adder 61 receives the non-inverting portion of output signal 51 from circuit 50 and the non-inverting portion of output signal 59 from circuit 58, adds the two signals together, and applies the resulting signal to the non-inverting input of circuit 64. Similarly, adder 62 receives the inverting portion of output signal 51 from circuit 50 and the inverting portion of output signal 59 from circuit 58, adds the two signals together, and applies the resulting signal to the inverting input of circuit 64.

[0025] During Phase I, circuit 71 receives a positive input (INp) signal and receives the same signal from circuit 64 as that received by circuit 50, forming a differential output signal. Circuit 72 receives an inverting input (INn) signal and receives the same signal from circuit 64 as that received by circuit 58, forming another differential output signal. In one embodiment, circuit 72 receives a signal of opposite polarity to that received by circuit 58 during Phase I, and circuit 71 receives a signal of opposite polarity to that received by circuit 50 during Phase II. Adder 73 receives the non-inverting portions of the output signals from circuits 71 and 72, adds them together, and forms a first result signal. Adder 74 receives the inverted portions of the output signals from circuits 71 and 72, adds them together, and forms a second result signal. Subtractor 75 receives the two result signals and subtracts them to form a common-mode control signal 76. One embodiment may include subtractor 75 subtracting the first result signal from adder 73 from the second result signal from adder 74 to form signal 76. Signal 76 is a control signal used to adjust the common mode voltage from circuit 64 .

[0026] See the example of the embodiment of Phase II. Figure 3 , buffer 35 is configured to selectively enable circuit 44 to pass the non-inverting input (INp) signal from input 26 to the inverting input of circuit 50. Thus, buffer 35 is configured to selectively disable switch 45 and enable switch 46 to facilitate this transfer. Moreover, circuit 36 ​​is selectively enabled to pass the inverted output (OTn) signal to circuit 44, and circuit 44 is selectively enabled to pass the inverted output (OTn) signal to the non-inverting input of circuit 50. Thus, switch 42 is selectively enabled and switch 41 is selectively disabled, while switch 47 is selectively disabled and switch 48 is selectively enabled to facilitate transfer to the non-inverting input of circuit 50.

[0027] Buffer 35 is also configured to selectively enable circuit 52 to pass the inverting input (INn) signal from input 27 to the non-inverting input of circuit 58. Thus, switch 56 is selectively enabled and switch 55 is selectively disabled to facilitate this transfer. In addition, circuit 36 ​​is selectively enabled to pass the non-inverting output (OTp) signal to circuit 52, and circuit 52 is selectively enabled to pass the non-inverting output signal to the inverting input of circuit 58. Thus, switch 40 is selectively enabled and switch 39 is selectively disabled, and switch 54 is selectively enabled and switch 53 is selectively disabled to facilitate transfer to the inverting input of circuit 58.

[0028] Circuit 50 receives a non-inverting input (INp) signal and an inverting output (OTn) signal and forms a differential output signal 51. Circuit 58 receives an inverting input (INn) signal and a non-inverting output (OTp) signal and forms a differential output signal 59. As before, adder 61 receives the non-inverting portions of output signal 51 and output signal 59 from respective circuits 50 and 58, adds the two signals together, and applies the resulting signal to the non-inverting output of circuit 64. Adder 62 receives the inverting portions of output signal 51 and output signal 59 from respective circuits 50 and 58, adds the two signals together, and applies the resulting signal to the inverting input of circuit 64. Adders 61 and 62 facilitate combining the two differential signals to form a single differential signal that can serve as an input to amplifier 64. Adders 61 and 62 also facilitate adding the signals together within buffer 35 and can also avoid the need for external resistors. The implementations of summer 61 and summer 62 form a stabilizing current that is added to or subtracted from the current entering amplifier 64 .

[0029] During Phase II, circuit 71 receives the positive input (INp) signal and receives the same signal from circuit 64 as that received by circuit 50, and forms a differential output signal. Circuit 72 receives the negative input (INn) signal and receives the same signal from circuit 64 as that received by circuit 58, and forms another differential output signal. Adder 73 receives the non-inverting portions of the output signals from circuits 71 and 72, adds them together, and forms a first result signal. Adder 74 receives the inverting portions of the output signals from circuits 71 and 72, adds them together, and forms a second result signal. Subtractor 75 receives the two result signals and subtracts them to form a common-mode signal 76.

[0030] From targeting Figures 2 to 3As can be seen from the operation explained in the circuit configuration, due to the chopping configuration provided by switches 36, 44, and 52, and the substantially unity gain and, alternately, common-mode adjustment circuit 70, the differential output signal from circuit 64, or alternately the feedback signal from circuit 36, is substantially the same value as the differential input signal received between inputs 26 and 27. Consequently, buffer 35 does not substantially interfere with or affect the value of the differential input signal. This does not cause a significant change in the value of the input signal, such as during a transition from Phase I to Phase II (or vice versa). Because the input signal is not disturbed, the time required for the differential output signal to settle to the correct value is greatly reduced. This condition of the output signal affecting the input signal is sometimes referred to as "kickback."

[0031] Additionally, buffer 35 alternately compares the non-inverting output (OTp) signal and the inverting output (OTn) signal to the non-inverting input (INp) signal and the inverting input (INn) signal. As will be appreciated by those skilled in the art, this operation compensates for any offset that may be introduced by buffer 35 and substantially eliminates offset in the differential output signal formed by the non-inverting output (OTp) signal and the inverting output (OTn) signal. One embodiment may include that only slight interference may be introduced into the differential input signal, such as, for example, due to offset in circuits 50 and 58. However, the value of the interference is significantly less than the value of the offset because it is capacitively divided between the capacitance of capacitors 21 and 24 and the parasitic input capacitance of the inputs of circuits 50 and 58. Because the capacitance of capacitors 21 and 24 is significantly greater than the parasitic input capacitance of circuits 50 and 58, signal coupling into the differential input signal is essentially negligible. Consequently, settling time is even further reduced.

[0032] Additionally, because the settling time is reduced, the frequency for selectively operating switches 36, 44, and 52 can be increased for given values ​​of capacitors 21 and 24. For example, in one embodiment, the chopping frequency for Phase I and Phase II operation is greater than the chopping frequency of low pass filter 20 ( Figure 1 ) cutoff frequency. Using a higher chopping frequency for a given cutoff frequency of the low-pass filter allows more inherent noise to be removed from the differential buffer. In addition, for a given chopping frequency, a lower cutoff frequency can be used, resulting in improved filtering of extraneous noise.

[0033] To facilitate providing the functionality described herein, input 26 is commonly connected to a first input of circuit 44 and a non-inverting input of circuit 71. One embodiment may include configuring input 26 to couple to a first RC filter, wherein input 26 can be commonly coupled to a first terminal of first capacitor 21 and a first terminal of first resistor 22. The second terminal of resistor 22 can be coupled to receive the first portion of the differential signal. For example, the second terminal of capacitor 21 can be coupled to a common reference voltage, such as ground. The first input of circuit 44 is commonly connected to a first terminal of switch 45 and a first terminal of switch 46. The second terminal of switch 45 is commonly connected to a first terminal of switch 48 and the non-inverting input of circuit 50. The inverting input of circuit 50 is commonly connected to a second terminal of switch 46 and a first terminal of switch 47. The second terminal of switch 47 is commonly connected to a second terminal of switch 48, the inverting input of circuit 70, and node 37. Node 37 is commonly connected to a first terminal of switch 39 and a first terminal of switch 42. Input 27 is commonly connected to a non-inverting input of circuit 72, a first terminal of switch 56, and a first terminal of switch 55. One embodiment may include configuring input 27 to couple to a second RC filter, wherein input 27 may be configured to be commonly coupled to the first terminal of second capacitor 24 and the first terminal of second resistor 23. The second terminal of resistor 23 may be coupled to receive the second portion of the differential signal. For example, the second terminal of capacitor 24 may be coupled to a common reference voltage, such as ground. The second terminal of switch 55 is commonly connected to the first terminal of switch 54 and the inverting input of circuit 58. The second terminal of switch 56 may be commonly connected to the non-inverting input of circuit 58 and the first terminal of switch 53. The second terminal of switch 53 is commonly connected to the second terminal of switch 54 and node 38. Node 38 is commonly connected to the inverting input of circuit 72, the first terminal of switch 41, and the first terminal of switch 40. The non-inverting output of circuit 50 is connected to the first input of adder 61, and the inverting output of circuit 50 is connected to the first input of adder 62. The second input of adder 62 is connected to the inverting output of circuit 58. The second input of adder 61 is connected to the non-inverting output of circuit 58. The output of adder 61 is connected to the non-inverting input of circuit 64, and the output of adder 62 is connected to the inverting input of circuit 64. The non-inverting output of circuit 64 is commonly connected to output 65, the second terminal of switch 39, and the second terminal of switch 40. The inverting output of circuit 64 is commonly connected to output 66, the second terminal of switch 42, and the second terminal of switch 41. Circuit 71 has a non-inverting output connected to a first input of adder 73 and an inverting output connected to a first input of adder 74. Circuit 72 has a non-inverting output connected to a second input terminal of adder 73 and an inverting output connected to a second input terminal of adder 74.Adder 74 has an output connected to a first input of a subtracter 75, which has a second input connected to the output of adder 73. The output of subtracter 75 is connected to the common mode control input of amplifier 64.

[0034] Figure 4 An example of a portion of an embodiment of a differential amplifier 80 is schematically shown, which may have circuits 50, 58, 64, or 71-72 ( Figures 2 to 3 ). Amplifier 80 includes transistor 81 and transistor 82 configured as a differential pair. Common current source 83 is configured to conduct the sum of the currents flowing through transistor 81 and transistor 82. Current source 84 is connected to form a bias current flowing through transistor 81, and current source 85 is connected to form a bias current flowing through transistor 82.

[0035] Embodiments of amplifier 80 may optionally include that sources 84 and 85 may be variable current sources. For example, current sources 84 and 85 may be configured to respond to the current from circuit 70 ( Figures 2 to 3 ) changes the amount of bias current provided to transistors 81 and 82. Those skilled in the art will recognize that circuits 50, 58, 64, or 71-72 ( Figures 2 to 3 ) may have other embodiments besides that of amplifier 80.

[0036] To help provide the functionality described herein, the gate of transistor 81 can be connected to receive the non-inverting portion of a differential input signal (such as, for example, a signal received by circuits 50, 58, 64, or 71-72), and the gate of transistor 82 can be configured to receive the inverting portion of the differential input signal. The source of transistor 81 can be commonly connected to the source of transistor 82 and a first terminal of current source 83. The second terminal of source 83 can be connected to a common return voltage, such as, for example, a ground reference voltage. The drain of transistor 81 can be commonly connected to the inverting output of circuit 80 and a first terminal of current source 84. The second terminal of current source 84 can be commonly connected to a first terminal of current source 85 and an operating voltage or operating power source for these circuits (such as, for example, a power supply voltage). The second terminal of current source 85 can be commonly connected to the drain of transistor 82 and the non-inverting output of circuit 80. Current source 84 can optionally have an optional control input that is commonly connected to the optional control input of current source 85 and is connected to receive signal 76.

[0037] Figure 5An enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 90 formed on a semiconductor die 91 is shown. In an embodiment, buffer 30 or buffer 35 or channel 18 may be formed on die 91. Die 91 may also include components that are not shown in the figure to simplify the drawing. Figure 5 The device or integrated circuit 90 can be formed on the die 91 by semiconductor manufacturing techniques known to those skilled in the art.

[0038] Based on all of the foregoing, one skilled in the art will recognize that one example of an implementation of a differential buffer may include:

[0039] a first differential input amplifier (such as, for example, amplifier 50) configured to receive both a non-inverting portion of the differential input signal (such as, for example, signal INp) and the first switching signal and to form an output signal comprising a first non-inverting output and a first inverting output;

[0040] a second differential input amplifier (such as, for example, amplifier 58) configured to receive both an inverted portion of the differential input signal (such as, for example, signal INn) and the second switching signal and to form another output signal including a second non-inverting output and a second inverting output;

[0041] an output amplifier (such as, for example, amplifier 64) having a non-inverting input coupled to receive a first signal representing a sum of a first non-inverting output and a second non-inverting output, the output amplifier having an inverting input coupled to receive a second signal representing a sum of a first inverting output and a second inverting output, the output amplifier being configured to form a differential output signal in response to the first signal and the second signal, wherein the differential output signal includes a non-inverting output signal and an inverting output signal;

[0042] a feedback chopping switch (such as, for example, circuit 36 ​​) configured to receive the non-inverting output signal and the inverting output signal;

[0043] a positive input chopping switch (such as, for example, circuit 44) configured to selectively form the first switching signal into one of a non-inverting output signal or an inverting output signal during a first time interval and selectively form the first switching signal into a different one of the non-inverting output signal or the inverting output signal during a second time interval; and

[0044] A negative input chopping switch (such as, for example, circuit 52) ​​is configured to selectively form the second switching signal as a non-inverting output signal or an inverting output signal, whichever is opposite to what the first switching signal is used as during the first interval, during a first time interval, and selectively form the second switching signal as a non-inverting output signal or an inverting output signal, whichever is opposite to what the first switching signal is used as during the second time interval, during a second time interval.

[0045] Embodiments of the differential buffer may include a positive input chopping switch having a first input configured to receive a non-inverting portion of the differential input signal and having a second input connected to a first output of a feedback chopping switch to receive a first switching signal from the feedback chopping switch.

[0046] In an embodiment, the negative input chopping switch may have a first input configured to receive an inverted portion of the differential input signal and may have a second input connected to the second output of the feedback chopping switch to receive the second switching signal.

[0047] One embodiment may include a feedback chopping switch that may have a first input connected to a non-inverting output of the output amplifier and may have a second input connected to an inverting output of the output amplifier.

[0048] Another embodiment may include a first adder having a first input connected to the first non-inverting output of the first differential input amplifier, a second input connected to the second non-inverting output of the second differential amplifier, and an output connected to the non-inverting input of the output amplifier.

[0049] One embodiment may include a second summer having a first input connected to the first inverting output of the first differential input amplifier, a second input connected to the second inverting output of the second differential input amplifier, and an output connected to the inverting input of the output amplifier.

[0050] In an embodiment, the positive input chopping switch may receive a non-inverting output signal from the feedback chopping switch during a first time interval and may receive an inverting output signal from the feedback chopping switch during a second time interval.

[0051] One embodiment may include a negative input chopping switch that may receive an inverting output signal from a feedback chopping switch during a first time interval and may receive a non-inverting output signal from the feedback chopping switch during a second time interval.

[0052] One embodiment may include a positive input chopping switch having a first output directly connected to a first input of a first differential input amplifier, having a second output directly connected to a second input of the first differential input amplifier, and not connected to a second differential input amplifier.

[0053] Another embodiment may include a negative input chopping switch that may have a first output directly connected to the first input of the second differential input amplifier, may have a second output directly connected to the second input of the second differential input amplifier, and may not be connected to the first differential input amplifier.

[0054] Those skilled in the art will also recognize that examples of implementations of semiconductor devices having differential buffers include:

[0055] a first input stage (such as, for example, circuit 50 ) having a first input and a second input;

[0056] a second input stage (such as, for example, circuit 58 ) having a third input and a fourth input;

[0057] an output stage (such as, for example, circuit 64 ) configured to receive signals from both the first input stage and the second input stage and to responsively form a non-inverting output signal (such as, for example, signal OTp) and an inverting output signal (such as, for example, signal OTn);

[0058] a feedback switch (such as, for example, circuit 36 ​​) configured to receive the non-inverting output signal and the inverting output signal, the feedback switch configured to alternately apply one of the non-inverting output signal or the inverting output signal as a first switching signal to a first output (such as, for example, node 37 ) during a first time interval and a second time interval, and the feedback switch configured to alternately apply the opposite of the non-inverting output signal or the inverting output signal as a second switching signal to a second output (such as, for example, node 38 ) during the first time interval and the second time interval;

[0059] a first switch (such as, for example, circuit 44 ) configured to receive a non-inverting portion of a differential input signal (such as, for example, signal INp), the first switch configured to apply the first signal and the non-inverting portion of the differential input signal to a first input stage (such as, for example, circuit 44 ) during a first time interval and a second time interval; and

[0060] A second switch (such as, for example, circuit 52) ​​configured to receive an inverted portion of a differential input signal (such as, for example, signal INn), the second switch configured to apply a second switching signal and the inverted portion of the differential input signal to a second input stage (58) during a first time interval and a second time interval.

[0061] In an embodiment, the semiconductor device may further include a non-inverting input configured to receive the sum of the non-inverting output of the first input stage and the non-inverting output of the second input stage, and the output stage further includes an inverting input configured to receive the sum of the inverting output of the first input stage and the inverting output of the second input stage.

[0062] Another embodiment may include a first input stage that does not receive an inverted portion of the differential input signal.

[0063] One embodiment may include a first input stage that receives a non-inverting portion of a differential input signal from a first switch on a first input during a first time interval and receives a non-inverting portion of the differential input signal from the first switch on a second input during a second time interval.

[0064] Those skilled in the art will also recognize that examples of embodiments of methods of forming differential buffers may include:

[0065] configuring a first input stage (such as, for example, circuit 50) to receive a first of a non-inverting output of the output stage (such as, for example, signal OTp) or an inverting output of the output stage (such as, for example, signal OTn) during a first time interval and to receive the opposite of the non-inverting output or the inverting output during a second time interval, wherein the first input stage receives a non-inverting portion of a differential input signal (such as, for example, signal INp) during the first time interval and during the second time interval; and

[0066] A second input stage (such as, for example, circuit 58) is configured to receive the opposite of the non-inverting output or the inverting output during a first time interval and to receive the first of the non-inverting output or the inverting output during a second time interval, wherein the second input stage receives an inverted portion of the differential input signal during the first time interval and during the second time interval.

[0067] Embodiments of the method may also include configuring a feedback switch (such as, for example, circuit 36) to receive a non-inverting output and an inverting output and to transmit a first of the non-inverting output or the inverting output to the first input stage during a first time interval (such as, for example, phase I) and to transmit the opposite of the non-inverting output or the inverting output to the second input stage during the first time interval.

[0068] The method may also have an embodiment that may include configuring the feedback switch to transmit the opposite of the non-inverting output or the inverting output to the first input stage during a second time interval (such as, for example, phase II), and to transmit the first of the non-inverting output or the inverting output to the second input stage during the second time interval.

[0069] One embodiment may include configuring a first switch (such as, for example, circuit 44) to apply the non-inverting portion of the differential input signal to the first input stage during both the first time interval and the second time interval, while applying the non-inverting output to the first input stage during the first time interval and applying the inverting output to the input stage during the second time interval.

[0070] One embodiment may include configuring the output stage to simultaneously receive outputs from the first input stage and the second input stage on the first input during the first time interval and the second time interval.

[0071] Another embodiment may include configuring the differential buffer to be preceded by an RC filter, wherein a cutoff frequency of the RC filter is less than a chopping frequency of the differential buffer.

[0072] Those skilled in the art will also recognize that examples of embodiments of methods of forming differential buffers may include:

[0073] configuring the differential buffer as a chopping buffer operating at a chopping frequency;

[0074] An RC filter is coupled before the differential buffer, wherein a cutoff frequency of the RC filter is lower than the chopping frequency.

[0075] Another embodiment may include configuring the output stage to receive signals from the first input stage and from the second input stage without a chopping switch interposed between the output of the first input stage and the input of the output stage.

[0076] In view of all of the foregoing, it is apparent that a novel device and method are disclosed. Among other features, this includes forming a differential buffer having a shortened settling time. The differential buffer includes a first input stage that alternately compares a non-inverting portion of an input signal with a non-inverting portion of an output and with an inverting portion of the output. The differential buffer also includes a second input stage that alternately compares an inverting portion of the input signal with an inverting portion of an output signal and a non-inverting portion of the output signal. One embodiment includes a feedback chopper switch that transmits the non-inverting portion of the output signal and the inverting portion of the output signal to the first input stage and the second input stage. One embodiment of the differential buffer is formed such that no chopper stage is present between the outputs of the two input stages and the input of the output amplifier stage.

[0077] Although the subject matter of this specification has been described through specific preferred embodiments and exemplary embodiments, the foregoing drawings and description of this specification merely depict typical and non-limiting examples of the embodiments of the subject matter and are therefore not to be considered as limiting the scope thereof, as many alternatives and modifications will be apparent to those skilled in the art.

[0078] As reflected in the claims below, aspects of the present invention may have fewer than all of the features of a single embodiment disclosed above. Therefore, the claims expressed below are hereby expressly incorporated into the description of the drawings, with each claim standing on its own as a separate embodiment of the present invention. Furthermore, although some embodiments described herein include some features included in other embodiments, but not others included therein, those skilled in the art will understand that combinations of features from different embodiments are intended to fall within the scope of the present invention and are intended to form different embodiments.

Claims

1. A differential buffer comprising: a first differential input amplifier configured to receive both a non-inverting portion of the differential input signal and the first switching signal and to form an output signal including a first non-inverting output and a first inverting output; a second differential input amplifier configured to receive both an inverted portion of the differential input signal and a second switching signal and to form another output signal including a second non-inverted output and a second inverted output; an output amplifier having a non-inverting input coupled to receive a first signal representing a sum of the first non-inverting output and the second non-inverting output, the output amplifier having an inverting input coupled to receive a second signal representing a sum of the first inverting output and the second inverting output, the output amplifier configured to form a differential output signal in response to the first signal and the second signal, wherein the differential output signal includes a non-inverting output signal and an inverting output signal; a feedback chopping switch configured to receive the non-inverting output signal and the inverting output signal; a positive input chopping switch configured to selectively form one of the non-inverting output signal or the inverting output signal as the first switching signal during a first time interval, and selectively form a different one of the non-inverting output signal or the inverting output signal as the first switching signal during a second time interval; and a negative input chopping switch configured to selectively form, during the first time interval, the non-inverting output signal or the inverting output signal, whichever is opposite to the first switching signal used during the first time interval, as the second switching signal, and selectively form, during the second time interval, the non-inverting output signal or the inverting output signal, whichever is opposite to the first switching signal used during the second time interval, as the second switching signal.

2. The differential buffer of claim 1 , further comprising a first adder having a first input connected to the first non-inverting output of the first differential input amplifier, a second input connected to the second non-inverting output of the second differential input amplifier, and an output connected to the non-inverting input of the output amplifier; and A second adder having a first input connected to the first inverting output of the first differential input amplifier, a second input connected to the second inverting output of the second differential input amplifier, and an output connected to the inverting input of the output amplifier.

3. The differential buffer according to claim 1, wherein the positive input chopping switch having a first output directly connected to a first input of the first differential input amplifier, having a second output directly connected to a second input of the first differential input amplifier, and not connected to the second differential input amplifier; and The negative input chopping switch has a first output directly connected to the first input of the second differential input amplifier, has a second output directly connected to the second input of the second differential input amplifier, and is not connected to the first differential input amplifier.

4. A semiconductor device having a differential buffer, comprising: a first input stage having a first input and a second input; a second input stage having a third input and a fourth input; an output stage configured to receive signals from both the first input stage and the second input stage and to responsively form a non-inverting output signal and an inverting output signal; a feedback switch configured to receive the non-inverting output signal and the inverting output signal, the feedback switch configured to alternately apply one of the non-inverting output signal or the inverting output signal as a first switching signal to a first output during a first time interval and a second time interval, and the feedback switch configured to alternately apply an opposite of the non-inverting output signal or the inverting output signal as a second switching signal to a second output during the first time interval and the second time interval; a first switch configured to receive a non-inverting portion of a differential input signal, the first switch configured to apply the first switching signal and the non-inverting portion of the differential input signal to the first input stage during the first time interval and the second time interval; as well as a second switch configured to receive an inverted portion of the differential input signal, the second switch configured to apply the second switching signal and the inverted portion of the differential input signal to the second input stage during the first time interval and the second time interval.

5. The semiconductor device according to claim 4, wherein The output stage includes a non-inverting input configured to receive the sum of the non-inverting output of the first input stage and the non-inverting output of the second input stage, and the output stage also includes an inverting input configured to receive the sum of the inverting output of the first input stage and the inverting output of the second input stage. The semiconductor device according to claim 4 , wherein: The first input stage does not receive the inverted portion of the differential input signal.

7. The semiconductor device according to claim 4, wherein The first input stage receives the non-inverting portion of the differential input signal from the first switch on the first input during the first time interval and receives the non-inverting portion of the differential input signal from the first switch on the second input during the second time interval.

8. A method of forming a differential buffer, comprising: configuring the differential buffer to be a chopped differential buffer operating at a chopping frequency; configuring a first input stage of the chopped differential buffer to receive a non-inverting output of the chopped differential buffer during a first time interval and to receive an inverting output of the chopped differential buffer during a second time interval; configuring a second input stage of the chopped differential buffer to receive the inverting output of the chopped differential buffer during the first time interval and to receive the non-inverting output of the chopped differential buffer during the second time interval; as well as An RC filter is coupled before the chopped differential buffer, wherein a cutoff frequency of the RC filter is lower than the chopping frequency.

9. The method according to claim 8, further comprising: configuring the first input stage to receive a non-inverting portion of a differential input signal during the first time interval and during the second time interval; as well as The second input stage is configured to receive an inverted portion of the differential input signal during the first time interval and during the second time interval.

10. The method according to claim 9, further comprising: configuring a feedback switch to receive the non-inverting output and the inverting output and to pass the non-inverting output to the first input stage during the first time interval and to pass the inverting output to the second input stage during the first time interval; as well as The feedback switch is configured to pass the inverting output to the first input stage during the second time interval and to pass the non-inverting output to the second input stage during the second time interval.

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