Method for manufacturing connection structure of semiconductor chip and manufacturing semiconductor package

Abstract

A method for manufacturing a connection structure for a semiconductor chip and a method for manufacturing a semiconductor package are provided. The method for manufacturing a connection structure for a semiconductor chip includes: preparing a semiconductor chip having a first surface on which connection pads are provided and a second surface opposite the first surface, and the semiconductor chip including a passivation layer provided on the first surface and covering the connection pads; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pads by removing the passivation layer exposed by the via hole; forming a redistribution via hole by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via hole and the insulating layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0022013 filed on February 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a method for manufacturing a connection structure of a semiconductor chip and a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a connection structure of a semiconductor chip and a method for manufacturing a semiconductor package that can prevent corrosion of a connection pad (pad, or "solder pad") of the semiconductor chip. Background Art

[0003] The connection structure is a structure for electrically connecting connection pads of a semiconductor chip to a printed circuit board (PCB) such as a main board of an electronic device.

[0004] Recently, a major trend in semiconductor chip technology development has been toward reducing the size of semiconductor chips. With the rapidly increasing demand for smaller semiconductor chips, there is a need to achieve compact semiconductor chips that include a large number of pins. Recently, in response to these technological demands, the patterns and vias of the internal redistribution layer of the connection structure that controls the redistribution function of the semiconductor chip have been meticulously formed through photolithography processes.

[0005] On the other hand, the photolithography process is a process of irradiating light onto a mask or photomask on which a circuit pattern is drawn to expose a photosensitive insulating layer and removing part of the photosensitive insulating layer by a developer to achieve a desired pattern, and when a redistribution layer is formed on the connection pad of a semiconductor chip by the photolithography process, there is a problem that the developer, cleaning agent, etc. come into contact with the aluminum (Al) connection pad and cause corrosion or damage to the connection pad. Summary of the Invention

[0006] An aspect of the present disclosure is to provide a method for manufacturing a connection structure of a semiconductor chip and a method for manufacturing a semiconductor package as follows: the method can improve process efficiency and reduce product defect rate by preventing corrosion and damage to connection pads in a process of forming a connection structure of a semiconductor chip and a semiconductor packaging process.

[0007] According to aspects of the present disclosure, a method of manufacturing a connection structure of a semiconductor chip may be provided, wherein contact between a chemical agent for forming a via hole and a connection pad is blocked in a process of forming a redistribution via or a connection structure.

[0008] According to aspects of the present disclosure, a method for manufacturing a connection structure of a semiconductor chip may include: preparing a semiconductor chip, the semiconductor chip including a first surface, a passivation layer and a second surface opposite to the first surface, a connection pad being provided on the first surface and the passivation layer covering the connection pad and the first surface on which no connection pad is provided; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

[0009] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package may include: preparing a semiconductor chip, the semiconductor chip having a first surface on which connection pads are provided and a second surface opposite to the first surface, and the semiconductor chip including a passivation layer provided on the first surface and covering the connection pads; forming an encapsulant on the second surface of the semiconductor chip, the encapsulant covering at least a portion of the semiconductor chip; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram illustrating an example of an electronic device system in which a semiconductor chip may be used;

[0012] Figure 2 is a schematic perspective view showing an example of a semiconductor package embedded in an electronic device;

[0013] Figure 3 is a schematic cross-sectional view showing a process of forming a connection structure on a semiconductor chip;

[0014] Figures 4A to 4D is a schematic cross-sectional view showing a damage process of a connection pad in a process of forming a via hole of a connection structure;

[0015] 5A to 5D is shown to prevent the Figures 4A to 4D A schematic cross-sectional view of a method for repairing a damaged connection structure of a connection pad;

[0016] Figures 6A to 6E is a schematic cross-sectional view illustrating a method of manufacturing a connection structure according to an exemplary embodiment of the present disclosure;

[0017] Figures 7A to 7G is a schematic cross-sectional view illustrating a method of manufacturing a connection structure according to another exemplary embodiment of the present disclosure;

[0018] Figure 8 is a schematic cross-sectional view showing a semiconductor package to which a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure is applied; and

[0019] Figure 9 is a schematic cross-sectional view illustrating a semiconductor package to which a method of manufacturing a semiconductor package according to another exemplary embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0020] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes, sizes, etc. of components may be exaggerated or reduced for clarity.

[0021] Here, the terms "lower side," "lower portion," "lower surface," etc. are used to refer to a direction toward the mounting surface of the fan-out semiconductor package relative to a cross section of the drawings, while "upper side," "upper portion," "upper surface," etc. are used to refer to a direction opposite to the direction toward the mounting surface of the fan-out semiconductor package. However, these directions are defined for convenience of explanation, and the claims are not specifically limited to the directions defined as described above.

[0022] In the description, the meaning of a component being "connected" to another component conceptually includes an indirect connection through an adhesive layer as well as a direct connection between the two components. In addition, "electrically connected" conceptually includes both physical connection and physical disconnection. It is understood that when a component is referred to by terms such as "first" and "second", the component is not limited thereto. These terms may be used only to distinguish the component from other components and may not limit the order or importance of the components. In some cases, without departing from the scope of the claims set forth herein, a first element may be referred to as a second element. Similarly, a second element may also be referred to as a first element.

[0023] The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be achievable by combining them in whole or in part with one another. For example, unless otherwise indicated, an element described in a particular exemplary embodiment may be understood as a description related to another exemplary embodiment even if it is not described in another exemplary embodiment.

[0024] The terms used herein are used only to describe exemplary embodiments rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular includes the plural.

[0025] semiconductor chips

[0026] The semiconductor chip may be an integrated circuit (IC) provided by integrating hundreds to millions or more components into a single chip. The semiconductor chip 120 may be formed on the basis of an effective wafer. In this case, the base material of the body 121 of the semiconductor chip 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.

[0027] Various circuits may be formed on the body 121. The connection pads 122 may electrically connect the semiconductor chip 120 to other components. The material of each of the connection pads 122 may be a conductive material such as aluminum (Al). The active surface of the semiconductor chip 120 refers to the surface of the semiconductor chip 120 on which the connection pads 122 are provided, and the inactive surface of the semiconductor chip 120 refers to the surface of the semiconductor chip 120 opposite to the active surface.

[0028] If necessary, a passivation layer 123 covering at least a portion of the connection pad 122 may be formed on the body 121. The passivation layer 123 may be an oxide layer, a nitride layer, or the like, or may be a double layer of an oxide layer and a nitride layer. An insulating layer (not shown) or the like may also be provided in other desired locations.

[0029] The semiconductor chip 120 can be: a memory chip such as a volatile memory (e.g., dynamic random access memory (DRAM)), a non-volatile memory (e.g., read-only memory (ROM)), a flash memory, etc.; an application processor chip such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; and a logic chip such as an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC), etc., but is not necessarily limited thereto.

[0030] Figure 1 is a schematic block diagram illustrating an example of an electronic device system in which a semiconductor chip may be used.

[0031] Reference Figure 1, the electronic device 1000 may house a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically or electrically connected to the motherboard 1010. These components may be connected to other components to be described below via various signal lines 1090.

[0032] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0033] The network-related components 1030 may include components operating according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (EV-DO), High-Speed ​​Packet Access Plus (HSPA+), High-Speed ​​Downlink Packet Access Plus (HSDPA+), High-Speed ​​Uplink Packet Access Plus (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, 5G protocols, and any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the above-described chip-related component 1020 .

[0034] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, other components 1040 may be combined with the chip-related components 1020 or the network-related components 1030 described above.

[0035] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disc (CD) drive (not shown), a digital versatile disc (DVD) drive (not shown), etc. However, these other components are not limited thereto, and other components for various purposes may be included depending on the type of the electronic device 1000, etc.

[0036] The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0037] Connection structure and semiconductor package

[0038] The connection structure refers to a structure including a conductive pattern formed on one surface of a semiconductor chip to redistribute connection pads of the semiconductor chip in, for example, a semiconductor package, an interposer in which the semiconductor chip is embedded, a main board, etc., to the outside.

[0039] Figure 2 is a schematic perspective view showing an example of a semiconductor package embedded in an electronic device.

[0040] Reference Figure 2, semiconductor packages can be used for various purposes in various electronic devices 1000 as described above. For example, a printed circuit board 1110 can be housed in the body 1101 of the smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the printed circuit board 1110. In addition, other components (such as a camera module 1130) that may or may not be physically or electrically connected to the printed circuit board 1110 can be housed in the body 1101. Some of the electronic components 1120 may be chip-related components (e.g., semiconductor packages 1121), but are not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0041] Typically, many sophisticated electronic circuits are integrated into semiconductor chips. However, semiconductor chips themselves may not be usable as finished semiconductor products and may be damaged by external physical or chemical impact. Therefore, semiconductor chips are not used on their own but are packaged and used in electronic devices and the like.

[0042] Semiconductor packaging is necessary because, in terms of electrical connection, there is a difference in circuit width between a semiconductor chip and the mainboard of an electronic device. Specifically, the size of the semiconductor chip's connection pads and the spacing between them are very fine, whereas the size of the component mounting pads on the mainboard used in electronic devices and the spacing between them are significantly larger than the size of the semiconductor chip's connection pads and the spacing between them. Therefore, it can be difficult to directly mount a semiconductor chip on a mainboard, and packaging technology is needed to mitigate the difference in circuit width between the semiconductor chip and the mainboard.

[0043] Semiconductor packages manufactured by packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.

[0044] A fan-in semiconductor package may have a package form in which all connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are arranged inside the semiconductor chip, and may have excellent electrical characteristics and can be produced at low cost. Therefore, many components installed in smartphones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smartphones have been developed to achieve fast signal transmission while having a compact size.

[0045] However, in a fan-in type semiconductor package, since all I / O terminals need to be arranged inside the semiconductor chip, the fan-in type semiconductor package has significant space limitations. Therefore, it is difficult to apply this structure to a semiconductor chip with a large number of I / O terminals or a semiconductor chip with a small size.

[0046] Furthermore, due to the above-mentioned disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the mainboard of the electronic device. This is because, even if the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip are increased through the redistribution process, the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in type semiconductor package on the mainboard of the electronic device.

[0047] A fan-out type semiconductor package may have a form in which the I / O terminals of the semiconductor chip are redistributed and set to the outside of the semiconductor chip through a connection structure formed on the semiconductor chip. As described above, in a fan-in type semiconductor package, all the I / O terminals of the semiconductor chip need to be set inside the semiconductor chip. Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the balls need to be reduced, so that it may not be possible to use a standardized ball layout in the fan-in type semiconductor package. On the other hand, as described above, a fan-out type semiconductor package has a form in which the I / O terminals of the semiconductor chip are redistributed and set to the outside of the semiconductor chip through a connection structure formed on the semiconductor chip. Therefore, even in the case where the size of the semiconductor chip is reduced, the standardized ball layout can be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of an electronic device without using a separate printed circuit board.

[0048] Figure 3 is a schematic cross-sectional view illustrating a process of forming a connection structure on a semiconductor chip.

[0049] Reference Figure 3 Semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state. Semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads 2222, and a passivation layer 2223 such as an oxide layer or a nitride layer. Body 2221 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Connection pads 2222 are formed on one surface of body 2221 and include a conductive material such as aluminum (Al). Passivation layer 2223 is formed on one surface of body 2221 and covers at least a portion of connection pads 2222. In this case, because connection pads 2222 may be very small, it may be difficult to mount the integrated circuit (IC) on a medium-sized printed circuit board (PCB) or a main board of an electronic device.

[0050] Therefore, depending on the size of the semiconductor chip 2220 , a connection structure 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222 .

[0051] The connection structure 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, forming a via hole 2243h opening the connection pad 2222, and then forming a wiring pattern 2242 and a via 2243.

[0052] Then, a passivation layer 2250 may be formed to protect the connection structure 2240, an opening 2251 may be formed, and an under bump metallurgy layer 2260 may be formed. In other words, a semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection structure 2240, the passivation layer 2250, and the under bump metallurgy layer 2260 may be manufactured through a series of processes.

[0053] Figures 4A to 4D is a schematic cross-sectional view illustrating a damage process of a connection pad in a process of forming a via hole of a connection structure.

[0054] For example, refer to Figures 4A to 4D , Figure 4A The effective surface of the bare semiconductor chip 120 may include a body 121, a connection pad 122 and a passivation layer 123. In the prior art, as Figure 4B As shown, the opening 123H is formed by partially removing the passivation layer 123 to perform a functional test of the semiconductor chip 120 at the wafer level. In this case, the connection pad 122 of aluminum (Al) is formed at Figure 4C and Figure 4D The exposed surface of the insulating layer 141 in the process of removing the portion covering the connection pad 122 to form the via hole 141H is damaged by a developer, a cleaning agent, an etchant, or the like.

[0055] 5A to 5D is shown to prevent the Figures 4A to 4D Schematic cross-sectional view of a method for repairing a damaged connection structure of a connection pad.

[0056] Reference 5A to 5D , in order to prevent corrosion of the connection pads, Figure 5A The opening 123H is formed in the passivation layer 123, a functional test of the connection pad 122 is performed, and then the Figure 5B The metal cover C covering the exposed surface of the connection pad 122 is shown in FIG. Figure 5C and Figure 5D In the process of forming the via hole 141H, the cleaning agent and the like are blocked from contact with the aluminum (Al) connection pad 122 to prevent corrosion of the connection pad 122. However, the manufacturing cost and lead time may increase due to the addition of a capping process using a metal such as copper (Cu).

[0057] Therefore, the present disclosure discloses a method for manufacturing a connection structure of a semiconductor chip and a method for manufacturing a semiconductor package as follows: it is possible to prevent damage and corrosion to the connection pads of the semiconductor chip due to chemical reagents in the process of forming a via hole that opens the connection pad, without performing a process of forming a metal cover in the process of forming a connection structure 140 that redistributes the connection pads of the semiconductor chip.

[0058] Hereinafter, a method of manufacturing a connection structure and a semiconductor package according to various exemplary embodiments in the present disclosure will be described in detail with reference to the accompanying drawings.

[0059] Figures 6A to 6E is a schematic cross-sectional view illustrating a method of manufacturing a connection structure according to an exemplary embodiment in the present disclosure.

[0060] Reference Figures 6A to 6E The method for manufacturing a connection structure according to an exemplary embodiment of the present disclosure may include: preparing a semiconductor chip 120 having a first surface, a second surface opposite to the first surface, a connection pad 122 disposed on the first surface, and a passivation layer 123 disposed on the first surface and covering the connection pad 122. Figure 6A ); forming an insulating layer 141 on the first surface of the semiconductor chip, the insulating layer 141 covering at least a portion of the passivation layer 123 ( Figure 6B ); forming a via hole 141H penetrating the insulating layer 141 to expose at least a portion of the passivation layer ( Figure 6C ); exposing at least a portion of the connection pad 122 by removing the passivation layer 123 exposed by the via hole 141H ( Figure 6D ); forming a redistribution via 143 by filling the via hole 141H with a conductive material; and forming a redistribution layer 142 ( Figure 6E ).

[0061] That is, in the method of manufacturing the connection structure according to the exemplary embodiment, the passivation layer 123 of the bare chip may be performed without removing the passivation layer 123 of the bare chip. Figures 6A to 6C Then, as shown in FIG. Figure 6D As shown in FIG, the passivation layer 123 exposed by the via hole 141H may be removed to form an opening 123H exposing the connection pad 122 .

[0062] Therefore, the contact between various chemical reagents used to form the via hole 141H and the connection pad 122 can be blocked by the passivation layer 123 included in the bare chip without performing a separate metal covering process, thereby improving the process efficiency of manufacturing the connection structure and reducing the manufacturing cost and lead time of the finished product.

[0063] Specifically, when problems such as coating defects, exposure defects, etc. of the insulating layer 141 occur in a photolithography process for realizing fine patterns, the photolithography process may be retried after removing the entire insulating layer 141 without damaging the connection pads 122 .

[0064] Hereinafter, respective processes of a method of manufacturing a connection structure of a semiconductor chip according to an exemplary embodiment of the present disclosure will be described in detail.

[0065] In the step of preparing the semiconductor chip 120, in order to form a connection structure on the connection pad 122, the semiconductor chip can be attached to a carrier (not shown), a tape (not shown), etc., so that the connection pad of the semiconductor chip faces upward. In this case, the semiconductor chip 120 can be in a packaging process in which the back surface or side surface of the semiconductor chip 120 is surrounded by an encapsulant, or can be in a component embedded substrate manufacturing process in which the back surface or side surface of the semiconductor chip 120 is embedded in a plurality of insulating substrates. However, the semiconductor chip 120 is not necessarily limited to being in an intermediate process such as a packaging process, and the process of encapsulating the semiconductor chip 120 can be performed simultaneously with the process of forming the insulating layer 141 described below.

[0066] The semiconductor chip 120 may include a body 121, connection pads 122, and a passivation layer 123. The semiconductor chip 120 may be, for example, a bare semiconductor chip in which the passivation layer 123 is not opened and covers the entire surface of the connection pads 122. In this case, the base material of the body 121 of the semiconductor chip 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed on the body 121.

[0067] The connection pads 122 may electrically connect the semiconductor chip 120 to other components and may be made of a conductive material such as aluminum (Al).

[0068] The passivation layer 123 may be an oxide layer, a nitride layer, or the like, or may be a double layer of an oxide layer and a nitride layer. An insulating layer (not shown) may also be provided in other desired locations. The semiconductor chip 120 may be: a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.; an application processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; and a logic chip, such as an ADC, an ASIC, etc., but is not necessarily limited thereto.

[0069] In the step of forming the insulating layer 141, the insulating layer 141 may be applied to the main body 121 of the semiconductor chip. In the present disclosure, the connection pads 122 are covered with the passivation layer 123, and therefore, the insulating layer 141 may be formed on the surface of the passivation layer 123. In addition, when other components such as an encapsulant of a semiconductor package, an insulating layer of a semiconductor chip embedded substrate, a core substrate, etc. are present on the opposite surface of the semiconductor chip, the insulating layer 141 may be formed not only on the main body of the semiconductor chip but also may extend onto the components present on the semiconductor chip.

[0070] The material of the insulating layer 141 can be an insulating material. In this case, the insulating material can be a photosensitive insulating material such as a photosensitive dielectric (PID) resin. That is, each of the plurality of insulating layers 141 can be a photosensitive insulating layer. When the insulating layer 141 has a photosensitive property, the insulating layer 141 can be formed to have a smaller thickness, and the fine pitch of the redistribution via 143 can be more easily achieved.

[0071] Each of the insulating layers 141 may be a photosensitive insulating layer comprising an insulating resin and an inorganic filler. When the insulating layers 141 are multiple layers, the materials of the insulating layers 141 may be the same as each other, or may be different from each other if necessary. When the insulating layers 141 are multiple layers, the insulating layers 141 may be integrated with each other according to the process, so that the boundaries between them may not be obvious. The number of insulating layers may be greater than the number of insulating layers shown in the drawings.

[0072] In the step of forming the via hole 141H, the via hole 141H may penetrate the insulating layer 141 covering the passivation layer 123 to expose the passivation layer 123. A method of forming the via hole 141H may be a physical or chemical method selected according to the type of the insulating layer 141 without being particularly limited.

[0073] The via hole 141H may have a cylindrical shape, a tapered shape whose diameter decreases toward one side, or the like.

[0074] Specifically, when a photosensitive insulating layer is used in order to achieve a fine pitch, the via hole 141H may be formed through a photolithography process including an exposure process and a development process.

[0075] The photolithography process is a process of irradiating light to a photomask or a photomask on which a circuit pattern is drawn to expose a photosensitive insulating layer applied to the semiconductor chip 120 and removing a portion of the photosensitive insulating layer by a developer to realize a desired pattern.

[0076] Typically, during the photolithography process, the developer or the cleaning solution for removing residues may come into contact with the connection pads, thereby corroding or damaging the connection pads. Therefore, in the present disclosure, the passivation layer 123 covering the connection pads may be maintained until the via hole 141H is formed to prevent contact between the chemical reagent used to form the via hole and the connection pads.

[0077] In the step of exposing at least a portion of connection pad 122, a portion of passivation layer 123 that protects the connection pad from the chemical reagent used to form the via hole can be removed to form an opening to expose the connection pad. Because passivation layer 123 is in direct contact with the connection pad, passivation layer 123 can be removed by dry etching without using a chemical reagent.

[0078] For example, after forming the via hole, the passivation layer 123 exposed by the via hole may be removed by plasma etching to form an opening 123H exposing the connection pad 122 .

[0079] Thus, the sidewall of the opening 123H may be connected to the inner wall of the via hole 141H. In addition, the width of the opening 123H may be smaller than or the same as the width of the via hole 141H.

[0080] That is, the via hole 141H and the opening 123H may have a tapered shape whose diameter decreases from one end of the via hole 141H toward the opening 123H.

[0081] In the steps of forming the redistribution vias 143 and the redistribution layer 142, conductive vias filling the via holes 141H and conductive patterns connecting the conductive vias to each other may be formed. The method of forming the redistribution vias 143 and the redistribution layer 142 may be any known method such as electroplating, electroless plating, etc. without being particularly limited.

[0082] The redistribution vias 143 may electrically connect the redistribution layers 142 , the connection pads 122 , and the like formed on different layers to one another, thereby obtaining an electrical path in the connection structure 140 .

[0083] The material of each of the redistribution vias 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0084] Each of the redistribution vias 143 may be a filled-type via completely filled with a conductive material, or may be a conformal via in which a conductive material may be formed along the wall of each of the via holes. In addition, each of the redistribution vias 143 may have any shape known in the art, such as a tapered shape, a cylindrical shape, etc.

[0085] The redistribution layers 142 may basically serve to redistribute the connection pads 122. The material of each of the redistribution layers 142 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0086] The redistribution layer 142 may perform various functions depending on the design of the corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern layer (not shown) and may also include a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern in addition to the ground (GND) pattern and the power (PWR) pattern. In addition, the redistribution layer 142 may include a via pad pattern.

[0087] Although not explicitly shown, the number of redistribution layers 142 may be greater or less than the number of redistribution layers 142 shown in the drawings.

[0088] On the other hand, after forming the connection structure 140, a process of forming an under-bump metal (not shown) on one surface of the connection structure 140 and a process of forming an electrical connection metal 150 for physical connection and / or electrical connection to an external substrate such as a main board can be sequentially performed.

[0089] Furthermore, a process of forming other components such as a semiconductor package, a semiconductor chip embedded substrate, etc. may be added before or after the method of forming a connection structure according to exemplary embodiments.

[0090] Figures 7A to 7G is a schematic cross-sectional view illustrating a method of manufacturing a connection structure according to another exemplary embodiment in the present disclosure.

[0091] Reference Figures 7A to 7G The method for manufacturing a connection structure according to another exemplary embodiment may further include: performing a functional test of the semiconductor chip through the connection pad 122 of the semiconductor chip before preparing the semiconductor chip 120 including the passivation layer 123 in the method for manufacturing a connection structure according to the exemplary embodiment ( Figure 7B ) and forming a passivation layer 123 ( Figure 7C ).

[0092] In detail, such as Figure 7A and Figure 7B As shown in , a functional test of the semiconductor chip may be performed by bringing the probes P into contact with the connection pads 122 before forming the passivation layer 123 .

[0093] Then, you can form Figure 7CThe passivation layer 123 may be an oxide layer, a nitride layer, or a double layer of an oxide layer and a nitride layer. In addition, an insulating layer (not shown) may be provided at other desired locations.

[0094] In a method of manufacturing a connection structure according to another exemplary embodiment, the reason for performing a functional test before forming the passivation layer 123 may be to prevent the connection pad 122 from being damaged in the process of forming the via hole, without additionally performing a process of forming a metal cover while leaving the connection pad 122 open before forming the via hole 141H in order to perform a functional test of the semiconductor chip.

[0095] On the other hand, when performing functional testing of the semiconductor chip, a recess 122R can be formed in the surface of the connection pad 122 using a probe P, and then the passivation layer 123 can be formed to be tightly attached to the surface of the connection pad 122 so that at least a portion of the passivation layer 123 can have a circular arc portion 123R corresponding to the recess 122R.

[0096] The arc portion 123R can be Figures 7D to 7G The recess 122R of the connection pad 122 is protected during the process of forming the via hole 141H and the opening 123H, and the contact area between the redistribution via 143 filling the via hole 141H and the connection pad 122 is increased, thereby improving the connection reliability between the connection pad 122 and the redistribution layer 142.

[0097] Other components are in accordance with Figures 6A to 6E Components described in the method of manufacturing a connection structure of the exemplary embodiment shown in FIG. 1 are repeated, and thus their detailed description is omitted.

[0098] Figure 8 is a schematic cross-sectional view illustrating a semiconductor package to which a method of manufacturing a semiconductor package according to an exemplary embodiment in the present disclosure is applied.

[0099] Figure 8A semiconductor package can be manufactured by a method for manufacturing a semiconductor package including the following steps: preparing a semiconductor chip 120 having a first surface and a second surface opposite to the first surface and including a passivation layer 123, wherein connection pads are provided on the first surface, and the passivation layer 123 is provided on the first surface and covers the connection pads; forming an encapsulant 130 on the second surface of the semiconductor chip 120, wherein the encapsulant 130 covers at least a portion of the semiconductor chip; forming an insulating layer 141 on the first surface of the semiconductor chip 120, wherein the insulating layer 141 covers at least a portion of the passivation layer 123; forming a via hole 141H penetrating the insulating layer 141 to expose at least a portion of the passivation layer 123; exposing at least a portion of the connection pad by removing the passivation layer 123 exposed by the via hole 141H; forming a redistribution via 143 by filling the via hole 141H with a conductive material; and forming a redistribution layer 142 on the redistribution via 143 and the insulating layer 141.

[0100] Reference Figure 8 In the region 'A' of the semiconductor package manufactured by the method of manufacturing a semiconductor package according to an exemplary embodiment, opposite side surfaces of the redistribution via 143 may be in contact with the passivation layer 123. This is because a via hole filled with the redistribution via 143 is formed and then only a portion of the passivation layer 123 exposed by the via hole is removed.

[0101] On the other hand, the method of manufacturing a semiconductor package according to an exemplary embodiment may include forming an encapsulant 130 on the second surface of the semiconductor chip 120 , the encapsulant 130 covering at least a portion of the semiconductor chip 120 .

[0102] The encapsulant 130 may encapsulate the semiconductor chip 120. The encapsulation form of the encapsulant 130 is not particularly limited, but may be a form in which the encapsulant 130 surrounds at least a portion of the semiconductor chip 120. For example, the encapsulant 130 may cover at least a portion of an inactive surface of the semiconductor chip 120 and may cover at least a portion of a side surface of the semiconductor chip 120.

[0103] The encapsulant 130 may include an insulating material. In this case, the insulating material may be a material including an insulating resin or including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in a thermosetting resin or a thermoplastic resin (such as ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT)), etc.

[0104] Alternatively, epoxy molding compound (EMC), photosensitive encapsulant (PIE), etc. can be used as the insulating material. Alternatively, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and / or a core material such as glass fabric can also be used as the insulating material.

[0105] Other components are in accordance with Figures 6A to 6E Components described in the method of manufacturing a connection structure of the exemplary embodiment shown in FIG. 1 are repeated, and thus their detailed description is omitted.

[0106] Figure 9 is a schematic cross-sectional view illustrating a semiconductor package to which a method of manufacturing a semiconductor package according to another exemplary embodiment of the present disclosure is applied.

[0107] Figure 9 The semiconductor package can be manufactured by a method for manufacturing a semiconductor package comprising the following steps: preparing a frame 110 having a through hole 110H; preparing a semiconductor chip 120 having a first surface and a second surface opposite to the first surface and comprising a passivation layer 123, wherein a connection pad is provided on the first surface, and the passivation layer 123 is provided on the first surface and covers the connection pad; disposing the semiconductor chip 120 in the through hole 110H; forming an encapsulant 130 on one surface of the frame 110 and the second surface of the semiconductor chip 120, wherein the encapsulant 130 covers the frame and the semiconductor chip. at least a portion of each of; forming an insulating layer 141 on the other surface of the frame 110 and the first surface of the semiconductor chip 120, the insulating layer 141 covering at least a portion of the frame 110 and the passivation layer 123; forming a via hole 141H penetrating the insulating layer 141 to expose at least a portion of the passivation layer 123; exposing at least a portion of the connection pad by removing the passivation layer 123 exposed by the via hole 141H; forming a redistribution via 143 by filling the via hole 141H with a conductive material; and forming a redistribution layer 142 on the redistribution via 143 and the insulating layer 141.

[0108] Reference Figure 9 In region 'A' of the semiconductor package manufactured by the method of manufacturing a semiconductor package according to another exemplary embodiment, opposite side surfaces of the redistribution via 143 may be in contact with the passivation layer 123. This is because a via hole filled with the redistribution via 143 is formed and then only a portion of the passivation layer 123 exposed by the via hole is removed.

[0109] On the other hand, a method of manufacturing a semiconductor package according to another exemplary embodiment may include preparing a frame 110 having a through hole 110H and forming an encapsulant 130 on one surface of the frame and a second surface of the semiconductor chip, the encapsulant 130 covering at least a portion of each of the frame and the semiconductor chip.

[0110] The frame 110 may improve the rigidity of the semiconductor package according to a specific material, and may serve to ensure uniformity in the thickness of the encapsulant 130 .

[0111] The frame 110 may have at least one through-hole 110H. The through-hole 110H may penetrate the frame 110, and the semiconductor chip 120 may be disposed in the through-hole 110H.

[0112] The semiconductor chip 120 may be disposed spaced apart from the wall of the through hole 110H by a predetermined distance and may be surrounded by the wall of the through hole 110H. However, such a form is merely an example and may be modified in various ways to have other forms, and the frame 110 may perform another function according to such a form.

[0113] If necessary, the frame 110 may be omitted, but the semiconductor package 100 including the frame 110 may be more advantageous in terms of ensuring board-level reliability.

[0114] The encapsulant 130 may fill at least a portion of the through-hole 110H and may encapsulate the semiconductor chip 120. The encapsulation form of the encapsulant 130 is not particularly limited, and may be a form in which the encapsulant 130 surrounds at least a portion of the semiconductor chip 120. For example, the encapsulant 130 may cover at least a portion of the frame 110 and at least a portion of the ineffective surface of the semiconductor chip 120, and may fill at least a portion of the space between the wall of the through-hole 110H and the side surface of the semiconductor chip 120.

[0115] Other components are in accordance with Figures 6A to 6E Components described in the method of manufacturing a connection structure of the exemplary embodiment shown in FIG. 1 are repeated, and thus their detailed description is omitted.

[0116] As described above, according to the exemplary embodiments in the present disclosure, a method for manufacturing a connection structure of a semiconductor chip and a method for manufacturing a semiconductor package can be provided as follows: the process of forming the connection structure of the semiconductor chip and the semiconductor packaging process can be used to improve process efficiency and reduce product defect rates by preventing corrosion and damage to the connection pads.

[0117] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a connection structure of a semiconductor chip, the method comprising: performing a functional test of the semiconductor chip through an upper surface of the connection pads of the semiconductor chip; forming a passivation layer covering the upper surface of the connection pad; preparing the semiconductor chip, the semiconductor chip having a first surface on which the connection pads are provided and a second surface opposite to the first surface, and the semiconductor chip including the passivation layer; forming an insulating layer on the first surface of the semiconductor chip, wherein the insulating layer covers at least a portion of the passivation layer; forming a via hole penetrating the insulating layer to expose at least a portion of the passivation layer by a photolithography process; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole through dry etching performed after the photolithography process; forming a redistribution via by filling the via hole with a conductive material; as well as forming a redistribution layer on the redistribution via and the insulating layer, wherein, in the step of performing the functional test of the semiconductor chip, a recess is formed in the upper surface of the connection pad, wherein, in the step of exposing at least a portion of the connection pad, the passivation layer exposed by the via hole is removed to form an opening of the recess exposing the connection pad, and The redistribution via contacts the recess of the connection pad through the opening.

2. The method according to claim 1, wherein The connection pads include aluminum.

3. The method according to claim 1, wherein The passivation layer includes an oxide layer, a nitride layer, or a double layer of an oxide layer and a nitride layer.

4. The method according to claim 1, wherein The insulating layer is a photosensitive insulating layer.

5. The method according to claim 1, wherein The step of forming the via hole is performed such that an inner wall of the via hole has a tapered or cylindrical structure.

6. The method according to claim 1, wherein In the step of exposing at least a portion of the connection pad, the passivation layer is removed so that a sidewall of the passivation layer has the opening connected to an inner wall of the via hole.

7. The method according to claim 6, wherein: The width of the opening is smaller than or equal to the width of the via hole.

8. The method according to claim 1, wherein In the step of forming the passivation layer, the passivation layer is closely attached to the surface of the connection pad.

9. The method according to claim 8, wherein The passivation layer has a circular arc portion closely attached to the concave portion of the connection pad.

10. A method for manufacturing a semiconductor package, the method comprising: performing a functional test of the semiconductor chip through an upper surface of the connection pads of the semiconductor chip; forming a passivation layer covering the upper surface of the connection pad; preparing the semiconductor chip, the semiconductor chip having a first surface on which the connection pads are provided and a second surface opposite to the first surface, and the semiconductor chip including the passivation layer; forming an encapsulant on the second surface of the semiconductor chip, wherein the encapsulant covers at least a portion of the semiconductor chip; forming an insulating layer on the first surface of the semiconductor chip, wherein the insulating layer covers at least a portion of the passivation layer; forming a via hole penetrating the insulating layer to expose at least a portion of the passivation layer by a photolithography process; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole through dry etching performed after the photolithography process; forming a redistribution via by filling the via hole with a conductive material; as well as forming a redistribution layer on the redistribution via and the insulating layer, wherein, in the step of performing the functional test of the semiconductor chip, a recess is formed in the upper surface of the connection pad, wherein, in the step of exposing at least a portion of the connection pad, the passivation layer exposed by the via hole is removed to form an opening of the recess exposing the connection pad, and The redistribution via contacts the recess of the connection pad through the opening.

11. The method according to claim 10, further comprising: Before the step of preparing the semiconductor chip, a frame having through holes is prepared. wherein the semiconductor chip is arranged in the through hole of the frame, The encapsulant is formed on one surface of the frame and the second surface of the semiconductor chip to cover at least a portion of each of the frame and the semiconductor chip, and The insulating layer is formed on the other surface of the frame and the first surface of the semiconductor chip to cover at least portions of the frame and the passivation layer.

12. The method according to claim 10, wherein: The redistribution vias are formed of a conductive material.

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