Semiconductor package with heat sink

Abstract

The present invention relates to a semiconductor package having a heat sink. According to one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, wherein at least a portion of the first surface is exposed through the molding, such that the substrate is configured to act as a heat sink.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 62 / 811,147, filed February 27, 2019, and U.S. Non-Provisional Patent Application No. 16 / 506,405, filed July 9, 2019, which claims priority to U.S. Provisional Patent Application No. 62 / 811,147, the contents of each of which are incorporated herein by reference in their entirety. Technical Field

[0003] This specification relates to a semiconductor package having a heat sink. Background Art

[0004] Conventional semiconductor packages may use relatively long wires to connect various devices in the package. These conventional semiconductor packages may have problems with high resistance and inductance losses, and the heat generated in these wires may be relatively high. Summary of the Invention

[0005] According to one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, wherein at least a portion of the first surface is exposed through the molding such that the substrate is configured to act as a heat sink.

[0006] According to some aspects, the semiconductor package includes one or more of the following features (or any combination thereof). The semiconductor package may include a metal trace coupled to a first surface of a substrate, at least a portion of the metal trace being exposed through a molding. The substrate may include a via extending between the first surface and the second surface. The semiconductor package may include a first leadframe portion coupled to the second surface of the substrate, and a second leadframe portion coupled to the second surface of the substrate, wherein a semiconductor die is disposed between the first leadframe portion and the second leadframe portion. In some examples, the semiconductor die is a first semiconductor die, and the semiconductor package further includes a second semiconductor die coupled to the second surface of the substrate and a third semiconductor die coupled to the second surface of the substrate. The semiconductor package may include a first metal trace coupled to the second surface of the substrate and a second metal trace coupled to the first metal trace, wherein the semiconductor die is coupled to the second metal trace. The semiconductor package may include a passive device coupled to the substrate and a metal trace coupled to the second surface of the substrate, wherein the passive device is coupled to the metal trace. The semiconductor package may include a leadframe portion coupled to the substrate and a passive device coupled to the leadframe portion.

[0007] According to one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a leadframe portion coupled to the substrate, a first metal trace coupled to the first surface of the substrate, at least one second metal trace coupled to the second surface of the substrate, and a molding encapsulating a semiconductor die and a majority of the substrate, wherein at least a portion of the first metal trace is exposed through the molding such that the substrate is configured to act as a heat sink.

[0008] According to some aspects, the semiconductor package may include one or more of the above / following features (or any combination thereof). The substrate includes a through-hole connecting the lead frame portion to the first metal trace. The at least one second metal trace may include two stacked metal traces. The semiconductor package may include a capacitor coupled to the lead frame portion or the substrate. The semiconductor die may be a first semiconductor die, the semiconductor package further including a second semiconductor die coupled to the at least one second metal trace and a third semiconductor die coupled to the at least one second metal trace. The first semiconductor die may be a low-side semiconductor die, the second semiconductor die may be a high-side semiconductor die, and the third semiconductor die may be a driver integrated circuit (IC) die.

[0009] According to one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, the substrate having a through-via extending between the first and second surfaces. The semiconductor package includes a leadframe portion coupled to the second surface of the substrate, a metal trace coupled to the first surface of the substrate, wherein the through-via connects the metal trace to the leadframe portion, a high-side semiconductor die coupled to the second surface of the substrate, a low-side semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, wherein at least a portion of the metal trace is exposed through the molding such that the substrate is configured to act as a heat sink.

[0010] According to some aspects, the semiconductor package includes one or more of the above / below features (or any combination thereof). The semiconductor package may include a first passive component coupled to a substrate and a second passive component coupled to the substrate. The semiconductor package may include a driver integrated circuit (IC) die, which is coupled to the second surface of the substrate. The high-side semiconductor die and the low-side semiconductor die may be coupled to the second surface of the substrate via a second metal trace and a third metal trace, and the driver IC die may be coupled to the second surface of the substrate via the second metal trace rather than the third metal trace.

[0011] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A semiconductor package according to an aspect is shown.

[0013] Figures 2A to 2H A semiconductor package according to another aspect is shown.

[0014] Figure 3A and Figure 3B According to one aspect, the substrate is shown exposed through the molding of the semiconductor package.

[0015] Figure 4A and Figure 4B A semiconductor package according to another aspect is shown.

[0016] Figures 5A to 5B A semiconductor package according to another aspect is shown.

[0017] Figures 6A to 6B A semiconductor package according to another aspect is shown.

[0018] 7A to 7C A semiconductor package according to another aspect is shown.

[0019] Figures 8A to 8B A semiconductor package according to another aspect is shown.

[0020] Figures 9A to 9B A semiconductor package according to another aspect is shown.

[0021] Figures 10A to 10C A semiconductor package according to another aspect is shown.

[0022] Figure 11 A semiconductor package according to another aspect is shown.

[0023] Figure 12 A semiconductor package according to another aspect is shown.

[0024] Figure 13 A semiconductor package according to another aspect is shown.

[0025] Figure 14 A semiconductor package according to another aspect is shown.

[0026] Figure 15 A semiconductor package according to another aspect is shown.

[0027] Figure 16 A semiconductor package according to another aspect is shown.

[0028] Figure 17 A semiconductor package according to another aspect is shown.

[0029] Figure 18A semiconductor package according to another aspect is shown. DETAILED DESCRIPTION

[0030] The present disclosure relates to a semiconductor package having a substrate (e.g., a ceramic substrate) wherein a portion of a surface of the substrate is exposed through a molding such that the substrate acts as a heat sink for one or more heat-generating (e.g., active) components of the package. The substrate includes a first surface and a second surface, and one or more semiconductor dies are coupled to the second surface of the substrate via one or more redistribution layers (e.g., metal traces). In some examples, the redistribution layer is coupled to the first surface of the substrate, and at least a portion of the redistribution layer on the first surface is exposed through the molding. In some examples, the redistribution layer on the first surface is plated with solder. The semiconductor packages discussed herein can reduce the resistance and inductance of the interconnect for at least some of the package components and can provide a path for heat to dissipate when the semiconductor package is activated.

[0031] Figure 1 A semiconductor package 100 according to one aspect is shown. The semiconductor package 100 can reduce the resistance and inductance of interconnects to at least some package components and can provide a path for heat generated when the semiconductor package 100 is activated.

[0032] For example, semiconductor package 100 includes a substrate 102 configured to expose at least a portion of substrate 102 through molding 112, thereby acting as a heat sink. In some examples, substrate 102 includes a ceramic interposer, and the ceramic interposer is configured to serve as a heat dissipation material. In some examples, when a portion of substrate 102 is exposed through molding 112, a heat dissipation path can be created through substrate 102 that allows heat generated by heat-generating components coupled to substrate 102 to be released. In some examples, the dielectric material of a first surface 105 of substrate 102 is exposed through molding 112 on the package exterior. In some examples, metal traces 114 (e.g., a redistribution layer) are coupled to the first surface 105 of substrate 102, and at least a portion of metal traces 114 are exposed through molding 112 on the package exterior. In some examples, the exposure of metal traces 114 through molding 112 can allow substrate 102 to act as a heat sink to release heat from semiconductor package 100. In some examples, the exposure of metal traces 114 through molding 112, in combination with vias 125 extending through substrate 102, can allow substrate 102 to act as a heat sink to release heat from semiconductor package 100. In some examples, the connection of vias 125 to leadframe portion 140 (which is in turn connected to one or more heat-generating components through one or more redistribution layers) can allow substrate 102 to act as a heat sink to release heat from semiconductor package 100.

[0033] In some examples, metal traces 114 are plated with solder. For example, a solder plating layer may be deposited on metal traces 114 during a lead trimming process. In some examples, the exposed, solderable metal traces 114 are configured to connect to another heat sink. In some examples, the first surface 105 of substrate 102 or metal traces 114 are exposed by grinding molding 112 to expose metal traces 114 or first surface 105 of substrate 102. In some examples, a recess is formed in molding 112 to expose at least a portion of first surface 105 or metal traces 114.

[0034] The molding 112 encapsulates at least a majority (e.g., greater than 50%, greater than 75%, greater than 85%, or greater than 90%) of the components of the semiconductor package 100, as compared to the surface area of ​​the components not covered by the molding 112. In some examples, the molding 112 encapsulates all components of the semiconductor package 100 except for a portion of the substrate 102 (and leads extending from the molding 112). In some examples, the molding 112 includes an inorganic material. In some examples, the molding 112 includes an organic material. In some examples, the molding 112 includes a combination of one or more organic materials and / or one or more inorganic materials. In some examples, the molding 112 includes an epoxy material formed from an epoxy resin. In some examples, the molding 112 includes a gel material (e.g., a silicone gel).

[0035] Semiconductor package 100 includes a semiconductor die 104 coupled to a second surface 107 of a substrate 102. In some examples, semiconductor die 104 is coupled to second surface 107 via one or more redistribution layers (e.g., one metal trace or two or more metal traces). In some examples, semiconductor die 104 is coupled (e.g., soldered) to a redistribution layer disposed on second surface 107 via one or more conductive features (e.g., pillars, bumps, etc.). In some examples, semiconductor die 104 is coupled to substrate 102 in a flip-chip configuration. In some examples, semiconductor die 104 includes a transistor (e.g., a bipolar junction transistor, a field-effect transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET)). In some examples, semiconductor die 104 includes one or more integrated circuits (ICs). In some examples, semiconductor die 104 includes a field-effect transistor (FET). In some examples, semiconductor die 104 includes a gallium nitride (GaN) low-side or high-side semiconductor die. In some examples, semiconductor die 104 includes a driver IC die. In some examples, a plurality of semiconductor dies are coupled to the second surface 107 of the substrate.

[0036] Semiconductor package 100 includes leadframe portion 140 and leadframe portion 142. Leadframe portion 140 and leadframe portion 142 are coupled to second surface 107 of substrate 102. In some examples, leadframe portion 140 and leadframe portion 142 are coupled to substrate second surface 107 via one or more redistribution layers.

[0037] In some examples, the substrate includes a through-hole 125 extending through substrate 102. In some examples, the substrate includes a plurality of through-holes 125. In some examples, through-holes 125 are holes having a metal fill. In some examples, through-holes 125 are copper-filled holes that enable metal traces 114 to be plated with solder. In some examples, through-holes 125 are coupled to leadframe portion 140. Through-holes 125 can connect metal traces 114 to leadframe portion 140, thereby enabling a current path to be formed during electrolytic solder plating. In some examples, metal traces 114, through-holes 125, and the connection of through-holes 125 to leadframe portion 140 (as well as the exposure of at least a portion of metal traces 114 through molding 112) create a heat dissipation path that allows heat to escape from semiconductor package 100, helping to prevent semiconductor package 100 from overheating and potentially damaging its components.

[0038] Figure 2A A semiconductor package 200 according to one aspect is shown. Figure 2B A cross-sectional view of a semiconductor package 200 taken along line 201 is shown according to one aspect. Figure 2C A cross-sectional view of semiconductor package 200 taken along line 203 is shown according to one aspect. Figure 2D An isometric top view of a semiconductor package 200 is shown, according to one aspect. Figure 2E FIG. 1 shows a package configuration diagram of a semiconductor package 200 according to one aspect. Figure 2F An isometric bottom view of a semiconductor package 200 is shown, according to one aspect. Figure 2G An isometric solid top view of a semiconductor package 200 is shown according to one aspect. Figure 2H FIG2 shows a cross-sectional view of a semiconductor package 200 according to one aspect. In some examples, the semiconductor package 200 comprises a package having molded-on two sides and formed-on four sides with leads.

[0039] The semiconductor package 200 can reduce the resistance and inductance of the interconnect for at least some package components and can provide a path for dissipating heat generated when the semiconductor package 200 is activated. For example, the semiconductor package 200 includes a substrate 202 that is configured to expose at least a portion of the substrate 202 through a molding 212, thereby acting as a heat sink. In some examples, the dielectric material of the surface of the substrate 202 is exposed through the molding 212 on the package exterior. In some examples, a redistribution layer (e.g., a metal trace or a copper metal trace) is coupled to the surface of the substrate 202, and at least a portion of the redistribution layer is exposed through the molding 212 on the package exterior, such as Figure 2G As shown. In some examples, the redistribution layer is plated with solder. For example, the solder plating can be deposited on the redistribution layer during the lead trimming process. In some examples, the surface of substrate 202 is exposed by grinding molding 212 to expose at least a portion of the surface or the redistribution layer. In some examples, a recess is formed in molding 212 to expose at least a portion of the surface or the redistribution layer.

[0040] Semiconductor package 200 includes substrate 202, first semiconductor die 204, second semiconductor die 206, and third semiconductor die 208. In some examples, first semiconductor die 204, second semiconductor die 206, and third semiconductor die 208 are active components within semiconductor package 200.

[0041] In some examples, first semiconductor die 204 includes a low-side semiconductor power device. In some examples, first semiconductor die 204 includes a transistor (e.g., a bipolar junction transistor, a field effect transistor, a metal oxide semiconductor field effect transistor (MOSFET)). In some examples, first semiconductor die 204 includes one or more integrated circuits (ICs). In some examples, first semiconductor die 204 includes a field effect transistor (FET). In some examples, first semiconductor die 204 includes a gallium nitride (GaN) low-side semiconductor die.

[0042] In some examples, second semiconductor die 206 includes a high-side semiconductor power device. In some examples, second semiconductor die 206 includes a transistor (e.g., a bipolar junction transistor, a field effect transistor, a metal oxide semiconductor field effect transistor (MOSFET)). In some examples, second semiconductor die 206 includes one or more ICs. In some examples, second semiconductor die 206 includes a field effect transistor (FET). In some examples, second semiconductor die 206 includes a gallium nitride (GaN) low-side semiconductor die. In some examples, third semiconductor die 208 includes a driver IC die. In some examples, third semiconductor die 208 includes a transistor (e.g., a bipolar junction transistor, a field effect transistor, a metal oxide semiconductor field effect transistor (MOSFET)). In some examples, third semiconductor die 208 includes one or more ICs. In some examples, semiconductor package 200 accommodates first semiconductor die 204 and second semiconductor die 206 at an isolation gap compatible with 650V-800V or higher rated voltage isolation (e.g., greater than 800V).

[0043] Molding 212 encapsulates at least most of the components of semiconductor package 200. In some examples, molding 212 encapsulates all components of semiconductor package 200 except for a portion of substrate 202 (and leads extending from molding 212). In some examples, molding 212 includes an inorganic material. In some examples, molding 212 includes an organic material. In some examples, molding 212 includes a combination of one or more organic materials and / or one or more inorganic materials. In some examples, molding 212 includes an epoxy material formed from an epoxy resin. In some examples, molding 212 includes a gel material (e.g., silicone gel).

[0044] First semiconductor die 204, second semiconductor die 206, and third semiconductor die 208 are coupled to substrate 202. In some examples, semiconductor package 200 includes one or more passive components 210 coupled to substrate 202. Passive components 210 can be any type of component that does not generate energy but can store or dissipate energy. In some examples, passive components 210 include capacitors. In some examples, passive components 210 include resistors, inductors, and / or transformers.

[0045] Semiconductor package 200 includes a lead frame that defines a plurality of leads, such as a first lead 230-1, a second lead 230-2, a third lead 230-3, a fourth lead 230-4, a fifth lead 230-5, a sixth lead 230-6, a seventh lead 230-7, an eighth lead 230-8, a ninth lead 230-9, a tenth lead 230-10, an eleventh lead 230-11, a twelfth lead 230-12, and a thirteenth lead 230-13. A portion of the leads may be considered a lead frame portion. In some examples, semiconductor package 200 includes fewer than thirteen leads. In some examples, semiconductor package 200 includes more than thirteen leads. The leads may define external contacts, pins, or input / outputs (I / Os) for connecting semiconductor package 200 to one or more external devices. In some examples, the semiconductor package 200 includes bonding bar components, such as a first bonding bar 232-1, a second bonding bar 232-2, a third bonding bar 232-3, and a fourth bonding bar 232-4, disposed at corner portions of the semiconductor package 200. The bonding bars (e.g., 232-1, 232-2, 232-3, and 232-4) are attached between the corners of the die mounting pad 211 and the lead frame, and may partially form barrier bars for keeping the leads separated at a desired interval during the package molding process.

[0046] Each of the leads can be any type of lead used in the package structure. In some examples, the leads include one or more curves or curved portions extending from the molding 212. In some examples, the first lead 230-1 is an input voltage (VIN) lead. In some examples, the second lead 230-2 is a switch (SW) lead. In some examples, the third lead 230-3 is a high power supply voltage (VDDH) lead. In some examples, the fourth lead 230-4 is a boot (BOOT) lead. In some examples, the fifth lead 230-5 is a power switch ground (PGND) lead. In some examples, the sixth lead 230-6 is a low power supply voltage (VDDL) lead. In some examples, the seventh lead 230-7 is a non-contact (NC) lead. In some examples, the eighth lead 230-8 is an enable (EN) lead. In some examples, the ninth lead 230-9 is a low-side input (LIN) lead. In some examples, the tenth lead 230-10 is a high-side input (HIN) lead. In some examples, the eleventh lead 230-11 is a DT lead. In some examples, the twelfth lead 230-12 is a signal ground (SGND) lead. In some examples, the thirteenth lead 230-13 is a power supply (VDD) lead.

[0047] Substrate 202 may include a dielectric material. In some examples, substrate 202 is a ceramic substrate. Substrate 202 includes a first surface 205 and a second surface 207 opposite first surface 205. In some examples, first surface 205 and second surface 207 are planar or substantially planar. In some examples, first surface 205 is considered a top surface. In some examples, first surface 205 is the surface exposed through molding 212. In some examples, second surface 207 is considered a bottom surface. In some examples, second surface 207 is the surface attached to the leadframe portion and / or first semiconductor die 204, second semiconductor die 206, and third semiconductor die 208. The distance between first surface 205 and second surface 207 may define the thickness of substrate 202. In some examples, the thickness of substrate 202 ranges from 15 to 100 mils. In some examples, the thickness of substrate 202 is at least 15 mils. In some examples, the thickness of substrate 202 is less than 15 mils.

[0048] like Figure 2B and Figure 2F As shown in FIG, the first semiconductor die 204 and the third semiconductor die 208 are coupled to the second surface 207 of the substrate 202. Figure 2C 、 Figure 2F and Figure 2H As shown in FIG, second semiconductor die 206 and passive devices 210 are coupled to second surface 207 of substrate 202. In some examples, first semiconductor die 204, second semiconductor die 206, and third semiconductor die 208 are coupled to second surface 207 of substrate 202 in a flip-chip configuration.

[0049] In some examples, three redistribution layers (e.g., metal traces) are coupled to (or formed on top of) substrate 202, including a top redistribution layer coupled to first surface 205 of substrate 202, a first bottom redistribution layer coupled to second surface 207 of substrate 202, and a second bottom redistribution layer coupled to the first bottom redistribution layer. In some examples, two redistribution layers are coupled to substrate 202 (e.g., the top redistribution layer is omitted). In some examples, one redistribution layer is coupled to substrate 202 (e.g., the top redistribution layer and the second bottom redistribution layer are omitted). Each of first semiconductor die 204, second semiconductor die 206, third semiconductor die 208, and passive devices 210 is connected to the first bottom redistribution layer and / or the second bottom redistribution layer.

[0050] In more detail, first metal trace 214 (eg, top redistribution layer) is coupled to first surface 205 of substrate 202. In some examples, first metal trace 214 is directly coupled to first surface 205 of substrate 202. In some examples, first metal trace 214 is a copper metal trace. Figure 2D As shown, at least a portion of first metal trace 214 can be exposed through molding 212. In some examples, the entire outer surface of first metal trace 214 is exposed through molding 212.

[0051] A second metal trace 216 (eg, a first bottom redistribution layer) is coupled to the second surface 207 of the substrate 202. In some examples, the second metal trace 216 is directly coupled to the second surface 207 of the substrate 202. In some examples, the second metal trace 216 is a copper metal trace. Figure 2B As shown, third semiconductor die 208 is connected to second metal trace 216. In some examples, third semiconductor die 208 is soldered to second metal trace 216. In some examples, third semiconductor die 208 is connected to second metal trace 216 via one or more conductive features (e.g., bumps, pillars, etc.). Third metal trace 218 (e.g., a second bottom redistribution layer) is coupled to a portion of second metal trace 216. In some examples, third metal trace 218 is directly coupled to a portion of second metal trace 216. In some examples, third metal trace 218 is a copper metal trace. In some examples, third metal trace 218 can serve as a spacer under the flip die (e.g., first semiconductor die 204, second semiconductor die 206) for proper mold fill. In some examples, third metal trace 218 can provide the correct Z height clearance to meet isolation requirements and for stack assembly when connected to a lead frame.

[0052] In some examples, first semiconductor die 204 is connected to third metal trace 218. In some examples, first semiconductor die 204 is soldered to third metal trace 218. In some examples, first semiconductor die 204 is connected to third metal trace 218 via one or more conductive features (e.g., bumps, pillars, etc.). In some examples, second semiconductor die 206 is connected to third metal trace 218. In some examples, second semiconductor die 206 is soldered to third metal trace 218. In some examples, second semiconductor die 206 is connected to third metal trace 218 via one or more conductive features (e.g., bumps, pillars, etc.).

[0053] like Figure 2BAs shown, leadframe portion 220 is connected to third metal trace 218, and leadframe portion 222 is connected to third metal trace 218. In some examples, leadframe portion 220 is part of a first lead 230-1 (e.g., a VIN lead), and leadframe portion 222 is part of a twelfth lead 230-12 (e.g., an SGND lead).

[0054] like Figure 2C As shown, leadframe portion 224, passive device 210, leadframe portion 226, and leadframe portion 228 are coupled to substrate 202 via at least one of second metal trace 216 or third metal trace 218. In some examples, leadframe portion 224 is connected to third metal trace 218. For example, second metal trace 216 and third metal trace 218 are disposed between leadframe portion 226 and substrate 202, and leadframe portion 224 is directly connected to third metal trace 218. In other examples, second metal trace 216 is disposed between leadframe portion 226 and substrate 202 (e.g., not third metal trace 218). In some examples, leadframe portion 224 is part of fifth lead 230-5 (e.g., a PGND lead).

[0055] In some examples, passive device 210 is directly bonded to substrate 202. In some examples, passive device 210 is connected to second metal trace 216. For example, second metal trace 216 is disposed between passive device 210 and substrate 202. In some examples, leadframe portion 226 is connected to third metal trace 218. In some examples, second metal trace 216 and third metal trace 218 are disposed between leadframe portion 226 and substrate 202. In some examples, leadframe portion 226 is part of sixth lead 230-6 (e.g., a VDDL lead). In some examples, leadframe portion 228 is connected to third metal trace 218. For example, second metal trace 216 and third metal trace 218 are disposed between leadframe portion 228 and substrate 202. In some examples, leadframe portion 228 is part of seventh lead 230-7 (e.g., an NC lead).

[0056] like Figure 2C and Figure 2FAs shown, substrate 202 includes a through-hole 225 extending through substrate 202. In some examples, substrate 202 includes a plurality of through-holes 225. In some examples, through-holes 225 are holes having a metal fill. In some examples, through-holes 225 are copper-filled through-holes that enable first metal trace 214 to be solder-plated. In some examples, through-holes 225 are coupled to leadframe portion 228. Through-holes 225 can connect first metal trace 214 to leadframe portion 228, thereby enabling a current path to be formed during electrolytic solder plating. Through-holes 225 can extend through substrate 202 between first metal trace 214 and second metal trace 216 at a location adjacent to leadframe portion 228. In some examples, as described above, leadframe portion 228 is part of an NC lead. In some examples, through-holes 225 can enable first metal trace 214 to be solder-plated. For example, if there is space available for an NC lead, the NC lead can be used as a temporary connection to the first metal trace 214 passing through the via 225. Therefore, during the lead trimming process, solder plating can be deposited on the first metal trace 214. In some examples, the NC lead can be soldered as a dummy lead on a printed circuit board (PCB).

[0057] Figure 3A and Figure 3B A semiconductor package 200 is shown with a top-side cooling option according to one aspect. Figure 3A and Figure 3B The semiconductor package 200 may include any of the features discussed with reference to the previous figures. For example, the first metal trace 214 is coupled to the first surface 205 of the substrate 202, and the leadframe portion 224, the second semiconductor die 206, the first semiconductor die 204, and the leadframe portion 220 are coupled to the second surface 207 of the substrate 202 (e.g., via the second metal trace 216 and the third metal trace 218).

[0058] exist Figure 3A In some examples, the top surface of the molding 212 is ground to expose the first metal trace 214. In this example, the top surface of the molding 212 is adjacent to and substantially flush with the top surface of the first metal trace 214. In some examples, the entire top surface of the first metal trace 214 is exposed through the molding 212. Figure 3B In some examples, a recess is formed in the molding 212 to expose the first metal trace 214. In some examples, a portion of the first metal trace 214 is exposed through the molding 212, and a portion of the first metal trace 214 is covered by the molding 212. In some examples, see Figure 3B , a top surface of first metal trace 214 is disposed below a top surface of molding 212 .

[0059] Figure 4A and Figure 4B A semiconductor package 400 is shown, which is similar to Figures 2A to 3B The semiconductor package 200 is shown in FIG. 2 , except that the seventh lead 430 - 7 (eg, an NC lead) is trimmed away (eg, hanging freely on the side of the package). Figure 4A A perspective view of a semiconductor package 400 according to an aspect is shown. Figure 4B A cross-section of semiconductor package 400 is shown along line 403 according to one aspect. Figure 4A and Figure 4B An example of an isolated solderable heat sink is shown. The semiconductor package 400 can include any of the features discussed with reference to the previous figures.

[0060] For example, semiconductor package 400 includes a substrate 402, a first semiconductor die 404, a second semiconductor die 406, a third semiconductor die 408, a passive device 410, a first metal trace 414, a second metal trace 416, and a third metal trace 418. Semiconductor package 400 includes a molding 412 that encapsulates all components of semiconductor package 400 except a portion of substrate 402 and portions of leads extending from molding 412. The semiconductor package 400 includes a lead frame that defines a plurality of leads, such as a first lead 430-1, a second lead 430-2, a third lead 430-3, a fourth lead 430-4, a fifth lead 430-5, a sixth lead 430-6, a seventh lead 430-7, an eighth lead 430-8, a ninth lead 430-9, a tenth lead 430-10, an eleventh lead 430-11, a twelfth lead 430-12, and a thirteenth lead 430-13.

[0061] like Figure 4B As shown, lead frame portion 424, passive device 410, lead frame portion 426, and lead frame portion 428 are coupled to substrate 402 via at least one of second metal trace 416 or third metal trace 418. In some examples, lead frame portion 424 is a portion of fifth lead 430-5 (e.g., a PGND lead). In some examples, lead frame portion 426 is a portion of sixth lead 430-6 (e.g., a VDDL lead). In some examples, lead frame portion 428 is a portion of seventh lead 430-7 (e.g., an NC lead).

[0062] like Figure 4BAs shown, substrate 402 includes a through hole 425 extending through substrate 402. In some examples, through hole 425 is a copper-filled through hole that enables first metal trace 414 to be solder-plated. For example, if there is space available for an NC lead, the NC lead can be used as a temporary connection to first metal trace 414 passing through through hole 425. Therefore, during the lead trimming process, solder plating can be deposited on first metal trace 414. In some examples, such as Figure 4A As shown, the seventh lead 430 - 7 (eg, an NC lead) is trimmed off (eg, hanging freely over the side of the package).

[0063] Figure 5A and Figure 5B A semiconductor package 500 is shown, which is similar to Figures 2A to 3B The semiconductor package 200 or Figure 4A and Figure 4B The semiconductor package 400 is different in that the neutral lead (eg, the eighth lead 530-8 (eg, the EN lead)) is used as the dielectric conductive path to the first metal trace 514. Figures 2A to 3B In the example of FIG, the seventh lead 230-7 (eg, NC lead) is used as an electrolyte conductive path to the first metal trace 214. Figure 4A and Figure 4B In the example of FIG. 4 , the seventh lead 430 - 7 (eg, NC lead) is used as an electrolyte conductive path to the first metal trace 414 , but the seventh lead 430 - 7 is smaller than the first metal trace 414 . Figures 2A to 3B The seventh lead 230-7 is shorter. Figure 5A and Figure 5B In the example of FIG. 5 , the eighth lead 530 - 8 (eg, the EN lead) is used as a dielectric conductive path to the first metal trace 514 .

[0064] Figure 5A A perspective view of a semiconductor package 500 according to an aspect is shown. Figure 5B A cross-section of semiconductor package 500 is shown along line 503 according to one aspect. Figure 5A and Figure 5B An example of an isolated solderable heat sink is shown. The semiconductor package 500 can include any of the features discussed with reference to the previous figures.

[0065] For example, semiconductor package 500 includes a substrate 502, a first semiconductor die 504, a second semiconductor die 506, a third semiconductor die 508, a passive device 510, a first metal trace 514, a second metal trace 516, and a third metal trace 518. Semiconductor package 500 includes a molding 512 that encapsulates most components of semiconductor package 500 except for a portion of substrate 502 and portions of leads extending from molding 512. The semiconductor package 500 includes a lead frame that defines a plurality of leads, such as a first lead 530-1, a second lead 530-2, a third lead 530-3, a fourth lead 530-4, a fifth lead 530-5, a sixth lead 530-6, a seventh lead 530-7, an eighth lead 530-8, a ninth lead 530-9, a tenth lead 530-10, an eleventh lead 530-11, a twelfth lead 530-12, and a thirteenth lead 530-13.

[0066] like Figure 5B As shown, lead frame portion 524, passive device 510, and lead frame portion 527 are coupled to substrate 502 via at least one of second metal trace 516 or third metal trace 518. In some examples, lead frame portion 524 is a portion of fifth lead 530-5 (e.g., a PGND lead). In some examples, lead frame portion 527 is a portion of eighth lead 530-8 (e.g., an EN lead).

[0067] like Figure 5B As shown, substrate 502 includes a via 525 extending through substrate 502. In some examples, via 525 is a copper-filled through-hole that enables first metal trace 514 to be solder-plated. For example, if there is insufficient space for a dummy lead (or non-functional lead (NC lead)), the neutral I / O lead can be used as a dielectric conductive path to first metal trace 514 (through via 525). In some examples, the EN lead can be considered neutral with respect to the PGND lead, the VIN lead, and the SW lead, and therefore may not have leakage limitations.

[0068] Figure 6A and Figure 6B A semiconductor package 600 is shown, which is similar to Figures 2A to 3B Semiconductor package 200, Figure 4A and Figure 4B The semiconductor package 400, or Figure 5A and Figure 5B The semiconductor package 500 is shown in FIG. 5 , except that a bonding bar (eg, the third bonding bar 632 - 3 ) is used as an electrolyte conductive path to the first metal trace 614 . Figure 6A A perspective view of a semiconductor package 600 according to an aspect is shown. Figure 6BA cross-section of semiconductor package 600 is shown along line 603 according to one aspect. Figure 6A and Figure 6B An example of an isolated solderable heat sink is shown. The semiconductor package 600 can include any of the features discussed with reference to the previous figures.

[0069] For example, semiconductor package 600 includes a substrate 602, a first semiconductor die 604, a second semiconductor die 606, a third semiconductor die 608, a passive device 610, a first metal trace 614, a second metal trace 616, a third metal trace 618, and a molding 612. Semiconductor package 600 includes a leadframe that defines a plurality of leads, such as a first lead 630-1, a second lead 630-2, a third lead 630-3, a fourth lead 630-4, a fifth lead 630-5, a sixth lead 630-6, a seventh lead 630-7, an eighth lead 630-8, a ninth lead 630-9, a tenth lead 630-10, an eleventh lead 630-11, a twelfth lead 630-12, and a thirteenth lead 630-13. In some examples, the semiconductor package 600 includes bonding bar members disposed at corner portions of the semiconductor package 600 , such as a first bonding bar 632 - 1 , a second bonding bar 632 - 2 , a third bonding bar 632 - 3 , and a fourth bonding bar 632 - 4 .

[0070] like Figure 6B As shown, lead frame portion 624, passive device 610, lead frame portion 626, lead frame portion 628, and bonding bar 629 are coupled to substrate 602 via at least one of second metal trace 616 or third metal trace 618. In some examples, lead frame portion 624 is a portion of fifth lead 630-5 (e.g., a PGND lead). In some examples, lead frame portion 626 is a portion of sixth lead 630-6 (e.g., a VDDL lead). In some examples, lead frame portion 628 is a portion of seventh lead 630-7 (e.g., an NC lead). In some examples, bonding bar portion 629 is a portion of third bonding bar 632-3.

[0071] like Figure 6B As shown, substrate 602 includes a through-hole 625 extending through substrate 602. In some examples, through-hole 625 is a copper-filled through-hole that enables solder plating of first metal trace 614. For example, if there is insufficient space for a dummy lead (non-functional lead (NC lead)) or a neutral I / O lead, a corner-cut bonding bar (e.g., third bonding bar 632-3) can be used as a dielectric conductive path to first metal trace 614 (through through-hole 625).

[0072] Figure 7A 、 Figure 7B and Figure 7C A semiconductor package 700 is shown having an exposed substrate configured as a heat sink and flat leads extending from the package. In some examples, semiconductor package 700 may be advantageous when there are Z-height limitations on the circuit board base. In some examples, semiconductor package 700 includes a one-sided molding with flat leads. Although semiconductor package 700 shows leads on four sides, semiconductor package 700 may include leads on only two sides. Semiconductor package 700 may include any of the features discussed with reference to the previous figures.

[0073] Figure 7A A perspective view of a semiconductor package 700 according to an aspect is shown. Figure 7B A cross-section of a semiconductor package 700 is shown along line 701 according to an aspect. Figure 7C A cross-section of semiconductor package 700 is shown along line 703 according to one aspect.

[0074] Semiconductor package 700 includes a substrate 702, a first semiconductor die 704, a second semiconductor die 706, and a third semiconductor die 708. In some examples, first semiconductor die 704 includes a low-side semiconductor power device. In some examples, second semiconductor die 706 includes a high-side semiconductor power device. Semiconductor package 700 includes a molding 712 that encapsulates at least most components of semiconductor package 700. In some examples, molding 712 encapsulates all components of semiconductor package 700 except a portion of substrate 702 and portions of leads extending from molding 712.

[0075] A first semiconductor die 704, a second semiconductor die 706, and a third semiconductor die 708 are coupled to a substrate 702. In some examples, the semiconductor package 700 includes one or more passive devices 710 coupled to the substrate 702. In some examples, the passive devices 710 include capacitors. In some examples, the passive devices 710 include resistors, inductors, and / or transformers.

[0076] Semiconductor package 700 includes a lead frame that defines a plurality of leads, such as a first lead 730-1, a second lead 730-2, a third lead 730-3, a fourth lead 730-4, a fifth lead 730-5, a sixth lead 730-6, a seventh lead 730-7, an eighth lead 730-8, a ninth lead 730-9, a tenth lead 730-10, an eleventh lead 730-11, a twelfth lead 730-12, and a thirteenth lead 730-13. A portion of the leads may be considered a lead frame portion. In some examples, semiconductor package 700 includes fewer than thirteen leads. In some examples, semiconductor package 700 includes more than thirteen leads. The leads may define external contacts, pins, or input / outputs (I / Os) for connecting semiconductor package 700 to one or more external devices. In some examples, semiconductor package 700 includes a bonding bar component as shown in the previous figures.

[0077] Each of the leads can be any type of lead used in a package structure. In some examples, the portion of the leads extending from the molding 712 is planar or flat (e.g., substantially without curvature). In some examples, the first lead 730-1 is a VIN lead, the second lead 730-2 is a SW lead, the third lead 730-3 is a VDDH lead, the fourth lead 730-4 is a BOOT lead, the fifth lead 730-5 is a PGND lead, the sixth lead 730-6 is a VDDL lead, the seventh lead 730-7 is an NC lead, the eighth lead 730-8 is an EN lead, the ninth lead 730-9 is a LIN lead, the tenth lead 730-10 is a HIN lead, the eleventh lead 730-11 is a DT lead, the twelfth lead 730-12 is a SGND lead, and the thirteenth lead 730-13 is a VDD lead.

[0078] The substrate 702 may include a dielectric material. In some examples, the substrate 702 is a ceramic substrate. The substrate 702 includes a first surface 705 and a second surface 707 opposite the first surface 705. In some examples, the first surface 705 and the second surface 707 are planar or substantially planar. In some examples, the first surface 705 is considered the top surface. In some examples, the first surface 705 is the surface exposed through the molding 712. In some examples, the second surface 707 is considered the bottom surface. In some examples, the second surface 707 is the surface attached to the leadframe portion and / or the first semiconductor die 704, the second semiconductor die 706, and the third semiconductor die 708. The distance between the first surface 705 and the second surface 707 may define the thickness of the substrate 702. In some examples, the thickness of the substrate 702 ranges from 15 to 100 mils. In some examples, the thickness of the substrate 702 is at least 15 mils. In some examples, the thickness of the substrate 702 is less than 15 mils.

[0079] like Figure 7B As shown, the first semiconductor die 704 and the third semiconductor die 708 are coupled to the second surface 707 of the substrate 702. Figure 7C As shown, second semiconductor die 706 and passive devices 710 are coupled to second surface 707 of substrate 702. In some examples, first semiconductor die 704, second semiconductor die 706, and third semiconductor die 708 are coupled to second surface 707 of substrate 702 in a flip-chip configuration.

[0080] In some examples, three redistribution layers (e.g., metal traces) are coupled to (or formed on top of) substrate 702, including a top redistribution layer coupled to first surface 705 of substrate 702, a first bottom redistribution layer coupled to second surface 707 of substrate 702, and a second bottom redistribution layer coupled to the first bottom redistribution layer. In some examples, two redistribution layers are coupled to substrate 702 (e.g., the top redistribution layer is omitted). In some examples, one redistribution layer is coupled to substrate 702 (e.g., the top redistribution layer and the second bottom redistribution layer are omitted). Each of first semiconductor die 704, second semiconductor die 706, third semiconductor die 708, and passive devices 710 is connected to the first bottom redistribution layer and / or the second bottom redistribution layer.

[0081] In more detail, a first metal trace 714 (e.g., a top redistribution layer) is coupled to the first surface 705 of the substrate 702. In some examples, the first metal trace 714 is directly coupled to the first surface 705 of the substrate 702. In some examples, the first metal trace 714 is a copper metal trace. At least a portion of the first metal trace 714 can be exposed through the molding 712. In some examples, the entire outer surface of the first metal trace 714 is exposed through the molding 712.

[0082] A second metal trace 716 (eg, a first bottom redistribution layer) is coupled to the second surface 707 of the substrate 702. In some examples, the second metal trace 716 is directly coupled to the second surface 707 of the substrate 702. In some examples, the second metal trace 716 is a copper metal trace. Figure 7BAs shown, the third semiconductor die 708 is connected to the second metal trace 716. In some examples, the third semiconductor die 708 is soldered to the second metal trace 716. In some examples, the third semiconductor die 708 is connected to the second metal trace 716 via one or more conductive features (e.g., bumps, pillars, etc.). A third metal trace 718 (e.g., a second bottom redistribution layer) is coupled to a portion of the second metal trace 716. In some examples, the third metal trace 718 is directly coupled to a portion of the second metal trace 716. In some examples, the third metal trace 718 is a copper metal trace. In some examples, the third metal trace 718 can serve as a spacer under the flip die (e.g., the first semiconductor die 704, the second semiconductor die 706) for proper mold fill. In some examples, the third metal trace 718 can provide the correct Z height clearance to meet isolation requirements and for stack assembly when connected to a lead frame.

[0083] In some examples, first semiconductor die 704 is connected to third metal trace 718. In some examples, first semiconductor die 704 is soldered to third metal trace 718. In some examples, first semiconductor die 704 is connected to third metal trace 718 via one or more conductive features (e.g., bumps, pillars, etc.). In some examples, second semiconductor die 706 is connected to third metal trace 718. In some examples, second semiconductor die 706 is soldered to third metal trace 718. In some examples, second semiconductor die 706 is connected to third metal trace 718 via one or more conductive features (e.g., bumps, pillars, etc.).

[0084] like Figure 7B As shown, leadframe portion 720 is connected to third metal trace 718, and leadframe portion 722 is connected to third metal trace 718. In some examples, leadframe portion 720 is part of a first lead 730-1 (e.g., a VIN lead), and leadframe portion 722 is part of a twelfth lead 730-12 (e.g., an SGND lead).

[0085] like Figure 7CAs shown, leadframe portion 740, passive device 710, second semiconductor die 706, first semiconductor die 704, and leadframe portion 742 are coupled to substrate 702 via at least one of second metal trace 716 or third metal trace 718. In some examples, leadframe portion 740 is connected to third metal trace 718. In some examples, leadframe portion 740 is part of fifth lead 730-5 (e.g., a PGND lead). In some examples, passive device 710 is bonded to second surface 707 of substrate 702. In some examples, passive device 710 is connected to second metal trace 716. In some examples, leadframe portion 742 is connected to third metal trace 718. In some examples, leadframe portion 742 is part of second lead 730-2 (e.g., a SW lead).

[0086] Figure 8A and Figure 8B A semiconductor package 800 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 800 may include leads on only two sides. The semiconductor package 800 may include any of the features discussed with reference to the previous figures. The semiconductor package 800 may be similar to the semiconductor packages discussed previously, except that the passive device 810 is coupled to the lead frame on a side opposite the substrate 802 and includes leads on both sides of the semiconductor package 800.

[0087] Figure 8A A perspective view of a semiconductor package 800 according to an aspect is shown. Figure 8B A cross-section of a semiconductor package 800 taken along line 801 according to one aspect is shown. Semiconductor package 800 includes a substrate 802, a first semiconductor die 804, a second semiconductor die 806, and a third semiconductor die 808. In some examples, first semiconductor die 804 includes a low-side semiconductor power device. In some examples, second semiconductor die 806 includes a high-side semiconductor power device. Semiconductor package 800 includes a molding 812 that encapsulates at least most components of semiconductor package 800. In some examples, molding 812 encapsulates all components of semiconductor package 800 except a portion of substrate 802 and portions of leads extending from molding 812.

[0088] The semiconductor package 800 includes a lead frame that defines a plurality of leads, such as a first lead 830-1 (e.g., a VIN lead), a second lead 830-2 (e.g., a SW lead), a third lead 830-3 (e.g., a VDDH lead), a fourth lead 830-4 (e.g., a BOOT lead), a fifth lead 830-5 (e.g., a PGND lead), a sixth lead 830-6 (e.g., a VDDL lead), a seventh lead 830-7 (e.g., an NC lead), an eighth lead 830-8 (e.g., an EN lead), a ninth lead 830-9 (e.g., a LIN lead), a tenth lead 830-10 (e.g., a HIN lead), an eleventh lead 830-11 (e.g., a DT lead), a twelfth lead 830-12 (e.g., an SGND lead), and a thirteenth lead 830-13 (e.g., a VDD lead). A portion of the leads may be considered a lead frame portion. In some examples, semiconductor package 800 includes fewer than thirteen leads. In some examples, semiconductor package 800 includes more than thirteen leads. Leads can define external contacts, pins, or input / outputs (I / O) for connecting semiconductor package 800 to one or more external devices. In some examples, semiconductor package 800 includes a bonding bar component as shown in the previous figures.

[0089] The substrate 802 may include a dielectric material. In some examples, the substrate 802 is a ceramic substrate. The substrate 802 includes a first surface 805 and a second surface 807 opposite the first surface 805. In some examples, the first surface 805 and the second surface 807 are planar or substantially planar. In some examples, the first surface 805 is considered the top surface. In some examples, the first surface 805 is the surface exposed through the molding 812. In some examples, the second surface 807 is considered the bottom surface. In some examples, the second surface 807 is the surface attached to the leadframe portion and / or the first semiconductor die 804, the second semiconductor die 806, and the third semiconductor die 808. The distance between the first surface 805 and the second surface 807 may define the thickness of the substrate 802. In some examples, the thickness of the substrate 802 ranges from 15 to 100 mils. In some examples, the thickness of the substrate 802 is at least 15 mils. In some examples, the thickness of the substrate 802 is less than 15 mils.

[0090] like Figure 8B As shown, a first semiconductor die 804 and a second semiconductor die 806 are coupled to a second surface 807 of the substrate 802. Also, a third semiconductor die 808 is coupled to the second surface 807 of the substrate 802. In some examples, the first semiconductor die 804, the second semiconductor die 806, and the third semiconductor die 808 are coupled to the second surface 807 of the substrate 802 in a flip-chip configuration.

[0091] In some examples, three redistribution layers (e.g., metal traces) are coupled to (or formed on top of) the substrate 802, including a top redistribution layer coupled to the first surface 805 of the substrate 802, a first bottom redistribution layer coupled to the second surface 807 of the substrate 802, and a second bottom redistribution layer coupled to the first bottom redistribution layer. In some examples, two redistribution layers are coupled to the substrate 802 (e.g., Figure 8B In some examples, one redistribution layer is coupled to substrate 802 (e.g., the top redistribution layer and the second bottom redistribution layer are omitted). Each of first semiconductor die 804, second semiconductor die 806, and third semiconductor die 808 is connected to the first bottom redistribution layer and / or the second bottom redistribution layer.

[0092] In more detail, the first metal trace (eg, top redistribution layer) ( Figure 8B 805 ). In some examples, the first metal trace is directly coupled to the first surface 805 of the substrate 802. In some examples, the first metal trace is a copper metal trace. At least a portion of the first metal trace may be exposed through the molding 812. In some examples, the entire outer surface of the first metal trace is exposed through the molding 812.

[0093] A second metal trace 816 (e.g., a first bottom redistribution layer) is coupled to the second surface 807 of the substrate 802. In some examples, the second metal trace 816 is directly coupled to the second surface 807 of the substrate 802. In some examples, the second metal trace 816 is a copper metal trace. In some examples, the third semiconductor die 808 is connected to the second metal trace 816. A third metal trace 818 (e.g., a second bottom redistribution layer) is coupled to a portion of the second metal trace 816. In some examples, the third metal trace 818 is directly coupled to the portion of the second metal trace 816. In some examples, the third metal trace 818 is a copper metal trace. In some examples, the first semiconductor die 804 is connected to the third metal trace 818. In some examples, the second semiconductor die 806 is connected to the third metal trace 818.

[0094] like Figure 8BAs shown, leadframe portion 820 is connected to third metal trace 818, and leadframe portion 822 is connected to third metal trace 818. In some examples, leadframe portion 820 is part of sixth lead 830-6 (e.g., VDDL lead), and leadframe portion 822 is part of third lead 830-3 (e.g., VDDH lead). Passive device 810 is coupled to the leadframe (on a surface opposite substrate 802). For example, one passive device 810 can be coupled to leadframe portion 820, and another passive device 810 can be coupled to leadframe portion 822.

[0095] Figure 9A and Figure 9B A semiconductor package 900 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 900 may include leads on only two sides. The semiconductor package 900 may include any of the features discussed with reference to the previous figures. The semiconductor package 900 may be similar to the semiconductor packages discussed previously, except that the passive device 910 is coupled to the lead frame adjacent to and on the same side as the substrate 902.

[0096] Figure 9A A perspective view of a semiconductor package 900 according to an aspect is shown. Figure 9B A cross-section of a semiconductor package 900 taken along line 901 according to an aspect is shown. Semiconductor package 900 includes a substrate 902, a first semiconductor die 904, a second semiconductor die 906, and a third semiconductor die 908. In some examples, first semiconductor die 904 includes a low-side semiconductor power device. In some examples, second semiconductor die 906 includes a high-side semiconductor power device. Semiconductor package 900 includes a molding 912 that encapsulates at least most components of semiconductor package 900. In some examples, molding 912 encapsulates all components of semiconductor package 900 except a portion of substrate 902 and portions of leads extending from molding 912.

[0097] The semiconductor package 900 includes a lead frame that defines a plurality of leads, such as a first lead 930-1 (e.g., a VIN lead), a second lead 930-2 (e.g., a SW lead), a third lead 930-3 (e.g., a VDDH lead), a fourth lead 930-4 (e.g., a BOOT lead), a fifth lead 930-5 (e.g., a PGND lead), a sixth lead 930-6 (e.g., a VDDL lead), a seventh lead 930-7 (e.g., an NC lead), an eighth lead 930-8 (e.g., an EN lead), a ninth lead 930-9 (e.g., a LIN lead), a tenth lead 930-10 (e.g., a HIN lead), an eleventh lead 930-11 (e.g., a DT lead), a twelfth lead 930-12 (e.g., an SGND lead), and a thirteenth lead 930-13 (e.g., a VDD lead). A portion of the leads may be considered a lead frame portion. In some examples, semiconductor package 900 includes fewer than thirteen leads. In some examples, semiconductor package 900 includes more than thirteen leads. Leads can define external contacts, pins, or input / outputs (I / O) for connecting semiconductor package 900 to one or more external devices. In some examples, semiconductor package 900 includes bonding bar components as shown in the previous figures.

[0098] Substrate 902 may include a dielectric material. In some examples, substrate 902 is a ceramic substrate. Substrate 902 includes a first surface 905 and a second surface 907 opposite first surface 905. In some examples, first surface 905 and second surface 907 are planar or substantially planar. In some examples, first surface 905 is considered a top surface. In some examples, first surface 905 is the surface exposed through molding 912. In some examples, second surface 907 is considered a bottom surface. In some examples, second surface 907 is the surface attached to the leadframe portion and / or first semiconductor die 904, second semiconductor die 906, and third semiconductor die 908. The distance between first surface 905 and second surface 907 may define the thickness of substrate 902. In some examples, the thickness of substrate 902 ranges from 15 to 100 mils. In some examples, the thickness of substrate 902 is at least 15 mils. In some examples, the thickness of substrate 902 is less than 15 mils.

[0099] like Figure 9B As shown, a first semiconductor die 904 and a second semiconductor die 906 are coupled to a second surface 907 of a substrate 902. Also, a third semiconductor die 908 is coupled to the second surface 907 of the substrate 902. In some examples, the first semiconductor die 904, the second semiconductor die 906, and the third semiconductor die 908 are coupled to the second surface 907 of the substrate 902 in a flip-chip configuration.

[0100] In some examples, three redistribution layers (e.g., metal traces) are coupled to (or formed on top of) the substrate 902, including a top redistribution layer coupled to the first surface 905 of the substrate 902, a first bottom redistribution layer coupled to the second surface 907 of the substrate 902, and a second bottom redistribution layer coupled to the first bottom redistribution layer. In some examples, two redistribution layers are coupled to the substrate 902 (e.g., Figure 9B In some examples, one redistribution layer is coupled to substrate 902 (e.g., the top redistribution layer and the second bottom redistribution layer are omitted). Each of first semiconductor die 904, second semiconductor die 906, and third semiconductor die 908 is connected to the first bottom redistribution layer and / or the second bottom redistribution layer.

[0101] In more detail, the first metal trace (eg, top redistribution layer) ( Figure 9B 905 ). In some examples, the first metal trace is directly coupled to the first surface 905 of the substrate 902. In some examples, the first metal trace is a copper metal trace. At least a portion of the first metal trace may be exposed through the molding 912. In some examples, the entire outer surface of the first metal trace is exposed through the molding 912.

[0102] A second metal trace 916 (e.g., a first bottom redistribution layer) is coupled to the second surface 907 of the substrate 902. In some examples, the second metal trace 916 is directly coupled to the second surface 907 of the substrate 902. In some examples, the second metal trace 916 is a copper metal trace. In some examples, the third semiconductor die 908 is connected to the second metal trace 916. A third metal trace 918 (e.g., a second bottom redistribution layer) is coupled to a portion of the second metal trace 916. In some examples, the third metal trace 918 is directly coupled to a portion of the second metal trace 916. In some examples, the third metal trace 918 is a copper metal trace. In some examples, the first semiconductor die 904 is connected to the third metal trace 918. In some examples, the second semiconductor die 906 is connected to the third metal trace 918.

[0103] like Figure 9BAs shown, leadframe portion 920 is connected to third metal trace 918, and leadframe portion 922 is connected to third metal trace 918. In some examples, leadframe portion 920 is part of sixth lead 930-6 (e.g., VDDL lead), and leadframe portion 922 is part of third lead 930-3 (e.g., VDDH lead). Passive device 910 is coupled to the leadframe (e.g., bonded to the top of the leadframe adjacent to and on the same side as substrate 902). For example, one passive device 910 can be coupled to leadframe portion 920, and another passive device 910 can be coupled to leadframe portion 922.

[0104] Figure 10A and Figure 10B FIG. 1 shows a semiconductor package 1000 having an exposed substrate surface configured as a heat sink according to one aspect. The semiconductor package 1000 may include leads on only two sides. The semiconductor package 1000 may include any of the features discussed with reference to the previous figures. The semiconductor package 1000 may be similar to Figure 8A and Figure 8B The semiconductor package 800 is similar to the semiconductor package 800, except that one or more portions of the third semiconductor die 1008 are connected to one or more leadframe portions using bonding wires 1060. For example, instead of rerouting the redistribution layer to the other side of the substrate 1002, the semiconductor package 100 can use one or more bonding wires 1060 to resolve potential I / O conflicts.

[0105] Figure 10A A perspective view of a semiconductor package 1000 according to an aspect is shown. Figure 10B A cross-section of a semiconductor package 1000 is shown along line 1001 according to one aspect. Figure 10C A cross-section of semiconductor package 100 taken along line 1003 is shown according to one aspect.

[0106] Semiconductor package 1000 includes a substrate 1002, a first semiconductor die 1004, a second semiconductor die 1006, and a third semiconductor die 1008. In some examples, first semiconductor die 1004 includes a low-side semiconductor power device. In some examples, second semiconductor die 1006 includes a high-side semiconductor power device. Semiconductor package 1000 includes a molding 1012 that encapsulates at least most components of semiconductor package 1000. In some examples, molding 1012 encapsulates all components of semiconductor package 1000 except a portion of substrate 1002 and portions of leads extending from molding 1012.

[0107] The semiconductor package 1000 includes a lead frame defining a plurality of leads, such as a first lead 1030-1 (e.g., a VIN lead), a second lead 1030-2 (e.g., a SW lead), a third lead 1030-3 (e.g., a VDDH lead), a fourth lead 1030-4 (e.g., a BOOT lead), a fifth lead 1030-5 (e.g., a PGND lead), a sixth lead 1030-6 (e.g., a VDDL lead), and a fourth lead 1030-7 (e.g., a BOOT lead). 10. The semiconductor package 1000 includes a first lead 1030-7 (e.g., an NC lead), a second lead 1030-8 (e.g., an EN lead), a third lead 1030-9 (e.g., a LIN lead), a fourth lead 1030-10 (e.g., a HIN lead), a fifth lead 1030-11 (e.g., a DT lead), a fifth lead 1030-12 (e.g., an SGND lead), and a fifth lead 1030-13 (e.g., a VDD lead). A portion of the leads may be considered a leadframe portion. In some examples, the semiconductor package 1000 includes fewer than thirteen leads. In some examples, the semiconductor package 1000 includes more than thirteen leads. The leads may define external contacts, pins, or input / outputs (I / Os) for connecting the semiconductor package 1000 to one or more external devices. In some examples, the semiconductor package 1000 includes a bonding bar component as shown in the previous figures.

[0108] Substrate 1002 may include a dielectric material. In some examples, substrate 1002 is a ceramic substrate. Substrate 1002 includes a first surface 1005 and a second surface 1007 opposite first surface 1005. In some examples, first surface 1005 and second surface 1007 are planar or substantially planar. In some examples, first surface 1005 is considered a top surface. In some examples, first surface 1005 is the surface exposed through molding 1012. In some examples, second surface 1007 is considered a bottom surface. In some examples, second surface 1007 is the surface attached to the leadframe portion and / or first semiconductor die 1004, second semiconductor die 1006, and third semiconductor die 1008. The distance between first surface 1005 and second surface 1007 may define the thickness of substrate 1002. In some examples, the thickness of substrate 1002 ranges from 15 to 100 mils. In some examples, the thickness of substrate 1002 is at least 15 mils. In some examples, the thickness of substrate 1002 is less than 15 mils.

[0109] like Figure 10B As shown, a first semiconductor die 1004 and a second semiconductor die 1006 are coupled to a second surface 1007 of the substrate 1002. Figure 10CAs shown, a third semiconductor die 1008 is coupled to the second surface 1007 of the substrate 1002. In some examples, the first semiconductor die 1004, the second semiconductor die 1006, and the third semiconductor die 1008 are coupled to the second surface 1007 of the substrate 1002 in a flip-chip configuration.

[0110] like Figure 10B As shown, leadframe portion 1020 is connected to substrate 1002, and leadframe portion 1022 is connected to substrate 1002. In some examples, leadframe portion 1020 is part of sixth lead 1030-6 (e.g., VDDL lead), and leadframe portion 1022 is part of third lead 1030-3 (e.g., VDDH lead). Passive devices 1010 are coupled to the leadframe (on a surface opposite substrate 1002). For example, one passive device 1010 can be coupled to leadframe portion 1020, and another passive device 1010 can be coupled to leadframe portion 1022. Figure 10C As shown, leadframe portion 1040 and leadframe portion 1042 are coupled to the substrate, and bond wires 1060 may be connected to leadframe portion 1042 and substrate 1002 .

[0111] In some examples, three redistribution layers (e.g., metal traces) are coupled to (or formed on top of) substrate 1002, including a top redistribution layer coupled to first surface 1005 of substrate 1002, a first bottom redistribution layer coupled to second surface 1007 of substrate 1002, and a second bottom redistribution layer coupled to the first bottom redistribution layer. In some examples, two redistribution layers are coupled to substrate 1002 (e.g., Figure 10B In some examples, one redistribution layer is coupled to substrate 1002 (e.g., the top redistribution layer and the second bottom redistribution layer are omitted). Each of first semiconductor die 1004, second semiconductor die 1006, and third semiconductor die 1008 is connected to the first bottom redistribution layer and / or the second bottom redistribution layer.

[0112] Figures 11 to 18 According to one aspect, a dual cooling technique for any of the aforementioned semiconductor packages is shown. Figures 11 to 18 The semiconductor package may include any of the features discussed with reference to the previous figures.

[0113] Figure 11A semiconductor package 1100 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1100 includes a substrate 1102 having a first surface 1105 and a second surface 1107. The semiconductor package 1100 includes a molding 1112 configured to encapsulate all components of the semiconductor package 1100 except for a portion of the substrate 1102 (e.g., a top surface of the substrate 1102) and portions of leads extending from the molding 1112. Figure 11 , the top surface of the molding 1112 is ground to expose the first surface 1105 of the substrate 1102 (eg, bare ceramic). In some examples, the entire top surface of the substrate 1102 is exposed through the molding 1112.

[0114] The semiconductor package 1100 includes a first semiconductor die 1104 (e.g., a low-side semiconductor power die) and a second semiconductor die 1106 (e.g., a high-side semiconductor power die). In addition, the semiconductor package 1100 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the aforementioned figures. In addition, the semiconductor package 1100 includes a passive device 1110 (e.g., a capacitor). The first semiconductor die 1104 and the second semiconductor die 1106 can be coupled to the substrate 1102 via one or more redistribution layers. In some examples, the first surface 1105 of the substrate 1102 is free of redistribution layers (e.g., bare ceramic is exposed).

[0115] See also Figure 11 1102 , a lead frame portion 1140, a first semiconductor die 1104, a second semiconductor die 1106, and a lead frame portion 1142 can be coupled to the second surface 1107 of the substrate 1102. The lead frame portion 1140 and the lead frame portion 1142 can be any portion of the leads discussed with reference to the previous figures. The passive devices 1110 can be coupled to the lead frame on the side opposite the substrate 1102. For example, one passive device 1110 can be coupled to the lead frame portion 1140 (at a position opposite the substrate 1102), and another passive device 1110 can be coupled to the lead frame portion 1142 (at a position opposite the substrate 1102).

[0116] Figure 12A semiconductor package 1200 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1200 includes a substrate 1202 having a first surface 1205 and a second surface 1207. The semiconductor package 1200 includes a metal trace 1214 (e.g., a top redistribution layer) coupled to the first surface 1205. The semiconductor package 1200 includes a molding 1212 configured to encapsulate all components of the semiconductor package 1200 except for a portion of the substrate 1202 (e.g., the top surface of the substrate 1202) and portions of the leads extending from the molding 1212. Figure 12 , the top surface of the molding 1212 is ground to expose the metal traces 1214 of the substrate 1202. In some examples, the entire metal traces 1214 are exposed through the molding 1212. In some examples, the metal traces 1214 are plated with solder.

[0117] The semiconductor package 1200 includes a first semiconductor die 1204 (e.g., a low-side semiconductor power die) and a second semiconductor die 1206 (e.g., a high-side semiconductor power die). Furthermore, the semiconductor package 1200 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the preceding figures. Furthermore, the semiconductor package 1200 includes a passive device 1210 (e.g., a capacitor). The first semiconductor die 1204 and the second semiconductor die 1206 may be coupled to the substrate 1202 via one or more redistribution layers.

[0118] See also Figure 12 1202 , a lead frame portion 1240, a first semiconductor die 1204, a second semiconductor die 1206, and a lead frame portion 1242 can be coupled to the second surface 1207 of the substrate 1202. The lead frame portion 1240 and the lead frame portion 1242 can be any portion of the leads discussed with reference to the previous figures. The passive devices 1210 can be coupled to the lead frame on the side opposite the substrate 1202. For example, one passive device 1210 can be coupled to the lead frame portion 1240 (at a position opposite the substrate 1202), and another passive device 1210 can be coupled to the lead frame portion 1242 (at a position opposite the substrate 1202).

[0119] Figure 13 A semiconductor package 1300 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1300 includes a substrate 1302 having a first surface 1305 and a second surface 1307. The semiconductor package 1300 includes a molding 1312 configured to encapsulate all components of the semiconductor package 1300 except for a portion of the substrate 1302 (e.g., a top surface of the substrate 1302) and portions of leads extending from the molding 1312. Figure 13, the top surface of the molding 1312 is ground to expose the first surface 1305 of the substrate 1302. In some examples, the entire top surface of the substrate 1302 is exposed through the molding 1312.

[0120] The semiconductor package 1300 includes a first semiconductor die 1304 (e.g., a low-side semiconductor power die) and a second semiconductor die 1306 (e.g., a high-side semiconductor power die). In addition, the semiconductor package 1300 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the aforementioned figures. In addition, the semiconductor package 1300 includes a passive device 1310 (e.g., a capacitor). The passive device 1310 may be coupled to a lead frame on the same side as the substrate 1302. The first semiconductor die 1304 and the second semiconductor die 1306 may be coupled to the substrate 1302 via one or more redistribution layers. In some examples, the first surface 1305 of the substrate 1302 is free of redistribution layers (e.g., bare ceramic is exposed).

[0121] See also Figure 13 1302 , a lead frame portion 1340, a first semiconductor die 1304, a second semiconductor die 1306, and a lead frame portion 1342 can be coupled to the second surface 1307 of the substrate 1302. The lead frame portion 1340 and the lead frame portion 1342 can be any portion of the leads discussed with reference to the previous figures. The passive devices 1310 can be coupled to the lead frame on the same side as the substrate 1302. For example, one passive device 1310 can be coupled to the lead frame portion 1340 (at the same side as the substrate 1302), and another passive device 1310 can be coupled to the lead frame portion 1342 (at the same side as the substrate 1302).

[0122] Figure 14 A semiconductor package 1400 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1400 includes a substrate 1402 having a first surface 1405 and a second surface 1407. The semiconductor package 1400 includes a metal trace 1414 (e.g., a top redistribution layer) coupled to the first surface 1405. In addition, the semiconductor package 1400 includes a metal spacer 1415 coupled to the metal trace 1414. In some examples, the metal spacer 1415 is a metal heat slug. The semiconductor package 1400 includes a molding 1412 that is configured to encapsulate all components of the semiconductor package 1400 except for a portion of the substrate 1402 (e.g., the top surface of the substrate 1402) and portions of the leads extending from the molding 1412. See Figure 14, the top of the molding 1412 is ground to expose the metal spacers 1415 of the substrate 1402. The metal spacers 1415 can help prevent accidental grinding of the top surface of the passive device 1410 (or other larger components included in the package).

[0123] The semiconductor package 1400 includes a first semiconductor die 1404 (e.g., a low-side semiconductor power die) and a second semiconductor die 1406 (e.g., a high-side semiconductor power die). Furthermore, the semiconductor package 1400 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the preceding figures. Furthermore, the semiconductor package 1400 includes a passive device 1410. The first semiconductor die 1404 and the second semiconductor die 1406 may be coupled to the substrate 1402 via one or more redistribution layers.

[0124] See also Figure 14 1402 , a lead frame portion 1440, a first semiconductor die 1404, a second semiconductor die 1406, and a lead frame portion 1442 can be coupled to the second surface 1407 of the substrate 1402. The lead frame portion 1440 and the lead frame portion 1442 can be any portion of the leads discussed with reference to the previous figures. The passive devices 1410 can be coupled to the lead frame on the same side as the substrate 1402. For example, one passive device 1410 can be coupled to the lead frame portion 1440 (at the same side as the substrate 1402), and another passive device 1410 can be coupled to the lead frame portion 1442 (at the same side as the substrate).

[0125] Figure 15 A semiconductor package 1500 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1500 includes a substrate 1502 having a first surface 1505 and a second surface 1507. The semiconductor package 1500 includes a molding 1512 configured to encapsulate all components of the semiconductor package 1500 except for a portion of the substrate 1502 (e.g., the top surface of the substrate 1502). Figure 15 In some examples, a recess is formed in molding 1512 to expose first surface 1505. In some examples, a portion of first surface 1505 is exposed through molding 1512, and a portion of first surface 1505 is covered by molding 1512. In some examples, first surface 1505 is disposed below a top surface of molding 1512.

[0126] Semiconductor package 1500 includes a first semiconductor die 1504 (e.g., a low-side semiconductor power die) and a second semiconductor die 1506 (e.g., a high-side semiconductor power die). In addition, semiconductor package 1500 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the preceding figures. In addition, semiconductor package 1500 includes passive components 1510. First semiconductor die 1504 and second semiconductor die 1506 can be coupled to substrate 1502 via one or more redistribution layers. In some examples, a first surface 1505 of substrate 1502 is free of redistribution layers (e.g., bare ceramic is exposed).

[0127] See also Figure 15 1502 , a lead frame portion 1540, a first semiconductor die 1504, a second semiconductor die 1506, and a lead frame portion 1542 can be coupled to the second surface 1507 of the substrate 1502. The lead frame portion 1540 and the lead frame portion 1542 can be any portion of the leads discussed with reference to the previous figures. The passive device 1510 can be coupled to the lead frame opposite the substrate 1502. For example, one passive device 1510 can be coupled to the lead frame portion 1540 (at a position opposite the substrate 1502), and another passive device 1510 can be coupled to the lead frame portion 1542 (at a position opposite the substrate 1502).

[0128] Figure 16 A semiconductor package 1600 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1600 includes a substrate 1602 having a first surface 1605 and a second surface 1607. The semiconductor package 1600 includes metal traces 1614 (e.g., a top redistribution layer) coupled to the first surface 1605. In some examples, the metal traces 1614 are plated with solder. The semiconductor package 1600 includes a molding 1612 that is configured to encapsulate all components of the semiconductor package 1600 except for a portion of the substrate 1602 (e.g., the top surface of the substrate 1602). Figure 16 , a recess is formed in molding 1612 to expose metal trace 1614. In some examples, a portion of metal trace 1614 is exposed through molding 1612, and a portion of metal trace 1614 is covered by molding 1612. In some examples, metal trace 1614 is disposed below a top surface of molding 1612.

[0129] Semiconductor package 1600 includes a first semiconductor die 1604 (e.g., a low-side semiconductor power die) and a second semiconductor die 1606 (e.g., a high-side semiconductor power die). Furthermore, semiconductor package 1600 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the preceding figures. Furthermore, semiconductor package 1600 includes passive components 1610. First semiconductor die 1604 and second semiconductor die 1606 may be coupled to substrate 1602 via one or more redistribution layers.

[0130] See also Figure 16 1602 , a lead frame portion 1640, a first semiconductor die 1604, a second semiconductor die 1606, and a lead frame portion 1642 can be coupled to the second surface 1607 of the substrate 1602. The lead frame portion 1640 and the lead frame portion 1642 can be any portion of the leads discussed with reference to the previous figures. The passive device 1610 can be coupled to the lead frame opposite the substrate 1602. For example, one passive device 1610 can be coupled to the lead frame portion 1640 (at a position opposite the substrate 1602), and another passive device 1610 can be coupled to the lead frame portion 1642 (at a position opposite the substrate 1602).

[0131] Figure 17 A semiconductor package 1700 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1700 includes a substrate 1702 having a first surface 1705 and a second surface 1707. The semiconductor package 1700 includes a molding 1712 configured to encapsulate all components of the semiconductor package 1700 except for a portion of the substrate 1702 (e.g., the top surface of the substrate 1702). Figure 17 , a recess is formed in molding 1712 to expose first surface 1705. In some examples, a portion of first surface 1705 is exposed through molding 1712, and a portion of first surface 1705 is covered by molding 1712. In some examples, first surface 1705 is disposed below a top surface of molding 1712.

[0132] The semiconductor package 1700 includes a first semiconductor die 1704 (e.g., a low-side semiconductor power die) and a second semiconductor die 1706 (e.g., a high-side semiconductor power die). In addition, the semiconductor package 1700 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the aforementioned figures. In addition, the semiconductor package 1700 includes a passive device 1710. The passive device 1710 may be coupled to a lead frame on the same side as the substrate 1702. The first semiconductor die 1704 and the second semiconductor die 1706 may be coupled to the substrate 1702 via one or more redistribution layers. In some examples, the first surface 1705 of the substrate 1702 is free of redistribution layers (e.g., bare ceramic is exposed).

[0133] See also Figure 17 , a lead frame portion 1740, a first semiconductor die 1704, a second semiconductor die 1706, and a lead frame portion 1742 can be coupled to the second surface 1707 of the substrate 1702. The lead frame portion 1740 and the lead frame portion 1742 can be any portion of the leads discussed with reference to the previous figures. The passive devices 1710 can be coupled to the lead frame on the same side as the substrate 1702. For example, one passive device 1710 can be coupled to the lead frame portion 1740 (at a location on the same side as the substrate 1702), and another passive device 1710 can be coupled to the lead frame portion 1742 (at a location on the same side as the substrate 1702).

[0134] Figure 18 A semiconductor package 1800 having an exposed substrate configured as a heat sink is shown according to one aspect. The semiconductor package 1800 includes a substrate 1802 having a first surface 1805 and a second surface 1807. The semiconductor package 1800 includes metal traces 1814 (e.g., a top redistribution layer) coupled to the first surface 1805. In some examples, the metal traces 1814 are plated with solder. The semiconductor package 1800 includes a molding 1812 configured to encapsulate all components of the semiconductor package 1800 except for a portion of the substrate 1802 (e.g., the top surface of the substrate 1802). Figure 18 In some examples, a recess is formed in molding 1812 to expose metal trace 1814. In some examples, a portion of metal trace 1814 is exposed through molding 1812, and a portion of metal trace 1814 is covered by molding 1812. In some examples, metal trace 1814 is disposed below a top surface of molding 1812.

[0135] Semiconductor package 1800 includes a first semiconductor die 1804 (e.g., a low-side semiconductor power die) and a second semiconductor die 1806 (e.g., a high-side semiconductor power die). Furthermore, semiconductor package 1800 may include a third semiconductor die (e.g., a driver IC die) as discussed with reference to the preceding figures. Furthermore, semiconductor package 1800 includes passive components 1810. First semiconductor die 1804 and second semiconductor die 1806 may be coupled to substrate 1802 via one or more redistribution layers.

[0136] See also Figure 18 , leadframe portion 1840, first semiconductor die 1804, second semiconductor die 1806, and leadframe portion 1842 can be coupled to second surface 1807 of substrate 1802. Leadframe portion 1840 and leadframe portion 1842 can be any portion of the leads discussed with reference to the previous figures. Passive devices 1810 can be coupled to the leadframe on the same side as substrate 1802. For example, one passive device 1810 can be coupled to leadframe portion 1840 (at the same side as substrate 1802), and another passive device 1810 can be coupled to leadframe portion 1842 (at the same side as substrate 1802).

[0137] It should be understood that in the foregoing description, when an element is referred to as being connected to another element, being electrically connected to another element, being coupled to another element or being electrically coupled to another element, the element may be directly connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly connected to another element or being directly coupled to another element, there is no intermediate element. Although the term "directly connected to" or "directly coupled to" may not be used throughout the detailed description, the element shown as being directly connected or directly coupled may be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings. The embodiments of the various technologies described herein may be implemented (for example, included therein) in digital electronic circuits, computer hardware, firmware, software or a combination thereof. The part of the method may also be performed by a dedicated logic circuit such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit), and the device may be implemented as the dedicated logic circuit.

[0138] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0139] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A semiconductor package, characterized in that: The semiconductor package comprises: a substrate having a first surface and a second surface opposite the first surface, the substrate including a central portion; a semiconductor die coupled to the central portion and the second surface of the substrate; a molding encapsulating the semiconductor die and a majority of the substrate, the molding covering a first portion of the first surface, a second portion of the first surface on the central portion being exposed through the molding, such that the substrate is configured to act as a heat sink; and A metal trace is coupled to the central portion and the first surface of the substrate, at least a portion of the metal trace being exposed through the molding.

2. The semiconductor package according to claim 1, wherein The substrate includes a through-hole extending between the first surface and the second surface.

3. The semiconductor package according to claim 1, wherein The semiconductor die is a first semiconductor die, the semiconductor package further comprising: a second semiconductor die coupled to the second surface of the substrate; and A third semiconductor die is coupled to the second surface of the substrate.

4. The semiconductor package according to claim 1, wherein The semiconductor package further comprises: a first metal trace coupled to the second surface of the substrate; and A second metal trace is coupled to the first metal trace, and the semiconductor die is coupled to the second metal trace.

5. The semiconductor package according to claim 1, wherein The semiconductor package further comprises: a lead frame portion coupled to the substrate; and A passive component is coupled to the lead frame portion.

6. A semiconductor package, characterized in that: The semiconductor package comprises: a substrate having a first surface and a second surface opposite the first surface, the substrate comprising a dielectric material, the substrate including a central portion; a lead frame portion coupled to the substrate; a first metal trace coupled to the central portion and the first surface of the substrate; at least one second metal trace coupled to the second surface of the substrate; a semiconductor die coupled to the central portion and the at least one second metal trace; and a molding encapsulating the semiconductor die and a majority of the substrate, the molding covering a first portion of the first surface, a second portion of the first surface on the central portion and at least a portion of the first metal trace being exposed through the molding, such that the substrate is configured to act as a heat sink.

7. The semiconductor package according to claim 6, wherein The substrate includes a via connecting the leadframe portion to the first metal trace, wherein the at least one second metal trace includes two stacked metal traces, the semiconductor package further comprising: A capacitor is coupled to the lead frame portion or the substrate.

8. The semiconductor package of claim 6, wherein the semiconductor die is a first semiconductor die, the semiconductor package further comprising: a second semiconductor die coupled to the at least one second metal trace; and a third semiconductor die coupled to the at least one second metal trace, The first semiconductor die is a low-side semiconductor die, the second semiconductor die is a high-side semiconductor die, and the third semiconductor die is a driver integrated circuit die.

9. A semiconductor package, characterized in that: The semiconductor package comprises: a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole extending between the first surface and the second surface, the substrate including a central portion; a lead frame portion coupled to the second surface of the substrate; a metal trace coupled to the central portion and the first surface of the substrate, the via connecting the metal trace to the leadframe portion; a high-side semiconductor die coupled to the central portion and the second surface of the substrate; a low-side semiconductor die coupled to the central portion and the second surface of the substrate; and a molding encapsulating the high-side semiconductor die, the low-side semiconductor die, and a majority of the substrate, the molding covering a first portion of the first surface, a second portion of the first surface on the center portion and at least a portion of the metal trace being exposed through the molding, such that the substrate is configured to act as a heat sink.

10. The semiconductor package according to claim 9, wherein The semiconductor package further comprises: a first passive component coupled to the substrate; a second passive component coupled to the substrate; and a driver integrated circuit die coupled to the second surface of the substrate, The high-side semiconductor die and the low-side semiconductor die are coupled to the second surface of the substrate via a second metal trace and a third metal trace, and the driver integrated circuit die is coupled to the second surface of the substrate via the second metal trace but not via the third metal trace.

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