Method for forming a fin field effect transistor

Abstract

The present invention describes a method and apparatus for passivating a fin field effect transistor (FinFET) semiconductor device and performing gate etching using an integrated atomic layer deposition (ALD) and etching process. The method includes performing a partial gate etch, depositing a passivation layer on the exposed surface of the semiconductor fin and the gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etching, deposition, and etching process are all performed in the same plasma chamber. The passivation layer is deposited on the sidewalls of the gate layer to maintain the gate profile of the one or more gate structures during etching.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Patent Application No. 15 / 820,263, filed on November 21, 2017, and entitled “ATOMIC LAYER DEPOSITION AND ETCH IN A SINGLE PLASMACHAMBER FOR FIN FIELD EFFECT TRANSISTOR FORMATION,” which is hereby incorporated by reference in its entirety and for all purposes. Technical Field

[0003] The present disclosure relates generally to integrated deposition and etch processes in semiconductor device fabrication, and more particularly to integrated atomic layer deposition (ALD) and etch processes during the formation of fin field effect transistors (FinFETs). Background Art

[0004] As the size of devices and features in the semiconductor industry continues to shrink, challenges have arisen in three-dimensional designs such as FinFETs. FinFETs are manufactured using thin vertical "fins" or fin structures extending from a substrate. A channel is formed in the vertical fin structure and a gate is provided above the vertical fin structure. FinFETs can reduce short channel effects and result in higher currents. Summary of the invention

[0005] The present disclosure relates to a method for performing in-situ ALD and etching during the formation of a FinFET semiconductor device. The method includes: in a plasma chamber, etching a gate layer of a FinFET semiconductor device to one or more top surfaces of one or more corresponding semiconductor fins of the FinFET semiconductor device. The method also includes: in the plasma chamber, depositing a first passivation layer on the exposed surfaces of the gate layer and the one or more semiconductor fins by atomic layer deposition (ALD). The method also includes: in the plasma chamber, etching the gate layer to the top surface of the insulating material layer of the FinFET semiconductor device to define one or more gate structures in the FinFET semiconductor device, wherein the one or more semiconductor fins extend perpendicular to the one or more gate structures.

[0006] In some embodiments, the gate layer comprises polysilicon. In some embodiments, etching the gate layer to the top surface of the insulating material layer comprises: etching a first portion of the gate layer to a first depth in the plasma chamber; depositing a second passivation layer on the exposed surface of the gate layer and the one or more semiconductor fins by ALD in the plasma chamber; and etching a second portion of the gate layer to the top surface of the insulating material layer in the plasma chamber. In some embodiments, the method further comprises: defining the one or more semiconductor fins from a semiconductor substrate before etching the gate layer to the one or more top surfaces of the one or more corresponding semiconductor fins; and depositing the gate layer above or around an upper portion of the one or more corresponding semiconductor fins before etching the gate layer to the one or more top surfaces of the one or more corresponding semiconductor fins. In some embodiments, the method further comprises: forming a gate mask above the gate layer before etching the gate layer to the one or more top surfaces of the one or more corresponding semiconductor fins, the gate mask defining an area for forming the one or more gate structures. The first passivation layer is conformally deposited on the sidewalls of the gate layer below the gate mask. In some embodiments, the thickness of the first passivation layer is between about 0.5nm and about 3nm, and the width of each of the gate structures is between about 5nm and about 50nm. In some embodiments, in etching the gate layer to the one or more top surfaces of the one or more corresponding semiconductor fins and etching the gate layer to each of the top surfaces of the insulating material layer, the etchant is substantially free of oxygen-containing gas. The etchant may include a bromine-containing reagent, a chlorine-containing reagent, or a combination thereof. In some embodiments, etching the gate layer to the one or more top surfaces of the one or more corresponding semiconductor fins and etching the gate layer to the top surface of the insulating material layer occurs to minimize lateral critical dimension (CD) loss. In some embodiments, etching the gate layer to the top surface of the insulating material layer is to remove the gate layer from each corner, and the corner is at the intersection of the one or more gate structures, the one or more semiconductor fins, and the insulating material layer. In some embodiments, the first passivation layer comprises silicon oxide (SiO x). In some embodiments, the step of depositing the first passivation layer by ALD includes: introducing a precursor into the plasma chamber to adsorb on the gate layer and the one or more top surfaces of the one or more corresponding semiconductor fins; transforming the precursor using plasma to form an adsorption-limited amount of the first passivation layer; and repeating the operations of introducing the precursor and transforming the precursor until the first passivation layer of a desired thickness is deposited on the gate layer and the exposed surfaces of the one or more semiconductor fins.

[0007] These and other aspects are further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an exemplary processing apparatus for performing etching and ALD operations according to some implementations.

[0009] Figure 2 is a perspective view showing a three-dimensional schematic diagram of an exemplary FinFET semiconductor device.

[0010] Figure 3A A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, illustrating a schematic diagram of an example of a partially fabricated FinFET semiconductor device before conventional gate etching.

[0011] Figure 3B The gate cross-section, fin cross-section, and top view are shown to illustrate Figure 3A Schematic diagram of an example of a partially fabricated FinFET semiconductor device after conventional gate etching and byproduct redeposition.

[0012] Figure 4A An example process flow for substrate transfer using conventional etching and ALD processing is shown.

[0013] Figure 4B An example process flow for substrate transfer using integrated etch and ALD processing is shown.

[0014] Figure 5 is a flow chart illustrating an exemplary method for passivating and forming a FinFET semiconductor device using etching and ALD processing according to some embodiments.

[0015] Fig. 6A A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, illustrating a schematic diagram of an example of a partially fabricated FinFET semiconductor device prior to gate etching according to some embodiments.

[0016] Figure 6B The gate cross-section, fin cross-section, and top view are shown, which illustrate Fig. 6ASchematic diagram of an example of a partially fabricated FinFET semiconductor device after a first gate etch according to some embodiments.

[0017] Figure 6C The gate cross-section, fin cross-section, and top view are shown, which illustrate Figure 6B Schematic diagram of an example of a partially fabricated FinFET semiconductor device after ALD passivation according to some embodiments.

[0018] Fig.6D The gate cross-section, fin cross-section, and top view are shown, which illustrate Figure 6C Schematic diagram of an example of a partially fabricated FinFET semiconductor device after a second gate etch according to some embodiments. DETAILED DESCRIPTION

[0019] Preface

[0020] In the following description, a large number of specific details are described to provide a thorough understanding of the present invention. The present invention can be practiced without some or all of these specific details. In other examples, conventional processing operations will not be described in detail in order not to make the present invention difficult to understand. Although the present invention is described together with specific embodiments, it should be understood that it is not intended to limit the present invention.

[0021] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing performed thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is performed on a wafer. However, the present disclosure is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various objects, such as printed circuit boards, etc.

[0022] Integrated Etching / ALD Processing Equipment

[0023] As feature sizes shrink, pitches become smaller, and complementary metal oxide semiconductor (CMOS) technology advances to smaller nodes, thin conformal deposition techniques will continue to become important. Atomic layer deposition (ALD) is a film-forming technique well suited for depositing thin conformal films because ALD deposits a single thin layer of material, the thickness of which is limited by the amount of one or more precursor reactants that can adsorb on the substrate surface prior to the film-forming chemistry itself (i.e., forming an adsorption-limited layer). Each layer formed by ALD is thin and conformal, and the formed film is substantially conformal to the shape of the underlying device structures and features.

[0024] Conventionally, ALD and etch processes are performed on separate tools or platforms. For example, an ALD chamber does not perform an etch process, and an etch chamber does not perform an ALD process. Plasma etch chambers that perform deposition processes utilize plasma-induced deposition processes to form films that are non-conformal and aspect ratio dependent.

[0025] According to some embodiments, Figure 1 1 is a schematic diagram of an exemplary processing apparatus for performing etching and ALD operations. The processing apparatus 100 may be an inductively coupled plasma processing apparatus. The processing apparatus 100 includes a plasma chamber 132 such as a plasma etching chamber. In some embodiments, the Kiyo TM The reactor is an example of a suitable reactor that can be used as a plasma etch chamber.

[0026] Details regarding the processing equipment 100 for performing etching and ALD operations are described in the following U.S. patent application: U.S. patent application No. 15 / 669,871, entitled “INTEGRATED ATOMIC LAYER PASSIVATION INTCP ETCH CHAMBER AND IN-SITU ETCH-ALP METHOD,” filed by Zhou et al. on August 4, 2017, which is incorporated herein by reference in its entirety and for all purposes.

[0027] The plasma chamber 132 may include an overall chamber structure that may be defined by chamber walls 114 and a window 106. The window 106 may be made of quartz or other dielectric materials. In some embodiments, the plasma chamber 132 includes a substrate support 116 disposed within the interior of the plasma chamber 132. In some embodiments, the substrate support 116 is an electrostatic chuck for supporting a substrate 112 on which a deposition / etching process is performed. The electrostatic chuck may include electrostatic electrodes for clamping and unclamping the substrate 112. A filter and a DC clamping power supply (not shown) may be provided for this purpose. Other control systems for lifting the substrate 112 off the substrate support 116 may also be provided. The substrate support 116 is configured to receive and hold the substrate 112.

[0028] In some implementations, the substrate support 116 may include a heater (not shown) to heat the substrate 112. The substrate support 116 may be operated at an elevated temperature, such as between about 20° C. and about 150° C. The temperature will depend on the processing operation and the particular recipe. In some implementations, the plasma chamber 132 may also be operated at a particular pressure, such as between about 1 mTorr and about 1 Torr.

[0029] In some embodiments, the processing apparatus 100 may include a radio frequency (RF) power supply 120, which may be used to provide bias / power to the substrate support 116. The RF power supply 120 may be defined by one or more RF generators. If multiple RF generators are provided, different frequencies may be used to achieve various tuning characteristics. A bias matching circuit 118 is coupled between the RF power supply 120 and the substrate support 116. In this manner, the RF power supply 120 is connected to the substrate support 116.

[0030] The coil 134 is positioned above the window 106. The coil 134 may be made of a conductive material and include at least one complete turn. Figure 1 The coil 134 shown in FIG. 1 includes at least three turns. The RF power supply 121 is configured to supply RF power to the coil 134. The matching circuit 102 is coupled between the RF power supply 121 and the coil 134. In this manner, the RF power supply 121 is connected to the coil 134. In some embodiments, an optional Faraday shield (not shown) is positioned between the coil 134 and the window 106. The Faraday shield can be maintained in a spaced relationship relative to the coil 134. The Faraday shield can be disposed directly above the window 106. The Faraday shield can prevent metal or other substances from being deposited on the window 106 of the plasma chamber 132.

[0031] RF power is supplied from the RF power supply 121 to the coil 134 so that an RF current flows through the coil 134. The RF current flowing through the coil 134 may generate an electromagnetic field around the coil 134. The electromagnetic field generates an induced current within the plasma chamber 132, and the induced current acts on the gas present in the plasma chamber 132 to generate plasma. Various ions and / or radicals from the plasma may interact with the substrate 112 to perform a deposition or etching operation.

[0032] In some embodiments, the processing apparatus 100 optionally includes a plasma grid (not shown) that can be used to divide the plasma chamber 132 into an upper portion and a lower portion. The plasma grid can be used to limit the amount of hot electrons that enter the lower portion of the plasma chamber 132. In some embodiments, the processing apparatus 100 is designed to operate such that the plasma present in the lower portion of the plasma chamber 132 is an ion-ion plasma, and the plasma present in the upper portion of the plasma chamber 132 is an electron-ion plasma.

[0033] The process gas may be introduced into the plasma chamber 132 from the top of the plasma chamber 132 through the first gas injector 104 and / or from the side of the plasma chamber 132 through the second gas injector 110. The process gas may include a vaporized liquid precursor or a vaporized solid precursor, which may be vaporized in a solid source vaporizer (not shown) upstream of the processing apparatus 100. One or more reactant gases may be supplied through the first gas injector 104 and / or the second gas injector 110. In some embodiments, a showerhead may be substituted for the gas injectors 104, 110. It should be understood that additional or other gas supply sources may be provided to supply different gases to the plasma chamber 132 for various types of operations.

[0034] Various ways of injecting gases into the plasma chamber 132 show that the process gases, vaporized liquid precursors, and / or vaporized solid precursors can be provided into the plasma chamber 132 from various locations. In some embodiments, only the first gas injector 104 is used. In some other embodiments, only the second gas injector 110 is used. In some other embodiments, both the first gas injector 104 and the second gas injector 110 are used. In some embodiments, the manifold 122 controls which gases are supplied to each of the different gas lines. The manifold 122 enables any type of gas (reactant, carrier, precursor, etc.) to be provided from any of the different gas lines. In some embodiments, the carrier gas may include, for example, oxygen (O 2 ), nitrogen (N 2 ), and helium (He). These gases may be introduced into the plasma chamber 132 unmixed, or may be mixed with other gases before being introduced into the plasma chamber 132.

[0035] Manifold 122 may be used to select, switch, and / or mix the outputs from respective ones of delivery systems 128. In some embodiments, delivery system 128 may include an etching gas delivery system 127 and a liquid delivery system 129. Etching gas delivery system 127 may be configured to output an etchant gas. Examples of etchant gases include, but are not limited to, chlorine (Cl 2 ), hydrogen bromide (HBr), and sulfur hexafluoride (SF 6 ). The liquid delivery system 129 may be configured to provide a liquid precursor that is vaporized and delivered in vapor form during the ALD process. The vaporized liquid precursor may be introduced into the plasma chamber 132 and may be adsorbed on the surface of the substrate 112. The adsorbed precursor may be converted using the plasma to form an adsorption-limited amount of film. An example liquid precursor may have a chemical composition of the following formula: C x H y N z O a Si b .

[0036] The vacuum pump 130 is connected to the plasma chamber 132 and can be used to draw process gases from the plasma chamber 132 and maintain a specific pressure within the plasma chamber 132. A valve 126 can be disposed between the exhaust 124 and the vacuum pump 130 to control the amount of vacuum draw applied to the plasma chamber 132. In some embodiments, the vacuum pump 130 can be a single or two-stage mechanical dry pump and / or a turbomolecular pump. In some embodiments, the vacuum pump 130 can be activated to purge the plasma chamber 132 after each ALD process is completed.

[0037] When the processing apparatus 100 is installed in a clean room or manufacturing facility, it can be coupled to the facility (not shown). The facility contains piping that provides process gases, vacuum, temperature control, and environmental particle control. When these facilities are installed in the target manufacturing facility, they can be coupled to the processing apparatus 100. In addition, the processing apparatus 100 can be coupled to a transfer chamber that allows a robot to transfer substrates in and out of the plasma chamber 132 using an automation system.

[0038] In some embodiments, a system controller 108 (which may include one or more physical or logical controllers) controls some or all operations of the processing device 100. The system controller 108 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor control board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with the system controller 108, or these instructions may be provided over a network. In certain embodiments, the system controller 108 executes system control software.

[0039] The system control software may include instructions for controlling the timing of the application and / or magnitude of any one or more of the following chamber operating conditions: the mixture and / or composition of gases, chamber pressure, chamber temperature, wafer / wafer support temperature, bias applied to the substrate (which may be zero in many embodiments), frequency and power applied to coils or other plasma generating components, substrate position, substrate movement speed, and other parameters of the particular process performed by the tool. The system control software may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operation of the process tool components necessary to perform the processes of the various process tools. The system control software may be encoded in any suitable computer readable programming language.

[0040] In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller 108. For example, instructions for setting the processing conditions for a stage may be included in a corresponding recipe stage. In some embodiments, the recipe stages may be configured sequentially so that the steps in the doping process are performed in a specific order for that process stage. For example, a recipe may be configured to perform etching operations and include one or more cycles of an ALD process performed between each of the etching operations.

[0041] In some embodiments, the system controller 108 is configured with instructions for performing one or more of the following operations: etching a first layer of the substrate 112 in the plasma chamber 132 to form a feature mask pattern, the feature mask pattern having a width less than a desired width of a plurality of structures to be formed by the feature mask pattern; depositing a first passivation layer on the feature mask pattern by ALD in the plasma chamber 132, the first passivation layer being deposited to have a thickness that increases the width of the feature mask pattern to the desired width; and etching a second layer of the substrate 112 in the plasma chamber 132 to form the plurality of structures having the desired width. The etching and deposition operations are performed in the plasma chamber 132 without causing a vacuum break. In some embodiments, the system controller 108 is further configured to perform the following operations: repeating the deposition and etching operations by ALD in the plasma chamber 132.

[0042] In some implementations, other computer software and / or programs may be employed. Examples of programs or portions of programs for this purpose include substrate positioning programs, process gas composition control programs, pressure control programs, heater control programs, and RF power control programs.

[0043] In some cases, the system controller 108 controls gas concentrations, substrate movement, and / or power supplied to the coils 134 and / or substrate support 116. The system controller 108 may control gas concentrations by, for example, opening and closing associated valves to produce one or more inlet gas streams that provide the appropriate concentrations of necessary reactants. Substrate movement may be controlled by, for example, instructing a substrate positioning system to move as required. Power supplied to the coils 134 and / or substrate support 116 may be controlled to provide a specific RF power level. If a grid is used, the RF power may be adjusted by the system controller 108 to produce an electron-ion plasma in the upper portion of the plasma chamber 132 and an ion-ion plasma in the lower portion of the plasma chamber 132. In addition, the system controller 108 may be configured to supply power to the substrate support 116 in the event that an electron-ion plasma is not formed in the lower portion of the plasma chamber 132.

[0044] The system controller 108 may control these or other aspects based on sensor outputs (e.g., when power, potential, pressure, etc. reaches a certain threshold), operational timing (e.g., opening valves at certain times in the process), or based on instructions received from a user.

[0045] In some implementations, the system controller 108 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 108 can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, substrate transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0046] In general, the system controller 108 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions sent to the system controller 108 in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to accomplish one or more process steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0047] In some implementations, the system controller 108 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 108 may be in the "cloud" or may be all or part of a wafer fab host system that may allow remote access to substrate processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set a process step to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the system controller 108 receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 108 is configured to interface with or control. Thus, as described above, the system controller 108 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed system controller 108 for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0048] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with the manufacture and / or preparation of semiconductor wafers or used for the manufacture and / or preparation of semiconductor substrates.

[0049] As described above, depending on one or more processing steps to be performed by the tool, the system controller 108 can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another system controller 108, or tools used in material transport of containers of substrates to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0050] FinFET semiconductor device

[0051] As device features in semiconductor devices shrink and pitches become smaller, the semiconductor industry is transitioning from planar complementary metal oxide semiconductor (CMOS) transistors to three-dimensional (3D) FinFET device architectures. FinFETs provide improved channel control and reduce short channel effects. Unlike traditional planar transistors where the gate is located above the channel, FinFETs have gates around the channel to provide electrostatic control on both sides. 3D device architectures introduce parasitic capacitance and critical dimensions that are challenging to control with shrinking device features and smaller pitches. This results in reduced gate length and pitch, which challenges current patterning methods.

[0052] Figure 2 2 is a perspective view showing a three-dimensional schematic diagram of an example of a FinFET semiconductor device. The FinFET semiconductor device 200 includes a substrate 202, wherein the substrate 202 may be a semiconductor substrate. In some embodiments, the substrate 202 includes a semiconductor material such as silicon, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide. In some embodiments, the substrate 202 may include a bulk silicon material or a silicon-on-insulator (SOI) structure.

[0053] The FinFET semiconductor device 200 also includes one or more semiconductor fins 204 (e.g., silicon fins) extending from the substrate 202. The one or more semiconductor fins 204 may include any suitable semiconductor material. In some embodiments, the one or more semiconductor fins 204 may be formed from the substrate 202 using an appropriate patterning process (e.g., a photolithography and etching process). In some embodiments, the one or more semiconductor fins 204 may be doped by an implantation process to introduce p-type or n-type impurities into the one or more semiconductor fins 204.

[0054] The FinFET semiconductor device 200 further includes an insulating material layer 230 on the substrate 202, which surrounds at least the lower portion of the one or more semiconductor fins 204. The upper portion of the one or more semiconductor fins 204 may protrude from the insulating material layer 230. The insulating material layer 230 may be planarized so that the upper portion of the one or more semiconductor fins 204 extends above the top surface of the insulating material layer 230. The insulating material layer 230 may include any suitable insulating material, such as silicon oxide (SiO x ) or silicon nitride (Si x N y In some embodiments, the insulating material layer 230 is an isolation structure, such as a shallow trench isolation (STI) structure. The isolation structure is used to limit electrical interference or crosstalk interference.

[0055] The FinFET semiconductor device 200 also includes a gate structure 210 over a portion of one or more semiconductor fins 204. In some embodiments, the gate structure 210 may include a gate dielectric layer (not shown), one or more gate spacers (not shown), and a gate electrode 215. The gate electrode 215 may include a conductive material, such as polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), a metal nitride, a metal silicide, a metal oxide, or a metal. In some embodiments, the gate electrode 215 includes polycrystalline silicon. In some embodiments, the gate structure 210 is formed over a central portion of each of the one or more semiconductor fins 204. In some embodiments, multiple gate structures 210 are formed over multiple semiconductor fins 204. It should be understood that although Figure 2 Only two semiconductor fins 204 and one gate structure 210 are shown, but various embodiments may include more or fewer semiconductor fins 204 and / or more gate structures 210 .

[0056] One or more semiconductor fins 204 may extend through opposite sides of the gate structure 210. One or more semiconductor fins 204 may be perpendicular to the gate structure 210. The gate structure 210 may intersect sidewalls of the one or more semiconductor fins 204. In some embodiments, one or more semiconductor fins 204 may be substantially parallel to each other.

[0057] Surface 204a is a top surface of one or more semiconductor fins 204. Surface 204a of one or more semiconductor fins 204 extending from one side of gate structure 210 corresponds to a source region, and surface 204b of one or more semiconductor fins 204 extending from the other side of gate structure 210 corresponds to a drain region. Gate structure 210 may be disposed over a channel region (not shown) of FinFET semiconductor device 200, wherein the channel region is located between source and drain regions.

[0058] In some embodiments, the FinFET semiconductor device 200 optionally includes a liner 212 that can separate the semiconductor material of the substrate 202 from the insulating material layer 230. In some embodiments, the FinFET semiconductor device 200 optionally includes one or more gate dielectric layers (not shown) formed over the insulating material layer 230 to separate the insulating material layer 230 from the gate structure 210. In some embodiments, the semiconductor device 200 optionally includes a gate mask 250 over the gate structure 210. The gate mask 250 can include any suitable soft mask or hard mask material for protecting the gate structure 210 during various patterning processes. In some embodiments, the gate mask 250 includes a hard mask material, such as silicon oxide, silicon nitride, silicon oxynitride, or other applicable materials. After the etching process, the gate mask 250 can remain intact to form the gate structure 210 and expose the one or more semiconductor fins 204.

[0059] An etching operation may be applied to form the profile of the final gate structure 210. In some embodiments, the plasma etching process etches through the gate material to form the final gate structure 210. This process may be referred to as a "gate etch". In many embodiments, the gate etching process may involve etching polysilicon with a covering gate mask 250, wherein the remaining polysilicon is the shape / position of the final gate structure 210. As the gate etch proceeds through the gate material, the gate etch encounters one or more semiconductor fins 204 that are perpendicular to the gate structure 210. The gate etch is selective for etching the gate material without etching the one or more semiconductor fins 204. The gate etch may etch through the remaining gate material to the top surface of the insulating material layer 230. However, when etching through the gate material from the top surface of the one or more semiconductor fins 204 to the top surface of the insulating material layer 230, it may be desirable to maintain a vertical etch profile. Otherwise, the gate structure 210 may have a reentrant profile with a risk of collapse, or a tapered profile with a loss of performance. The tapered profile may result in residual material at a three-dimensional (3D) corner 260 where the top surface of the gate structure 210, at least one of the semiconductor fins 204, and the insulating material layer 230 intersect. Figure 3A-3B How the remaining material is formed at the 3D corner 260 is discussed in more detail in . With shrinking technology nodes and smaller pitches, it may be challenging to maintain a vertical etch profile in gate etching to avoid a reentrant profile or a tapered profile while maintaining critical dimensions of the FinFET semiconductor device 200. The challenge may be more pronounced at the 3D corner 260 of the FinFET semiconductor device 200.

[0060] 3D Corner Residue

[0061] Figure 3A A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, illustrating a schematic diagram of an example of a partially fabricated FinFET semiconductor device prior to conventional gate etching. Figure 3B A schematic diagram of a partially fabricated FinFET semiconductor device example after conventional gate etching and byproduct redeposition is shown, showing a gate cross-sectional view, a fin cross-sectional view, and a top view. As used herein, a gate cross-sectional view is a view parallel to the gate direction. In other words, the gate structure extends into and out of the page in the gate cross-sectional view. As used herein, a fin cross-sectional view is a view parallel to the fin direction. In other words, the semiconductor fin extends into and out of the page in the fin cross-sectional view.

[0062] Prior to performing a gate etch, a partially fabricated FinFET semiconductor device 300 may be formed by defining a set of semiconductor fins 308 from a semiconductor substrate, forming an insulating material layer 306 around lower portions of the semiconductor fins 308, forming a gate layer 304 over and around upper portions of the semiconductor fins 308, and forming a gate mask 302 over portions of the gate layer 304. The gate mask 302 may be used as a mask to pattern the profile of a gate structure 310 to be formed after the gate etch, wherein each of the semiconductor fins 308 may be respectively perpendicular to the gate mask 302. In some embodiments, a thin layer of a passivation material (not shown) may be disposed on the semiconductor fins 308 to protect the semiconductor fins during the gate etch.

[0063] Prior to the gate etch, the gate layer 304 may surround and cover the semiconductor fin 308. The gate etch etches the gate layer 304 to the top surface 306 of the insulating material layer, removing the gate layer 304 without etching the semiconductor fin 308 or etching the outline of the gate layer 304 under the gate mask 302. The gate etch removes the gate layer 304 and forms a gate structure 310 of the FinFET semiconductor device 320, as shown in FIG. Figure 3B As shown. In order to form a gate structure 310 having a substantially vertical profile, the gate etch according to some embodiments will be an anisotropic vertical etch. It is desirable to have a gate etch that substantially maintains a vertical gate profile, which minimizes the load between isolated and dense structures and minimizes center-to-edge non-uniformity. In addition, the gate etch according to some embodiments will be selective to the gate material on the fin material or any passivation material disposed on the semiconductor fin 308. For example, the etching rate of the gate material (e.g., polysilicon) may be at least 100 times, at least 300 times, at least 500 times, or at least 1000 times greater than the etching rate of the passivation material (e.g., oxide) disposed on the semiconductor fin 308. Therefore, it is also desirable to have a gate etch that is highly selective to the gate material relative to other exposed materials.

[0064] In some embodiments, the conventional gate etch process may be a plasma etch process using an etchant such as a bromine-containing agent, a chlorine-containing agent, a fluorine-containing agent, or a combination thereof. For example, the etchant may include chlorine (Cl 2 ), hydrogen bromide (HBr), carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), trifluoromethane (CHF 3 ) or a combination thereof. During a conventional gate etching process of the polysilicon of the gate layer 304, the etchant may react with the polysilicon to form volatile byproducts and non-volatile byproducts. For example, volatile byproducts that may be generated during a conventional gate etching process may include silicon tetrachloride (SiCl 4 ), silicon tetrabromide (SiBr 4 ) or a combination thereof. Non-volatile byproducts that may be formed during conventional gate etching processes may include silicon trichloride (SiCl 3 ), silicon dichloride (SiCl 2 ), silicon tribromide (SiBr 3 ), silicon dibromide (SiBr 2 ) or a combination thereof. In some embodiments, the volatile byproducts may react with high energy electrons or other substances and dissociate to form non-volatile byproducts. Such non-volatile byproducts may also be referred to as "global byproducts". Global byproducts are typically observed on the gate mask 302.

[0065] The volatile byproducts of the reaction between the polysilicon and the etchant can be pumped out or otherwise removed from the process chamber. The non-volatile byproducts of the reaction between the polysilicon and the etchant can be adsorbed, adhered, or formed on the sidewalls and surfaces of the gate mask 302, the gate structure 310, and the semiconductor fin 308 during the gate etching process. The non-volatile byproducts can be deposited on the sidewalls and surfaces of the gate mask 302 and the gate structure 310, thereby forming a Figure 3B In addition, non-volatile byproducts may also be deposited on the sidewalls and surfaces of the semiconductor fins 308 to form a first passivation byproduct layer 312. Figure 3B The second passivation byproduct layer 314 is shown. This non-volatile byproduct will form volatile SiCl due to insufficient Cl / Br around the etching front. 4 or SiBr 4 As previously described, a thin passivation layer (not shown) may be disposed on at least the top surface of the semiconductor fin 308 prior to conventional gate etching processes, and a second passivation byproduct layer 314 may be added to the thin passivation layer for more protection.

[0066] During the conventional gate etch process, the non-volatile byproducts can act as a passivation material to protect the gate structure 310 and the semiconductor fin 308. Therefore, the conventional gate etch process provides a plasma-based passivation technique for the redeposition of the etch byproducts, which can be used to maintain the sidewall profile and avoid lateral etching into the gate structure 310 and the semiconductor fin 308. In some embodiments, the conventional gate etch process can include a "flash" passivation process. The "flash" passivation process can refer to the process of stimulating a gas such as oxygen (O 2 ), carbon dioxide (CO 2 ) and / or nitrogen (N 2 ) to form a plasma of dissociated radicals to react with the surface and form a passivation material layer (e.g., oxide or nitride) on the surface. For example, the plasma source may apply RF power to the gas for a short time ranging from about 0.5 seconds to about 5 seconds. Where conventional gate etching processes include oxygen "fast" passivation processes, non-volatile byproducts formed on the sidewalls and surfaces of the gate mask 302, the gate structure 310, and the semiconductor fin 308 may include, for example, silicon oxychloride (SiOCl 3 ) and silicon oxybromide (SiOBr 3 The first passivation byproduct layer 312 and the second passivation byproduct layer 314 may include an oxide formed from a “fast” passivation process, wherein the oxide provides additional protection for the gate structure 310 and the semiconductor fin 308 during a conventional gate etch process.

[0067] Conventional gate etching processes may depend on the aspect ratio of the features being etched, which may cause more non-volatile byproducts to be deposited near the top of the gate structure 310 and the top of the semiconductor fin 308. Higher aspect ratios and smaller critical dimension (CD) spaces may cause more etchants and passivation species from the plasma to react near the top of the gate structure 310 and the top of the semiconductor fin 308. Figure 3B, the first passivation byproduct layer 312 may be formed as a ridge or protrusion at the top of the gate mask 302 and the gate structure 310, and the second passivation byproduct layer 314 may also be formed as a ridge or protrusion at the top of the semiconductor fin 308. The first passivation byproduct layer 312 acts as a shielding mask to preserve the vertical gate profile of the gate structure 310, and the second passivation byproduct layer 314 acts as a shielding mask to protect the semiconductor fin 308. However, each ridge of the first passivation byproduct layer 312 and the second passivation byproduct layer 314 may block the underlying portion of the gate layer 304 from being directional ion-etched by conventional gate etching. Specifically, each ridge of the first passivation byproduct layer 312 and the second passivation byproduct layer 314 may form a "shadow" above an area that the directional ions will not reach. As shown in Figure 3B As shown in the top view of FIG. 3 , the first passivation byproduct layer 312 and the second passivation byproduct layer 314 meet at a corner 316 where the semiconductor fin 308 intersects the gate structure 310. The corner 316 may correspond to Figure 2 3D corner 260 of FinFET semiconductor device 200. Shielding of first passivation byproduct layer 312 and shielding of second passivation byproduct layer 314 make it difficult to remove gate layer 304 at 3D corner 316. This results in residual gate material at 3D corner 316 of FinFET semiconductor device 350, which may lead to performance degradation.

[0068] Attempts to mitigate residual gate material at 3D corner 316 include applying an isotropic etch component in the gate etch process. Although the isotropic etch component can remove at least some residual gate material at 3D corner 316, the isotropic etch component can result in uncontrollable reentrant profile and lateral CD loss.

[0069] Integrated Etch / ALD Passivation

[0070] Embodiments of the present invention relate to FinFET semiconductor devices fabricated with passivation portions and methods for gate etching using in-situ ALD and etching. The in-situ ALD and etching techniques for passivating and etching FinFET semiconductor devices minimize or avoid the redeposition of etching byproducts described above. The passivation techniques disclosed herein enable the formation of a conformal passivation layer on the surface and sidewalls of a gate mask, one or more gate structures, and one or more semiconductor fins. After the gate layer is partially etched to one or more top surfaces of one or more corresponding semiconductor fins, the conformal passivation layer can be deposited by ALD. After depositing the conformal passivation layer, the gate layer is then etched to reach the top surface of the insulating material layer. The gate etching and ALD operations can be performed in a plasma chamber. Therefore, the cycle of the ALD and etching steps is performed in the same chamber or tool. In some embodiments, the cycle of the ALD and etching steps is performed in a plasma chamber. Figure 1The method is performed in the plasma processing device.

[0071] Using different chambers for deposition and etching increases processing time, processing steps and costs, which can have a negative impact on yield. In addition, using different chambers requires transferring the substrate from one chamber to another, which results in a vacuum break and increases the likelihood of unwanted materials or particles coming into contact with the substrate. This can cause a loss of functionality and / or integrity of the material on the substrate. In addition, a cleaning process is typically required between etching and deposition processes, which can affect the material properties and structure on the substrate. For example, a dilute hydrogen fluoride (HF) acid cleaning process has an impact on the mask structure and can have an adverse effect on performance.

[0072] Figure 4A An example process flow for substrate transport using conventional etching and ALD processing is shown. It should be understood that Figure 4A This process flow in is not limited to the gate etching scheme described above, but can be applied to other schemes using conventional etching and ALD processing. Figure 4A In the embodiment of the present invention, a substrate is provided in an etching chamber and an etching step is performed at box 401, the substrate is transferred to a cleaning chamber for a cleaning step at box 403, the substrate is transferred to an ALD chamber for an ALD step at box 405, the substrate is transferred back to the same or different cleaning chamber for a cleaning step at box 407, and the substrate is transferred back to the same or different etching chamber 409 at box 409. In performing an etch-deposition-etch sequence, the substrate may undergo 4 substrate transfers and pass through 3-5 different chambers. In some embodiments, the etching step in box 401 may define etching a portion of the gate layer, the ALD step in box 405 may passivate the structure of the FinFET semiconductor device, and the gate layer may be completely etched in box 409 to define the final gate structure of the FinFET semiconductor device.

[0073] In order to passivate the structure of the FinFET semiconductor device while avoiding the problems associated with performing etching steps and deposition steps in different tools, a plasma etching chamber suitable for performing deposition can be used. Conventional deposition processes used in plasma etching chambers can include chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD) processes. However, such deposition processes typically deposit non-conformal films. More specifically, the deposition process depends on the aspect ratio and deposits more material in more open spaces or wider spacings, thus resulting in uneven deposition across features or structures with different aspect ratios. Specifically, the deposition at isolated features will be more than at dense features, and the CD deviation at isolated features will be larger than that at dense features.

[0074] Embodiments of the present disclosure relate to integrated ALD steps and etching steps in a plasma chamber. By using in-situ ALD rather than performing ALD in a different chamber or using CVD / PECVD in the same chamber, stand-alone ALD tools and additional cleaning tools can be eliminated or reduced. And by eliminating additional substrate transfer and cleaning time, processing time and cost are reduced. In addition, the use of in-situ ALD avoids vacuum breaks between substrate transfers (e.g., between ex-situ deposition and cleaning), which may expose the substrate to unwanted materials, atmosphere, and / or moisture. The use of in-situ ALD also reduces the effects of non-uniform deposition on structures or features with different aspect ratios. In-situ ALD can involve ALD performed in a plasma etch chamber, such as the above-mentioned Figure 1 The plasma chamber in the processing equipment 100 is shown in FIG.

[0075] Figure 4B An example of a process flow using integrated etching and ALD processing for substrate transfer is shown. It should be understood that in Figure 4B Such a process flow is not limited to the above-mentioned gate etching scheme, but can be applied to other schemes using ALD and etching processing. Figure 4B In the embodiment of the present invention, a substrate is provided in an etching chamber and an etching step is performed at box 451, the substrate is maintained in the same etching chamber and an ALD step is performed at box 453, the substrate is maintained in the same etching chamber to perform an etching step at box 455, and the substrate is transferred to a cleaning chamber to perform a cleaning step at box 457. In performing an etch-deposition-etch sequence, the substrate may undergo one substrate transfer through two different chambers. In some embodiments, the etching step in box 451 may etch a portion of the gate layer, the ALD step in box 453 may passivate the structure of the FinFET semiconductor device, and the gate layer may be etched in box 455 to define the final gate structure of the FinFET semiconductor device.

[0076] Figure 5 5 is a flow chart illustrating an exemplary method for passivating and forming a FinFET semiconductor device using etching and ALD processes according to some embodiments. The operations in process 500 may be performed in a different order and / or with different, fewer, or additional operations. Figure 5 Reference Figures 6A-6D To explain.

[0077] Prior to frame 510 of process 500, process 500 may optionally include defining one or more semiconductor fins from a semiconductor substrate of a FinFET semiconductor device. One or more semiconductor fins may be defined as extending above the top surface of an insulating material layer on a semiconductor substrate. An insulating material layer may also be disposed around the lower portion of the one or more semiconductor fins. The upper portion of the one or more semiconductor fins may extend above the top surface of the insulating material layer. In some embodiments, the one or more semiconductor fins and the semiconductor substrate may include semiconductor materials such as silicon, germanium, or a combination thereof. In some embodiments, the insulating material layer may include insulating materials such as silicon oxide or silicon nitride. In some embodiments, the step of defining the one or more semiconductor fins may include etching a semiconductor substrate to form a shape of the fin extending from the semiconductor substrate, depositing the insulating material layer on the semiconductor substrate and around the lower portion of the one or more semiconductor fins, and flattening the insulating material layer so that the upper portion of the one or more semiconductor fins is exposed and extends from the top surface of the insulating material layer.

[0078] In some embodiments, it may be optionally included that after defining the one or more semiconductor fins, a gate layer is deposited above and around the upper portion of the one or more semiconductor fins. The gate layer may be disposed on the top surface of the insulating material layer. The gate layer may surround and cover the upper portion of the one or more semiconductor fins. In some embodiments, the gate layer may include polysilicon or metal.

[0079] In some embodiments, it may be optional to form a gate mask over the gate layer after depositing the gate layer. The gate mask may be deposited and patterned on the gate layer to shield portions of the gate layer, thereby defining the final profile of the gate structure of the FinFET semiconductor device. One or more semiconductor fins may be perpendicular to the gate mask on the gate layer. In some embodiments, the gate mask may include a hard mask material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0080] Fig. 6AA gate cross-sectional view, a fin cross-sectional view, and a top view are shown, illustrating a schematic diagram of an example of a partially fabricated FinFET semiconductor device prior to gate etching, according to some embodiments. Prior to performing the gate etching, the partially fabricated FinFET semiconductor device 600 may be formed by: defining a group of semiconductor fins 608 from a semiconductor substrate, forming an insulating material layer 606 around a lower portion of the semiconductor fins 608, forming a gate layer 604 above and around the semiconductor fins 608, and forming a gate mask 602 above a portion of the gate layer 604. The gate mask 602 may serve as a mask to pattern the outline of a gate structure 610 to be formed after the gate etching, wherein each semiconductor fin 608 is perpendicular to the gate mask 602. Prior to the gate etching, the gate layer 604 may surround and cover the semiconductor fins 608, or at least surround the top surfaces and sidewalls of the longitudinally extending semiconductor fins 608. Fig. 6A In the top view and gate cross-sectional view of FIG. 6 , the semiconductor fin 608 is not visible and is covered by the gate layer 604 .

[0081] Back to Figure 5 In frame 510 of process 500, the gate layer of the FinFET semiconductor device is etched in a plasma chamber to one or more top surfaces of one or more corresponding semiconductor fins. The etching can be stopped when one or more top surfaces of the one or more corresponding semiconductor fins are exposed. In some embodiments, a passivation material layer (e.g., an oxide layer) may be disposed on the one or more semiconductor fins to protect the one or more semiconductor fins during gate etching, so that the etching can stop at the passivation material layer. The etching performs a partial gate etching without etching the remaining gate layer in the space between or directly adjacent to the one or more semiconductor fins. The plasma chamber can be configured to perform subsequent etching and deposition processes. Aspects of the plasma chamber can refer to Figure 1 The processing device 100 is described in detail.

[0082] The etch performed in block 510 may be an anisotropic plasma etch that is selective to the gate material of the gate layer relative to other exposed materials. For example, the etch may be selective to polysilicon relative to hard mask materials and passivation materials that may be encountered during the etch. To perform the etch, the etch may be performed from a substrate including, for example, Cl 2 , HBr, CF 4 , SF 6 , CHF 3 or a combination thereof. Thus, the etching performed at block 510 involves an etchant that may include a bromine-containing reagent, a chlorine-containing reagent, a fluorine-containing reagent, or a combination thereof. In some embodiments, the plasma-generating gas does not include, for example, O 2 and CO 2Typically, oxygen-containing gases in plasma processes, such as plasma-based "fast" passivation processes, help to form non-volatile etch byproduct redeposition. This minimizes or eliminates oxides formed by redeposition of etch byproducts. Therefore, the etch performed at block 510 is substantially free of oxygen-containing gases.

[0083] In some embodiments, the plasma generated by the etching performed in box 510 can be an ion-driven plasma, wherein the ion-driven plasma (e.g., ion-ion plasma) can contain a higher proportion of negatively charged species than the electron-driven plasma (e.g., electron-ion plasma), that is, more ions than electrons. However, it should be understood that the plasma generated in the etching at box 510 is not necessarily an ion-driven plasma. The plasma conditions can be optimized to form an ion-driven plasma. Ion-driven plasma can be applied in anisotropic etching processes with minimal effect on the gate profile or CD. As the etching proceeds to one or more top surfaces of one or more corresponding semiconductor fins, the gate profile is maintained at minimum lateral CD loss. As used throughout the present disclosure with respect to lateral CD loss, "minimum lateral CD loss" means that the lateral CD loss does not exceed 5% of the original CD. For example, the minimum lateral CD loss may refer to a lateral CD loss of no more than 5nm.

[0084] In some embodiments, a plasma grid can be used to partition a plasma chamber to facilitate the generation of an ion-ion plasma. An example of a plasma grid is described in U.S. Pat. No. 9,633,846, filed on November 30, 2015 to Paterson et al., entitled "INTERNAL PLASMA GRID APPLICATION FOR SEMICONDUCTOR FABRICATION," which is incorporated herein by reference in its entirety and for all purposes. Ion-driven plasma can reduce the formation of non-volatile etching byproducts in the plasma chamber, particularly non-volatile etching byproducts associated with global byproducts.

[0085] Figure 6B A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, illustrating the structure of the fin after the first gate etch according to some embodiments. Fig. 6ASchematic diagram of an example of a partially fabricated FinFET semiconductor device. After a first gate etch, in the partially fabricated FinFET semiconductor device 620, at least a portion of the gate layer 604 is removed. The portion of the removed gate layer 604 reaches the top surface of the semiconductor fin 608. After the first gate etch, the gate layer 604 below the gate mask 602 and the gate layer 604 in the space between and directly adjacent to the semiconductor fins 608 remain. The first gate etch is selective to the gate material of the gate layer 604 without significantly etching the gate mask 602 and the semiconductor fin 608, and the first gate etch is anisotropic to maintain a substantially vertical profile for the gate electrode / structure to be formed subsequently. Figure 6B In the top view of FIG. 6 , the top surface of the semiconductor fin 608 is exposed and surrounded by the remaining gate layer 604 .

[0086] Back to Figure 5 In block 520 of process 500, a first passivation layer is deposited by atomic layer deposition (ALD) in a plasma chamber on the exposed surfaces of the gate layer and one or more semiconductor fins. This includes at least the sidewalls of the gate layer and one or more top surfaces of the one or more corresponding semiconductor fins. In some embodiments, the first passivation layer is at least conformally deposited on the gate mask, the gate layer, and the exposed surfaces (including the sidewalls) of the one or more semiconductor fins. The ALD performed in block 520 is performed in the same plasma chamber as the etching performed in block 510 without introducing a vacuum break between operations.

[0087] ALD is a technique for depositing thin layers of material using continuous self-limiting reactions. Typically, an ALD cycle includes the operation of delivering and adsorbing at least one reactant to a substrate surface, and then reacting the adsorbed reactant with one or more reactants to form a portion of a thin film layer. Unlike CVD techniques, ALD processes use surface self-limiting deposition reactions to deposit films layer by layer. A typical ALD cycle may include: (i) a batching step for delivering and adsorbing precursor materials onto a substrate surface, (ii) sweeping excess precursor materials from a chamber and leaving a self-limiting monolayer on the substrate surface, (iii) delivering reactant materials to react with the adsorbed precursor materials, and (iv) sweeping unreacted reactant materials or reaction byproducts from the chamber. The batching step may adsorb the precursor material in a self-limiting manner, such that once the active sites are occupied by the precursor material, little or no additional precursor material will be adsorbed on the substrate surface. The reactant material may also react with the precursor material in a self-limiting or adsorption-limited manner. A sweep step may optionally be performed to remove excess precursor material, reaction byproducts, and / or unreacted reactant material from the chamber, thereby completing the ALD cycle.ALD can be used to provide highly conformal films with high step coverage, even in high aspect ratio features.

[0088] The first passivation layer can be conformally deposited on the exposed surfaces of the gate mask, the gate layer, and one or more semiconductor fins by ALD. The ALD process for conformally depositing the first passivation layer can occur in one or more cycles, wherein each cycle produces an adsorption-limited amount of passivation material on the exposed surfaces of the gate mask, the gate layer, and one or more semiconductor fins. Each cycle may include a dosing step in which a controlled amount of a precursor material is delivered to the substrate surface and adsorbed on the substrate surface in a self-limiting manner. This is also known as "soaking" the substrate surface to saturation. Each cycle may further include a conversion step after the dosing step, in which a reactant material is provided to react with the precursor material on the substrate surface and form an adsorption-limited amount of passivation material. The reactant material may include a reactant gas, wherein an RF power source generates a reactant gas plasma in a plasma chamber. The reactant gas may, for example, include an oxygen-containing gas (e.g., O 2 ) or nitrogen-containing gases (such as N 2 or NH 3 ). The free radicals and other charged species of the reactant gas react with the precursor material to convert the precursor material into an adsorption-limited amount of passivation material. In some embodiments, the reactant gas is exposed to RF power delivery for a relatively short time (e.g., between about 0.5 seconds and about 5 seconds) to form a plasma to convert the precursor material. This is also referred to as a "fast" operation, which uses a plasma of RF power delivered in a relatively short time to convert the precursor material on the substrate surface. In some embodiments, a sweep step can remove excess precursor material, reaction byproducts, and / or unreacted reactant material from the plasma chamber to complete the cycle. In some embodiments, the batching step and the conversion step can be repeated until a passivation layer of the desired thickness is deposited.

[0089] The first passivation layer may include, for example, an oxide (e.g., SiO x or nitrides (such as Si x N y ). The first passivation layer is used to protect the gate layer directly below the gate mask, thereby acting as a sidewall protection layer in the gate electrode / structure to be subsequently formed in the FinFET semiconductor device during a subsequent etching process such as the etching process described in box 530. Unlike the above-mentioned protrusions of passivation material formed during the redeposition of etching byproducts, the first passivation layer conformally follows the gate contour of the subsequently formed gate electrode / structure. In other words, the first passivation layer "freezes" the gate contour of the sidewall in the subsequent etching process. The first passivation layer deposited on one or more top surfaces of one or more corresponding semiconductor fins can also increase the protection of the one or more corresponding semiconductor fins during a subsequent etching process such as the etching process described in box 530.

[0090] The first passivation layer is conformally deposited by ALD and may have a high step coverage, such as a step coverage greater than 85%, greater than 90%, or greater than 95%. The high conformality of the first passivation layer provides a first passivation layer with a relatively uniform thickness on the exposed surface of one or more top surfaces of the gate mask, the gate layer, and one or more corresponding semiconductor fins. The first passivation layer deposited by ALD is used to passivate the exposed surface and is quite thin to limit the impact on CD. In some embodiments, the thickness of the first passivation layer may be between about 0.1nm and about 5nm or between about 0.5nm and about 3nm. In some embodiments, the width of the gate mask or the gate electrode / structure to be formed is greater than the thickness of the first passivation layer. For example, the width of the gate mask is between about 5nm and about 50nm, and the width of the gate / structure to be formed is between about 5nm and about 50nm. Therefore, the CD increment from the deposition of the first passivation layer is minimized.

[0091] Figure 6C A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, which illustrate that according to some embodiments, Figure 6B Schematic diagram of an example of a partially fabricated FinFET semiconductor device after ALD. In the partially fabricated FinFET semiconductor device 640, a passivation layer 612 is deposited on the exposed surfaces (including the sidewalls) of the gate mask 602, the gate layer 604, and the semiconductor fin 608. This includes the sidewalls of the gate layer 604 below the gate mask 602 and the top surface of the semiconductor fin 608. The passivation layer 612 is relatively thin and conformally follows the shape of the gate mask 602, the gate layer 604, and the exposed surfaces of the semiconductor fin 608, following the vertical contour of the gate layer 604 below the gate mask 602. Figure 6C In the top view, the top surface of the semiconductor fin 608 , the gate layer 604 , and the gate mask 602 are all covered by the passivation layer 612 .

[0092] Back to Figure 5 In block 530 of process 500, the gate layer of the FinFET semiconductor device is etched in a plasma chamber to the top surface of the insulating material layer to define one or more gate structures. The one or more semiconductor fins are perpendicular to the one or more gate structures. The etching may finally stop when the top surface of the insulating material layer is exposed. The etching at block 530 is performed in the same plasma chamber as the etching at block 510 and the deposition at block 520, and no vacuum break is caused between the operations.

[0093] The etching is a gate etch that removes the remaining gate layer in the space between one or more semiconductor fins or directly adjacent to these fins. The etching forms a groove, a trench or a feature in the space between one or more semiconductor fins. The etching performed at frame 530 may be an anisotropic plasma etch, thereby minimizing the formation of a concave profile or a tapered profile in one or more semiconductor fins and one or more gate structures. The etching maintains the gate profile of one or more gate structures with minimal lateral CD loss. The etching also maintains the fin profile of one or more semiconductor fins with minimal lateral CD loss. Even in very small (e.g., equal to or less than about 8nm) CD spaces, after the etching of frame 530, only very little or no residual gate material remains. In some embodiments, the etching removes the residual gate material at the 3D corner where the top surface of one or more gate structures, one or more semiconductor fins, and the insulating material layer intersect.

[0094] As with the etch performed at block 510, the etch performed at block 530 is selective to the gate material of the gate layer relative to other exposed materials (e.g., the first passivation layer) and may be free of oxygen-containing gases. To perform this etch, a gas including, for example, Cl 2 , HBr, CF 4 , SF 6 , CHF 3 or a combination thereof. Thus, the etching performed at block 530 involves an etchant that may include a bromine-containing reagent, a chlorine-containing reagent, a fluorine-containing reagent, or a combination thereof. In some embodiments, the plasma-generating gas does not include, for example, O 2 and CO 2 Oxygen-containing gases such as , thereby minimizing or eliminating oxides formed by redeposition of etching byproducts. In some embodiments, the plasma generated by the etching performed at block 530 may be an ion driven plasma.

[0095] Although the etching at box 530 can be performed as a single etching operation, it should be understood that the etching at box 530 can be performed as one or more etching-deposition-etching operations. In other words, the partial gate etching can partially penetrate the first portion of the gate layer to a certain depth, then perform an ALD passivation process, and then restart the gate etching through the second portion of the gate layer. In some embodiments, the etching at box 530 includes partially etching the first portion of the gate layer to a first depth in a plasma chamber, depositing a second passivation layer by ALD at least on the exposed surface (including the sidewalls) of the gate layer and one or more semiconductor fins in the plasma chamber, and then completely or partially etching the second portion of the gate layer to a second depth in the plasma chamber. The etching-deposition-etching sequence can be repeated until the gate layer is removed to a desired depth that reaches the top surface of the insulating material layer. The sequence can be repeated in the same plasma chamber without introducing a vacuum break between operations.

[0096] The second passivation layer deposited by ALD can serve as a sidewall protection layer to protect one or more semiconductor fins during gate etching. Unlike the above-mentioned ridges of passivation material formed during the redeposition of etching byproducts, the second passivation layer conformally follows the fin contour of one or more semiconductor fins. In other words, the second passivation layer "freezes" the fin contour of the sidewall during subsequent etching processes.

[0097] Fig.6D A gate cross-sectional view, a fin cross-sectional view, and a top view are shown, which illustrate that according to some embodiments, Figure 6CSchematic diagram of an example of a partially manufactured FinFET semiconductor device after a second gate etch. After the second gate etch, the FinFET semiconductor device 660 includes the final profile of the gate structure 610. The second gate etch removes the gate layer 604 to the top surface of the insulating material layer 606 to expose the semiconductor fin 608 and form the gate structure 610. The semiconductor fin 608 is perpendicular to the gate structure 610. At the corner 616 where the semiconductor fin 608 intersects the gate structure 610, there is very little or no residual gate material from the gate layer 604. The second gate etch substantially removes the residual gate material from the corner 616. The passivation layer 612 can maintain the gate profile of the gate structure 610 during the second gate etch and have minimal lateral CD loss. The gate profile of the gate structure 610 after the second gate etch can be substantially vertical. In some embodiments, an additional passivation layer 614 can be deposited on the sidewalls of the semiconductor fin 608 to maintain the fin profile of the semiconductor fin 608 during the second gate etch with minimal lateral CD loss. The additional passivation layer 614 can be conformally deposited by ALD between etching operations of the second gate etch and follow the fin profile of the semiconductor fin 608. One or both of the passivation layer 612 and the additional passivation layer 614 provide robust protection for the gate structure 610 and the semiconductor fin 608 during the etching operation without forming a "shadow" over areas that the directed ions may not reach. Figure 6C In the top view of FIG. 6 , the insulating material layer 606 is exposed, and the passivation layers 612 , 614 are formed along the sidewalls of the gate structure 610 and the semiconductor fin 608 .

[0098] in conclusion

[0099] Although the above embodiments have been described in some detail for the purpose of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. An etching method, comprising: In a plasma chamber, etching a gate layer of a FinFET semiconductor device to expose a top surface of one or more semiconductor fins of the FinFET semiconductor device; In the plasma chamber, after etching the gate layer to the exposed top surface of the one or more semiconductor fins, depositing a first passivation layer on the exposed surface of the gate layer and the one or more semiconductor fins by atomic layer deposition; as well as In the plasma chamber, after depositing the first passivation layer by atomic layer deposition, the gate layer is etched to expose a top surface of the insulating material layer of the FinFET semiconductor device to define one or more gate structures in the FinFET semiconductor device and expose sidewalls of the semiconductor fins, wherein the one or more semiconductor fins extend perpendicularly to the one or more gate structures, The etching of the gate layer to expose the top surface of the insulating material layer comprises: In the plasma chamber, etching a first portion of the gate layer to a first depth above the top surface of the insulating material layer; depositing a second passivation layer on the exposed surfaces of the gate layer and the one or more semiconductor fins by atomic layer deposition in the plasma chamber; and In the plasma chamber, a second portion of the gate layer is etched to the top surface of the insulating material layer. The method of claim 1 , wherein the gate layer comprises polysilicon.

3. The method according to claim 1, further comprising: defining the one or more semiconductor fins from a semiconductor substrate before etching the gate layer to expose the top surface of the one or more semiconductor fins; as well as The gate layer is deposited over or around upper portions of the one or more semiconductor fins before etching the gate layer to expose the top surface of the one or more semiconductor fins.

4. The method according to claim 1, further comprising: Before etching the gate layer to expose the top surface of the one or more semiconductor fins, a gate mask is formed over the gate layer, the gate mask defining an area for forming the one or more gate structures. The method of claim 4 , wherein the first passivation layer is conformally deposited on sidewalls of the gate layer below the gate mask. 6 . The method according to claim 1 , wherein the thickness of the first passivation layer is between 0.5 nm and 3 nm, and the width of each of the gate structures is between 5 nm and 50 nm.

7. The method according to any one of claims 1 to 5, wherein in the plasma chamber, the operations of etching the gate layer to expose the top surface of the one or more semiconductor fins, depositing by atomic layer deposition, and etching the gate layer to expose the top surface of the insulating material layer are all performed without introducing vacuum destruction between operations.

8. The method according to any one of claims 1 to 5, wherein in each of etching the gate layer to expose the top surface of the one or more semiconductor fins and etching the gate layer to expose the top surface of the insulating material layer, the etchant is substantially free of oxygen-containing gas.

9. The method of claim 8, wherein the etchant comprises a bromine-containing agent, a chlorine-containing agent, or a combination thereof.

10. The method of any one of claims 1 to 5, wherein after etching the gate layer to expose the top surface of the insulating material layer, a profile of the one or more gate structures is substantially vertical.

11. The method of any one of claims 1 to 5, wherein etching the gate layer to expose the top surface of the one or more semiconductor fins and etching the gate layer to expose the top surface of the insulating material layer occurs to minimize lateral critical dimension (CD) loss.

12. The method according to any one of claims 1 to 5, wherein etching the gate layer to expose the top surface of the insulating material layer is to remove the gate layer from each corner, wherein the corner is where the one or more gate structures, the one or more semiconductor fins, and the insulating material layer intersect. 13 . The method of claim 1 , wherein before etching the gate layer to expose the top surface of the one or more semiconductor fins, the top surface of the one or more semiconductor fins comprises an oxide layer. 14 . The method according to claim 1 , wherein the one or more gate structures are parallel to each other, and the one or more semiconductor fins are parallel to each other, and the one or more semiconductor fins extend through the one or more gate structures.

15. The method according to any one of claims 1 to 5, wherein the first passivation layer comprises silicon oxide (SiO x ).

16. The method according to any one of claims 1 to 5, wherein the step of depositing the first passivation layer by atomic layer deposition comprises: introducing a precursor into the plasma chamber to adsorb on the gate layer and on the top surface of the one or more semiconductor fins; converting the precursor using a plasma to form an adsorption-limited amount of the first passivation layer; as well as The operations of introducing the precursor and converting the precursor are repeated until the first passivation layer having a desired thickness is deposited on the gate layer and the exposed surfaces of the one or more semiconductor fins.

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