Weight unit and memory device

Abstract

The present invention discloses a weight unit and a memory device. The weight unit includes: a first field-effect transistor and a first resistive memory element connected to the drain of the first field-effect transistor; a second field-effect transistor and a second resistive memory element connected to the drain of the second field-effect transistor, the drain of the first field-effect transistor being connected to the gate of the second field-effect transistor, and the drain of the second field-effect transistor being connected to the gate of the first field-effect transistor; a third field-effect transistor and a third resistive memory element connected to the drain of the third field-effect transistor; and a fourth field-effect transistor and a fourth resistive memory element connected to the drain of the fourth field-effect transistor, the drain of the third field-effect transistor being connected to the gate of the fourth field-effect transistor, and the drain of the fourth field-effect transistor being connected to the gate of the third field-effect transistor.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Application No. 62 / 812,600, filed on March 1, 2019, and U.S. Provisional Application No. 62 / 812,819, filed on March 1, 2019, both with the USPTO, and to U.S. Application No. 16 / 448,842, filed on June 21, 2019, with the USPTO, the disclosures of which are hereby incorporated herein by reference in their entireties. Technical Field

[0003] The present disclosure provides a ternary weight cell configuration having logical values {1, 0, -1}, where even if the MTJ has on / off ratios of only 2 to 3, the on / off ratio of the output current will be closer to that of a transistor (10 4 to 10 5 ). Background Art

[0004] There is an increasing demand for hardware accelerators for machine learning (ML) applications. The computation that dominates most of these ML applications is matrix vector multiplication. It is possible to perform matrix vector multiplication very efficiently in analog form through a crossbar network. However, in order to represent weights, a memory element must be introduced in each weight cell. Static random access memory (SRAM) is large and power-inefficient. Non-volatile memory options such as redundant random access memory (RRAM), flash memory (FLASH), or spin-torque transfer magnetic random access memory (STT-MRAM) are typically affected by a set of other challenges including low on / off ratios, high variability, and non-compatible programming voltages. Summary of the Invention

[0005] According to one embodiment, a weight unit is provided. The weight unit includes: a first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET and a third resistive memory element connected to the drain of the third FET; and a fourth FET and a fourth resistive memory element connected to the drain of the fourth FET, the drain of the third FET being connected to the gate of the fourth FET, and the drain of the fourth FET being connected to the gate of the third FET.

[0006] According to one embodiment, a memory device is provided. The memory device includes an array of weight units, each weight unit including: a first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET and a third resistive memory element connected to the drain of the third FET; and a fourth FET and a fourth resistive memory element connected to the drain of the fourth FET, the drain of the third FET being connected to the gate of the fourth FET, and the drain of the fourth FET being connected to the gate of the third FET. The memory device includes a processor configured to perform inference using the array of weight units by: setting an input for a row of weight units in the array of weight units according to a logical value of a corresponding neuron; and reading an output of a column of weight units in the array of weight units.

[0007] According to one embodiment, a memory device is provided. The memory device includes an array of weight units, each weight unit including: a first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; a second FET and a second resistive memory element connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET; a third FET and a third resistive memory element connected to the drain of the third FET; and a fourth FET and a fourth resistive memory element connected to the drain of the fourth FET, the drain of the third FET being connected to the gate of the fourth FET, and the drain of the fourth FET being connected to the gate of the third FET. The processor is configured to write to the resistive memory element according to a direction of a current supplied to the resistive memory element. Description of the Drawings

[0008] The above-mentioned and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, where:

[0009] Figure 1 is a circuit diagram of a weight unit according to an embodiment.

[0010] Figure 2 is a circuit diagram of an array of weight units according to an embodiment.

[0011] Figure 3 is a graph of the current output of an array of weight units according to an embodiment.

[0012] Figure 4 is a block diagram of an electronic device in a network environment according to an embodiment.

[0013] Description of the reference numerals in the drawings

[0014] 100, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224: weight units;

[0015] 102: first magnetic tunnel junction;

[0016] 104: second magnetic tunnel junction;

[0017] 106: third magnetic tunnel junction;

[0018] 108: fourth magnetic tunnel junction;

[0019] 110: first field-effect transistor;

[0020] 112, 122, 132, 142: drains;

[0021] 114, 124, 134, 144: gates;

[0022] 116, 126, 136, 146: sources;

[0023] 120: second field-effect transistor;

[0024] 130: third field-effect transistor;

[0025] 140: fourth field-effect transistor;

[0026] 200: array of weight units;

[0027] 300: graph;

[0028] 302, 304, 306, 308, 310: lines;

[0029] 400: network environment;

[0030] 401, 402, 404: Electronic devices;

[0031] 408: Server;

[0032] 420: Processor;

[0033] 421: Main processor;

[0034] 423: Auxiliary processor;

[0035] 430: Memory;

[0036] 432: Volatile memory;

[0037] 434: Non-volatile memory;

[0038] 436: Internal memory;

[0039] 438: External memory;

[0040] 440: Program;

[0041] 442: Operating system;

[0042] 444: Middleware;

[0043] 446: Application;

[0044] 450: Input device;

[0045] 455: Sound output device;

[0046] 460: Display device;

[0047] 470: Audio module;

[0048] 476: Sensor module;

[0049] 477: Interface;

[0050] 478: Connection terminal;

[0051] 479: Haptic module;

[0052] 480: Camera module;

[0053] 488: Power management module;

[0054] 489: Battery;

[0055] 490: Communication module;

[0056] 492: Wireless communication module;

[0057] 494: Wired communication module;

[0058] 496: User identification module;

[0059] 497: Antenna module;

[0060] 498: First network;

[0061] 499: Second network;

[0062] I out 、 Output;

[0063] I out 1、I out 1B、I out 2、I out 2B、I out 3、I out 3B、I out 4、I out 4B、I out 5、I out 5B、I out 6、I out 6B: Output line;

[0064] G + 、 G - 、 Conductance;

[0065] G H : High conductance state;

[0066] G L : Low conductance state;

[0067] Input;

[0068] V r : Read voltage;

[0069] V w : Write voltage. Detailed implementation manner

[0070] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that although the same elements are illustrated in different drawings, the same elements will be denoted by the same reference numerals. In the following description, specific details such as detailed configurations and components are provided only to assist in the overall understanding of the embodiments of the present disclosure. Therefore, it is apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and configurations are omitted for clarity and conciseness. The terms described below are defined in consideration of the functions in the present disclosure and may vary according to the user, the user's intention, or custom. Therefore, the definitions of the terms should be determined based on the content throughout the specification.

[0071] The present disclosure may have various modifications and various embodiments. In the disclosure, embodiments are described in detail below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

[0072] Although ordinal terms such as first and second may be used to describe various elements, the structural elements are not limited by the terms. The terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, a second structural element may also be referred to as a first structural element. As used herein, the term "and / or" includes any and all combinations of one or more related items.

[0073] The terms used herein are only used to describe various embodiments of the present disclosure but are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In the present disclosure, it should be understood that the terms "include" or "have" indicate the presence of features, numbers, steps, operations, structural elements, parts, or combinations thereof, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, structural elements, parts, or combinations thereof.

[0074] Unless otherwise defined, all terms used herein have the same meaning as those understood by those skilled in the art to which the present disclosure pertains. Terms defined as in a general dictionary will be interpreted as having the same meaning as the context in the relevant technical field and will not be interpreted as having an ideal or overly formal meaning unless clearly defined in the present disclosure.

[0075] An electronic device according to an embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the present disclosure, the electronic device is not limited to those electronic devices described above.

[0076] The terms used in this disclosure are not intended to limit the disclosure, but are intended to include various changes, equivalents, or alternatives for the corresponding embodiments. Regarding the description of the accompanying drawings, like reference numerals may be used to refer to like or related elements. Unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an object may include one or more of the things. As used herein, each of such phrases as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the objects listed together with the corresponding one in the phrase. As used herein, terms such as "first", "second", "the first", and "the second" may be used to distinguish a corresponding component from another component, but are not intended to limit the component in other aspects (e.g., importance or order). It is expected that if an element (e.g., a first element) is related (with or without the terms "operatively" or "communicatively") "coupled to", "couples to", "connected to", or "connects to" another element (e.g., a second element), it indicates that the element may be directly (e.g., wired), wirelessly, or via a third element coupled to the other element.

[0077] As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic", "logic block", "part", and "circuitry". A module may be a single integrated component for performing one or more functions, or the smallest unit or a part thereof. For example, according to an embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0078] In an exemplary scenario, a ternary weight cell for semi-digital matrix vector multiplication consists of four magneto tunnel junctions (MTJs) and four N-type field effect transistors. Each MTJ is a memory device that can be in one of two states: a high resistance state or a low resistance state. Existing MTJ technology can only achieve a relatively small high / low conductance ratio (usually only about 2 to 3). The present disclosure provides a ternary weight cell configuration with logical values {1, 0, -1}, where even if the MTJ has an on / off ratio of only 2 to 3, the on / off ratio of the output current will be closer to that of the transistor (10 4 to 10 5 ). Additionally, the weight cell produces complementary outputs on two lines (output and output bar).

[0079] Figure 1 is a circuit diagram of a weight cell 100 according to an embodiment. The weight cell 100 includes a first magneto tunnel junction (MTJ) 102, a second MTJ 104, a third MTJ 106, and a fourth MTJ 108. The weight cell 100 also includes a first field effect transistor (FET) 110, a second FET 120, a third FET 130, and a fourth FET 140. Although p-type FETs can be utilized, FET 110, FET 120, FET 130, and FET 140 are depicted as n-type FETs (NFETs). FET 110 includes a drain 112, a gate 114, and a source 116. Similarly, FET 120 includes a drain 122, a gate 124, and a source 126. The weight cell 100 includes a first cross-coupling such that the drain 112 of FET 110 is connected to the gate 124 of FET 120 and the drain 122 of FET 120 is connected to the gate 114 of FET 110. FET 130 includes a drain 132, a gate 134, and a source 136. Similarly, FET 140 includes a drain 142, a gate 144, and a source 146. The weight cell 100 includes a second cross-coupling such that the drain 132 of FET 130 is connected to the gate 144 of FET 140 and the drain 142 of FET 140 is connected to the gate 134 of FET 130.

[0080] MTJ 102 has a conductance G + , while MTJ 104 has a conductance MTJ 106 has a conductance G - , while MTJ 108 has a conductance The weight unit 100 includes six external connections: the input of MTJ 102 the input of MTJ 104 the input of MTJ106 the input of MTJ 108 the first output I out and the second output Each MTJ (102 to 108) can be in one of two states: a high conductance state G H or a low conductance state G L either. Cross-coupling allows for a high on / off ratio of the output. MTJs marked with the same symbol (i.e., MTJ 102 and MTJ 104 are marked with +, while MTJ 106 and MTJ108 are marked with -) have different conductance states, and the configuration of the conductances determines the logical value of the weight unit 100, as depicted in Table 1.

[0081] Table 1

[0082]

[0083] During inference, the weight unit 100 performs a multiplication operation in analog form based on the potential on the input lines and the state of the weight unit 100. The product is the analog current on the output line I out and the controlled complementary output on the output line The output lines are all held at the read voltage V r where the read voltage should be small enough such that the current through the MTJ is less than the current that would cause a state change (i.e., a read disturbance fault). The logical value of the input is determined by the same potential applied to the two pairs of input lines. If two lines are set to an input of 2V r and the input and the input and the input and the input are set to ground respectively, then the input has a logical value of 1. If all four input lines are set to the read voltage V r then the input has a logical value of 0. The state of the weight unit 100 is determined by the conductance states of the four MTJs, as depicted in Table 1.

[0084] The output is provided based on the current placed on the output line. The output current (e.g., the read current) is either zero or equal to ±I r = G L V r where the two values are within the limits of no leakage current and zero series resistance of the transfer transistor respectively.

[0085] Figure 2It is a circuit diagram of the weight cell array 200 according to an embodiment. The weight cell array 200 includes two rows of weight cells. Among them, the first row includes weight cells 202 to weight cell 212, and the second row includes weight cells 214 to weight cell 224. To perform inference using the weight cell array 200, the inputs for each row are set according to the logical values corresponding to the neurons. Then the output lines are read in parallel along each column (i.e., output line I out 1 to output line I out 6B), and the total current on the output I out is measured and the total current is divided by I r to obtain the product of the binary multiplication between N input neurons and N ternary weights in a given column. In addition, within the limit where the change is negligible, the current on the line is known.

[0086] Figure 3 It is a graph 300 of the current output of the weight cell array 200 according to an embodiment. Referring to the weight cell array 200, each weight cell has a logical value. The weight cell 202 has a logical value of -1; the weight cell 204 has a logical value of -1; the weight cell 206 has a logical value of -1; the weight cell 208 has a logical value of 0; the weight cell 210 has a logical value of 0; the weight cell 212 has a logical value of 1; the weight cell 214 has a logical value of -1; the weight cell 216 has a logical value of 0; the weight cell 218 has a logical value of 1; the weight cell 220 has a logical value of 0; the weight cell 222 has a logical value of 1; and the weight cell 224 has a logical value of 1.

[0087] Referring to the graph 300, the currents read at the output of each column are different, thereby representing different values for different pairs of logical values along each column. The output at the output line I out 1 is plotted at line 302; the output at the output line I out 2 is plotted at line 304; the outputs at the output line I out 3 and the output line I out 4 are plotted at line 306; the output at the output line I out 5 is plotted at line 308; and the output at the output line I out 6 is plotted at line 310.

[0088] Depending on which pair of MTJs is being written and in which direction ("down" or "up"), writing a given cell requires a separate step, and the direction is defined as the direction of the current relative to Figure 1 the direction of the weight cell 100 shown in. Any MTJ can be written in either direction in one of the three steps outlined in Tables 2 and 3.

[0089] Table 2

[0090]

[0091] Table 2 is an overview of the row-by-row write operation. Define V w as the write voltage, which should be large enough to switch the MTJ. Each row is written once, where each one in the column is programmed based on the voltage of the I out line and line. Each row should be written twice: once to write down any MTJ with a + sign (e.g., MTJ 102 and MTJ 104), and a second time to write up any MTJ with a - sign (e.g., MTJ 106 and MTJ 108).

[0092] Table 3

[0093]

[0094] Table 3 is an overview of the column-by-column write operation. Define V w as the write voltage, which should be large enough to switch the MTJ. For all rows in the column in a single step, MTJs with a + sign (e.g., MTJ 102 and MTJ 104) can be written up column by column and MTJs with a - sign (e.g., MTJ 106 and MTJ 108) can be written down column by column.

[0095] Other non-volatile memory technologies can be utilized instead of STT-MRAM resistive memory elements, such as pulse code modulation (PCM), flash memory, ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), etc. The transistor can be alternatively implemented with a p-type field effect transistor. In the case of PFET, all polarities are reversed for inference and writing.

[0096] Figure 4 is a block diagram of an electronic device 401 in a network environment 400 according to an embodiment. Refer to Figure 4, in the network environment 400, the electronic device 401 can communicate with the electronic device 402 via the first network 498 (e.g., a short-range wireless communication network), or communicate with the electronic device 404 or the server 408 via the second network 499 (e.g., a long-range wireless communication network). The electronic device 401 can communicate with the electronic device 404 via the server 408. The electronic device 401 may include a processor 420, a memory 430, an input device 450, a sound output device 455, a display device 460, an audio module 470, a sensor module 476, an interface 477, a haptic module 479, a camera module 480, a power management module 488, a battery 489, a communication module 490, a subscriber identification module (SIM) 496, or an antenna module 497. At least one of the components may be omitted from the electronic device 401 (e.g., the display device 460 or the camera module 480), or one or more other components may be added to the electronic device 401. Some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 476 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 460 (e.g., a display).

[0097] The processor 420 can execute, for example, software (e.g., the program 440) to control at least one other component (e.g., a hardware component or a software component) of the electronic device 401 coupled to the processor 420, and can perform various data processing or computations. As at least part of the data processing or computation, the processor 420 can load commands or data received from another component (e.g., the sensor module 476 or the communication module 490) in the volatile memory 432, process the commands or data stored in the volatile memory 432, and store the resulting data in the non-volatile memory 434. The processor 420 may include a main processor 421 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 423 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that can operate independently of the main processor 421 or in combination with the main processor. Additionally or alternatively, the auxiliary processor 423 can be used to consume less power than the main processor 421, or perform specific functions. The auxiliary processor 423 may be implemented separately from the main processor 421 or as part of the main processor.

[0098] The auxiliary processor 423 may control at least some of the functions or states related to at least one of the components of the electronic device 401 (e.g., the display device 460, the sensor module 476, or the communication module 490) instead of the main processor 421 when the main processor 421 is in an inactive (e.g., sleep) state or together with the main processor 421 when the main processor 421 is in an active state (e.g., executing an application). The auxiliary processor 423 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 480 or the communication module 490) that is functionally related to the auxiliary processor 423.

[0099] The memory 430 may store various data used by at least one component of the electronic device 401 (e.g., the processor 420 or the sensor module 476). The various data may include, for example, input data or output data of software (e.g., the program 440) and commands related to the software. The memory 430 may include a volatile memory 432 or a non-volatile memory 434.

[0100] The program 440 may be stored in the memory 430 as software and may include, for example, an operating system (OS) 442, middleware 444, or an application 446.

[0101] The input device 450 may receive commands or data to be used by other components of the electronic device 401 (e.g., the processor 420) from the outside of the electronic device 401 (e.g., a user). The input device 450 may include, for example, a microphone, a mouse, or a keyboard.

[0102] The sound output device 455 may output a sound signal to the outside of the electronic device 401. The sound output device 455 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving incoming calls. The receiver may be implemented separately from the speaker or as part of the speaker.

[0103] The display device 460 may visually provide information to the outside of the electronic device 401 (e.g., a user). The display device 460 may include, for example, a display, a hologram device, or a projector, and a control circuit system for controlling the corresponding one of the display, the hologram device, and the projector. The display device 460 may include a touch circuit system for detecting a touch or a sensor circuit system (e.g., a pressure sensor) for measuring the intensity of the force caused by the touch.

[0104] The audio module 470 can convert sound into an electrical signal and vice versa. The audio module 470 can obtain sound via the input device 450, or output sound via the sound output device 455 or a headset of an external electronic device 402 that is directly (e.g., wired) or wirelessly connected to the electronic device 401.

[0105] The sensor module 476 can detect the operating state of the electronic device 401 (e.g., power or temperature) or the environmental state outside the electronic device 401 (e.g., the state of the user), and then generate an electrical signal or data value corresponding to the detected state. The sensor module 476 can include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0106] The interface 477 can support one or more specified protocols to be used for the electronic device 401 to be directly (e.g., wired) or wirelessly connected to an external electronic device 402. The interface 477 can include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0107] The connection terminal 478 can include a connector through which the electronic device 401 can be physically connected to an external electronic device 402. The connection terminal 478 can include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headset connector).

[0108] The haptic module 479 can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus, which can be recognized by the user via a tactile sensation or a proprioceptive sensation. The haptic module 479 can include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0109] The camera module 480 can capture a still image or a moving image. The camera module 480 can include one or more lenses, an image sensor, an image signal processor, or a flash.

[0110] The power management module 488 can manage the power supplied to the electronic device 401. The power management module 488 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0111] The battery 489 can supply power to at least one component of the electronic device 401. The battery 489 can include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0112] The communication module 490 can support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 401 and an external electronic device (e.g., the electronic device 402, the electronic device 404, or the server 408) and performing communication via the established communication channel. The communication module 490 can include one or more communication processors, which can operate independently of the processor 420 (e.g., the AP) and support direct (e.g., wired) communication or wireless communication. The communication module 490 can include a wireless communication module 492 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 494 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with an external electronic device via a first network 498 (e.g., a short-range communication network, such as Bluetooth TM , wireless-fidelity (Wi-Fi) direct, or the Infrared Data Association (IrDA) standard) or a second network 499 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). These different types of communication modules can be implemented as a single component (e.g., a single IC), or can be implemented as multiple components (e.g., multiple ICs) that are discrete from each other. The wireless communication module 492 can use the user information (e.g., an international mobile subscriber identity (IMSI)) stored in the user identification module 496 to identify and authenticate the electronic device 401 in a communication network (such as the first network 498 or the second network 499).

[0113] The antenna module 497 may transmit signals or power to the outside of the electronic device 401 (e.g., an external electronic device) or receive signals or power from the outside of the electronic device (e.g., an external electronic device). The antenna module 497 may include one or more antennas and may select at least one antenna suitable for a communication scheme to be used in a communication network such as the first network 498 or the second network 499 from the antennas, for example, through the communication module 490 (e.g., the wireless communication module 492). Then, signals or power may be transmitted or received between the communication module 490 and the external electronic device via the selected at least one antenna.

[0114] At least some of the above components may be interconnected and transmit signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme such as a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI).

[0115] According to one embodiment, commands or data may be transmitted or received between the electronic device 401 and the external electronic device 404 via a server 408 coupled to the second network 499. Each of the electronic devices 402 and 404 may be a device of the same type or a different type from the electronic device 401. All or some of the operations to be performed at the electronic device 401 may be performed at one or more of the external electronic devices 402, 404, or 408. For example, if the electronic device 401 should automatically or in response to a request from a user or another device perform a function or service, then instead of or in addition to performing the function or the service, the electronic device 401 may also request one or more external electronic devices to perform at least part of the function or service. One or more of the external electronic devices that receive the request may perform at least part of the requested function or service or additional functions or additional services related to the request and transmit the result of the execution to the electronic device 401. The electronic device 401 may provide the result (with or without further processing the result) as at least part of a reply to the request. To this end, for example, cloud computing, distributed computing, or client-server computing technologies may be used.

[0116] One embodiment may be implemented as software (e.g., program 440) that includes one or more instructions stored in a storage medium (e.g., internal memory 436 or external memory 438) readable by a machine (e.g., electronic device 401). For example, a processor of electronic device 401 may invoke at least one of the one or more instructions stored in the storage medium and execute at least one of the one or more instructions, with or without one or more other components under the control of the processor. Thus, the machine is operable to perform at least one function in accordance with the at least one invoked instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but this term does not distinguish between cases where data is stored semi-permanently in the storage medium and cases where data is stored temporarily in the storage medium.

[0117] According to one embodiment, the method of the present disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or distributed online via an app store (e.g., Play Store TM ) (e.g., downloaded or uploaded), or distributed directly between two user devices (e.g., smartphones). If distributed online, at least a portion of the computer program product may be generated temporarily or stored at least temporarily in a machine-readable storage medium (such as the memory of a manufacturer's server, the server of an app store, or a relay server).

[0118] According to one embodiment, each of the above components (e.g., module or program) may include a single entity or multiple entities. One or more of the above components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may still perform the one or more functions in the same or similar manner as each of the multiple components performed the one or more functions corresponding to each of the multiple components before integration. Operations performed by a module, program, or another component may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be performed in a different order or omitted, or one or more other operations may be added.

[0119] Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure can be modified in various forms without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be determined only based on the described embodiments, but should be determined based on the appended claims and their equivalents.

Claims

1. A weight unit, comprising: A first field effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field effect transistor; A second field effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field effect transistor, the drain of the first field effect transistor being connected to the gate of the second field effect transistor, and the drain of the second field effect transistor being connected to the gate of the first field effect transistor; A third field effect transistor and a third resistive memory element, the third resistive memory element being connected to the drain of the third field effect transistor; And A fourth field effect transistor and a fourth resistive memory element, the fourth resistive memory element being connected to the drain of the fourth field effect transistor, the drain of the third field effect transistor being connected to the gate of the fourth field effect transistor and the drain of the fourth field effect transistor being connected to the gate of the third field effect transistor, wherein the third resistive memory element is connected to the source of the first field effect transistor, and the fourth resistive memory element is connected to the source of the second field effect transistor.

2. The weight unit according to claim 1, wherein the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor comprise n-type field effect transistors.

3. The weight unit according to claim 1, wherein the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor comprise p-type field effect transistors.

4. The weight unit according to claim 1, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element comprise magnetic tunnel junctions.

5. The weight unit according to claim 1, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element comprise resistive random access memory elements.

6. The weight unit according to claim 1, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element comprise ferroelectric random access memory elements.

7. The weight unit according to claim 1, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element comprise pulse code modulation memory elements.

8. The weight unit according to claim 1, wherein a first voltage is input to the source of the fourth field effect transistor, and a second voltage different from the first voltage is input to the second resistive memory element.

9. The weight unit according to claim 8, wherein a current is output from the source of the fourth resistive memory element and the second field effect transistor.

10. The weight unit according to claim 1, further comprising a first external connection to a lead of the first resistive memory element and a second external connection to a lead of the second resistive memory element.

11. The weight unit according to claim 10, further comprising a third external connection to the source of the third field effect transistor and a fourth external connection to the source of the fourth field effect transistor.

12. The weight unit according to claim 1, wherein the weight unit generates a logical value based on the conductance of the first resistive memory element, the conductance of the second resistive memory element, the conductance of the third resistive memory element, and the conductance of the fourth resistive memory element.

13. A memory device, comprising: An array of weight units, each weight unit comprising: A first field effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field effect transistor; A second field effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field effect transistor, the drain of the first field effect transistor being connected to the gate of the second field effect transistor, and the drain of the second field effect transistor being connected to the gate of the first field effect transistor; A third field effect transistor and a third resistive memory element, the third resistive memory element being connected to the drain of the third field effect transistor; And A fourth field effect transistor and a fourth resistive memory element, the fourth resistive memory element being connected to the drain of the fourth field effect transistor, the drain of the third field effect transistor being connected to the gate of the fourth field effect transistor, and the drain of the fourth field effect transistor being connected to the gate of the third field effect transistor; And A processor configured to perform inference with the array of weight units by: Setting an input for a row of weight units in the array of weight units according to a logical value of a corresponding neuron; and Reading an output of a column of weight units from the array of weight units.

14. The memory device according to claim 13, wherein the processor is further configured to perform inference by measuring a total current from the read output and dividing the total current by an output current.

15. The memory device according to claim 13, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element comprise magnetic tunnel junctions.

16. The memory device according to claim 13, wherein the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor comprise n-type field effect transistors.

17. A memory device, comprising: An array of weight units, each weight unit comprising: A first field effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field effect transistor; A second field effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field effect transistor, the drain of the first field effect transistor being connected to the gate of the second field effect transistor, and the drain of the second field effect transistor being connected to the gate of the first field effect transistor; A third field effect transistor and a third resistive memory element, the third resistive memory element being connected to the drain of the third field effect transistor; And A fourth field effect transistor and a fourth resistive memory element, the fourth resistive memory element being connected to the drain of the fourth field effect transistor, the drain of the third field effect transistor being connected to the gate of the fourth field effect transistor, and the drain of the fourth field effect transistor being connected to the gate of the third field effect transistor; And A processor configured to write to the first resistive memory element and the second resistive memory element according to the direction of current supplied to the first resistive memory element and the second resistive memory element, wherein the third resistive memory element is connected to the source of the first field effect transistor, and the fourth resistive memory element is connected to the source of the second field effect transistor.

18. The memory device according to claim 17, wherein the processor is configured to write to the first resistive memory element and the second resistive memory element row by row in the weight cell array.

19. The memory device according to claim 17, wherein the processor is configured to write to the first resistive memory element and the second resistive memory element column by column in the weight cell array.

20. The memory device according to claim 17, wherein the first resistive memory element, the second resistive memory element, the third resistive memory element, and the fourth resistive memory element include magnetic tunnel junctions.

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