Display unit, display device, and method for manufacturing a display unit

Abstract

The present disclosure relates to a display unit, a display device, and a method of manufacturing a display unit. The display unit includes: a signal line electrically connected to a pixel disposed in a display area; a signal pad unit disposed in a peripheral area adjacent to the display area and including a signal pad electrically connected to the signal line; an inspection pad unit disposed in a conduction inspection area and including an inspection pad electrically connected to the signal pad, wherein the inspection pad is configured to receive a conduction inspection signal; and a power supply voltage line configured to apply a power supply voltage to the pixel, the power supply voltage line extending from the inspection pad unit to the peripheral area, and the power supply voltage line being divided into a plurality of sub-lines by at least one slit pattern in a cutout area between the peripheral area and the conduction inspection area.

Description

Technical Field

[0001] Some embodiments of the inventive concept relate to a display unit, a display device, and a method of manufacturing the display unit. Background Art

[0002] Recently, various flat panel display devices having reduced weight and volume compared to cathode ray tube (CRT) displays have been developed. The flat panel display devices include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting diode (OLED) displays, inorganic electroluminescent displays, and quantum dot light emitting diode (QLED or QD-LED) displays.

[0003] An OLED display displays an image by using an organic light emitting diode that emits light through recombination between electrons and holes. The OLED display has a fast response speed and is driven at low power consumption.

[0004] The OLED display includes an organic light emitting display panel, and the organic light emitting display panel performs an array inspection for checking electrical defects in a display unit state and a conduction inspection for checking conduction defects.

[0005] After the array inspection and the conduction inspection, a module process is performed. The module process includes: a step of cutting an inspection area of the organic light emitting display panel, the inspection area having inspection pads and inspection circuits formed thereon for the array inspection and the conduction inspection; and a step of attaching a polarizing plate, a protective film, and a flexible circuit board on which a driving chip is mounted to the cut organic light emitting display panel. Summary of the Invention

[0006] Some embodiments of the inventive concept provide a display unit for preventing cracks during a manufacturing process, a display device including the display unit, and a method of manufacturing the display unit.

[0007] According to some embodiments of the inventive concept, a display unit includes: signal lines electrically connected to pixels disposed in a display area; a signal pad unit disposed in a peripheral area adjacent to the display area and including signal pads electrically connected to the signal lines; an inspection pad unit disposed in a conduction inspection area and including inspection pads electrically connected to the signal pads, wherein the inspection pads are configured to receive a conduction inspection signal; and a power voltage line for applying a power voltage to the pixels, the power voltage line extending from the inspection pad unit to the peripheral area, and the power voltage line being divided into a plurality of sub-lines by at least one slit pattern in a cutout area between the peripheral area and the conduction inspection area.

[0008] In some embodiments of the inventive concept, the display unit may further include: an insulating film exposing the at least one slit pattern and the plurality of sub-lines located in the cutting area. The slit pattern

[0009] In some embodiments of the inventive concept, the insulating film may include: an inorganic insulating film disposed over a gate electrode of a transistor included in the pixel; and an organic insulating film disposed over a source electrode and a drain electrode of the transistor.

[0010] In some embodiments of the inventive concept, the at least one slit pattern may have a width corresponding to an extending direction of a cutting line and a length corresponding to a direction intersecting the extending direction.

[0011] In some embodiments of the inventive concept, the width of the at least one slit pattern may be greater than a pitch of laser spots used during a cutting process.

[0012] In some embodiments of the inventive concept, the plurality of sub-lines may have a line width corresponding to the extending direction of the cutting line, and the line width is greater than the pitch of the laser spots.

[0013] In some embodiments of the inventive concept, a width of the power supply voltage line located in the cutting area may be determined based on resistivity characteristics of the plurality of sub-lines.

[0014] In some embodiments of the inventive concept, the display unit may further include: a conduction checking circuit disposed in the conduction checking area and electrically connected to the checking pad unit.

[0015] In some embodiments of the inventive concept, the pixel may include an organic light emitting diode, and the power supply voltage line may include at least one of a first power supply voltage line for transmitting a first power supply voltage to the organic light emitting diode and a second power supply voltage line for transmitting a second power supply voltage to the organic light emitting diode.

[0016] In some embodiments of the inventive concept, the peripheral area may include: a first peripheral area in which the signal pad unit is disposed, a second peripheral area adjacent to the first peripheral area, a third peripheral area facing the second peripheral area, and a fourth peripheral area facing the first peripheral area. The first peripheral area to the fourth peripheral area may surround the display area, and the first power supply voltage line may extend from the checking pad unit and be disposed in the first peripheral area.

[0017] In some embodiments of the inventive concept, the second power supply voltage line may extend from the inspection pad unit and be disposed in the second peripheral region, the third peripheral region, and the fourth peripheral region.

[0018] According to some embodiments of the inventive concept, a display device includes: a display unit including: signal lines electrically connected to pixels disposed in a display area; a signal pad unit disposed in a peripheral region adjacent to the display area and including signal pads electrically connected to the signal lines; and power supply voltage lines disposed in the peripheral region to apply a power supply voltage to the pixels and divided into a plurality of sub-lines in an edge region; and a flexible printed circuit board bonded to the signal pad unit through an anisotropic conductive film, wherein a driving integrated circuit for driving the display unit is mounted above the flexible printed circuit board.

[0019] In some embodiments of the inventive concept, the display unit may further include: an insulating film exposing the plurality of sub-lines disposed in the edge region.

[0020] In some embodiments of the inventive concept, the insulating film may include: an inorganic insulating film disposed above a gate electrode of a transistor included in the pixel; and an organic insulating film disposed above a source electrode and a drain electrode of the transistor.

[0021] In some embodiments of the inventive concept, the pixel may include an organic light-emitting diode, and the power supply voltage line may include at least one of a first power supply voltage line and a second power supply voltage line, the first power supply voltage line transmitting a first power supply voltage to the organic light-emitting diode, and the second power supply voltage line transmitting a second power supply voltage to the organic light-emitting diode.

[0022] In some embodiments of the inventive concept, the peripheral region may include: a first peripheral region in which the signal pad unit is disposed, a second peripheral region adjacent to the first peripheral region, a third peripheral region facing the second peripheral region, and a fourth peripheral region facing the first peripheral region, the first peripheral region to the fourth peripheral region may surround the display area, and the first power supply voltage line may extend from the edge region and be disposed in the first peripheral region.

[0023] In some embodiments of the inventive concept, the second power supply voltage line may extend from the edge region and be disposed in the second peripheral region, the third peripheral region, and the fourth peripheral region.

[0024] According to some embodiments of the inventive concept, in a method of manufacturing a display unit, a signal line is formed, the signal line being electrically connected to pixels disposed in a display area; a signal pad is formed, the signal pad being disposed in a peripheral area adjacent to the display area and electrically connected to the signal line; an inspection pad is formed, the inspection pad being disposed in a conduction inspection area and electrically connected to the signal pad such that a conduction inspection signal is applied to the inspection pad; and a power voltage line is formed, the power voltage line extending from the inspection pad to the peripheral area and being divided into a plurality of sub-lines by at least one slit pattern in a cut-out area between the peripheral area and the conduction inspection area.

[0025] In some embodiments of the inventive concept, the at least one slit pattern and the plurality of sub-lines may be exposed by removing an insulating film disposed above the at least one slit pattern and the plurality of sub-lines in the cut-out area.

[0026] In some embodiments of the inventive concept, the at least one slit pattern may have a width of the slit pattern corresponding to an extending direction of a cutting line, the width of the slit pattern may be greater than a pitch of laser spots in a cutting process, the plurality of sub-lines may have a line width corresponding to the extending direction of the cutting line, and the line width may be greater than the pitch of the laser spots. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the inventive concept will be more fully understood by describing in detail some embodiments of the inventive concept with reference to the accompanying drawings.

[0028] Figure 1 is a plan view for explaining a display unit according to an embodiment of the inventive concept.

[0029] Figure 2 is for explaining an embodiment of the inventive concept Figure 1 of a pixel circuit diagram of a pixel included in a display unit.

[0030] Figure 3 is for explaining a conduction inspection device of a display unit for an embodiment of the inventive concept Figure 1 of.

[0031] Figure 4 is Figure 1 an enlarged view of a part 'A' to explain a structure of a power voltage line according to an embodiment of the inventive concept.

[0032] Figure 5 is Figure 4 an enlarged view of a part 'B' for explaining a slit pattern and sub-lines in a cut-out area according to an embodiment of the inventive concept.

[0033] Figure 6 is a cross-sectional view of a display unit according to an embodiment of the inventive concept. Figure 1 of the display unit.

[0034] Figure 7 and Figure 8 are schematic views for explaining a laser cutting process according to a comparative example and an embodiment of the inventive concept, respectively.

[0035] Figure 9A and Figure 9B are conceptual diagrams depicting various voltage lines according to some embodiments of the inventive concept.

[0036] Figure 10 is a plan view of a display device according to an embodiment of the inventive concept. Detailed Description of Specific Embodiments

[0037] Some embodiments of the inventive concept provide a display unit for preventing cracks during a manufacturing process, a display device including the display unit, and a method of manufacturing the display unit.

[0038] Hereinafter, some embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout this application, like reference numerals may refer to like elements.

[0039] It will be understood that when an element or layer is referred to as being "on," "above," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly above, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0040] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the inventive concept. As used herein, unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0041] It will be further understood that when used in this specification, the terms "comprises," "comprising," "includes," "including," "has," "having," and the like specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] For ease of description, in this document, spatial relative terms such as "under", "below", "beneath", "underneath", "above", "over", and "on" may be used to describe the relationship of one element or feature shown in the figure with another element (s) or feature (s). It will be understood that such spatial relative terms are also intended to cover different orientations of the device during use or operation, in addition to the orientation depicted in the drawings. For example, if the device is flipped in the drawing, an element described as "under", "beneath", or "underneath" another element or feature will then be oriented "above" the other element or feature. Thus, the example terms "under" and "underneath" can cover both the "above" and "below" orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it will also be understood that when a layer or element is referred to as being "between" two layers or two elements, the layer or element may be the only layer or element between the two layers or two elements, or there may also be one or more intermediate layers or elements.

[0043] Figure 1 is a plan view of a display unit for illustrating an embodiment according to the inventive concept. Figure 2 is for illustrating an embodiment according to the inventive concept Figure 1 of a pixel circuit diagram of a pixel included in the display unit. Figure 3 is for illustrating for an embodiment according to the inventive concept Figure 1 of a concept diagram of a turn-on inspection device of a display unit.

[0044] Refer to Figure 1 , the display unit 100 includes: pixels PX that display an image; a first power voltage line VL1 that transmits a first power voltage ELVDD to the pixels PX; and a second power voltage line VL2 that transmits a second power voltage ELVSS to the pixels PX.

[0045] In an embodiment of the inventive concept, the pixels PX may include organic light emitting diodes, the first power voltage ELVDD may be a high power voltage applied to the organic light emitting diodes, and the second power voltage ELVSS may be a low power voltage applied to the organic light emitting diodes.

[0046] For example, the display unit 100 may include a display area DA in which the pixels PX are arranged and a non-display area surrounding the display area DA in which the first power voltage line VL1 and the second power voltage line VL2 are arranged.

[0047] The display area DA may include a plurality of pixels PX arranged in a matrix form, and a plurality of data lines DL and a plurality of scan lines SL electrically connected to the plurality of pixels PX.

[0048] The data lines DL may extend in a first direction DR1 and may be arranged in a second direction DR2 intersecting the first direction DR1.

[0049] The scan lines SL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0050] Reference Figure 2 , the pixel PX may include a pixel circuit PXC.

[0051] The pixel circuit PXC may include an organic light emitting diode OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0052] The anode of the organic light emitting diode OLED may be electrically connected to the first transistor T1 via the sixth transistor T6, and the cathode may be electrically connected to the second power supply voltage ELVSS. The organic light emitting diode OLED may generate light having a luminance corresponding to the amount of current supplied from the first transistor T1.

[0053] The first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS so that current flows to the organic light emitting diode OLED.

[0054] The seventh transistor T7 may be electrically connected between the initialization power supply VINT and the anode of the organic light emitting diode OLED. Additionally, the gate electrode of the seventh transistor T7 may be electrically connected to the (i + 1)-th scan line S1i+1 or the (i - 1)-th scan line S1i-1. When a scan signal is supplied to the (i + 1)-th scan line S1i+1 or the (i - 1)-th scan line S1i-1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply VINT can be supplied to the anode of the organic light emitting diode OLED. Here, the initialization power supply VINT may be set to a voltage lower than the data signal.

[0055] The sixth transistor T6 may be electrically connected between the first transistor T1 and the organic light emitting diode OLED. Additionally, the gate electrode of the sixth transistor T6 may be electrically connected to the i-th light emission control line E1i. When a light emission control signal is supplied to the i-th light emission control line E1i, the sixth transistor T6 may be turned on.

[0056] The fifth transistor T5 may be electrically connected between the first power supply voltage ELVDD and the first transistor T1. Additionally, the gate electrode of the fifth transistor T5 may be electrically connected to the i-th light emission control line E1i. When a light emission control signal is supplied to the i-th light emission control line E1i, the fifth transistor T5 may be turned on.

[0057] The first electrode of the first transistor T1 (driving transistor) may be electrically connected to the first power supply voltage ELVDD via the fifth transistor T5, and the second electrode may be electrically connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. Additionally, the gate electrode of the first transistor T1 may be electrically connected to the first node N1. In response to the voltage of the first node N1, the first transistor T1 may control the amount of current flowing from the first power supply voltage ELVDD through the organic light emitting diode OLED to the second power supply voltage ELVSS.

[0058] The third transistor T3 may be electrically connected between the second electrode of the first transistor T1 and the first node N1. Additionally, the gate electrode of the third transistor T3 may be electrically connected to the i-th scan line S1i. When a scan signal is supplied to the i-th scan line S1i, the third transistor T3 may be turned on so that the second electrode of the first transistor T1 may be electrically connected to the first node N1. Thus, when the third transistor T3 is turned on, the first transistor T1 may be electrically connected in the form of a diode.

[0059] The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power supply VINT. Additionally, the gate electrode of the fourth transistor T4 may be electrically connected to the (i - 1)-th scan line S1i - 1. When a scan signal is supplied to the (i - 1)-th scan line S1i - 1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply VINT may be supplied to the first node N1.

[0060] The second transistor T2 may be electrically connected between the m-th data line Dm and the first electrode of the first transistor T1. Additionally, the gate electrode of the second transistor T2 may be electrically connected to the i-th scan line S1i. When a scan signal is supplied to the i-th scan line S1i, the second transistor T2 may be turned on so that the m-th data line Dm may be electrically connected to the first electrode of the first transistor T1.

[0061] The storage capacitor CST may be electrically connected between the first power supply voltage ELVDD and the first node N1. The storage capacitor CST may store a data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

[0062] Return reference Figure 1, the non-display area includes a first peripheral area PA1, a second peripheral area PA2, a third peripheral area PA3, and a fourth peripheral area PA4 surrounding the display area DA. Additionally, the non-display area may include a cutout area CA adjacent to the first peripheral area PA1 and a conduction check area TSA adjacent to the cutout area CA.

[0063] The first peripheral area PA1 corresponds to the first end of the data line DL and is adjacent to the display area DA. The first peripheral area PA1 may include a fan-out area FOA and a signal pad area SPA.

[0064] Fan-out lines FOL electrically connected to signal lines such as the data line DL may be arranged in the fan-out area FOA. Signal pad units SPD may be disposed in the signal pad area SPA, and signal pads electrically connected to the fan-out lines FOL are arranged on or above the signal pad units SPD.

[0065] The second peripheral area PA2 corresponds to the first end of the scan line SL and is adjacent to the display area DA.

[0066] The third peripheral area PA3 corresponds to the second end of the scan line SL and is adjacent to the display area DA.

[0067] The fourth peripheral area PA4 corresponds to the second end of the data line DL and is adjacent to the display area DA.

[0068] The cutout area CA is disposed between the first peripheral area PA1 and the conduction check area TSA. After the conduction check process and before the module process, the cutout area CA is cut along a cutting line CL set by a laser cutting process.

[0069] The conduction check area TSA may include: a conduction pad unit TPD on which check pads are arranged, to which a check signal for performing a conduction check process is applied; and a conduction check circuit TSC electrically connected to the conduction pad unit TPD. The check pads may be electrically connected to the signal pads of the signal pad unit SPD. The conduction check circuit TSC may be electrically connected to the data line DL and the scan line SL arranged in the display area DA.

[0070] The check control signal and the check data signal provided from the conduction pad unit TPD may be applied to the data line DL and the scan line SL to turn on the pixel PX, so that a conduction check process can be performed.

[0071] In an embodiment of the inventive concept, the conduction pad unit TPD may be arranged in a structure that is horizontally symmetric with respect to the display area DA. For example, the conduction pad unit TPD may include a first inspection pad unit TPD1 corresponding to the second peripheral area PA2 and a second inspection pad unit TPD2 corresponding to the third peripheral area PA3.

[0072] Referring Figure 3 , the conduction inspection device 200 may include an inspection control unit 201 and an inspection signal output unit 202.

[0073] The inspection control unit 201 may generate a plurality of inspection signals corresponding to an inspection mode. For example, the inspection signals may include a first power supply voltage ELVDD, a second power supply voltage ELVSS, a voltage of an initialization power supply VINT, and a plurality of inspection data signals DCR, DCG, and DCB.

[0074] The inspection signal output unit 202 may be electrically connected to the conduction pad unit TPD of the display unit 100 and may provide the inspection signals to the conduction pad unit TPD.

[0075] Returning to the reference Figure 1 , in an embodiment of the inventive concept, the first power supply voltage line VL1 may include a first voltage line L11, a second voltage line L12, and a third voltage line L13.

[0076] The first voltage line L11 is electrically connected to the first inspection pad unit TPD1 and extends from the conduction inspection area TSA via the cutout area CA to the signal pad area SPA of the first peripheral area PA1 along the first direction DR1.

[0077] The second voltage line L12 is electrically connected to the second inspection pad unit TPD2 and extends from the conduction inspection area TSA via the cutout area CA to the signal pad area SPA of the first peripheral area PA1 along the first direction DR1.

[0078] The third voltage line L13 extends from the fan-out area FOA of the first peripheral area PA1 in the second direction DR2 and is electrically connected to the first voltage line L11 and the second voltage line L12.

[0079] In an embodiment of the inventive concept, the second power supply voltage line VL2 may include a first voltage line L21, a second voltage line L22, and a third voltage line L23.

[0080] The first voltage line L21 is electrically connected to the first inspection pad unit TPD1, extends from the conduction inspection area TSA via the cutout area CA to the signal pad area SPA and the fan-out area FOA of the first peripheral area PA1 along the first direction DR1, and continuously extends in the first direction DR1 in the second peripheral area PA2.

[0081] The second voltage line L22 is electrically connected to the second inspection pad unit TPD2, extends from the conduction inspection area TSA through the cutting area CA to the signal pad area SPA and the fan-out area FOA of the first peripheral area PA1 along the first direction DR1, and continuously extends along the first direction DR1 in the third peripheral area PA3.

[0082] The third voltage line L23 extends along the second direction DR2 in the fourth peripheral area PA4 and is electrically connected to the first voltage line L21 and the second voltage line L22.

[0083] In an embodiment of the inventive concept, in the cutting area CA, at least one of the first power supply voltage line VL1 and the second power supply voltage line VL2 may be branched or divided into a plurality of sub-lines by at least one slit pattern. The at least one slit pattern may have a length corresponding to a direction intersecting the extending direction of the cutting line CL and may have a width corresponding to the extending direction of the cutting line CL. The sub-lines may be arranged in the extending direction of the cutting line CL.

[0084] The total maximum current capacity for driving the organic light-emitting diode OLED included in the pixel PX is at the level of several tens of amperes, and as the size of the organic light-emitting display increases, the current capacity with respect to the power supply voltage may increase. Accordingly, the widths of the first power supply voltage line VL1 and the second power supply voltage line VL2 may increase. When the width of the metal line increases, defects such as cracks may occur in the display unit during the laser cutting process due to incomplete laser processing.

[0085] According to an embodiment of the inventive concept, in order to prevent defects such as cracks that may occur during the cutting process, in the cutting area CA, at least one of the first power supply voltage line VL1 and the second power supply voltage line VL2 may be divided into a plurality of sub-lines by at least one slit pattern. The width of the slit pattern may be set in consideration of the spacing of the laser spots.

[0086] Figure 4 is Figure 1 an enlarged view of part 'A' of to illustrate the structure of the power supply voltage line according to an embodiment of the inventive concept. Figure 5 is Figure 4 an enlarged view of part 'B' of for illustrating the slit pattern and the sub-lines in the cutting area according to an embodiment of the inventive concept.

[0087] Refer to Figure 4 and Figure 5 The first power supply voltage line VL1 may transmit the first power supply voltage ELVDD, and the second power supply voltage line VL2 may transmit the second power supply voltage ELVSS.

[0088] At least one of the first power supply voltage line VL1 and the second power supply voltage line VL2 may include at least one slit pattern SP in the cutout region CA.

[0089] As shown in the figure, the first power supply voltage line VL1 has a first width W1 in the conduction check region TSA and the first peripheral region PA1, and includes a slit pattern SP in the cutout region CA between the conduction check region TSA and the first peripheral region PA1. In the cutout region CA, the first power supply voltage line VL1 may be divided into a first sub-line VL_S1 and a second sub-line VL_S2 by the slit pattern SP. Each of the first sub-line VL_S1 and the second sub-line VL_S2 may have a second width W2 smaller than the first width W1.

[0090] In addition, the second power supply voltage line VL2 may have a first width W1 in the conduction check region TSA and the first peripheral region PA1, and may include a slit pattern SP in the cutout region CA between the conduction check region TSA and the first peripheral region PA1. In the cutout region CA, the second power supply voltage line VL2 may be divided into a first sub-line VL_S1 and a second sub-line VL_S2 by the slit pattern SP. Each of the first sub-line VL_S1 and the second sub-line VL_S2 may have a second width W2 smaller than the first width W1.

[0091] In an embodiment of the inventive concept, the width SW of the slit pattern SP may be set to be greater than or equal to the pitch LP of the laser spots used in the laser cutting process (SW≥LP).

[0092] In an embodiment of the inventive concept, the second width W2 (which may also be referred to as the line width) of each of the first sub-line VL_S1 and the second sub-line VL_S2 may be set to be greater than or equal to the pitch LP of the laser spots (W2≥LP).

[0093] Figure 6 is a cross-sectional view of a Figure 1 display unit according to an embodiment of the inventive concept.

[0094] Refer to Figure 1 , Figure 4 and Figure 6 , the display unit 100 may include a pixel region PXA in which pixels PX are formed and a cutout region CA cut by a laser cutting process.

[0095] The display unit 100 may include a substrate 110, and the substrate 110 may include the pixel region PXA and the cutout region CA.

[0096] The substrate 110 may be a transparent or opaque insulating substrate. For example, the substrate 110 may include glass or plastic, such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), or polyacrylate.

[0097] Referring to the pixel region PXA of the display unit 100, a buffer layer 115 may be disposed on or above the substrate 110. The buffer layer 115 may block the penetration of impurities such as oxygen and moisture through the substrate 110. Additionally, the buffer layer 115 may provide a flat surface on top of the substrate 110. The buffer layer 115 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. Optionally, the buffer layer 115 may be omitted.

[0098] The thin-film transistor TFT and the storage capacitor CST (e.g., Figure 2 the storage capacitor CST) may be disposed on or above the buffer layer 115. The thin-film transistor TFT may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 150. In an embodiment of the inventive concept, the thin-film transistor TFT may have a top-gate structure in which the gate electrode 130 is located above the semiconductor layer 120. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the thin-film transistor TFT may have a bottom-gate structure in which the gate electrode 130 is located below the semiconductor layer 120.

[0099] The semiconductor layer 120 may be disposed on or above the buffer layer 115. The semiconductor layer 120 may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor, etc. The semiconductor layer 120 may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0100] The gate insulating film 125 covering the semiconductor layer 120 may be disposed on or above the buffer layer 115. The gate insulating film 125 may isolate the gate electrode 130 from the semiconductor layer 120. The gate insulating film 125 may include silicon nitride, silicon oxide, or silicon oxynitride, etc.

[0101] The gate electrode 130 may be disposed on or above the gate insulating film 125. The gate electrode 130 may overlap with the channel region of the semiconductor layer 120. The gate electrode 130 may be formed of a first metal layer. The first metal layer may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or an alloy thereof.

[0102] The interlayer insulating film 135 covering the gate electrode 130 may be provided on or above the gate insulating film 125. The interlayer insulating film 135 may isolate the source electrode 140 and the drain electrode 150 from the gate electrode 130. The interlayer insulating film 135 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0103] The source electrode 140 and the drain electrode 150 may be provided on or above the interlayer insulating film 135. The source electrode 140 and the drain electrode 150 may be electrically connected to the source region and the drain region of the semiconductor layer 120 through contact holes formed in the interlayer insulating film 135 and the gate insulating film 125, respectively. The source electrode 140 and the drain electrode 150 may be formed of a second metal layer. The second metal layer may include aluminum alloy. The aluminum alloy may include one of copper (Cu), vanadium (V), and silicon (Si).

[0104] In an embodiment of the inventive concept, the second metal layer may include a first layer, a second layer, and a third layer that are sequentially stacked. For example, the first layer may be provided under the bottom surface of the second layer, and the third layer may be provided on or above the top surface of the second layer. The first layer, the second layer, and the third layer may have a Ti / Al / Ti stack structure including titanium (Ti), aluminum alloy, and titanium, respectively.

[0105] The storage capacitor CST includes a first storage electrode 133 formed of the same first metal layer as the gate electrode 130 and a second storage electrode 153 formed of the same second metal layer as the source electrode 140 and the drain electrode 150. The second storage electrode 153 overlaps the first storage electrode 133, and the storage capacitor CST may be defined in an overlapping region between the first storage electrode 133 and the second storage electrode 153.

[0106] The planarization layer 175 may be provided on or above the interlayer insulating film 135 to have a large thickness for covering the source electrode 140, the drain electrode 150, and the second storage electrode 153. The planarization layer 175 may include an organic material such as acrylic resin, epoxy resin, polyimide resin, or polyester resin.

[0107] The first electrode 180 may be provided on or above the planarization layer 175. The first electrode 180 may be electrically connected to the drain electrode 150 of the thin film transistor TFT through a contact hole formed in the planarization layer 175. The first electrode 180 may include indium tin oxide (ITO), silver, and ITO.

[0108] The pixel defining layer 190 covering the first electrode 180 may be disposed on or above the planarization layer 175. The pixel defining layer 190 may include an opening exposing the top surface of the first electrode 180 and define a light-emitting region. The pixel defining layer 190 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin.

[0109] The organic light-emitting layer 210 may be disposed in the opening exposing the top surface of the first electrode 180. The organic light-emitting layer 210 may include a low-molecular organic compound or a high-molecular organic compound. In an embodiment of the inventive concept, the organic light-emitting layer 210 may emit red light, green light, or blue light. In an embodiment of the inventive concept, when the organic light-emitting layer 210 emits white light, the organic light-emitting layer 210 may include a multi-layer structure including a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, or may include a single-layer structure including a red light-emitting material, a green light-emitting material, and a blue light-emitting material.

[0110] The second electrode 230 may be disposed on or above the organic light-emitting layer 210. For example, the second electrode 230 may be disposed on or above the organic light-emitting layer 210 and the pixel defining layer 190. The second electrode 230 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0111] Referring to the cutout region CA of the display unit 100, the buffer layer 115 may be disposed on or above the substrate 110.

[0112] The gate insulating film 125 may be disposed on or above the buffer layer 115. The first power supply voltage line VL1 and the second power supply voltage line VL2 formed of a first metal layer may be disposed on or above the gate insulating film 125.

[0113] In the cutout region CA, the first power supply voltage line VL1 may include at least one slit pattern SP and include a plurality of sub-lines VL_S1 and VL_S2. In addition, the second power supply voltage line VL2 may include at least one slit pattern SP and include a plurality of sub-lines VL_S1 and VL_S2. At least one slit pattern SP and the sub-lines VL_S1 and VL_S2 may be formed in a process of patterning the first metal layer.

[0114] In the cutting region CA, the interlayer insulating film 135 exposes the sub-lines VL_S1 and VL_S2 of the first power supply voltage line VL1 and at least one slit pattern SP. The interlayer insulating film 135 may be formed of an inorganic material. The interlayer insulating film 135 formed on the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP or the interlayer insulating film 135 formed above the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP may be removed in a subsequent process for forming a gate pad. However, the inventive concept is not limited thereto, and the interlayer insulating film 135 formed on the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP or the interlayer insulating film 135 formed above the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP may be removed by various subsequent etching processes.

[0115] In addition, in the cutting region CA, the planarization layer 175 exposes the sub-lines VL_S1 and VL_S2 of the first power supply voltage line VL1 and at least one slit pattern SP. The planarization layer 175 may be formed of an organic material. The planarization layer 175 formed above the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP may be removed in a process of forming a via hole (e.g., a contact hole in which the first electrode 180 of the pixel region PXA contacts the drain electrode 150). However, the inventive concept is not limited thereto, and the planarization layer 175 formed on the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP or the planarization layer 175 formed above the sub-lines VL_S1 and VL_S2 and at least one slit pattern SP may be removed by various subsequent etching processes.

[0116] The sub-lines VL_S1 and VL_S2 corresponding to the first power supply voltage line VL1 in the cutting region CA and at least one slit pattern SP may be exposed to the outside in a laser cutting process.

[0117] In addition, the interlayer insulating film 135 and the planarization layer 175 may expose the sub-lines VL_S1 and VL_S2 of the second power supply voltage line VL2 and at least one slit pattern SP.

[0118] The sub-lines VL_S1 and VL_S2 corresponding to the second power supply voltage line VL2 in the cutting region CA and at least one slit pattern SP may be exposed to the outside in a laser cutting process.

[0119] The sub-lines VL_S1 and VL_S2 and the slit pattern SP are exposed in the laser cutting process so that failures and defects such as cracks due to lack of laser processing can be prevented.

[0120] In addition, the power supply voltage lines of the cutting region CA are formed to include sub-lines VL_S1 and VL_S2 each including at least one slit pattern SP, so that failures and defects such as cracks due to incomplete laser processing can be prevented during the laser cutting process.

[0121] In an embodiment of the inventive concept, although the first power supply voltage line VL1 and the second power supply voltage line VL2 are shown to be formed of a first metal layer in the cutting region CA, the present invention is not limited thereto, and the first power supply voltage line VL1 and the second power supply voltage line VL2 may be formed of another metal material having excellent resistivity characteristics used during the process of manufacturing a display unit.

[0122] Figure 7 and Figure 8 are schematic views for explaining laser cutting processes according to a comparative example and an embodiment of the inventive concept, respectively.

[0123] Figure 7 is a conceptual diagram of laser processing performed on a cutting region CA in which a metal line ML having a thick width W_C is provided according to the comparative example. Figure 8 is a conceptual diagram of laser processing performed on a plurality of metal sub-lines ML_S each including a plurality of slit patterns SP according to an embodiment of the inventive concept.

[0124] Referring to Figure 7 , when a metal line ML having a width greater than the pitch LP of a plurality of laser spots is provided in the cutting region CA according to the comparative example, during the laser cutting process, due to the metal line, the laser spots cannot penetrate to the substrate of the display unit and are reflected by the metal line, and thus defects such as cracks may occur in the display unit.

[0125] Referring to Figure 8 , when the cutting region CA according to an embodiment of the inventive concept includes at least one slit pattern SP having a width greater than or equal to the pitch LP of the laser spots and a metal sub-line ML_S having a width W_E greater than or equal to the pitch LP of the laser spots is provided, during the laser cutting process, the laser can easily penetrate to the substrate of the display unit through the slit pattern SP and prevent the laser from being reflected on the metal sub-line ML_S, so that defects such as cracks can be prevented.

[0126] Figure 9A and Figure 9B are conceptual diagrams for describing various voltage lines according to some embodiments of the inventive concept.

[0127] In an embodiment of the inventive concept, referring to Figure 9A, the power supply voltage line VL_E1 may be formed of the same metal layer as the metal layer in the cutout region CA and the adjacent regions TSA and PA1 (e.g., the conduction check region TSA and the first peripheral region PA1) adjacent to the cutout region CA.

[0128] The power supply voltage line VL_E1 includes a plurality of sub-lines in the cutout region CA, and a plurality of slit patterns are included between the sub-lines.

[0129] Due to the same resistivity characteristics, the power supply voltage line VL_E1 may have a first width W1 in the adjacent regions TSA and PA1, and may have a second width W2 in the cutout region CA that is larger than the first width W1 by the width of the slit.

[0130] In an embodiment of the inventive concept, referring to Figure 9B , the power supply voltage line VL_E2 may be formed of a metal layer different from the metal layer in the cutout region CA and the adjacent regions TSA and PA1 adjacent to the cutout region CA.

[0131] The power supply voltage line VL_E2 includes a plurality of sub-lines in the cutout region CA, and a plurality of slit patterns are included between the sub-lines.

[0132] The power supply voltage line VL_E2 may be formed of a metal layer having a relatively low resistivity characteristic in the adjacent regions TSA and PA1, and may be formed of a metal layer having a relatively high resistivity characteristic in the cutout region CA.

[0133] Therefore, the power supply voltage line VL_E2 may have a third width W3 in the adjacent regions TSA and PA1 based on the resistivity characteristic, and may have a fourth width W4 smaller than the third width W3 in the cutout region CA.

[0134] For example, when the resistivity of the power supply voltage line VL_E2 in the adjacent regions TSA and PA1 is substantially the same as the resistivity of the power supply voltage line VL_E1 described in Figure 9A , and the power supply voltage line VL_E2 has a relatively high resistivity characteristic in the cutout region CA, the number of sub-lines of the power supply voltage line VL_E2 may be smaller than the number of sub-lines of the power supply voltage line VL_E1 shown in Figure 9A .

[0135] As described above, the number and width of the metal sub-lines may be determined differently based on the resistivity of the metal sub-lines formed in the cutout region.

[0136] Figure 10 is a plan view of a display device according to an embodiment of the inventive concept.

[0137] Referring to Figure 10, the display device may include a display unit 100A and a flexible printed circuit board 300.

[0138] After the laser cutting process is completed for the display unit 100 shown in Figure 1 , the display unit 100A has a state in which the conduction check area TSA is cut off.

[0139] Similar to Figure 1 the display unit 100, the display unit 100A may include a display area DA and a first peripheral area PA1, a second peripheral area PA2, a third peripheral area PA3, and a fourth peripheral area PA4 surrounding the display area DA.

[0140] For the display unit 100A, the conduction check area TSA included in the display unit 100 in Figure 1 may be removed, and a part of the cut-off area CA may be removed.

[0141] Figure 1 A part of the cut-off area CA of

[0142] In Figure 1 the cut-off area CA, the first power supply voltage line VL1 and the second power supply voltage line VL2 include a plurality of sub-lines, and the plurality of sub-lines include at least one slit pattern. Accordingly, at least one of the first power supply voltage line VL1 and the second power supply voltage line VL2 may include a plurality of sub-lines VL_S1 and VL_S2 in the edge area EA of the display unit 100A.

[0143] The flexible printed circuit board 300 may be bonded to the signal pad unit SPD by using an anisotropic conductive film, and the signal pad unit SPD has a plurality of signal pads provided in the signal pad area SPA of the first peripheral area PA1. The flexible printed circuit board 300 may have a driving integrated circuit 310 mounted thereon for driving the display unit 100A.

[0144] After the laser cutting process, the display unit 100A may be attached to the flexible printed circuit board 300 through a module process.

[0145] In addition, at least one polarizing plate, a protective film, etc. may be attached to the display unit 100A through a module process.

[0146] According to some embodiments of the inventive concept as described above, the metal line is formed to include a plurality of sub-lines, and the plurality of sub-lines are separated from each other by at least one slit pattern in a cutting region of the display unit so that malfunctions and defects caused by laser processing of the metal line can be prevented. In addition, the organic insulating film and the inorganic insulating film located on or above at least one slit pattern and the sub-lines are removed in the cutting region to expose at least one slit pattern and the sub-lines so that malfunctions and defects caused by incomplete laser processing can be prevented.

[0147] The inventive concept can be applied to any electronic device including a display device. For example, the inventive concept can be applied to a smart phone, a tablet computer, a mobile phone, a personal computer (PC), a household appliance, a laptop computer, and the like.

[0148] Although the inventive concept has been shown and described with reference to some embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the inventive concept set forth by the present disclosure.

Claims

1. A display device, wherein, The display device includes: A display unit, including: signal lines electrically connected to pixels disposed in a display area; a signal pad unit provided in a peripheral area adjacent to the display area and including signal pads electrically connected to the signal lines; an inspection pad unit including inspection pads electrically connected to the signal pads; and power voltage lines provided in the peripheral area, the power voltage lines being electrically connected to the inspection pads, and the power voltage lines being configured to apply a power voltage to the pixels and being divided into a plurality of sub-lines by at least one slit pattern in an edge area; and A flexible printed circuit board bonded to the signal pad unit through an anisotropic conductive film, wherein a driving integrated circuit configured to drive the display unit is mounted above the flexible printed circuit board.

2. The display device according to claim 1, wherein, The display unit further includes an insulating film that exposes the plurality of sub-lines provided in the edge area.

3. The display device according to claim 2, wherein, The insulating film includes: An inorganic insulating film provided above a gate electrode of a transistor included in the pixel; and An organic insulating film provided above a source electrode and a drain electrode of the transistor.

4. The display device according to claim 1, wherein, The pixel includes an organic light-emitting diode, and wherein the power voltage line includes at least one of a first power voltage line and a second power voltage line, the first power voltage line being configured to transmit a first power voltage to the organic light-emitting diode, and the second power voltage line being configured to transmit a second power voltage to the organic light-emitting diode.

5. The display device according to claim 4, wherein, The peripheral area includes: a first peripheral area in which the signal pad unit is provided, a second peripheral area adjacent to the first peripheral area, a third peripheral area facing the second peripheral area, and a fourth peripheral area facing the first peripheral area, wherein the first peripheral area to the fourth peripheral area surround the display area, and wherein the first power voltage line extends from the edge area and is provided in the first peripheral area.

6. The display device according to claim 5, wherein, The second power voltage line extends from the edge area and is provided in the second peripheral area, the third peripheral area, and the fourth peripheral area.

7. A display unit, wherein, The display unit includes: Signal lines electrically connected to pixels disposed in a display area; A signal pad unit provided in a peripheral area adjacent to the display area and including signal pads electrically connected to the signal lines; An inspection pad unit provided in a conduction inspection area and including inspection pads electrically connected to the signal pads, wherein the inspection pads are configured to receive a conduction inspection signal; and Power voltage lines electrically connected to the inspection pads and configured to apply a power voltage to the pixels, the power voltage lines extending from the inspection pad unit to the peripheral area, and the power voltage lines being divided into a plurality of sub-lines by at least one slit pattern in a cutout area between the peripheral area and the conduction inspection area.

8. The display unit according to claim 7, wherein, The display unit further includes: An insulating film that exposes the at least one slit pattern and the plurality of sub-lines located in the cutout area.

9. The display unit according to claim 8, wherein, The insulating film includes: An inorganic insulating film provided above a gate electrode of a transistor included in the pixel; and An organic insulating film is provided over a source electrode and a drain electrode of the transistor.

10. A method of manufacturing a display unit, wherein, The method includes: forming a signal line electrically connected to a pixel disposed in a display area; forming a signal pad disposed in a peripheral area adjacent to the display area and electrically connected to the signal line; forming an inspection pad disposed in a conduction inspection area and electrically connected to the signal pad such that a conduction inspection signal is applied to the inspection pad; and forming a power supply voltage line electrically connected to the inspection pad, the power supply voltage line extending from the inspection pad to the peripheral area and being divided into a plurality of sub-lines by at least one slit pattern in a cut-out area between the peripheral area and the conduction inspection area.

Images