Clock generator and method for generating clock signal

Abstract

The clock generator includes an oscillator that generates a clock signal as its output. The frequency of the clock signal depends on the bias current. A feedback circuit receives the clock signal and generates a feedback signal indicating the frequency of the clock signal. A voltage detector uses the feedback signal to generate a charging voltage, compares the charging voltage with the source voltage, and generates a detection signal indicating the comparison between the two. A control voltage generator uses the detection signal to generate a control voltage. The bias current is generated by a bias current source using the control voltage.

Description

Technical Field

[0001] The present invention relates to a clock signal generator, and more particularly to a reference-free clock signal generator. Background Art

[0002] Most portable devices require an independent clock generator that provides a clock signal with the required frequency. However, temperature, voltage levels, and other factors may affect the accuracy of the clock signal.

[0003] Therefore, it is necessary to generate a clock signal with less frequency drift and lower power consumption. Summary of the Invention

[0004] This summary is provided to introduce a selected, simplified version of the concepts detailed below in the Detailed Description. This summary is not intended to identify key or essential features of the claims, nor is it intended to limit the scope of the claims.

[0005] According to one embodiment, a clock generator for generating a clock signal is provided, comprising:

[0006] an oscillator that generates a clock signal;

[0007] a feedback circuit connected to the oscillator to receive the clock signal, the feedback circuit generating a feedback signal indicative of a frequency of the clock signal;

[0008] a voltage detector connected to the feedback circuit to receive the feedback signal, wherein the voltage detector compares the source voltage with a charging voltage generated using the feedback signal to generate a detection signal indicative of a comparison between the source voltage and the charging voltage;

[0009] a control voltage generator connected to the voltage detector to receive the detection signal, the control voltage generator generating a control voltage using the detection signal;

[0010] A bias current source is connected to the control voltage generator to receive the control voltage. The bias current source generates a bias current using the control voltage. The frequency of the clock signal generated by the oscillator is determined by the bias current.

[0011] Illustratively, the voltage detector includes a charging capacitor providing a charging voltage, and the charging capacitor is charged in response to the feedback signal.

[0012] Illustratively, the voltage detector is connected to the bias current source in response to the feedback signal.

[0013] Illustratively, in response to the voltage detector being connected to the bias current source, the charging capacitor receives a charging current from the bias current source, and the charging current is a mirror image of the bias current.

[0014] Example:

[0015] The voltage detector includes a comparator receiving a source voltage at a first input terminal and a charging voltage at a second input terminal;

[0016] The feedback circuit generates a latch signal in response to the clock signal, and provides the latch signal to a latch terminal of the comparator; and

[0017] The comparator provides a detection signal indicative of a comparison between the source voltage and the charge voltage in response to the latch signal.

[0018] Illustratively, the control voltage generator is connected to the voltage detector to provide the control voltage to the voltage detector, and the voltage detector generates the source voltage using the control voltage.

[0019] Illustratively, the voltage detector includes an NMOS transistor having a gate receiving a control voltage, a drain receiving an input current, and a source providing a source voltage; the source is grounded via a resistor, and a bias current is a mirror image of the input current.

[0020] Illustratively, the bias current source includes a PMOS transistor having a source connected to a supply voltage, a drain and a gate connected to each other; the drain of the PMOS transistor is connected to the drain of the NMOS transistor of the voltage detector to provide the input current.

[0021] Illustratively, the feedback circuit is a frequency divider configured to divide the frequency of the clock signal to generate the feedback signal.

[0022] Illustratively, the control voltage generator increases the control voltage in response to the detection signal indicating that the source voltage is lower than the charge voltage, and decreases the control voltage in response to the detection signal indicating that the source voltage is higher than the charge voltage.

[0023] For example, the control voltage generator includes a control capacitor having a first plate connected to ground and a second plate for providing a control voltage. The control capacitor is charged to increase the control voltage in response to a detection signal indicating that the source voltage is lower than the charging voltage, and is discharged to reduce the control voltage in response to the detection signal indicating that the source voltage is higher than the charging voltage.

[0024] Illustratively, the control voltage generator further includes an upper capacitor and a lower capacitor respectively connected to the second plate of the control capacitor, the upper capacitor being configured to charge the control capacitor in response to the detection signal indicating that the source voltage is lower than the charging voltage, and the lower capacitor being configured to discharge the control capacitor in response to the detection signal indicating that the source voltage is higher than the charging voltage.

[0025] According to another embodiment, a method for generating a clock signal includes:

[0026] The bias current source uses a control voltage to generate a bias current;

[0027] The oscillator uses a bias current to generate a clock signal;

[0028] The feedback circuit generates a feedback signal using the clock signal, the feedback signal indicating the frequency of the clock signal;

[0029] The voltage detector compares the charging voltage generated using the feedback signal with the source voltage generated using the control voltage;

[0030] a voltage detector generating a detection signal in response to a comparison between the charging voltage and the source voltage; and

[0031] The control voltage generator generates a control voltage using the detection signal.

[0032] Illustratively, generating the bias current includes:

[0033] The NMOS transistor receives a control voltage at its gate;

[0034] The first PMOS transistor receives a supply voltage at its source;

[0035] connecting the drain of the first PMOS transistor to the drain of the NMOS transistor to provide an input current;

[0036] Using the second PMOS transistor as a mirror image of the first PMOS transistor; and

[0037] The second PMOS transistor generates a bias current.

[0038] Illustratively, comparing the charge voltage to the source voltage includes:

[0039] In response to the feedback signal, providing a charging current to the charging capacitor to charge the charging capacitor;

[0040] The charging capacitor generates a charging voltage;

[0041] The NMOS transistor receives a control voltage at its gate and an input current at its drain, wherein the bias current is a mirror image of the input current;

[0042] providing a source voltage at a source of the NMOS transistor; and

[0043] A comparator compares the charge voltage to the source voltage.

[0044] Illustratively, generating the control voltage includes:

[0045] The control voltage is increased in response to the source voltage being lower than the charge voltage by:

[0046] connecting the control capacitor to the upper capacitor to charge the control capacitor; and

[0047] A control capacitor provides the control voltage; or

[0048] The control voltage is reduced in response to the source voltage being higher than the charge voltage by:

[0049] connecting the control capacitor to the lower capacitor to discharge the control capacitor; and

[0050] The control capacitor provides the control voltage.

[0051] According to another embodiment, there is provided a clock generator comprising:

[0052] a control voltage generator for generating a control voltage;

[0053] a bias current source connected to the control voltage generator, the bias current source generating a bias current using the control voltage;

[0054] an oscillator connected to a bias current source, the oscillator using the bias current to generate a clock signal;

[0055] a feedback circuit coupled to the oscillator, the feedback circuit using the clock signal to generate a feedback signal indicative of a frequency of the clock signal; and

[0056] a voltage detector connected to the feedback circuit and the control voltage generator, the voltage detector generating a detection signal indicating a comparison between a charging voltage generated using the feedback signal and a source voltage generated using the control voltage;

[0057] The control voltage generator uses the detection signal to change the control voltage.

[0058] Illustratively, the clock generator further includes a control transistor having a gate connected to the control voltage generator to receive the control voltage, a drain connected to receive the input current, and a source connected to the voltage detector to provide the source voltage.

[0059] Example:

[0060] The bias current source includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor connected as a diode, wherein the first PMOS transistor has a source connected to a supply voltage and a drain providing an input voltage; the second PMOS transistor is a mirror image of the first PMOS transistor to provide a bias current; and the third PMOS transistor is a mirror image of the first PMOS transistor to provide a charging current.

[0061] The voltage detector includes a charging capacitor providing a charging voltage, and the charging capacitor is connected to the third PMOS transistor to be charged with a charging current in response to a feedback signal.

[0062] Illustratively, the control voltage generator includes a control capacitor providing the control voltage, and the control capacitor is connected to the upper capacitor to be charged or connected to the lower capacitor to be discharged depending on the detection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to make the foregoing of the present invention understood in a more specific manner, a further detailed description of the present invention can be obtained with reference to the embodiments, some of which are shown by the accompanying illustrations. The accompanying illustrations only show typical embodiments of the present invention, and because the present invention can have other equally effective embodiments, the accompanying illustrations should not be understood as limiting the scope of the present invention. The accompanying drawings are drawn to facilitate understanding rather than to measure the present invention. For those skilled in the art, the benefits of the claimed subject matter will be readily understood after reading this description and combining the accompanying illustrations. In the accompanying drawings, similar reference numerals are used to indicate similar elements, and:

[0064] Figure 1 is a block diagram of a clock generator according to an exemplary embodiment of the present invention;

[0065] Figure 2 yes Figure 1 A circuit diagram of a clock generator; and

[0066] Figure 3 yes Figure 1 Timing diagram of the clock generator signals. DETAILED DESCRIPTION

[0067] Figure 1 1 is a block diagram of a clock generator 100 according to an exemplary embodiment of the present invention. Clock generator 100 includes a voltage-controlled oscillator (VCO) 102, a bias current source 104, a control voltage generator 106, a feedback circuit 108, and a voltage detector 110. VCO 102 generates a clock signal as an output of clock generator 100. VCO 102 operates using a bias current provided by bias current source 104, and the frequency of the generated clock signal is adjusted using the bias current. In this embodiment, VCO 102 includes a ring oscillator having a plurality of delay gates connected in series. The delay gates receive a bias current from bias current source 104 and adjust a delay time based on the bias current, thereby adjusting the frequency of the generated clock signal.

[0068] Feedback circuit 108 is connected to VCO 102 to receive a clock signal. Feedback circuit 108 uses the clock signal to generate a feedback signal, which is representative of the frequency of the clock signal. Feedback circuit 108 is connected to voltage detector 110 to provide the feedback signal to voltage detector 110. In this embodiment, feedback circuit 108 includes a frequency divider. The frequency divider generates a feedback signal whose frequency is a fraction of the frequency of the clock signal from VCO 102. Thus, the frequency divider of feedback circuit 108 divides the frequency of the clock signal to generate a feedback signal whose frequency is representative of, but lower than, the frequency of the clock signal.

[0069] The voltage detector 110 compares the charge voltage with the source voltage and generates a detection signal representing the comparison result. Specifically, the voltage detector 110 is connected to the feedback circuit 108 to receive the feedback signal. The charge voltage is generated using the feedback signal. The source voltage is generated using the control voltage from the control voltage generator 106. To generate the source voltage, the voltage detector is also connected to the control voltage generator 106 to receive the control voltage.

[0070] As previously described, the control voltage generator 106 generates a control voltage. Furthermore, the control voltage generator 106 is connected to the voltage detector 110 to receive a detection signal. The control voltage generator 106 uses the detection signal to adjust the control voltage. The generated control voltage is provided to the bias current source 104 to generate a bias current.

[0071] Voltage detector 110 compares a charge voltage, which indicates the frequency of the clock signal, with a source voltage, which indicates the control voltage used to generate the clock signal. A detection signal from voltage detector 110 reflects the difference between the charge voltage and the source voltage and is used to adjust the control voltage. If the frequency of the clock signal drifts due to factors such as temperature, the detection signal will indicate the frequency drift. Using the detection signal, the control voltage is adjusted, thereby changing the bias current used to generate the clock signal to maintain a stable frequency of the clock signal (i.e., prevent the frequency of the clock signal from drifting).

[0072] Now go to Figure 2 , which shows Figure 1 A circuit diagram of an embodiment of a clock generator.

[0073] VCO 102 includes a ring oscillator 202. Ring oscillator 202 includes a plurality of delay gates connected in series, each receiving a bias current IVCO from bias current source 104. Although three delay gates are shown, it will be appreciated that oscillator 202 may include more than three delay gates. Ring oscillator 202 generates a clock signal. In the illustrated embodiment, VCO 102 further includes a level shifter 204 connected to the output of ring oscillator 202. Level shifter 204 performs a level shift on the clock signal, typically level-shifting it upward, and provides the level-shifted clock signal, clock_out, as the output of clock generator 100.

[0074] The voltage detector 110 includes a charging capacitor C chrg , a first switch S1, and a second switch S2. Charging capacitor C chrg The first plate is connected to the ground and the second plate is connected to the first switch S1. The second switch S2 is connected to the charging capacitor C chrg Between the second plate and ground. Charging capacitor C chrg Provide a charging voltage V on the second plate chrg The first switch S1 is controlled by the feedback signal from the feedback circuit 108 and operates to charge the capacitor C chrg When the first switch S1 is closed in response to the feedback signal, the charging capacitor C chrg Connected to bias current source 104 to receive charging current I chrg , which charges the capacitor C chrg On the other hand, when the first switch S1 is open and the second switch S2 is closed, the charging capacitor C chrg grounded and discharged. Then, the charging capacitor C chrg Provided charging voltage V chrg to ground level.

[0075] The voltage detector 110 includes a comparator 206. The comparator 206 has a first input terminal (non-inverting input terminal) and a second input terminal (inverting input terminal). The first input terminal of the comparator 206 receives the source voltage V res , the second input terminal is connected to the charging capacitor C chrg The second plate receives the charging voltage V chrgIn the illustrated embodiment, comparator 206 is a latching comparator that further receives a latch signal from feedback circuit 108 at a latch terminal. In response to the latch signal, comparator 206 provides a detection signal as the output of voltage detector 110. In this embodiment, feedback circuit 108 generates a latch signal based on clock signal clock_out to ensure that comparator 206 generates the detection signal based on a comparison between a charge voltage corresponding to the current frequency of clock signal clock_out and a source voltage used to generate a clock signal having the current frequency.

[0076] Source voltage V res The voltage is generated by a source voltage generator 208 connected to the first input terminal of the comparator 206. Various embodiments of the voltage detector 110 may include the source voltage generator 208, while other embodiments may not include the source voltage generator 208. In the embodiment shown, the source voltage generator 208 includes an NMOS transistor 210 and a resistor 212. The NMOS transistor 210 has the following features: connected to the control voltage generator 106 to receive the control voltage V ctrl The gate terminal is connected to the bias current source 104 to receive the input current I input The drain terminal of the comparator 206 is connected to the first input terminal of the comparator 206 to provide a source voltage V res The resistor 212 is connected between the source terminal of the NMOS transistor 210 and the ground. The NMOS transistor 210 responds to the control voltage V ctrl And conduction or judgment, and provide source voltage V accordingly res . Source voltage V res Determined by the following formula: V res =V ctrl -V thn , where V thn is the threshold voltage of the NMOS transistor 210 .

[0077] The control voltage generator 106 includes an upper capacitor C up and the lower capacitor C dn . Upper capacitor C up After setting the switch S set_1 And connected to the supply voltage V dd , lower capacitor C dn After setting the switch S set_2 And connected to ground. Set switch S set_1 and set the switch S set_1 The setting signal is received by the feedback circuit 108. The switch S is set set_1 and set the switch S set_2 Closed and opened in response to the set signal to respectively connect the capacitor C up Charging and lower capacitor Cdn Discharge. Upper capacitor C up and the lower capacitor C dn Both are connected to the control capacitor C ctrl Specifically, the control capacitor C ctrl It has: a first plate connected to the ground, and a control voltage C ctrl The second plate of the capacitor C up After the upper control switch S up And connected to the control capacitor C ctrl The second plate of the lower capacitor C dn Through the lower control switch S down And connected to the control capacitor C ctrl The second plate.

[0078] In operation, if the detection signal generated by the comparator 206 indicates that the source voltage V res Higher than the charging voltage V chrg , then the lower control switch S down Close to lower capacitor C dn and control capacitor C ctrl connected, which will control the capacitor C ctrl discharge, thereby making the control capacitor C ctrl Provides control voltage V ctrl On the other hand, if the detection signal indicates that the source voltage V res Lower than the charging voltage V chrg , then the upper control switch S up Close to put the upper capacitor C up and control capacitor C ctrl connected, which controls the capacitance C ctrl charging, so that the control voltage V ctrl In this embodiment, the detection signal provided by the comparator 206 is a differential signal. The differential signal is provided to the upper control switch S up and down control switch S down .

[0079] The bias current source 104 includes first to third PMOS transistors 214, 216, and 218, which are connected as a current mirror. The sources of the first, second, and third PMOS transistors 214, 216, and 218 are connected to the supply voltage V dd The gate and source of the first PMOS transistor 214 are connected together, so that the first PMOS transistor 214 acts as a diode. The drain of the first PMOS transistor 214 provides an input current I to the control transistor 210. input The gates of the first to third PMOS transistors 214, 216, and 218 are connected together. The drain of the second PMOS transistor 216 is connected to the charging capacitor C chrgProvide charging current I chrg The drain of the third PMOS transistor 218 provides a bias current I VCO It is understandable that the bias current I VCO and charging current I chrg is the input current I input Mirror image.

[0080] Figure 1 、 Figure 2 The operation of the clock generator 100 shown will be combined with Figure 3 Explain, Figure 3 is the timing of each signal in the clock generator 100. Figure 3 The signals shown in are:

[0081] “clock_out”: clock signal generated by VCO 102;

[0082] “chrg”: a feedback signal generated by the feedback circuit 108 and used to control the first switch S1 of the voltage detector 110;

[0083] “V chrg ”: charging capacitor C chrg a charging voltage provided to the second input terminal of the comparator 206;

[0084] “latch”: a latch signal provided by the feedback circuit 108 to the latch terminal of the comparator 206;

[0085] “up”: comparator 206 provides the upper control switch S up Detection signal;

[0086] “down”: comparator 206 provides the down control switch S down Detection signal;

[0087] “V ctrl ”: control voltage generated by the control voltage generator 106; and

[0088] “set”: Feedback circuit 108 provides the upper set switch S set_1 and set the switch S set_2 The setting signal.

[0089] By time t 31Initially, the VCO 102 generates a clock signal "clock_out" having a specified frequency. The feedback circuit 108 receives the clock signal "clock_out" and provides a feedback signal "chrg" to the first switch S1. In the embodiment shown, the frequency of the feedback signal "chrg" applied to the first switch S1 is half the frequency of the clock signal "clock_out". When the feedback signal "chrg" is high, the first switch S1 is closed. This causes the charging current I chrg is supplied to the charging capacitor C chrg , to charge the capacitor C chrg Therefore, during the period when the feedback signal "chrg" remains high, the charging voltage "V chrg " rises. The set signal "set" provided by the feedback circuit 108 is high to set the upper switch S set_1 and set the switch S set_2 Closed. The closed switch makes the upper capacitor C up is charged, and the lower capacitor C dn Discharged.

[0090] At time t32, the feedback signal "chrg" turns from high to low, and the charging voltage "V chrg " is maintained at its charged level. The charging voltage "V chrg ” is provided to the inverting input terminal of the comparator 206. At the non-inverting input terminal of the comparator 206, a source voltage V used to generate the clock signal “clock_out” is received. res . Then at time t 33 , the latch signal “latch” provided by the feedback circuit 108 to the latch terminal of the comparator 206 jumps to a high level, so that the comparator 206 outputs a voltage based on the source voltage V res and charging voltage "V chrg "The comparison between the detection signals.

[0091] At the time t when the latch signal “latch” turns high 33 , source voltage V res Lower than the charging voltage "V chrg ”, so that the comparator 206 provides the upper control switch S up On the other hand, at time t 33 , provided to set the switch S set_1 and set the switch S set_2 The setting signal "set" jumps to low level. The high detection signal "up" will control the switch S up closed to allow the supplied voltage V dd Charged upper capacitor C up For control capacitor Cctrl Charge. Thus, the control capacitor C ctrl The control voltage "V ctrl "rise.

[0092] It is understood that if the frequency of the generated clock signal "clock_out" decreases, then the time per cycle of the clock signal increases based on the equation t=1 / f, where t is the cycle time of the clock signal and f is the frequency. The feedback signal "chrg" will have more time to close the first switch S1 of the voltage detector 110 and charge the capacitor C. chrg Charging. Charging capacitor C chrg Charging current I chrg The longer the charging time, the higher the charging voltage V chrg In this example, the frequency of the clock signal "clock_out" needs to be increased, and it is necessary to use the detection signal to increase the control voltage V ctrl , thereby increasing the bias current I VCO .

[0093] Then, the increased control voltage V ctrl The input current I input Increases, mirroring the input current I input The bias current I VCO increases, causing the frequency of the clock signal "clock_out" to increase. 33 , the feedback signal "dis_chrg" provided to the second switch S2 jumps to a high level, so that the charging capacitor C chrg discharge, thereby charging voltage V chrg to ground level.

[0094] At time t 34 , that is, the end of the high bit of the latch signal "latch" and the beginning of the high bit of the feedback signal "chrg", the charging capacitor C chrg Another round of charging begins to generate a charging voltage V that represents the frequency of the latest clock signal "clock_out" chrg .

[0095] During the subsequent time t when the latch signal “latch” is high 35 , source voltage V res Higher than the charging voltage "V chrg ", which means that the charging capacitor C chrg The charging time is shorter than expected, and the frequency of the clock signal "clock_out" is higher. ctrl " and bias current I VCO Pull down to reduce the frequency of the clock signal.35 , provided to the lower control switch S down The detection signal "down" turns to high. down Close to control the capacitor C ctrl and the lower capacitor C dn Connect the control capacitor C ctrl Charge and reduce the control voltage V ctrl Since the bias current I VCO decreases, the frequency of the generated clock signal “clock_out” decreases.

[0096] Control voltage V ctrl The amount of increase or decrease depends on the control capacitor C ctrl and upper capacitor C up Or lower capacitor C dn The ratio between the capacitance values ​​is shown as:

[0097] or

[0098] It is understood that the frequency of the clock signal "clock_out" can be adjusted by configuring the capacitor C up , lower capacitor C dn , and control capacitor C ctrl to adjust.

[0099] The clock generator described herein forms a regulation loop by generating a charging voltage signal representing the frequency of a generated clock signal, comparing the charging voltage signal with a control voltage signal generated based on the clock signal, and using a detection signal generated by the comparison to adjust the control voltage signal to further adjust the bias current provided to the oscillator. This allows the frequency of the clock signal to be maintained at a relatively stable level despite temperature, aging, and other environmental factors.

[0100] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art in forming a clear understanding of and implementing the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this description that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0101] It should be understood that with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and that other positional relationships may be substituted when the orientation of the device changes during manufacturing or operation. As described above, those positional relationships are described only for the sake of clarity and are not limiting.

[0102] While the foregoing description of this specification refers to specific embodiments and specific figures, the invention is not limited thereto, as defined by the appended claims. The figures described are intended to be illustrative and non-limiting. In the figures, the dimensions of elements may be exaggerated for illustrative purposes and may not be drawn to scale. This description also encompasses discrete variations in tolerances and properties of elements and operating modes. It also encompasses various variations of the invention.

[0103] The word "comprising" as used in this description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form "a" or "an" is used to refer to a definite or indefinite element, the plural number of the element shall be included. Thus, the word "comprising" should not be understood as being limited to the items listed thereafter, nor should it be understood as excluding other elements or steps; the scope of the description "a device comprising items A and B" should not be limited to a device comprising only elements A and B. This description indicates that, for the purposes of this description, only elements A and B of the device are relevant. "Connected", "coupled", and "coupled" all indicate that there is an electrical connection between the coupled or connected elements, and do not mean that there are no intermediate elements between them. When describing transistors and their connections, the words gate, drain, and source are interchangeable with gate, drain, source, and gate terminal, drain terminal, and source terminal.

[0104] It will be apparent to those skilled in the art that various detailed changes can be made without departing from the scope of the claims of the present invention.

Claims

1. A clock generator for generating a clock signal, characterized in that: include: an oscillator that generates a clock signal; a feedback circuit connected to the oscillator to receive the clock signal, the feedback circuit generating a feedback signal indicative of a frequency of the clock signal; a voltage detector connected to the feedback circuit to receive the feedback signal, wherein the voltage detector compares the source voltage with a charging voltage generated using the feedback signal to generate a detection signal indicative of a comparison between the source voltage and the charging voltage; a control voltage generator connected to the voltage detector to receive the detection signal, the control voltage generator generating a control voltage using the detection signal; a bias current source connected to the control voltage generator to receive the control voltage, the bias current source generating a bias current using the control voltage, the frequency of the clock signal generated by the oscillator being determined by the bias current; The voltage detector includes a charging capacitor providing a charging voltage, and the charging capacitor is charged in response to the feedback signal.

2. The clock generator according to claim 1, wherein: The voltage detector includes a comparator receiving a source voltage at a first input terminal and a charging voltage at a second input terminal; The feedback circuit generates a latch signal in response to the clock signal and provides the latch signal to a latch terminal of the comparator; as well as The comparator provides a detection signal indicative of a comparison between the source voltage and the charge voltage in response to the latch signal.

3. The clock generator according to claim 1, wherein: The control voltage generator includes a control capacitor having a first plate connected to ground and a second plate for providing a control voltage. The control capacitor is charged to increase the control voltage in response to a detection signal indicating that the source voltage is lower than the charging voltage, and is discharged to reduce the control voltage in response to a detection signal indicating that the source voltage is higher than the charging voltage.

4. A method for generating a clock signal, characterized in that: include: generating a bias current using a control voltage; generating a clock signal using a bias current; generating a feedback signal using the clock signal, the feedback signal indicating a frequency of the clock signal; comparing a charging voltage generated using the feedback signal with a source voltage generated using the control voltage; generating a detection signal indicative of a comparison between the charging voltage and the source voltage; as well as generating a control voltage using the detection signal; Generating bias current includes: receiving a supply voltage at a source of the first PMOS transistor and a source of the second PMOS transistor; connecting the gate of the first PMOS transistor and the gate of the second PMOS transistor together; providing an input current at a drain of the first PMOS transistor for generating a source voltage using a control voltage; Using the second PMOS transistor as a mirror image of the first PMOS transistor; and A bias current is generated at the drain of the second PMOS transistor.

5. The method according to claim 4, characterized in that Generating a source voltage using a control voltage involves: receiving a control voltage at the gate of the NMOS transistor; connecting a drain of the first PMOS transistor to a drain of the NMOS transistor to provide an input current, wherein the bias current is a mirror image of the input current; and A source voltage is provided at the source of the NMOS transistor.

6. The method according to claim 4, characterized in that Comparing the charge voltage to the source voltage involves: receiving a supply voltage at a source of the third PMOS transistor; connecting the gate of the third PMOS transistor and the gate of the first PMOS transistor together; providing a charging current at a drain of the third PMOS transistor; In response to the feedback signal, providing a charging current to the charging capacitor to charge the charging capacitor; The charging capacitor generates a charging voltage; and The charge voltage is compared to the source voltage.

7. A clock generator, characterized in that: include: a control voltage generator for generating a control voltage; a bias current source connected to the control voltage generator, the bias current source generating a bias current using the control voltage; an oscillator connected to a bias current source, the oscillator using the bias current to generate a clock signal; a feedback circuit coupled to the oscillator, the feedback circuit using the clock signal to generate a feedback signal indicative of a frequency of the clock signal; a voltage detector connected to the feedback circuit and the control voltage generator, the voltage detector generating a detection signal indicating a comparison between a charging voltage generated using the feedback signal and a source voltage generated using the control voltage; as well as a control transistor having a gate connected to the control voltage generator to receive a control voltage, a drain connected to receive an input current, and a source connected to the voltage detector to provide a source voltage; The control voltage generator uses the detection signal to change the control voltage.

8. The clock generator according to claim 7, wherein: The bias current source includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor connected as a diode, the first PMOS transistor having: a source connected to a supply voltage, and a drain providing an input voltage; The second PMOS transistor is a mirror image of the first PMOS transistor to provide a bias current; the third PMOS transistor is a mirror image of the first PMOS transistor to provide a charging current; as well as The voltage detector includes a charging capacitor providing a charging voltage, and the charging capacitor is connected to the third PMOS transistor to be charged with a charging current in response to a feedback signal.

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