Chip reset via communication interface terminal

Abstract

The present disclosure generally relates to chip reset via communication interface terminals. In one embodiment, an integrated circuit includes: a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal, and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the communication interface is not selected.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods, and more particularly, embodiments relate to chip reset via a communication interface terminal. Background Art

[0002] Generally, a circuit, such as a system on chip (SoC) or an application specific integrated circuit (ASIC), has a power supply voltage range within which the circuit operates normally. If the system starts operating when the power supply voltage is below the operating voltage range, the system may malfunction. For example, a power management integrated circuit (PMIC) may have an operating power supply voltage ranging from 3V to 5.5V. Starting the operation of such a PMIC at a voltage of, for example, 2V may cause such a PMIC to start in an unknown state.

[0003] Circuits generally use reset signals to bring the system to a defined state during startup. For example, Figure 1 The integrated circuit (IC) 102 is shown receiving a reset signal after startup to place the IC 102 in a known state. Figure 1 As shown in the figure, when the power supply voltage V DD When the RC circuit 106 increases, it is used to maintain the reset voltage V RST is low. When the voltage V RST When the reset voltage V RST When the reset voltage V RST When the supply voltage V DD within the operating supply voltage range of IC 102.

[0004] Some ICs do not use a dedicated reset terminal (e.g., a pin or pad), but instead include a power-on reset (POR) to detect that power has been applied to the IC. After detecting that power has been applied, the POR circuit internally generates a reset signal to place the IC in a known state. Summary of the invention

[0005] According to one embodiment, an integrated circuit includes: a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has: a first input coupled to a first terminal of the plurality of terminals and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal, and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the communication interface is not selected.

[0006] According to one embodiment, an integrated circuit includes: a serial peripheral interface (SPI) interface configured to be coupled to an SPI communication bus and an input circuit. The SPI interface has: an SPI clock terminal, a chip select terminal, and a plurality of data terminals. The input circuit has a first input coupled to the SPI clock terminal of the plurality of data terminals and a second input coupled to a data segment of a plurality of data terminals among the plurality of data terminals. The first input of the input circuit is configured to receive a first signal, and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the SPI interface is not activated.

[0007] According to one embodiment, a method for resetting an integrated circuit includes: receiving a first signal via a first terminal of the integrated circuit, the first terminal being coupled between a communication bus and a communication interface; receiving a second signal via a second terminal of the integrated circuit, the second terminal being coupled between the communication bus and the communication interface; causing a reset signal to be in a first state of the reset signal when the first signal is in a first state of the first signal; causing the reset signal to be in a first state of the reset signal when the second signal is in a first state of the second signal; causing the reset signal to be in a second state of the reset signal when the first signal is in a second state of the first signal for at least a first duration and the second signal is in a second state of the second signal, causing the reset signal to be in a second state of the reset signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal; and resetting the integrated circuit to a known state when the reset signal is in a third state. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An IC is shown which receives a reset signal after startup to place the IC in a known state;

[0010] Figure 2 A schematic diagram of an IC with chip reset by reusing terminals of a serial peripheral interface (SPI) interface according to an embodiment of the present invention is shown;

[0011] Figure 3 A waveform diagram is shown according to an embodiment, which illustrates Figure 2 SPI signal of the SPI terminal of the IC;

[0012] Figure 4 A schematic diagram of an input circuit according to an embodiment of the present invention is shown, the input circuit being used to generate an internal reset signal based on an SPI terminal;

[0013] Figure 5 A schematic diagram of an IC with chip reset by reusing the terminals of a quad SPI interface according to an embodiment of the present invention is shown;

[0014] Figure 6 The embodiment of the present invention is shown Figure 5 A schematic diagram of a system of ICs having at least one more IC coupled to an SPI communication bus of the SPI;

[0015] Figure 7 A schematic diagram showing an IC with chip reset by reusing a terminal of a serial wire debug (SWD) interface according to an embodiment of the present invention; and

[0016] Figure 8 A flow chart of a method according to an embodiment of the present invention is shown, the method being used to reset an integrated circuit.

[0017] Unless expressly indicated otherwise, corresponding reference numerals and symbols in the different figures refer to corresponding parts.The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0018] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative ways to make and use the present invention, and the specific embodiments discussed do not limit the scope of the present invention.

[0019] The following description explains various specific details to provide a deep understanding of several example embodiments according to the present description. The embodiments can be obtained without one or more specific details, or the embodiments can be obtained by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid confusing different aspects of the embodiments. Reference to "an embodiment" in this description indicates that a specific configuration, structure, or feature described according to the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that appear at different points described herein do not necessarily refer to the same embodiment. In addition, specific configurations, structures, or features can be combined in any appropriate manner in one or more embodiments.

[0020] Embodiments of the present invention will be described in a specific context, such as chip reset using SPI terminals or SWD terminals. For example, embodiments of the present invention can be used with other communication protocols such as Joint Test Action Group (JTAG) or other serial or parallel communication protocols.

[0021] In one embodiment of the present invention, the IC can be reset to a known state via the SPI terminal. By reusing the SPI terminal to reset the IC, the use of an internal POR circuit and a dedicated reset terminal can be advantageously avoided. By avoiding the use of an internal POR circuit, some embodiments can advantageously reduce die area, which can result in a reduced cost per die. By avoiding the use of a dedicated reset terminal, (e.g., because of a lower pin count) some embodiments can advantageously reduce package size, which can result in lower packaging costs.

[0022] Figure 2 FIG. 2 is a schematic diagram of an IC 202 having a chip reset by reusing terminals of a communication interface such as an SPI interface according to an embodiment of the present invention. Figure 2 As shown in FIG. 4 , IC 202 includes: an SPI slave 208 and an input circuit 400, wherein the SPI slave 208 forms a communication interface of IC 202. The SPI slave 208 includes: a chip select terminal CS_N, which is configured to receive a signal V CS_N , through which the SPI slave 208 is selected and deselected; Master Out Slave In (MOSI) terminal, MOSI is configured to receive the signal V MOSI , data is received by the SPI slave 208 via the MOSI terminal; the master input slave output (MISO) terminal, MISO is configured to generate a signal V MISO , via which MISO data is sent by the SPI slave 208; and a clock terminal SCLK, which is configured to receive a signal V SCLK , the signal V SCLK is used as a clock signal for the SPI bus 206. The input circuit 400 is configured to receive a first signal and a second signal, which may correspond to the signal V CS_N and V MOSI As in Figure 2 As shown in FIG. 2 , IC 202 includes terminals SCLK, MISO, MOSI, and CS_N, corresponding to terminals SCLK, MISO, MOSI, and CS_N of SPI slave 208 .

[0023] During normal operation, the SPI master 204 may initiate communication with the IC 202 via the SPI bus 206, and the IC 202 may communicate with the SPI master 204 using the SPI slave 208 via the SPI bus 206. For example, the SPI master 204 may assert (i.e., set in its active state) the terminal CS_N to select the SPI slave 208 to communicate with the SPI slave 208, and the SPI master may de-assert (i.e., set in its deactivated state) the terminal CS_N to deselect the SPI slave 208 so that the SPI slave 208 ignores the communication from the SPI bus 206. For example, the SPI master 204 may initiate communication with the IC 202 via the SPI bus 206 by setting the signal V CS_N The CS_N terminal is asserted from high to low and can be switched by signaling V CS_N Transition from low to high to de-assert the CS_N terminal.

[0024] When the SPI slave 208 is selected, the SPI master 204 generates a clock signal at the terminal SCLK at a frequency supported by the SPI, and sends data to the SPI slave 208 via the terminal MOSI. Then, the SPI slave 208 processes the data with the signal V MOSI Data transmitted from SPI master 204 (e.g., in the case of a write command, writing a specified register in the register map of IC 202). If applicable (e.g., when SPI slave 208 receives a read command), SPI slave 208 receives the data transmitted from SPI master 204 via terminal MISO with signal V MISO The data is sent back to the SPI master 204. When the terminal CS_N is de-asserted (e.g., when the signal V CS_N When the SPI slave 208 is not selected, the SPI slave 208 ignores (ie, does not process) data from the SPI bus 206 (eg, ignores the signal V at the terminals SCLK and MOSI). SCLK and V MOSI switch).

[0025] SPI master 204 may be, for example, a microcontroller, a processor, a digital signal processor (DSP), an ASIC, or other device having an SPI master interface. IC 202 may be a PMIC, an ASIC, a driver, a radar circuit, or any other device having an SPI slave interface.

[0026] SPI slave 208 can be implemented in any manner known in the art. In some embodiments, SPI slave 208 supports SPI frequencies above 1 MHz, (such as 10 MHz, 50 MHz or higher). Frequencies below 1 MHz can also be supported by SPI slave 208.

[0027] In one embodiment of the present invention, the chip select terminal and the master output slave input terminal of the SPI communication bus are used to reset the IC to place the IC in a known state. The reset can be issued after power-on (e.g., immediately after power is applied to the IC), or at any time during operation. In one embodiment, when the chip select terminal is de-asserted (e.g., high), asserting the master output slave input terminal (e.g., high) causes the IC to be reset to a known state.

[0028] In some embodiments, the known state of the IC can be a predetermined state (e.g., defined by a default value of a register map of the IC). For example, mapping bits of the IC on a register can configure one or more analog or digital blocks. The IC can be placed in a known state by resetting the register map to a default value and providing such a default value to one or more analog or digital blocks.

[0029] Figure 3 2 shows a waveform diagram illustrating SPI signals at the SPI terminal of IC 202 according to one embodiment. Figure 3 As shown in , when terminal CS_N is deasserted (eg, high), transitioning terminal MOSI to a low state causes internal reset signal RESET_N (eg, low) to be asserted. Asserting internal reset signal RESET_N causes IC 202 to be placed in a known state.

[0030] When terminal CS_N is asserted, active SPI communication between SPI master 204 and SPI slave 208 may be ongoing, and switching terminal MOSI to a low state does not change the state of internal reset signal RESET_N. The change in the state of terminal MOSI also does not result in a blank time T after deasserting terminal CS_N. blank During the change in the state of the internal reset signal RESET_N.

[0031] In some embodiments, the blank time T blank It can be between 4ns and 10ns. In some embodiments, the blank time T blank It can be higher than 10ns, or lower than 4ns. In some embodiments, the blank time T blank It may be at least equal to or longer than half a period of the communication bus frequency (such as half a period of the clock signal at terminal SCLK).

[0032] Although the internal reset signal RESET_N is illustrated as an active low signal (ie, asserted when low and de-asserted when high), some embodiments may use an active high reset signal (ie, asserted when high and de-asserted when low).

[0033] Advantages of some embodiments include the ability to asynchronously reset an IC to place it in a known state without using a dedicated reset terminal and without using a POR circuit internal to the IC circuit.

[0034] Figure 4 Schematic diagram of an input circuit 400 for generating an internal reset signal RESET_N based on an SPI terminal according to an embodiment of the present invention is shown. The input circuit 400 includes a delay circuit 402, an AND gate 404, a NAND gate 406 and an inverter 408.

[0035] During normal operation, when the signal V CS_N When the reset signal RESET_N at the output of the NAND gate 406 is high, the output of the AND gate 404 is low, which causes the reset signal RESET_N at the output of the NAND gate 406 to become high. MOSI The state of the signal V CS_N When the output of the delay circuit 402 switches from low to high, the output of the delay circuit 402 is in the blank time T blank = remains low, which makes the output of AND gate 404 low, which makes the reset signal RESET_N at the output of NAND gate 406 to be low during the blank time T blank becomes high, and the signal V MOSI The state of the signal V CS_N Above the blank time T blank After the time is high, the output of AND gate 404 is high, which causes the reset signal RESET_N at the output of NAND gate 406 to be equal to the signal V MOSI In this state, when the signal V MOSI is high, the reset signal RESET_N is high (deasserted), and when the signal V MOSI When the terminal is low, the reset signal RESET_N is low (asserted).

[0036] When power is applied to IC 202, input circuit 400 is enabled by default. In some embodiments, the input circuit can be disabled during normal operation, for example, when IC 202 enters a low power mode. For example, in some embodiments, IC 202 includes additional circuits (not shown), such as an input driver coupled between a chip select terminal CS_N of IC 202 and delay circuit 402, and an input driver coupled between a MOSI terminal of IC 202 and AND gate 406. In such embodiments, such input driver programs can be enabled by default.

[0037] For example, the delay circuit 402 may be implemented as a plurality of inverters connected in series. Other implementations are also possible.

[0038] For example, as in Figure 2As shown in , IC 202 can be reset by reusing two terminals of a single SPI communication interface. In some embodiments, the IC may include a multi-way I / O SPI interface, such as a dual SPI interface, a quad SPI interface, or an octal SPI interface. In such embodiments, two terminals of such a multi-way I / O SPI interface can be used to reset the IC to put it in a known state. For example, Figure 5 FIG. 5 is a schematic diagram of an IC 502 according to an embodiment of the present invention. The IC 502 includes a quad SPI slave 508. The quad SPI slave 508 includes: a CS_N The chip select terminal CS_N is configured to receive and send signals V IO0 、V IO1 、V IO2 and V IO3 Input / output terminal I O0 ,I O1 ,I O2 and I O3 , and is configured to receive a signal V SCLK The clock terminal SCLK. Figure 5 As shown in FIG. 5 , IC 502 includes terminals SCLK, IO0, IO1, IO2, IO3, and CS_N, which correspond to terminals SCLK, IO0, IO1, IO2, IO3, and CS_N of quad SPI slave 508 .

[0039] When operating at the same SPI clock frequency, the quad SPI communication bus 506 can have a data bandwidth up to 4 times that of the single SPI communication bus 206. For example, by coupling the input circuit 400 to the chip select terminal CS_N and the I / O terminal IO3, the IC 502 can be reset in a manner similar to the IC 202. In some embodiments, another I / O terminal (such as IO2, IO1, or IO0) instead of IO3 can be used to couple to the input circuit 400.

[0040] In some embodiments, one or more ICs having, for example, a single SPI interface may be coupled to SPI communication bus 506 without interfering with the reset operation of IC 502. For example, Figure 6 A schematic diagram of a system 600 having IC 502 and having at least one SPI slave 602 coupled to a SPI communication bus 606 is shown in accordance with one embodiment of the present invention. SPI slave 602 may operate in a similar manner as SPI slave 208.

[0041] As in Figure 6As shown in FIG. 5 , when the quad SPI slave 508 (CS_N deasserted) is not selected, the SPI slave 602 (CS2_N asserted) can be selected, and the SPI master 604 can communicate with the SPI slave 602 via the SPI communication bus 606 (e.g., using terminal IO0 as the master-out slave-in terminal and IO1 as the master-in slave-out terminal). During the communication between the SPI slave 602 and the SPI master 604, the IC 502 cannot be accidentally reset because the terminal IO3 is not used in such communication (i.e., the terminal IO3 is not switched during the communication between the SPI master 604 and the SPI slave 602 via the SPI communication bus 606).

[0042] Despite Figure 6 A single SPI slave 602 is shown coupled to the SPI communication bus 606 , but in some embodiments, more than one SPI slave may be coupled to the SPI communication bus 606 .

[0043] It will be appreciated that an IC having another multiplexed I / O SPI interface (eg, an octal SPI interface) may be implemented in a similar manner as IC 502 in system 600 .

[0044] It will be appreciated that the mechanism of resetting the IC by reusing the terminals of the communication interface is not limited to SPI, but can be extended to other communication protocols that can reuse two terminals. Figure 7 Schematic diagram of an IC 702 with chip reset by reusing the terminals of a SWD (Serial Wire Debug) interface according to an embodiment of the present invention is shown. Figure 7 As shown in FIG. 7 , IC 702 includes a SWD interface 708. SWD interface 708 includes an input clock terminal SWCLK, a data input and output terminal SWDIO, and a serial line output terminal SWO.

[0045] As in Figure 7 As shown in FIG. 7 , by using an input circuit (such as input circuit 400), a reset signal can be generated within IC 702 without using a dedicated reset terminal. In some embodiments, delay circuit 402 can cause a delay of at least equal to the time when the SWCLK signal is high (e.g., half a cycle of the SWCLK signal) or longer. Therefore, toggling SWCLK during normal debugging does not cause the internal reset signal RESET_N to be asserted. To cause a reset, SWCLK is asserted (e.g., high), and SWDIO is idle for at least a period of time equal to the blank time T blank The time is asserted.

[0046] SWD is a bidirectional protocol that is often used for debugging purposes. The SWCLK terminal is configured to receive the clock signal VSWCLK The SWDIO pin is used to signal V SWDIO The SWO terminal is configured to generate a signal V SWO , to help debug tracing. SWD interface 708 can be implemented in any manner known in the art.

[0047] Figure 8 A flow chart of an embodiment method 800 for resetting an integrated circuit according to an embodiment of the present invention is shown. For example, method 800 may be implemented by an IC coupled to an SPI communication bus, such as ICs 202 and 502. Method 800 may also be implemented by, for example, an IC coupled to other types of communication buses, such as IC 702.

[0048] During step 802, the IC receives a first signal and a second signal via a first terminal and a second terminal of the IC, the first terminal and the second terminal of the IC being coupled to a first terminal and a second terminal of a communication interface of the IC. In some embodiments, the communication interface may be an SPI slave (such as SPI slave 208). In such embodiments, the first signal and the second signal may correspond to signals V CS_N and V MOSI , and the first terminal and the second terminal may correspond to the chip select terminal CS_N and the master-output slave input terminal MOSI, respectively. In other embodiments, the communication interface may be a multi-channel IO SPI interface (such as SPI slave 508). In another embodiment, the communication interface may be a SWD interface (such as SWD interface 708). Other communication interfaces may be used.

[0049] During step 804, a circuit such as input circuit 400 determines the state of the first signal. If the first signal is in the first state of the first signal (e.g., low), the IC returns to step 802. If the first signal is in the second state of the first signal (e.g., high), during step 806, the input circuit determines the state of the second signal.

[0050] If the second signal is in the first state of the second signal (e.g., high), the IC returns to step 802. If the second signal is in the second state of the second signal (e.g., low), the IC is reset to a known state during step 808. In some embodiments, the IC is reset when the input circuit asserts a reset signal such as RESET_N (e.g., transitions the reset signal from a first state of the reset signal (e.g., high) to a second state of the reset signal (e.g., low)).

[0051] Exemplary embodiments of the invention are summarized here. Other embodiments may also be understood from the entirety of the specification and claims submitted herein.

[0052] Example 1. An integrated circuit comprising: a communication interface configured to be coupled to a communication bus, the communication interface having a plurality of terminals; and an input circuit having a first input coupled to a first terminal of the plurality of terminals, and the input circuit having a second input coupled to a second terminal of the plurality of terminals, the first input of the input circuit being configured to receive a first signal, and the second input of the input circuit being configured to receive a second signal, wherein the input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the communication interface is not selected.

[0053] Example 2. The integrated circuit according to Example 1, wherein the input circuit is configured to: cause the reset signal to be in the first state of the reset signal when the first signal is in the first state of the first signal; cause the reset signal to be in the first state of the reset signal when the second signal is in the first state of the second signal; and cause the reset signal to be in the second state of the reset signal when the first signal is in the second state of the first signal for at least a first duration and the second signal is in the second state of the second signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal.

[0054] Example 3. An integrated circuit according to one of Examples 1 or 2, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

[0055] Example 4. An integrated circuit according to one example of Examples 1 to 3, wherein the input circuit includes: a delay circuit having an input coupled to a first input of the input circuit; an AND gate having a first input coupled to an output of the delay circuit and a second input coupled to the first input of the input circuit; an inverter having an input coupled to the second input of the input circuit; and a NAND gate having a first input coupled to the output of the AND gate, a second input coupled to the output of the inverter, and an output coupled to the output of the input circuit.

[0056] Example 5. The integrated circuit according to one example of examples 1 to 4, wherein the first duration is longer than 4 ns.

[0057] Example 6. The integrated circuit of one example of examples 1 to 5, wherein the first duration is approximately 10 ns.

[0058] Example 7. The integrated circuit according to one example of Examples 1 to 6, wherein the communication interface is configured to be selectable based on the first signal.

[0059] Example 8. The integrated circuit according to one example of Examples 1 to 7, wherein the communication interface is configured to: be selected when the first signal is low; and not be selected when the first signal is high.

[0060] Example 9. The integrated circuit of one example of Example 1 to Example 8, wherein the communication interface is a serial peripheral interface (SPI) interface.

[0061] Example 10. An integrated circuit according to one of Examples 1 to 9, wherein the SPI interface is a single SPI interface having a chip select terminal, a master in slave out terminal, a master out slave in terminal, and a SPI clock terminal, and wherein a first input of the input circuit is coupled to the chip select terminal, and a second input of the input circuit is coupled to the master out slave in terminal.

[0062] Example 11. An integrated circuit according to one example of Examples 1 to 10, wherein the SPI interface is a multi-IO SPI interface having: a chip select terminal, an SPI clock terminal, and a plurality of input-output terminals, and wherein a first input of the input circuit is coupled to the chip select terminal, and a second input of the input circuit is coupled to one of the plurality of input-output terminals.

[0063] Example 12. The integrated circuit of one example of Example 1 to Example 11, wherein the communication interface is a serial wire debug (SWD) interface.

[0064] Example 13. The integrated circuit of one of Examples 1 to 12, wherein the first input of the input circuit is coupled to an input clock terminal of the SWD interface, and the second input of the input circuit is coupled to data input and data output terminals of the SWD interface.

[0065] Example 14. The integrated circuit according to one of Examples 1 to 13, wherein the first signal is a periodic signal, and wherein the input circuit comprises: a delay circuit coupled to the first input of the input circuit, the delay circuit configured to generate a delay equal to or greater than half a period of the periodic signal.

[0066] Example 15. An integrated circuit comprising: a serial peripheral interface (SPI) interface configured to be coupled to a SPI communication bus, the SPI interface having: an SPI clock terminal, a chip select terminal, and a plurality of data terminals; and an input circuit having a first input coupled to the SPI clock terminal of the plurality of data terminals, and a second input coupled to one of the plurality of data terminals, the first input of the input circuit being configured to receive a first signal, and the second input of the input circuit being configured to receive a second signal, wherein the input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the SPI interface is not activated.

[0067] Example 16. The integrated circuit according to Example 15, wherein the input circuit is configured to: cause the reset signal to be in the first state of the reset signal when the first signal is in the first state of the first signal; cause the reset signal to be in the first state of the reset signal when the second signal is in the first state of the second signal; and cause the reset signal to be in the second state of the reset signal when the first signal is in the second state of the first signal for at least the first duration and the second signal is in the second state of the second signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal.

[0068] Example 17. The integrated circuit of one example of example 15 or 16, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

[0069] Example 18. The integrated circuit according to one example of Examples 15 to 17, wherein the input circuit includes: a delay circuit having an input coupled to a first input of the input circuit; an AND gate having a first input coupled to an output of the delay circuit and a second input coupled to the first input of the input circuit; an inverter having an input coupled to the second input of the input circuit; and a NAND gate having a first input coupled to the output of the AND gate, a second input coupled to the output of the inverter, and an output coupled to the output of the input circuit.

[0070] Example 19. The integrated circuit of one example of Example 15 to Example 18, wherein the SPI interface comprises a single SPI interface.

[0071] Example 20. The integrated circuit of one example of Example 15 to Example 19, wherein the SPI interface is a quad SPI interface.

[0072] Example 21. A method of resetting an integrated circuit, the method comprising: receiving a first signal via a first terminal of the integrated circuit, the first terminal being coupled between a communication bus and a communication interface; receiving a second signal via a second terminal of the integrated circuit, the second terminal being coupled between the communication bus and the communication interface; causing a reset signal to be in a first state of the reset signal when the first signal is in a first state of the first signal; causing the reset signal to be in a first state of the reset signal when the second signal is in a first state of the second signal; causing the reset signal to be in a second state of the reset signal when the first signal is in a second state of the first signal for at least a first duration and the second signal is in a second state of the second signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal; and resetting the integrated circuit to a known state when the reset signal is in a third state.

[0073] Example 22. The method of Example 21, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

[0074] Example 23. The method of one example of Example 21 or Example 22, wherein the communication bus is a serial peripheral interface (SPI) communication, and the communication interface is a SPI interface.

[0075] Example 24. The method according to one example of examples 21 to 23, wherein the first signal is a periodic signal, and the first duration is equal to or greater than a half period of the periodic signal.

[0076] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations with reference to the illustrative embodiments of the present invention and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims cover any such modifications or embodiments.

Claims

1. An integrated circuit, comprising: a communication interface configured to be coupled to the communication bus, the communication interface having a plurality of terminals; as well as An input circuit having a first input coupled to a first terminal of the plurality of terminals and having a second input coupled to a second terminal of the plurality of terminals, the first input of the input circuit being configured to receive a first signal, and the second input of the input circuit being configured to receive a second signal, wherein the second signal is a data signal, wherein the first signal is a clock signal or a communication interface selection signal to selectively cause the communication interface to process the data signal, and wherein the input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the communication interface is not selected.

2. The integrated circuit of claim 1 , wherein the input circuit is configured as: causing the reset signal to be in the first state of the reset signal when the first signal is in the first state of the first signal; causing the reset signal to be in the first state of the reset signal when the second signal is in the first state of the second signal; and The reset signal is caused to be in the second state of the reset signal when the first signal is in the second state of the first signal for at least a first duration and the second signal is in the second state of the second signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal.

3. The integrated circuit of claim 2, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

4. The integrated circuit of claim 2, wherein the input circuit comprises: a delay circuit having an input coupled to the first input of the input circuit; an AND gate having a first input coupled to the output of the delay circuit and a second input coupled to the first input of the input circuit; an inverter having an input coupled to the second input of the input circuit; as well as A NAND gate has a first input coupled to the output of the AND gate, a second input coupled to the output of the inverter, and an output coupled to the output of the input circuit. The integrated circuit of claim 2 , wherein the first duration is longer than 4 ns. The integrated circuit of claim 5 , wherein the first duration is 10 ns. 7 . The integrated circuit of claim 1 , wherein the communication interface is configured to be selectable based on the first signal.

8. The integrated circuit of claim 7, wherein the communication interface is configured to: is selected when the first signal is low; and Not selected when the first signal is high.

9. The integrated circuit of claim 1, wherein the communication interface is a serial peripheral interface (SPI) interface.

10. The integrated circuit of claim 9, wherein the SPI interface is a single SPI interface having: a chip select terminal, a master input slave output terminal, a master output slave input terminal, and a SPI clock terminal, and wherein the first input of the input circuit is coupled to the chip select terminal, and the second input of the input circuit is coupled to the master output slave input terminal.

11. The integrated circuit of claim 9, wherein the SPI interface is a multi-IO SPI interface having: a chip select terminal, a SPI clock terminal, and a plurality of input-output terminals, and wherein the first input of the input circuit is coupled to the chip select terminal, and the second input of the input circuit is coupled to one of the plurality of input-output terminals.

12. The integrated circuit of claim 1, wherein the communication interface is a through-wire debug (SWD) interface.

13. The integrated circuit of claim 12, wherein the first input of the input circuit is coupled to an input clock terminal of the SWD interface, and the second input of the input circuit is coupled to data input and output terminals of the SWD interface.

14. The integrated circuit of claim 1 , wherein the first signal is a clock signal, and wherein the input circuit comprises a delay circuit coupled to the first input of the input circuit, the delay circuit being configured to generate a delay equal to or greater than half a period of the clock signal.

15. An integrated circuit comprising: A serial peripheral interface SPI interface, which is configured to be coupled to a SPI communication bus, the SPI interface having: an SPI clock terminal, an SPI chip select terminal and a plurality of data terminals; as well as an input circuit having a first input coupled to the SPI chip select terminal and a second input coupled to one of the plurality of data terminals, the first input of the input circuit being configured to receive a first signal, and the second input of the input circuit being configured to receive a second signal, wherein the input circuit is configured to generate a reset signal at an output of the input circuit based on the first signal and the second signal when the SPI interface is not activated.

16. The integrated circuit of claim 15, wherein the input circuit is configured to: causing the reset signal to be in the first state of the reset signal when the first signal is in the first state of the first signal; causing the reset signal to be in the first state of the reset signal when the second signal is in the first state of the second signal; and The reset signal is caused to be in the second state of the reset signal when the first signal is in the second state of the first signal for at least a first duration and the second signal is in the second state of the second signal, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal.

17. The integrated circuit of claim 16, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

18. The integrated circuit of claim 16, wherein the input circuit comprises: a delay circuit having an input coupled to the first input of the input circuit; an AND gate having a first input coupled to the output of the delay circuit and a second input coupled to the first input of the input circuit; an inverter having an input coupled to the second input of the input circuit; as well as A NAND gate has a first input coupled to the output of the AND gate, a second input coupled to the output of the inverter, and an output coupled to the output of the input circuit.

19. The integrated circuit of claim 15, wherein the SPI interface comprises a single SPI interface.

20. The integrated circuit of claim 15, wherein the SPI interface is a quad SPI interface.

21. A method for resetting an integrated circuit, the method comprising: receiving a first signal via a first terminal of the integrated circuit, the first terminal being coupled between a communication bus and a communication interface; receiving a second signal via a second terminal of the integrated circuit, the second terminal being coupled between the communication bus and the communication interface, wherein the second signal is a data signal, wherein the first signal is a clock signal or a communication interface selection signal to selectively cause the communication interface to process the data signal; causing a reset signal to be in a first state of the reset signal when the first signal is in a first state of the first signal; causing the reset signal to be in the first state of the reset signal when the second signal is in the first state of the second signal; causing the reset signal to be in the second state of the reset signal when the first signal is in the second state of the first signal for at least a first duration, the second signal is in the second state of the second signal, and the communication interface is not selected, wherein the first state of the first signal is opposite to the second state of the first signal, wherein the first state of the second signal is opposite to the second state of the second signal, and wherein the first state of the reset signal is opposite to the second state of the reset signal; and When the reset signal is in the second state, the integrated circuit is reset to a known state.

22. The method of claim 21, wherein the first state of the first signal is high, the second state of the first signal is low, the first state of the second signal is high, the second state of the second signal is low, the first state of the reset signal is high, and the second state of the reset signal is low.

23. The method of claim 21, wherein the communication bus is a Serial Peripheral Interface (SPI) communication, and wherein the communication interface is a SPI interface.

24. The method of claim 21, wherein the first signal is a periodic signal, and wherein the first duration is equal to or greater than half a period of the periodic signal.

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