Microwave integrated circuit

Abstract

A microwave integrated circuit (1) includes: a semiconductor substrate (3); a plurality of amplification units formed in the semiconductor substrate; a wiring (W3) formed in one layer wiring (19c) other than the uppermost layer wiring (19d) and the lowermost layer wiring (19a) among the plurality of layer wirings (19a - 19d) formed on the semiconductor substrate and supplying power to the plurality of amplification units; a plurality of vias (21a) connecting a plurality of conductive regions (51) formed in the layer wiring (19c), the wiring being sandwiched between the plurality of conductive regions, other conductive regions (53, WG) formed in regions sandwiching the wiring in two layer wirings (19b, 19d) immediately above and immediately below the layer wiring (19c), each of the plurality of vias forming a via structure that is connected to conductive regions (55, 59) of the lowermost layer wiring through a plurality of other vias (21b, 21d).

Description

Technical Field

[0001] The present disclosure relates to a microwave integrated circuit. Background Art

[0002] In the prior art, microwave integrated circuits in which microwave devices are integrated have been used. As a microwave integrated circuit, Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-309121), Patent Document 2 (Japanese Unexamined Patent Publication No. 2010-205941), or Patent Document 3 (Japanese Unexamined Patent Publication No. 2017-085040) discloses a multilayer monolithic microwave integrated circuit (MMIC) in which an insulating layer and wiring layers are stacked on a semiconductor substrate, and circuit elements such as transistors are formed on the semiconductor substrate. According to the structure of such a multilayer MMIC, reduction in the area occupied by the circuit can be achieved.

[0003] In recent years, in microwave integrated circuits having the structure of the multilayer MMIC in the above prior art, reduction in the circuit size has been demanded. However, in microwave integrated circuits in the prior art having a reduced circuit size, in some cases, oscillation occurs between output signals due to insufficient isolation between circuit units. Further, in such a microwave integrated circuit, in order to make the operating points of transistors the same in an amplifier circuit having a multi-stage configuration, in some cases, adjustment of the bias voltage applied to the transistors is complicated. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a microwave integrated circuit including: a semiconductor substrate; a plurality of amplification units formed in the semiconductor substrate; a power supply line formed in one of the wiring layers among a plurality of wiring layers formed on the semiconductor substrate, except for the uppermost wiring layer and the lowermost wiring layer, and used for supplying power to the plurality of amplification units; and a plurality of through holes connecting a plurality of conductive regions sandwiching the power supply line formed in the one wiring layer and other conductive regions formed in regions sandwiching the power supply line between two wiring layers immediately above and immediately below the one wiring layer, wherein each of the plurality of through holes forms a through hole structure that is connected to at least one of the uppermost wiring layer and the lowermost wiring layer through a plurality of other through holes.

[0005] Alternatively, according to another aspect of the present disclosure, there is provided a microwave integrated circuit including: a first-stage amplifier that amplifies an input high-frequency signal having a first frequency; a main system amplification stage that amplifies and outputs a signal having the first frequency branched from the output of the first-stage amplifier; a branch stage that generates a signal having a double frequency of the first frequency by multiplying another signal having the first frequency branched from the output of the first-stage amplifier; and a subsystem amplification stage that amplifies and outputs the signal having the double frequency output from the branch stage, wherein the first-stage amplifier, the main system amplification stage, the branch stage, and the subsystem amplification stage are integrated on a common semiconductor substrate, and wherein the amplification circuits constituting the first-stage amplifier, the amplification circuits included in the branch stage, the amplification circuits included in the main system amplification stage, and the amplification circuits included in the subsystem amplification stage are connected in series in a DC manner between a power supply and ground, and each is a current reuse type amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view of a microwave integrated circuit 1 according to an embodiment.

[0007] Figure 2 is Figure 1 a cross-sectional view of the microwave integrated circuit 1.

[0008] Figure 3 is a block diagram illustrating Figure 1 the overall circuit configuration of the microwave integrated circuit 1.

[0009] Figure 4 is a diagram illustrating the arrangement of circuit units, the path of the bias voltage applied to the circuit units, and the RF signals input / output between the circuit units when viewed from the front surface side of the microwave integrated circuit 1; Figure 1 when viewed from the front surface side of the microwave integrated circuit 1;

[0010] Figure 5 is a diagram illustrating Figure 1 the circuit configuration of the amplification units configured in the microwave integrated circuit 1;

[0011] Figure 6 is a cross-sectional view of the microwave integrated circuit 1 near the wirings W1 and W3 in a direction perpendicular to the formation direction of the wiring W1; Figure 1 when viewed from the front surface side of the microwave integrated circuit 1;

[0012] Figure 7 is a plan view of a via hole structure formed on a multilayer wiring layer 5;

[0013] Figure 8 is a diagram illustrating Figure 7 the appearance of the arrangement of the via hole structure in; and

[0014] Figure 9 is a graph showing the effect of preventing oscillation of the output signal by the microwave integrated circuit 1. Detailed Embodiment

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, in the description of the drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0016] [Configuration of Microwave Integrated Circuit]

[0017] Figure 1 is a plan view of the microwave integrated circuit 1 according to an embodiment, and Figure 2 is a cross-sectional view of the microwave integrated circuit 1. Figure 1 and Figure 2 The microwave integrated circuit 1 illustrated in is an integrated circuit that amplifies and outputs a microwave signal, and is a wafer-level chip-scale package (WLCSP) chip, which is an MMIC capable of realizing flip-chip packaging in a face-down manner. The microwave integrated circuit 1 includes a semiconductor substrate 3 that is a GaAs substrate in which circuit units including a field effect transistor (FET) and the like are formed, a multilayer wiring layer 5 stacked on the semiconductor substrate 3, and solder balls 9 formed on a surface 7 of the multilayer wiring layer 5 opposite to the semiconductor substrate 3. For example, the semiconductor substrate 3 and the multilayer wiring layer 5 have a rectangular plan view with dimensions of 2.3 mm × 1.66 mm in the plan view.

[0018] A conductive film 15 serving as a terminal for each of the circuit elements such as the FET 11 and the resistance element 13 formed inside the semiconductor substrate 3 is formed on the front surface of the semiconductor substrate 3 on the side closer to the multilayer wiring layer 5, a protective film 16 is formed on the back surface of the semiconductor substrate 3, and the multilayer wiring layer 5 is laminated on the front surface of the semiconductor substrate 3 on which the conductive film 15 is formed. The multilayer wiring layer 5 has a five-layer structure of a first insulating layer 17a, a second insulating layer 17b, a third insulating layer 17c, a fourth insulating layer 17d, and a fifth insulating layer 17e. A first layer wiring 19a is formed on a surface of the first insulating layer 17a closer to the second insulating layer 17b, a second layer wiring 19b is formed on a surface of the second insulating layer 17b closer to the third insulating layer 17c, a third layer wiring 19c is formed on a surface of the third insulating layer 17c closer to the fourth insulating layer 17d, and a fourth layer wiring 19d is formed on a surface of the fourth insulating layer 17d closer to the fifth insulating layer 17e.

[0019] The first insulating layer 17a is formed on the front surface of the semiconductor substrate 3 with two layers including a polyimide film and a SiN film. Among them, the conductive film 15 corresponding to the respective electrodes of the FET 11 and the space between the conductive films 15 are covered with a SiN film (SiN passivation film). For example, the first insulating layer 17a is formed such that the thickness of the polyimide film is 1.4 μm and the thickness of the SiN film is 0.1 μm. The first layer wiring 19a is formed on the front surface of the first insulating layer 17a by performing gold plating on the metal seed layer. For example, the first layer wiring 19a is formed such that the thickness of the metal seed layer is 0.515 μm and the thickness of the gold plating is 1 μm.

[0020] The second to fourth insulating layers 17b to 17d are respectively formed on the first to third insulating layers 17a to 17c with two layers of a SiN film and a polyimide film. For example, the second insulating layer 17b is formed with two-layer thicknesses of 0.33 μm and 2.0 μm, the third insulating layer 17c is formed with two-layer thicknesses of 0.3 μm and 2.0 μm, and the fourth insulating layer is formed with two-layer thicknesses of 0.2 μm and 2.0 μm. The second to fourth layer wirings 19b to 19d are formed by performing gold plating on the metal seed layer on the front surface of each of the second to fourth insulating layers 17b to 17d. For example, the second layer wiring 19b and the third layer wiring 19c are formed with a metal seed layer thickness of 0.205 μm and a gold plating thickness of 1 μm, and the fourth layer wiring 19d is formed with a metal seed layer thickness of 0.205 μm and a gold plating thickness of 2 μm.

[0021] The fifth insulating layer 17e is formed on the fourth insulating layer 17d with two layers including a SiN film and a polyimide film. For example, the fifth insulating layer 17e is formed with two-layer thicknesses of 0.2 μm and 2.5 μm. A plurality of solder balls 9 are two-dimensionally arranged and formed on the front surface of the fifth insulating layer 17e. The plurality of solder balls 9 are spherical conductors electrically connected to the circuit units inside the semiconductor substrate 3 or the first to fourth layer wirings 19a to 19d. When the microwave integrated circuit 1 is flip-chip packaged on the mounting substrate, the solder balls 9 are electrically connected to the wirings on the mounting substrate.

[0022] In the multilayer wiring layer 5 having the above configuration, the solder balls 9, the conductive film 15, and the first to fourth layer wirings 19a to 19d are electrically connected to each other through the through holes 21 penetrating at least one of the first insulating layer 17a to the fifth insulating layer 17e. In addition, passive components such as capacitors 23 are formed in the multilayer wiring layer 5. For example, in the second insulating layer 17b in a state where the passive component is connected to any one of two layers of wirings such as the first layer wiring 19a and the second layer wiring 19b.

[0023] Figure 3is a block diagram showing the overall circuit configuration in the microwave integrated circuit 1. As Figure 3 shown in, the microwave integrated circuit 1 is configured by integrating a low-noise amplifier (LNA) 31 as a first-stage amplifier, a main system amplification stage, a branch stage, and a subsystem amplification stage on a semiconductor substrate 3. The first-stage amplifier amplifies an RF signal (high-frequency signal) having a first frequency (e.g., a frequency of 38 GHz) input from an input terminal (signal input terminal) P IN After being amplified by the low-noise amplifier 31, the main system amplification stage amplifies the RF signal having the first frequency as one of two branch RF signals. After being amplified by the low-noise amplifier 31, the branch stage generates a frequency-doubled wave having a double frequency of the first frequency (e.g., an RF signal having a frequency of 77 GHz) as the other of the two branch RF signals by multiplying the RF signal having the first frequency, and the subsystem amplification stage amplifies and outputs the frequency-doubled wave output from the branch stage.

[0024] The main system amplification stage has a configuration of a two-stage amplification circuit, in which a driver amplifier 33 and a power amplifier 35 are connected in series, and the main system amplification stage outputs an RF signal having the first frequency amplified to a predetermined signal strength (e.g., 50 mW) from an output terminal (signal output terminal) P OUT1 The branch stage has a configuration in which a frequency multiplier 39 is sandwiched between a low-noise amplifier 37 and a low-noise amplifier 41 as a two-stage amplification circuit, and amplifies and outputs an RF signal having a second frequency. The subsystem amplification stage has a configuration of a two-stage amplification circuit, in which a driver amplifier 43 and a power amplifier 45 are connected in series, and the subsystem amplification stage is connected as a subsequent stage of the branch stage. In the branch stage, the RF signal branched from the low-noise amplifier 31 is amplified by the low-noise amplifier 37, the frequency multiplier 39 multiplies the frequency of the RF signal to generate a frequency-doubled wave having a second frequency (e.g., an RF signal having a frequency of 77 GHz), and then, the low-noise amplifier 41 amplifies the frequency-doubled wave again. In addition, the frequency-doubled wave generated by the branch stage is sequentially amplified by the driver amplifier 43 and the power amplifier 45 of the subsystem amplification stage, and thus, the amplified wave is output from the output terminal P OUT2 as a frequency-doubled wave having a predetermined signal strength (e.g., 30 mW).

[0025] In the above circuit components, each of the amplification unit including the low-noise amplifier 31, the low-noise amplifiers 37 and 41 included in the branch stage, the driver amplifier 33 and the power amplifier 35 included in the main system amplification stage, and the driver amplifier 43 and the power amplifier 45 included in the subsystem amplification stage adopts a configuration of a current-reuse type amplifier including two-stage FETs, as described later. On the other hand, the frequency multiplier 39 is configured with a single-stage field effect transistor (FET) as a nonlinear element, and by setting the bias voltage to be deep or shallow, due to the nonlinearity of the input / output characteristics, the frequency multiplier 39 can easily generate harmonics by performing a nonlinear operation to output an output signal including harmonic components from the drain. Then, the frequency multiplier 39 outputs only a predetermined harmonic wave (for example, a double harmonic wave) from the drain by providing a limitation (cutoff frequency) to the frequency band.

[0026] Figure 4 The figure shows the layout of the circuit units, the path of the bias voltage applied to the circuit units, and the RF signals input / output between the circuit units when viewed from the front surface side of the microwave integrated circuit 1. Here, the path of the bias voltage is illustrated by a solid line, and the path of the RF signals (including harmonic waves) is illustrated by a dashed line. The path of the bias voltage is formed by the third-layer wiring 19c, and the path of the RF signals is formed by the first-layer wiring 19a and the second-layer wiring 19b.

[0027] A solder ball 9a having the function of an input terminal P IN is provided on one side 5a side of the multilayer wiring layer 5 of the microwave integrated circuit 1, and in order to prevent oscillation of the output caused by coupling between the input and the output, a solder ball 9b having the function of an output terminal P OUT2 of the subsystem amplification stage is provided on the side 5b opposite to the one side 5a of the multilayer wiring layer 5. In addition, in order to prevent oscillation of the output caused by coupling between the input and the output and coupling with the subsystem amplification stage, a solder ball 9c having the function of an output terminal P OUT1 of the main system amplification stage is provided on the side 5c side of the multilayer wiring layer 5 adjacent to either the one side 5a or 5b.

[0028] The layout of the circuit units corresponding to the layout of the solder balls 9a, 9b, and 9c is set as follows. The low-noise amplifier 31 is arranged near the center of one side 5a corresponding to the position of the solder ball 9a, and the frequency multipliers 39, low-noise amplifiers 41, driver amplifiers 43, and power amplifiers 45 that make up the branch stage and the subsystem amplification stage are arranged side by side between one side 5a and one side 5b near one side 5d opposite to one side 5c. On the other hand, for the driver amplifier 33 and the power amplifier 35 that make up the main system amplification stage, in order to ensure the layout space, the driver amplifier 33 is arranged near one side 5b from the center of the front surface, and the power amplifier 35 is arranged on one side 5c near the solder ball 9c. Corresponding to the above layout, a wiring W1 for transmitting the RF signal along one side 5c is provided between the output of the driver amplifier 33 and the input of the power amplifier 35 in the first-layer wiring 19a as a path for the RF signal.

[0029] In addition, paths (power supply lines) for supplying bias voltages (electric power) to the corresponding circuit units and solder balls 9 are also formed in the multilayer wiring layer 5 of the microwave integrated circuit 1. That is, the solder ball 9d for supplying the common bias voltage (first power supply voltage) VDD1 for driving the low-noise amplifier 31 and the first-stage driver amplifier 33 of the main system amplification stage and the solder ball 9e for supplying the bias voltage (fourth power supply voltage) VDD4 for driving the power amplifier 35 of the subsequent stage of the main system amplification stage are set on one side 5a of the front surface of the multilayer wiring layer 5. On the third-layer wiring 19c, a wiring W2 for electrically connecting the solder ball 9e to the power amplifier 35 is formed, and a wiring W3 for electrically connecting the solder ball 9d to the low-noise amplifier 31 and the driver amplifier 33 is formed. The wiring W3 is formed adjacent to the wiring W1 for the RF signal between the driver amplifier 33 and the power amplifier 35 on the center side of the front surface of the multilayer wiring layer 5. That is, the wiring W3 is formed between the position of the solder ball 9a as the input terminal P IN and the position of the solder ball 9c as the output terminal P OUT1 and between the position of the low-noise amplifier 31 and the position of the wiring W1. In addition, the solder ball 9f for supplying the common bias voltage (second power supply voltage) VDD2 for driving the low-noise amplifier 37, the frequency multiplier 39, and the low-noise amplifier 41 included in the branch stage and the solder balls 9g and 9h for supplying the common bias voltage (third power supply voltage) VDD3 for driving the driver amplifier 43 and the power amplifier 45 of the subsystem amplification stage are set on one side 5b side of the front surface of the multilayer wiring layer 5. Wirings for electrically connecting each of the solder balls 9f, 9g, and 9h to each circuit unit are also provided in the third-layer wiring 19c.

[0030] Next, reference will be made to Figure 5Describe the circuit configuration of an amplification unit including low-noise amplifiers 31, 37, and 41; driver amplifiers 33 and 43; and power amplifiers 35 and 45. Each circuit unit is configured as a current-reuse type amplifier, which includes two-stage FETs connected in series between a power supply and ground in a DC manner and connected in series between the input and output of an RF signal in an AC manner.

[0031] That is, each amplification unit includes FETs T1 and T2, transmission lines L1 to L4, capacitors C1 to C4, and a resistive element R1. In FET T1, the gate G1 is connected to the input terminal In in an AC manner through capacitor C3, and the source S1 of FET T1 is grounded. The input terminal In is a terminal for inputting an RF signal. In addition, the gate G1 of FET T1 is electrically connected to the power supply terminal VGG for applying a gate bias through transmission line L1, and the power supply terminal VGG is grounded in an AC manner through capacitor C1. In addition, the gate G2 of FET T2 is connected to the drain D1 of FET T1 through transmission lines L2 and L3, and the source S2 of FET T2 is grounded in an AC manner through capacitor C2. Further, the source S2 of FET T2 is connected to the connection point N1 between transmission line L2 and transmission line L3 through transmission line L4 and resistive element R1. In addition, the drain D2 of FET T2 is connected to the output terminal Out for outputting an RF signal in an AC manner through capacitor C4, and is also connected to the power supply terminal VDD for applying a bias voltage. Capacitors C3 and C4 are coupling capacitors for blocking DC components.

[0032] In the amplification unit having such a configuration, the bias current flowing from the power supply terminal VDD to FET T2 flows out from the source S2, flows through the resistive element R1 and transmission line L4, flows into the drain D1 of FET T1, and is discharged to ground from the source S1 of FET T1. In this way, by connecting FET T2 and FET T1 in series between the power supply terminal VDD and ground in a DC manner, a configuration can be achieved in which the bias current supplied to FET T2 is reused even in FET T1.

[0033] In addition, the resistive element R1 has the function of operating FET T2 in a self-bias manner. That is, the flow of the bias current in the resistive element R1 causes a voltage drop, and this voltage drop results in the application of the gate bias to FET T2.

[0034] In addition, the transmission line L4 has a length of λ / 4 corresponding to the wavelength λ (including the harmonic wave) of the RF signal targeted as the amplification unit. Therefore, it is possible to prevent the path of the bias voltage from affecting the RF signal propagated through the transmission lines L2 and L3. That is, since one end side of the transmission line L4 is grounded in an AC manner through the capacitor C2, the transmission line L4 is substantially disconnected in an AC manner when observed from the connection point N1. As a result, the path of the transmission line L4 does not affect the RF signal propagated through the transmission lines L2 and L3.

[0035] Furthermore, the gate bias (fixed bias) is directly applied from the power supply terminal VGG to the gate G1 of the FET T1. Since the transmission line L1 between the power supply terminal VGG and the gate G1 is also set to have a length of λ / 4 and one end of the transmission line L1 is grounded in an AC manner, the path of the transmission line L1 does not substantially affect the RF signal propagated from the input terminal In to the gate G1. As described above, the FET T1 and the FET T2 are connected in series in an AC manner between the input terminal In and the output terminal Out, enabling effective amplification and output of the RF signal.

[0036] In addition, although the amplification unit having the above configuration has a configuration in which the FET T1 operates with a fixed bias and the FET T2 operates with a self-bias, it is also possible to allow the FET T1 to operate with a self-bias by grounding the source S1 of the FET T1 to a parallel circuit of a resistor element and a capacitor having the same resistance value as the resistor element R1 and by directly grounding the gate G1 to a resistor element having a meaningful resistance value or a transmission line having a length of λ / 4. At this time, by setting the two FETs T1 and T2 to the same size (the same gate width), the operating conditions of the two FETs become the same. As in Figure 5 the circuit configuration, in a configuration where one FET T1 has a fixed bias and the other FET T2 has a self-bias, by adjusting the operating point of the FET T1 by adjusting the fixed bias, it is possible to balance the distortion characteristics and the maximum output characteristics of the two-stage amplifier circuit.

[0037] The size (gate width) of the FET included in each amplification unit is set to be the same, for example, as follows.

[0038] Low noise amplifier 31: 80μm

[0039] Driver amplifier 33 (38 GHz): 240μm

[0040] Power amplifier 35 (38 GHz): 400μm

[0041] Driver amplifier 43 (77 GHz): 160μm

[0042] Power amplifier 45 (77 GHz): 300 μm

[0043] That is, the size ratio of the FETs included in the two amplifiers 33 and 35 constituting the main system amplification stage is set to 3:5, the size ratio of the FETs included in the two amplifiers 43 and 45 constituting the sub-system amplification stage is set to 8:15, and the size ratio of the total size of the FETs included in the two amplifiers 33 and 35 constituting the main system amplification stage to the total size of the FETs included in the two amplifiers 43 and 45 constituting the sub-system amplification stage is set to 32:23. Therefore, the required output can be obtained within the specified temperature range.

[0044] Next, reference will be made to Figures 6 to 8 Describe the via structure for signal shielding formed in the multilayer wiring layer 5 of the microwave integrated circuit 1. Figure 6 is a cross-sectional view of the microwave integrated circuit 1 near the wirings W1 and W3 in a direction perpendicular to the formation direction of the wirings W1 and W3, Figure 7 is a plan view of the via structure formed in the multilayer wiring layer 5, and Figure 8 is a plan view schematically showing the appearance of the arrangement of the via structure. Additionally, in Figure 6 the illustration of the solder ball 9 is omitted.

[0045] As Figure 6 illustrated in, the third layer wiring 19c on the third insulating layer 17c is provided with the wiring W3 for supplying a bias voltage, the first layer wiring 19a on the first insulating layer 17a is arranged in parallel with the wiring W1 for transmitting an RF signal, and the fourth layer wiring 19d on the fourth insulating layer 17d is provided with a ground wiring layer WG connected to ground through the solder ball 9. Then, a plurality of conductive regions 51 are formed on the third insulating layer 17c in parallel with the wiring W3 to serve as the third layer wiring 19c, where the wiring W3 is sandwiched from both sides, and a conductive region 53 is formed on the second insulating layer 17b above the region including the wiring W3 and the plurality of conductive regions 51 sandwiching the wiring W3. The plurality of conductive regions 51 are electrically connected to the ground wiring layer WG of the fourth layer wiring 19d immediately above through the via 21a penetrating the fourth insulating layer 17d corresponding to the planar shape of the conductive region 51 and are electrically connected to the conductive region 53 of the second layer wiring 19b immediately below through the via 21a penetrating the third insulating layer 17c corresponding to the planar shape of the conductive region 51. Since the ground wiring layer WG is formed in the range covering the wiring W3 and the plurality of conductive regions 51, the wiring W3 is surrounded from a direction perpendicular to the extending direction by the ground wiring layer WG, the via 21a, the conductive regions 51, and the conductive region 53, and the via 21a and the conductive regions 51 and 53 are grounded through the ground wiring layer WG.

[0046] In addition, the following via structure is also added to the via structure formed by via 21a and conductive regions 51 and 53. That is, an additional via structure including via 21b penetrating the second insulating layer 17b, conductive region 55 formed as the first-layer wiring 19a, via 21c penetrating the first insulating layer 17a, and conductive region 57 formed on the semiconductor substrate 3 is provided between conductive region 53 and semiconductor substrate 3. Additionally, an additional via structure is further provided. That is, an additional via structure is provided between conductive region 53 and semiconductor substrate 3, which includes: via 21d, which penetrates the second insulating layer 17b and is formed parallel to via 21b; conductive region 59, which is formed as the first-layer wiring 19a; via 21e, which penetrates the first insulating layer 17a; and conductive region 61, which is formed on the semiconductor substrate 3. Through this additional via structure, the via structure including via 21a is electrically connected to conductive regions 55 and 59 on the first-layer wiring 19a and conductive regions 57 and 61 on the semiconductor substrate 3.

[0047] A plurality of via structures and additional via structures are provided along a plurality of wirings for supplying bias in the multilayer wiring 5. In Figure 7 , the solid line indicated by reference numeral BS1 in the drawing shows the shape of the additional via structure formed by vias 21b and 21c along wiring W3, and the solid line indicated by reference numeral BS2 in the same drawing shows the shape of the additional via structure formed by vias 21d and 21e along wiring W3. Therefore, two additional via structures are formed in a staggered manner along wiring W3. Additionally, as Figure 8 illustrated, in the additional via structure, the lengths of vias 21b and 21c along wiring W3 and the lengths of vias 21d and 21e are set to be shorter than λ / 8 corresponding to the wavelength λ of the RF signal to be processed by the microwave integrated circuit 1, and the arrangement intervals (gaps) of a plurality of vias 21b and 21c and a plurality of vias 21d and 21e along wiring W3 are also set to be less than λ / 8. Additionally, the via structure including via 21a can also be formed in a similar shape and arrangement.

[0048] Return Figure 6 , other via structures for electrically connecting the semiconductor substrate 3 to the uppermost fourth-layer wiring 19d are also formed near the edges in the multilayer wiring layer 5. That is, a plurality of conductive regions 63 are formed on the semiconductor substrate 3, and conductive regions 65, 67, and 69 are respectively formed on the first to third insulating layers 17a to 17c in shapes and ranges corresponding to conductive region 63, and the plurality of conductive regions 63, 65, 67, and 69 are electrically connected to the ground wiring layer WG through a plurality of vias 21f formed in shapes and ranges corresponding to the plurality of conductive regions. A plurality of other via structures are formed along each of the edges 5a, 5b, 5c, and 5d of the multilayer wiring layer 5, asFigure 2 as shown by the solid line BS3 in FIG. 1, and the length and interval along each of the sides 5a, 5b, 5c and 5d are set to be less than λ / 8.

[0049] In the above-described microwave integrated circuit 1, the wiring W3 for supplying power to the plurality of amplification units is surrounded by a plurality of through-holes 21a extending above the second to fourth layer wirings 19b to 19d and conductive regions 53 and 51 on the second layer wiring 19b and the third layer wiring 19c, and the plurality of through-holes 21a and the conductive regions 53 and 51 are electrically connected to the ground wiring layer WG. Further, the through-hole structure is connected to an additional through-hole structure formed between the second layer wiring 19b and the semiconductor substrate 3. By such a through-hole structure, the electrical interference between the plurality of amplification units formed on the semiconductor substrate 3 is reduced. As a result, the oscillation in the output signal can be effectively reduced. Specifically, by using such a through-hole structure, the space between the input of the low-noise amplifier 31 and the wiring W1 (the input of the power amplifier 35) connecting the driver amplifier 33 and the power amplifier 35 can be electrically shielded, and the oscillation in the main system output signal can be reduced. In particular, although the solder ball 9a having the function of the input terminal P IN and the solder ball 9c having the function of the main system output terminal P OUT1 are provided on the adjacent sides 5a and 5c sides (see Figure 4 ), but according to the through-hole structure of the present embodiment, the solder balls 9a and 9c are electrically isolated from each other. As a result, the oscillation in the output signal can be reduced more effectively.

[0050] In particular, the length of the through-hole structure along the wiring is shorter than the length λ / 8 corresponding to the wavelength λ of the RF signal targeted by the microwave integrated circuit 1. According to such a configuration, a situation in which the through-hole structure functions as an antenna to pick up the RF signal can be prevented, and thus, the signal shielding effect of the plurality of through-hole structures can be improved. Further, since the interval between the plurality of through-hole structures along the wiring is also shorter than the length of λ / 8, the propagation of the RF signal between the plurality of through-hole structures can be prevented, and thus, the signal shielding effect of the plurality of through-hole structures can be improved, and the oscillation in the output signal can be reduced more effectively.

[0051] In addition, in the present embodiment, other through-hole structures are also formed connecting from the front surface of the semiconductor substrate 3 to the uppermost fourth layer wiring 19d. Therefore, a signal shielding effect can be exhibited between the semiconductor substrate 3 and the fourth layer wiring 19d, and thus, the oscillation of the output signal can be further reduced. In particular, since the other through-hole structures are formed in a rectangular shape along the sides 5a, 5b, 5c and 5d of the multilayer wiring layer 5, the propagation of the RF signal between the input terminal and the output terminal (for example, between the two solder balls 9a and 9c) passing through the outside of the sides 5a, 5b, 5c and 5d of the multilayer wiring layer 5 can be prevented.

[0052] In addition, the plurality of via structures provided in this embodiment are arranged in two columns along the wiring in a staggered manner. Therefore, by reducing the gap for linearly removing signals through a plurality of via structures arranged side by side and in parallel along the wiring, the RF signal shielding effect can be improved. As a result, the oscillation in the output signal can be reduced more effectively.

[0053] Figure 9 It is a graph showing the effect of preventing oscillation of the output signal (isolation effect between terminals) by the microwave integrated circuit 1. Here, compared with a comparative example that does not include a via structure, the intensity of the oscillation component (isolation between terminals) (dB) observed when changing the frequency of the RF signal processed in the main system in various ways is illustrated. According to this result, in the microwave integrated circuit 1, the oscillation intensity (isolation between terminals) at 38 GHz is increased by approximately 5 dB.

[0054] In addition, in the microwave integrated circuit 1 according to the embodiment, each amplification unit integrated on the semiconductor substrate 3 has a configuration of a current reuse type amplifier. For this reason, since the current supplied to the two-stage FETs included in the respective amplification units becomes a common current, it is not necessary to adjust the bias voltage to match the operating point of the FET. In addition, even when one FET constituting each amplification unit operates with a self-bias voltage and the other FET operates with a fixed bias voltage, it is possible to contribute to the adjustment of the bias voltage.

[0055] In addition, the microwave integrated circuit 1 adopts the following configuration: the bias voltages VDD1 to VDD3 are supplied as common bias voltages to a plurality of amplification units. With this configuration, it is possible to perform bias adjustment in a plurality of amplification units simultaneously and in parallel. Therefore, it is possible to further contribute to the adjustment of the bias voltage.

[0056] Previously, although the principles of the present disclosure have been illustrated and described in the preferred embodiments, those skilled in the art will understand that the present disclosure can be modified in arrangement and details without departing from the principles. The present disclosure is not limited to the specific configuration disclosed in this embodiment. Therefore, all modifications and changes derived from the scope and spirit of the claims are claimed.

[0057] In the above embodiment, although the wiring for supplying the bias voltage in the multilayer wiring layer 5 is formed in the third-layer wiring 19c, the wiring can be formed in other wiring layers except for the topmost layer wiring 19d and the bottommost layer wiring 19a. In this case, the via structures surrounding the wiring are arranged corresponding to the position of the wiring.

[0058] In addition, the plurality of via structures do not have to be electrically connected to both the uppermost layer wiring 19d and the lowermost layer wiring 19a, but the plurality of via structures can be connected to either the uppermost layer wiring 19d or the lowermost layer wiring 19a. Further, the ground wiring layer WG does not necessarily have to be formed on the uppermost layer wiring 19d. For example, the ground wiring layer WG can be formed on the lowermost layer wiring 19a. In this case, the plurality of via structures (including other via structures) are formed by the ground wiring layer WG that is electrically connected to the lowermost layer wiring 19a.

Claims

1. A microwave integrated circuit, comprising: A semiconductor substrate; A plurality of amplification units formed in the semiconductor substrate; A power supply line formed in one of the plurality of wiring layers formed on the semiconductor substrate, excluding the topmost wiring layer and the bottommost wiring layer, the power supply line being used to supply power to the plurality of amplification units; And A plurality of through holes connecting a plurality of conductive regions formed in the one wiring layer with the power supply line interposed therebetween and other conductive regions formed in regions sandwiching the power supply line in two wiring layers immediately above and immediately below the one wiring layer, Wherein each of the plurality of through holes forms a through hole structure, the through hole structure being connected to at least one of the topmost wiring layer and the bottommost wiring layer through a plurality of other through holes, and wherein the length of each of the plurality of through holes along the power supply line is shorter than λ / 8 corresponding to the signal wavelength λ targeted by the microwave integrated circuit.

2. The microwave integrated circuit according to claim 1, wherein, The interval of the plurality of through holes along the power supply line is shorter than λ / 8 corresponding to the signal wavelength λ targeted by the microwave integrated circuit.

3. The microwave integrated circuit according to claim 1 or 2, wherein, The plurality of through holes are grounded through the topmost wiring layer or the bottommost wiring layer.

4. The microwave integrated circuit according to claim 1 or 2, Among them, The semiconductor substrate has a rectangular planar shape, and has a signal input terminal on one side of the rectangle and a signal output terminal on another side adjacent to the one side, and Wherein the signal input terminal and the signal output terminal are electrically separated through the through hole structure.

5. The microwave integrated circuit according to claim 1 or 2, further comprising a plurality of other through holes penetrating the plurality of wiring layers and connecting the semiconductor substrate and the topmost wiring layer.

6. The microwave integrated circuit according to claim 1 or 2, wherein, The through hole structure further includes a plurality of additional through holes formed along the plurality of other through holes, and the plurality of other through holes and the plurality of additional through holes are arranged in a staggered manner with respect to each other.

7. A microwave integrated circuit, comprising: A first-stage amplifier configured to amplify an input high-frequency signal having a first frequency; A main system amplification stage configured to amplify and output a signal having the first frequency branched from the output of the first-stage amplifier; A branch stage configured to generate a signal having a double frequency of the first frequency by multiplying another signal having the first frequency branched from the output of the first-stage amplifier; And A subsystem amplification stage configured to amplify and output the signal having the double frequency output from the branch stage, Wherein the first-stage amplifier, the main system amplification stage, the branch stage, and the subsystem amplification stage are integrated on a common semiconductor substrate, and Among them, the amplifier circuits constituting the first-stage amplifier, the amplifier circuits included in the branch stage, the amplifier circuits included in the main system amplifier stage, and the amplifier circuits included in the subsystem amplifier stage are connected in series between the power supply and the ground in a DC manner, and each is a current-reuse type amplifier including two-stage transistors connected in series between the signal input and the signal output in an AC manner.

8. The microwave integrated circuit according to claim 7, Among them, The size ratio of the transistors included in the two amplifier circuits constituting the main system amplifier stage is 3:5, Among them, the size ratio of the transistors included in the two amplifier circuits constituting the subsystem amplifier stage is 8:15, and Among them, the ratio of the total size of the transistors constituting the main system amplifier stage to the total size of the transistors constituting the subsystem amplifier stage is 32:

23.

9. The microwave integrated circuit according to claim 7 or 8, wherein The branch stage includes two amplifier circuits and a frequency multiplier sandwiched between the two amplifier circuits, and the frequency multiplier includes a field effect transistor as a nonlinear element.

10. The microwave integrated circuit according to claim 9, Among them, The first power is commonly supplied to the first-stage amplifier and the first-stage amplifier circuit of the main system amplifier stage, Among them, the second power is commonly supplied to the two amplifier circuits included in the branch stage, Among them, the third power is commonly supplied to the amplifier circuits included in the subsystem amplifier stage, and Among them, the fourth power is supplied to the amplifier circuit of the last stage of the main system amplifier stage.

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