Charge pump with load-driven clock frequency management

Abstract

Embodiments of the present disclosure relate to charge pumps with load-driven clock frequency management. A charge pump circuit has load-driven clock frequency management. The charge pump circuit includes a CCO that generates a CCO output signal having a frequency that is generally proportional to a feedback current, and a charge pump that is operated by the CCO output signal and boosts a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sense circuit senses a load current drawn by the load, and generates the feedback current having a magnitude that varies as a function of the sensed load current if the magnitude of the load current is between a low load current threshold and a high load current. If the magnitude of the sensed load current is not between the low load current threshold and the high load current threshold, the magnitude of the feedback current does not vary with the sensed load current.

Description

Technical Field

[0001] This application relates to the field of charge pumps, and more particularly to charge pump circuits that use load current as feedback to regulate the oscillator within the charge pump circuit. Background Technology

[0002] Charge pumps are commonly used in analog electronic circuits to boost or invert voltages without using inductors. A typical charge pump utilizes a switched capacitor operated by a clock signal generated by an oscillator. Such charge pumps are effective for boosting or inverting voltages.

[0003] However, in some (or most) cases, the output of the charge pump is supplied to a variable load, meaning the load draws different amounts of current at different times. As explained, since the charge pump uses capacitors to provide the boosted voltage, it should be understood that as current is delivered by the charge pump, the charge stored in these capacitors is depleted. Therefore, when the charge pump delivers sufficient current, the output voltage of the charge pump will drop. Since the frequency of the oscillator used to operate the charge pump partially determines the recharging rate of the capacitors, it can be understood that, although the load draws current, the oscillator must operate at a sufficiently high frequency in order to keep the output voltage of the charge pump at a constant level.

[0004] One solution is to simply set the oscillator frequency at a sufficiently high constant frequency so that, under worst-case operating conditions, the capacitor charges fast enough to keep the voltage output by the charge pump at a constant level, independent of the current drawn by the load. However, the drawback of this approach is that losses due to the switching within the charge pump are high when the load is not drawing much current.

[0005] Another solution is to operate the oscillator in pulse-skipping mode, where the oscillator is enabled when load current is needed and disabled otherwise. This is sufficient to reduce pump losses when the load is not drawing much current. However, the downside is that pulse-skipping introduces unwanted harmonics, which is particularly undesirable when using a charge pump to drive a ballast transistor as a power source.

[0006] Therefore, further development in the field of charge pump technology is needed. Summary of the Invention

[0007] This document discloses a circuit including a current controller oscillator (CCO) configured to generate a CCO output signal at an output having a frequency generally proportional to the feedback current. A charge pump circuit operates by the CCO output signal and is configured to boost the supply voltage to generate a charge pump output voltage at the output, which is coupled to a load. A current sensing circuit is configured to sense the load current drawn by the load and, if the magnitude of the load current is between a low load current threshold and a high load current threshold, generates a feedback current having an amplitude varying according to the sensed load current. Note that if the magnitude of the sensed load current is not between the low load current threshold and the high load current threshold, the current sensing circuit does not generate a feedback current having an amplitude varying according to the sensed load current.

[0008] This document also discloses an embodiment of a method. The method involves using a charge pump, operating based on an output signal from a current-controlled oscillator (CCO), to boost a supply voltage to a charge pump output voltage supplied to a load. The method also includes sensing a load current flowing into the load due to the charge pump output voltage, and generating a feedback current generally proportional to the load current if the magnitude of the load current is between a low load current threshold and a high load current threshold. The method further includes adjusting the frequency of the output signal from the CCO based on the feedback current. Note that the frequency of the output signal is proportional to the feedback current. Attached Figure Description

[0009] Figure 1A This is a block diagram of an electronic device that uses a charge pump circuit to drive a load according to an embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A A schematic diagram of an electronic device, showing details of a charge pump circuit.

[0011] Figure 1C It is based on embodiments of this disclosure that utilize, such as Figures 1A to 1B A block diagram of an embodiment of an electronic device with a charge pump circuit to drive a ballast transistor.

[0012] Figure 2A This is a block diagram of an electronic device using a charge pump circuit to drive a load, according to another embodiment of the present disclosure.

[0013] Figure 2B yes Figure 2A A schematic diagram of an electronic device, showing details of a charge pump circuit.

[0014] Figure 2C yes Figure 2A A schematic diagram of an electronic device, showing details of another embodiment of a charge pump circuit.

[0015] Figure 2D It is according to an embodiment of this disclosure that the use of, such as Figure 2A-2C A block diagram of an embodiment of an electronic device with a charge pump circuit to drive a ballast transistor.

[0016] Figure 3 It is such as being able to Figure 1A-1C and Figure 2A-2D A schematic diagram of the current-controlled oscillator used in this study.

[0017] Figure 4 It shows that it is aimed at Figure 1A-1C and Figure 2A-2D The curve of load current versus frequency of the output signal of the current-controlled oscillator.

[0018] Figure 5 It is shown Figure 2C The actual feedback current characteristic of the charge pump circuit versus the load current curve.

[0019] Figure 6 It is shown Figure 2C The curves showing the load power supply characteristics of the charge pump circuit. Detailed Implementation

[0020] The following disclosure enables those skilled in the art to manufacture and use the technical solutions disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed or suggested herein. Note that in this detailed description section, components are described as “coupled,” meaning that these components can be directly electrically connected without intermediate components, or connected via other components.

[0021] First refer to Figure 1A Disclosed is an electronic device 50, which includes a charge pump circuit 100 to boost the supply voltage VCC to a charge pump output voltage VHCP applied to a load 60. The load 60 draws a load current ILOAD. A current sensor 99 senses the load current ILOAD and generates a feedback current IFBK representing the load current ILOAD (e.g., having an amplitude that varies according to the load current ILOAD, such as being proportional to the load current).

[0022] The current controller oscillator (CCO) 54 receives the feedback current IFBK and generates a CCO output signal OUTcco, which has a frequency that is proportional to the received feedback current IFBK (e.g., approximately proportional, proportional, directly proportional, or otherwise related to it). Therefore, as the amplitude of the feedback current IFBK increases, the frequency of the CCO output signal OUTcco increases.

[0023] Typically, a charge pump 100 includes a driver and a rectifier. The driver can be any switching circuit that generates a rectangular signal, and the rectifier can be any circuit that is correctly phase-commutated to deliver pumped charge to its output capacitor.

[0024] exist Figure 1B Further details of an exemplary configuration of a charge pump 100 for electronic device 50 are shown below. However, it should be understood that any charge pump satisfying the general description given above can be used. Here, inverters 51 and 55 receive the CCO output signal OUTcco as input. Inverter 51 provides its output to inverter 53. Capacitor C1 couples the output of inverter 53 to node N1. Capacitor C2 couples the output of inverter 55 to node N4. Capacitor C3 is coupled between power supply node VCC and node N2.

[0025] The bridge rectifier is formed by diodes D1-D4. Diode D1 has its anode coupled to node N1 and its cathode coupled to node N2. Diode D2 has its cathode coupled to node N1 and its anode coupled to node N3. Diode D3 has its anode coupled to node N3 and its cathode coupled to node N4. Diode D4 has its anode coupled to node N4 and its cathode coupled to node N2.

[0026] The operation of charge pump 100 will now be described. In this specification, it is assumed that “high” refers to the voltage of VCC and “low” refers to ground, although it should be understood that other values ​​may be used in some applications. For ease of explanation of the voltages at nodes and capacitors, the voltage drop across diodes will be neglected, but it should be understood that the actual voltage values ​​will be less than the stated voltage values ​​due to the voltage drop across diodes D1-D4.

[0027] Consider the startup conditions, where neither C1 nor C2 is charged, and assume the CCO output signal OUTcco is low. This causes the output of inverter 53 to go low and the output of inverter 55 to go high. Since the output of inverter 53 is low and capacitor C1 is not yet charged, node N1 will go low, diode D2 will be forward biased by VCC, and capacitor C1 will charge to VCC. At this time, since the output of inverter 55 is high and capacitor C2 is not yet charged, diode D3 will not be forward biased, and therefore capacitor C2 will not charge.

[0028] When the CCO output signal OUTcco goes high, the output of inverter 53 will go high, and the output of inverter 55 will go low. Since the output of inverter 53 is high, the potential at the output of inverter 53 is added to the potential stored in capacitor C1, meaning the voltage at node N1 will be 2*VCC. Since node N2 is at VCC, diode D1 will become forward biased, and capacitors C1 and C3 will share charge. As a result, assuming C1 and C3 have equal capacitance, capacitor C3 will be charged to 1.5*VCC. Also at this time, since the output of inverter 55 is low and capacitor C2 is not yet charged, node N4 will be low, diode D3 will be forward biased at VCC, and capacitor C2 will be charged to VCC.

[0029] Repeat this operation. Therefore, for example, when the CCO output signal OUTcco returns to low, the output of inverter 53 will go low, and the output of inverter 55 will go high. Since the output of inverter 55 is high, the potential at the output of inverter 55 is added to the potential stored in capacitor C2, meaning the voltage at node N4 will be 2*VCC. Since node N2 is at VCC, diode D4 will become forward biased, and capacitors C2 and C3 will share charge, resulting in capacitor C3 being charged to 1.75*VCC.

[0030] Ultimately, through this pumping that occurs in each half-cycle of the CCO output signal OUTcco, C3 will be charged to approximately 2*VCC.

[0031] The potential applications of the charge pump 100 and the frequency regulation of its CCO 54 via the directly received feedback current IFBK are discussed. Figure 1C The electronic device 60 is shown. Electronic device 60 includes a charge pump 100 and a CCO 54, which operate as described above. Here, the output VCHP of the charge pump 100 is used to bias the gate of a ballast NMOS transistor (power NMOS transistor) T1, which in turn provides an output OUT for powering other components (not shown). The ballast transistor T1 has its drain coupled to VCC and provides an output OUT at its source. Electronic device 60 also includes a pull-down NMOS transistor T2, having its drain coupled to the gate of the ballast NMOS transistor T1, its source coupled to ground, and its gate biased by a pull-down signal PULL DOWN. Additionally, a soft-start control circuit 52 is coupled to ground via a capacitor C2 and provides bias to the ballast transistor T1 during startup when the charge pump 100 charges its output.

[0032] The advantages of the charge pump 100 and CCO 54 arrangement become apparent in the context of the electronic device 60. Once the gate of the ballast transistor T1 is fully charged to put it into linear operation mode, the ballast transistor T1 draws very little current or no current from the charge pump 100. If the frequency of the CCO output signal OUTcco is constant, the high switching losses within the charge pump 100 will increase the consumed quiescent current. However, using the arrangement shown, where the feedback current IFBK controls the frequency of the CCO output signal OUTcco, the amplitude of the feedback current IFBK will be very low once the gate of the ballast transistor T1 is fully charged. This will result in a lower frequency of the CCO output signal OUTcco, reducing switching losses and thus reducing the power consumption of the electronic device 60. In fact, the frequency of the CCO output signal OUTcco may be as low as (or in some cases even lower) 100 kHz in this case, which will reduce switching losses by up to 60 times. With a high magnitude of feedback current IFBK indicating a high current flowing into the gate of ballast transistor T1, the frequency of the CCO output signal OUTcco may be as high as (or in some cases higher than) 6MHz, while VCHP remains at a constant level despite drawing high current.

[0033] Now for reference Figure 2A Disclosed is an electronic device 70 including a charge pump circuit 100 that boosts the supply voltage VCC to a charge pump output voltage VHCP applied to a load 60. The load 60 draws a load current ILOAD. A current sensor 56 senses the load current ILOAD and generates a feedback current IFBK, which has a generally constant magnitude when the load current ILOAD is below a low load current threshold, a generally constant or asymptotically increasing magnitude when the load current ILOAD is above a high load current threshold, and is related to the load current ILOAD when the load current ILOAD is between the low and high load current thresholds (e.g., nearly proportional, proportional, directly proportional, or other relationships).

[0034] Therefore, from Figure 4 As can be seen from the graph, the frequency of the CCO output signal OUTcco remains generally constant at a low frequency threshold when the load current ILOAD is below the low load current threshold, and generally remains constant at a high frequency threshold or asymptotically rises to the high frequency threshold when the load current ILOAD is above the high load current threshold. Furthermore, when the load current ILOAD is between the low and high load current thresholds, it is related to the load current ILOAD (e.g., almost proportional, proportional, directly proportional, or otherwise). Figure 4As can be seen, when the load current ILOAD is between the low and high load current thresholds, the frequency of the CCO output signal generally (but not perfectly) increases linearly. The purpose of controlling the frequency of the CCO output signal is to maintain the lowest possible output impedance of the charge pump 100 under all load conditions, while focusing on reducing switching losses.

[0035] The purpose of the feedback current IFBK generated by the current sensor 56 is to keep the frequency of the CCO output signal OUTcco at a minimum non-zero threshold, where the load current ILOAD is below the low load current threshold, so as to keep VCHP at a generally constant level. This allows the frequency of the CCO output signal OUTcco to increase as the load current ILOAD increases, so that VCHP remains at a generally constant level. This also protects the components of the charge pump 100 or the current sensor 56 from damage if the load current ILOAD rises above the high load current threshold, even if the load current ILOAD increases.

[0036] More details about the current sensor 56 of electronic device 70 are in Figure 2B As shown above. Here, CCO 54 and charge pump 100 are as described above. Figure 1B The current sensor 56 includes a current-sensing resistor R1 coupled between node N2 and load 60. The PMOS transistor DCT has its source coupled to node N2, its drain coupled to load 60, and its gate coupled to the drain. The PMOS transistor MP has its source coupled to node N2, its drain directly electrically connected to CCO 54 without intermediate components, and its gate coupled to the gate and drain of the PMOS transistor DCT.

[0037] In operation, the PMOS transistors MP and DCT form a current mirror, with the drain of DCT forming the input of the current mirror and the drain of MP forming the output. Therefore, IFBK is a mirror version of ILOAD, meaning the frequency of the CCO output signal OUTcco will be related to the load current ILOAD. Current sensing performed by current sensor 56 will work without resistor R1, but the result will be a drop of 1*VGS on DCT. To overcome this drawback and allow a higher VCHP under no-load conditions, resistor R1 is used. Resistor R1 does not contribute to current sensing but is used to ensure that VOUT eventually reaches VCHP in a completely unloaded state (where the gate of DCT is fully charged). The value of R1 can be high, such as 1MΩ, while the inherent output impedance of charge pump 100 at its maximum operating frequency can be 10kΩ.

[0038] Therefore, the output impedance of charge pump 100 will be 1MΩ until the voltage across R1 reaches the appropriate VGS to turn on the DCT (current sensing cannot be performed before this). Once the voltage across R1 reaches the appropriate VGS to turn on the DCT to begin current sensing, the output impedance will drop, and CCO 54 will begin tracking IFBK (and therefore, ILOAD).

[0039] In short, the current sensor 56 provides very little current or no current until the voltage drop across resistor R1 reaches the required VGS of the DCT, meaning the DCT is either off or in the subthreshold region. In this mode, the charge pump 100 operates at its minimum frequency. The advantage of this design of the current sensor 56 is that, under no-load conditions, it does not draw current from node N2, thus allowing the VCHP to be at its maximum possible value.

[0040] Another embodiment of the current sensor 56' of electronic device 70' is in Figure 2C As shown above. Here, CCO 54 and charge pump 100 are as described above. Figure 2B The current sensor 56' includes a current-sensing resistor R2 coupled between node N2 and load 60. A diode D is coupled between node N2 and load 60. A resistor R3 is coupled between node N2 and the source of PMOS transistor MP1. The drain of PMOS transistor MP1 generates a feedback current IFBK and is directly electrically connected to CCO 54 without any intermediate components. PMOS transistor MP2 has its source coupled to load 60, its drain coupled to current source 57, and its gate coupled to its drain and the gate of PMOS transistor MP1.

[0041] During operation, if the load current ILOAD is zero, the source voltages of PMOS transistors MP1 and MP2 will be equal, and MP1 and MP2 will act as current mirrors, causing the reference current IREF (e.g., 100nA) to be reflected to the drain of PMOS transistor MP1 as the feedback current IFBK. The minimum amplitude that IFBK will reach will be lower than the minimum current defined internally by CCO54. Therefore, the minimum frequency of OUTcco will be precisely defined internally by CCO54. Once IFBK becomes higher than the minimum current internally by CCO54, the frequency of OUTcco changes according to IFBK.

[0042] If the load current ILOAD is non-zero, but the voltage across resistor R2 (generated by the load current ILOAD flowing through R2) is insufficient to forward bias diode D, then the source voltages of PMOS transistors MP1 and MP2 will be unequal, and the current mirror operation will be unbalanced. In this case, the load current ILOAD will control the bias of PMOS transistor MP1, and the feedback current IFBK will be related to the load current ILOAD (e.g., almost proportional, proportional, directly proportional, or otherwise).

[0043] Once the voltage across resistor R2 becomes sufficient to forward bias diode D, diode D will clamp resistor R2, thereby reducing the output impedance of charge pump 54 under high load conditions. Before diode D becomes forward biased, CCO 54 outputs OUTcco at its maximum output frequency. Also in this case, the maximum frequency of OUTcco will be limited within CCO, rather than by the IFBK from current sensor 56.

[0044] Note that in Figure 2C In this design, the load current ILOAD does not flow through MP2, but rather through R2, and also through diode D at higher current points. The current source IREF is used to pre-bias the current mirror formed by PMOS transistors MP1 and MP2, resulting in a very small amplitude of the feedback current IFBK under no-load conditions. However, IFBK in this state cannot be used to set the minimum frequency of OUTcco; instead, the minimum frequency of OUTcco is set directly within CCO 54 itself.

[0045] therefore, Figure 2C The main advantage of this design is that current sensing starts from a very low load current ILOAD amplitude level because the current sensing is based on the ΔVGS of PMOS transistors MP2 and MP1. Current sensing continues until the voltage drop across R2 reaches saturation at the forward voltage of diode D. At this point, CCO 54 is already outputting OUTcco at its maximum frequency. Diode D helps ensure minimal output impedance under heavy load conditions. However, note that with this design, some current from charge pump 100 is consumed under no-load conditions.

[0046] exist Figure 2DThe potential use of the charge pump 100 and its frequency regulation of its CCO 54 via the feedback current IFBK are illustrated in electronic device 80. Electronic device 80 includes a charge pump 100 and CCO 54 operating as described above. Here, the output VCHP of the charge pump 100 is used to bias the gate of a ballast NMOS transistor (power NMOS transistor) T1, which in turn provides an output OUT for powering other components (not shown). Ballast transistor T1 has its drain coupled to VCC and provides an output OUT at its source. Electronic device 60 also includes a pull-down NMOS transistor T2, having its drain coupled to the gate of ballast NMOS transistor T2, its source coupled to ground, and its gate biased by a pull-down signal PULL DOWN. Furthermore, a soft-start control circuit 52 is coupled to ground via capacitor C2 and provides bias to ballast transistor T1 during startup when the charge pump 100 charges its output.

[0047] The advantages of the charge pump 100 and CCO 54 arrangement become apparent in the context of the electronic device 80. Once the gate of the ballast transistor T1 is fully charged to put it into linear operation mode, the ballast transistor T1 draws very little current or no current from the charge pump 100. If the frequency of the CCO output signal OUTcco is constant, the high switching losses within the charge pump 100 will increase the quiescent current consumed. However, using the arrangement shown, once the gate of the ballast transistor T1 is fully charged, the feedback current IFBK will be low, resulting in a lower frequency of the CCO output signal OUTcco, thereby reducing switching losses and thus reducing power. In this case, the frequency of the CCO output signal OUTcco can actually be as low as (or in some cases below) 100kHz, thus reducing switching losses by up to sixty times. With a high feedback current IFBK indicating a large current flowing into the gate of the ballast transistor T1, the frequency of the CCO output signal OUTcco can be as high as (or in some cases above) 6MHz, maintaining a constant VCHP despite the high current draw.

[0048] Figure 5 What is shown is for Figure 2C The feedback current IFBK of the charge pump circuit is proportional to the load current ILOAD. It can be seen that the feedback current IFBK is relatively proportional to the load current ILOAD until the current sensor 56' saturates, at which point the feedback current IFBK gradually increases towards the maximum current.

[0049] Figure 6 The image shown is for... Figure 2C The output voltage VOUT of the charge pump circuit 100 versus the load current ILOAD is plotted.

[0050] Now for reference Figure 3 For example, can be with Figure 1A-1C The sample CCO54 is used in conjunction with the devices shown in 2A-2D. A detailed description will be given below, but a brief description will follow first. In short, the CCO54 is a low-power oscillator designed as a two-phase structure to achieve minimal switching losses. The timing of one clock phase is defined by components M2, C4, M6, and M3, and the timing of the other clock phase is defined by components M4, C5, M7, and M5. Devices M8 and M9 are used for the reset capacitor. This CCO structure generates a symmetrical square wave signal, where the ratio between pulses and gaps is approximately 50:50 (depending on the matching of the components between the first and second phases).

[0051] More specifically, CCO 54 includes PMOS transistors M1-M5 coupled in a current mirror arrangement. The sources of PMOS transistors M1-M5 are coupled to VCC, and the gates of PMOS transistors M1-M5 are coupled to each other and to the drain of PMOS transistor M1.

[0052] A first current source 91 draws the maximum CCO current IMAX from the drain of PMOS transistor M1, and a second current source 92 draws the minimum CCO current IMIN from the drain of PMOS transistor M1. A current mirror is formed by NMOS transistors M10 and M11. The drain of M11 is coupled to current source 91, the source of M11 is coupled to ground, and the gate of M11 is coupled to the gate and drain of M10. The drain of M10 is coupled to receive IFBK and is coupled to the gate of M10, and the source of M10 is coupled to ground.

[0053] Capacitor C4 is coupled between the drain of PMOS transistor M2 and ground. NMOS transistor M6 has its gate coupled to the drain of PMOS transistor M2, its drain coupled to the drain of PMOS transistor M3, and its source coupled to ground. Capacitor C5 is coupled between the drain of PMOS transistor M4 and ground. NMOS transistor M7 has its drain coupled to the drain of PMOS transistor M5, its source coupled to ground, and its gate coupled to the drain of PMOS transistor M4.

[0054] Buffer 81 has its output coupled to the drain of PMOS transistor M5 and its first input coupled to NAND gate 85. Buffer 83 has its input coupled to the drain of PMOS transistor M3 and its output coupled to the first input of NAND gate 87. The output of NAND gate 85 is coupled to the second input of NAND gate 87, and the output of NAND gate 87 is coupled to the second input of NAND gate 85, thus forming an SR flip-flop. NMOS transistor M8 has its drain coupled to the drain of PMOS transistor M2, its source coupled to ground, and its gate coupled to the output of NAND gate 87. NMOS transistor M9 has its drain coupled to the drain of PMOS transistor M4, its source coupled to ground, and its gate coupled to the output of NAND gate 85. The CCO output signal OUTcco is generated at the output of NAND gate 85.

[0055] The feedback current IFBK is received by a current mirror formed by NMOS transistors M10 and M11. If IFBK is zero, the bias current for M1 is limited by the current IMIN drawn from current source 92, for example, setting the frequency for OUTcco to 100kHz. If the feedback current IFBK is higher than the current IMAX drawn from current source 91, the bias current for M1 is the sum of the currents IMIN and IMAX drawn from current source 92, for example, setting the frequency for OUTcco to 6MHz, since the drain current of M11 is limited by current source 91. If the feedback current IFBK is between IMAX and IMIN, the bias current for M1 is proportional to IFBK.

[0056] To understand the operation, assume that the output of buffer 81 is high and the output of buffer 83 is low. The low output of buffer 83 causes the output of NAND gate 87 to be high, which means that the output of NAND gate 85 (and therefore the CCO output signal OUTcco) will be low. The low output of NAND gate 85 and the low output of buffer 83 keep the output of NAND gate 87 high, and thus the output of NAND gate 85 stabilizes at this point.

[0057] When the output of NAND gate 87 is high, transistor M8 is turned on, so capacitor C4 is not charged. When the output of NAND gate 85 is low, NMOS transistor M9 is turned off, so capacitor C5 will be charged by PMOS transistor M4. Therefore, once capacitor C5 is fully charged to turn on transistor M7, current will be drawn from the input of buffer 81, and the output of buffer 81 will go low, thereby pulling the output of NAND gate 85 high (and thus CCO outputs the signal OUTcco), turning on transistor M9 and discharging capacitor C5.

[0058] At this point, NAND gate 85 remains high, causing the output of NAND gate 87 to go low. This turns off transistor M8, and capacitor C4 begins to charge from PMOS transistor M2. Once capacitor C4 is fully charged to turn on transistor M6, current is drawn from the input of buffer 83, causing the output of buffer 83 to go low, the output of NAND gate 87 to go high, and the initial conditions described above to be restored. This operation continues to cycle, generating the CCO output signal OUTcco, which has a frequency that depends on the time required for capacitors C4 and C5 to charge. The faster capacitors C4 and C5 charge, the higher the frequency of the CCO output signal OUTcco; the slower capacitors C4 and C5 charge, the lower the frequency of the CCO output signal OUTcco. Since the charging time of capacitors C4 and C5 is proportional to the magnitude of the bias current of M1 (such as the feedback current IFBK under certain operating conditions as described above), this means that the frequency of the CCO output signal OUTcco will be proportional to the magnitude of the feedback current IFBK.

[0059] Current source 91 is formed by NMOS transistor M13, having its drain coupled to the drain of PMOS transistor M1, its source coupled to the drain of NMOS transistor M11, and its gate coupled to the gate of M12. Current source 92 is formed by NMOS transistor M14, having its drain coupled to the drain of PMOS transistor M1, its source coupled to ground, and its gate coupled to the gates of NMOS transistors M13 and M12. NMOS transistor M12 has its drain coupled to current source 93 to receive a constant current, its source coupled to ground, and its gate coupled to the gates of NMOS transistors M13 and M14.

[0060] This is only possible with Figure 1A-1C and Figure 2A-2D The device shown is a CCO 54 design used in conjunction with other CCO designs. It should be understood that other CCO designs may also be suitable.

[0061] It should be understood that the operation of CCO 54 based on the received feedback signal IFBK is not pulse skipping and cannot be considered a pulse skipping mode. Although the frequency of the CCO output signal OUTcco varies, as those skilled in the art will understand, it does not skip pulses and continuously generates pulses for the CCO output signal OUTcco.

[0062] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure as disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A circuit comprising: A current controller oscillator (CCO) is configured to generate a CCO output signal at the CCO output with a frequency that is generally proportional to the feedback current. A charge pump circuit, operated by a CCO output signal and configured to increase the supply voltage to generate a charge pump output voltage at a charge pump output node associated with the output of the circuit, the output of which is coupled to a load; and A current sensing circuit includes a first transistor and a second transistor with their drains connected to the CCO. The current sensing circuit is configured to sense a load current drawn by the load and, if the magnitude of the load current is between a low load current threshold and a high load current threshold, generate a feedback current having an amplitude that varies according to the sensed load current. The sources of both the first and second transistors are directly connected to the charge pump output node, and the drain of the second transistor is connected to the load; or The sources of the first transistor and the second transistor are respectively connected to the charge pump output node via a resistor, the drain of the second transistor is connected to a current source, and the source of the second transistor is connected to the load.

2. The circuit of claim 1, wherein if the amplitude of the sensed load current is not between the low load current threshold and the high load current threshold, the current sensing circuit generates a feedback current that does not have an amplitude that varies according to the sensed load current.

3. The circuit of claim 1, wherein when the sources of the first transistor and the second transistor are directly connected to the charge pump output node, the current sensing circuit comprises: The first resistor is directly electrically connected between the output node of the charge pump and the output of the circuit. The second P-channel transistor is directly connected in series between the charge pump output node and the output of the circuit. and The first p-channel transistor has a source that is directly electrically connected to the output node of the charge pump and a drain that is directly electrically connected to the CCO.

4. The circuit of claim 3, wherein the drain of the first p-channel transistor is directly electrically connected to the CCO in an uninterrupted manner without intermediate components, such that the feedback current flows directly from the output of the circuit to the CCO.

5. The circuit of claim 1, wherein when the sources of the first transistor and the second transistor are respectively connected to the charge pump output node via a resistor, the current sensing circuit comprises: The first resistor is directly electrically connected between the charge pump output node and the output of the circuit. A diode is directly electrically connected between the charge pump output node and the output of the circuit; The second resistor has a first terminal that is directly electrically connected to the output node of the charge pump; The first p-channel transistor has a source that is directly electrically connected to the second terminal of the second resistor, a drain that is directly electrically connected to the CCO, and a gate; and The second p-channel transistor has a source that is directly electrically connected to the output of the circuit, a drain that is directly electrically connected to a reference current source to receive a reference current therefrom, and a gate that is directly electrically coupled to the gate of the first p-channel transistor and the drain of the second p-channel transistor. The first p-channel transistor generates the feedback current at its drain.

6. The circuit of claim 5, wherein the drain of the first p-channel transistor is directly electrically connected to the CCO in an uninterrupted manner without intermediate components, such that the feedback current flows directly from the output of the circuit to the CCO.

7. The circuit of claim 1, wherein if the sensed load current is below the low load current threshold, the current sensing circuit generates the feedback current which is generally constant.

8. The circuit of claim 1, wherein if the sensed load current is higher than the high load current threshold, the current sensing circuit generates a gradually increasing feedback current.

9. The circuit of claim 1, wherein the load is the gate of a power transistor, and the charge pump output voltage is used to charge the gate of the power transistor, and wherein once the power transistor is in linear operating mode, the frequency of the CCO output signal proportional to the feedback current is used to reduce the frequency of the CCO output signal.

10. The circuit of claim 1, wherein the charge pump circuit comprises: First capacitor, second capacitor, and third capacitor; The first inverter and the second inverter are coupled in series between the CCO output and the first plate of the first capacitor; A third inverter is coupled between the CCO output and the first terminal of the second capacitor; and Bridge rectifiers include: A first diode has an anode coupled to a first node and a cathode coupled to a second node, wherein the second node is a charge pump output node; The second diode has a cathode coupled to the first node and an anode coupled to the third node; The third diode has an anode coupled to the third node and a cathode coupled to the fourth node; and A fourth diode has an anode coupled to the fourth node and a cathode coupled to the second node; The second plate of the first capacitor is coupled to the first node; The second plate of the second capacitor is coupled to the fourth node; and The third capacitor has a first plate coupled to the power supply voltage and the third node, and a second plate coupled to the output of the charge pump circuit and the second node.

11. The circuit of claim 1, wherein the charge pump circuit lacks a switch.

12. The circuit of claim 1, wherein the CCO does not operate in pulse skipping mode.

13. A method for operating a circuit including a current-controlled oscillator (CCO), a charge pump, and a current sensor, comprising: The charge pump, which operates based on the output signal from the current-controlled oscillator (CCO), boosts the power supply voltage to a charge pump output voltage supplied to the load, wherein the charge pump output voltage is generated at a charge pump output node associated with the output of the circuit, the output of which is coupled to the load. The load current flowing into the load due to the output voltage of the charge pump is sensed by the current sensor, wherein the current sensor includes: a first transistor with its drain connected to the CCO; and a second transistor; If the magnitude of the load current is between a low load current threshold and a high load current threshold, a feedback current that is generally proportional to the load current is generated; and The frequency of the output signal from the CCO is adjusted according to the feedback current, wherein the frequency of the output signal is proportional to the feedback current. The sources of both the first and second transistors are directly connected to the charge pump output node, and the drain of the second transistor is connected to the load; or The sources of the first transistor and the second transistor are respectively connected to the charge pump output node via a resistor, the drain of the second transistor is connected to a current source, and the source of the second transistor is connected to the load.

14. The method of claim 13, wherein the load is the gate of a power transistor, and the charge pump output voltage is used to charge the gate of the power transistor, and wherein once the power transistor is in a linear operating mode, the frequency of the output signal from the CCO is adjusted according to the feedback current to reduce the frequency of the output signal from the CCO.

15. The method of claim 13, wherein if the magnitude of the load current is not between the low load current threshold and the high load current threshold, the feedback current is not generated in a manner generally proportional to the load current.

16. The method of claim 13, wherein adjusting the frequency of the output signal from the CCO does not involve operating the CCO in a pulse-skipping mode.

17. A circuit comprising: A current controller oscillator (CCO) with a CCO input and a CCO output; The charge pump circuit includes: First capacitor, second capacitor, and third capacitor; The first inverter and the second inverter are coupled in series between the CCO output and the first plate of the first capacitor; A third inverter is coupled between the CCO output and the first terminal of the second capacitor; and Bridge rectifiers include: The first diode has an anode coupled to a first node and a cathode coupled to a second node; The second diode has a cathode coupled to the first node and an anode coupled to the third node; The third diode has an anode coupled to the third node and a cathode coupled to the fourth node; and A fourth diode has an anode coupled to the fourth node and a cathode coupled to the second node; The second plate of the first capacitor is coupled to the first node; The second plate of the second capacitor is coupled to the fourth node; and The third capacitor has a first plate coupled to the power supply voltage and the third node, and a second plate coupled to the output of the charge pump circuit and the second node; and The current sensing circuit includes: The first resistor is directly electrically connected between the second node and the output of the circuit. The second P-channel transistor is directly connected in series between the second node and the output of the circuit; and The first p-channel transistor has a source that is directly electrically connected to the second node and a drain that is directly electrically connected to the CCO.

18. The circuit of claim 17, wherein the drain of the first p-channel transistor is directly electrically connected to the CCO in an uninterrupted manner without any intermediate components.

19. A circuit comprising: A current controller oscillator (CCO) with a CCO input and a CCO output; The charge pump circuit includes: First capacitor, second capacitor, and third capacitor; The first inverter and the second inverter are coupled in series between the CCO output and the first plate of the first capacitor; A third inverter is coupled between the CCO output and the first terminal of the second capacitor; and Bridge rectifiers include: The first diode has an anode coupled to a first node and a cathode coupled to a second node; The second diode has a cathode coupled to the first node and an anode coupled to the third node; The third diode has an anode coupled to the third node and a cathode coupled to the fourth node; and A fourth diode has an anode coupled to the fourth node and a cathode coupled to the second node; The second plate of the first capacitor is coupled to the first node; The second plate of the second capacitor is coupled to the fourth node; and The third capacitor has a first plate coupled to the power supply voltage and the third node, and a second plate coupled to the output of the charge pump circuit and the second node; and The current sensing circuit includes: The first resistor is directly electrically connected between the second node and the output of the circuit. The diode is directly electrically connected between the second node and the output of the circuit; The second resistor has a first terminal that is directly electrically connected to the second node; The first p-channel transistor has a source directly electrically connected to the second terminal of the second resistor, a drain directly electrically connected to the CCO, and a gate; and The second p-channel transistor has a source that is directly electrically connected to the output of the circuit, a drain that is directly electrically connected to a reference current source to receive a reference current therefrom, and a gate that is directly electrically coupled to the gate of the first p-channel transistor and the drain of the second p-channel transistor.

20. The circuit of claim 19, wherein the drain of the first p-channel transistor is directly electrically connected to the CCO input in an uninterrupted manner without intermediate components.

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