Semiconductor storage device

Abstract

An embodiment of the present invention provides a semiconductor storage device capable of reducing power consumption. The semiconductor storage device of the embodiment of the present invention has a laminate, a first column, and a second column. The laminate is formed by alternately laminating a plurality of conductive layers and a plurality of insulating layers along a first direction. The first column is disposed in the laminate. The second column is disposed in the laminate and is parallel to the first column in the first direction. The second column includes a channel film. The first column includes a channel film, a core, and a conductive layer. The core is disposed on the central side of the first column in the second direction relative to the channel film of the first column. The conductive layer is disposed between the channel film of the second column and the core in the first direction in a manner that is in contact with the channel film of the second column. The conductive layer includes at least one of a metal layer and a silicide layer.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2019-049665 (filing date: March 18, 2019). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0004] A NAND (Not And) type flash memory in which memory cells are three-dimensionally stacked is known. Summary of the invention

[0005] The present invention provides a semiconductor storage device capable of reducing power consumption.

[0006] The semiconductor storage device of the embodiment has a stacked body, a first columnar body, and a second columnar body. The stacked body is formed by alternately stacking a plurality of conductive layers and a plurality of insulating layers along a first direction. The first columnar body is arranged in the stacked body. The second columnar body is arranged in the stacked body and is parallel to the first columnar body in the first direction. The second columnar body includes a channel film. The first columnar body includes a channel film, a core, and a conductive layer. The core is arranged on the central side of the first columnar body in the second direction than the channel film of the first columnar body. The conductive layer is arranged between the channel film of the second columnar body and the core in the first direction in a manner of contacting with the channel film of the second columnar body. The conductive layer includes at least one of a metal layer and a silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing the system configuration of the semiconductor storage device according to the first embodiment.

[0008] Figure 2 This is a diagram showing an equivalent circuit of the memory cell array according to the first embodiment.

[0009] Figure 3 It is a plan view showing a part of the memory cell array according to the first embodiment.

[0010] Figure 4 It is a cross-sectional view showing a part of the memory cell array according to the first embodiment.

[0011] Figure 5 This is an enlarged cross-sectional view of a boundary portion between a first columnar body and a second columnar body of the memory cell array according to the first embodiment.

[0012] Figure 6 It is a cross-sectional view showing an example of a manufacturing step of the memory cell array according to the first embodiment.

[0013] Figure 7 It is a cross-sectional view showing an example of a manufacturing step of the memory cell array according to the first embodiment.

[0014] Figure 8 It is a cross-sectional view showing an example of a manufacturing step of the memory cell array according to the first embodiment.

[0015] Fig. 9 It is a cross-sectional view showing an example of a manufacturing step of the memory cell array according to the first embodiment.

[0016] Fig.10 This is a cross-sectional view showing an enlarged upper end portion of a first columnar body in an example of a manufacturing step of the memory cell array according to the first embodiment.

[0017] Fig.11 This is a cross-sectional view showing an enlarged upper end portion of a first columnar body in an example of a manufacturing step of the memory cell array according to the first embodiment.

[0018] Fig.12 This is a cross-sectional view showing an enlarged upper end portion of a first columnar body in an example of a manufacturing step of the memory cell array according to the first embodiment.

[0019] Fig.13 This is a cross-sectional view showing an enlarged upper end portion of a first columnar body in an example of a manufacturing step of the memory cell array according to the first embodiment.

[0020] Fig.14 This is an enlarged cross-sectional view of a boundary portion between a first columnar body and a second columnar body of a conventional memory cell array.

[0021] Fig.15 This is an enlarged cross-sectional view of a boundary portion between a first columnar body and a second columnar body of a memory cell array according to a second embodiment.

[0022] Fig.16 This is a cross-sectional view showing an enlarged upper end portion of a first pillar in an example of a manufacturing step of a memory cell array according to the second embodiment.

[0023] Fig.17 This is a cross-sectional view showing an enlarged upper end portion of a first pillar in an example of a manufacturing step of a memory cell array according to the second embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, a semiconductor memory device of an embodiment will be described with reference to the accompanying drawings. In the following description, the same reference symbols are used to mark the components having the same or similar functions. For components having the same or similar functions, the description is sometimes not repeated. The numbers following the characters constituting the reference symbols are used to distinguish between elements having the same structure that are referenced by reference symbols containing the same characters. In the case where it is not necessary to distinguish between the elements represented by reference symbols containing the same characters, these elements are referenced by reference symbols containing only the same characters.

[0025] In the following description, the +X direction, -X direction, +Y direction, and -Y direction are directions parallel to the surface of the semiconductor substrate of the semiconductor storage device of the embodiment. The +X direction is the direction from one string group toward another string group of the semiconductor storage device of the embodiment. The -X direction is the opposite direction of the +X direction. When the +X direction and the -X direction are not distinguished, these directions are simply referred to as the "X direction". The +Y direction and the -Y direction are directions intersecting the X direction. The -Y direction is the opposite direction of the +Y direction. When the +Y direction and the -Y direction are not distinguished, these directions are simply referred to as the "Y direction". The +Z direction and the -Z direction are directions intersecting the X direction and the Y direction. The +Z direction is the direction from the semiconductor substrate of the semiconductor storage device of the embodiment toward the laminate (refer to Figure 4 ). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, these directions are simply referred to as the "Z direction". Sometimes the "+Z direction" is referred to as "up" and the "-Z direction" is referred to as "down". The expressions "up" and "down" are for convenience and do not define the direction of gravity. In this embodiment, the +Z direction is an example of the "first direction".

[0026] In this specification, "connection" includes not only physical connection but also electrical connection. In this specification, "extending in direction A" means, for example, that the dimension in direction A is greater than the smallest dimension among the dimensions in directions X, Y, and Z. "Direction A" is an arbitrary direction.

[0027] (First embodiment)

[0028] The overall configuration of the semiconductor memory device according to the first embodiment will be described. The semiconductor memory device according to the present embodiment is a nonvolatile semiconductor memory device, such as a NAND flash memory.

[0029] Figure 1 1 is a block diagram showing a system configuration of a semiconductor memory device 1 according to the present embodiment. The semiconductor memory device 1 includes a memory cell array 10 , a row decoder 11 , a sense amplifier 12 , and a sequencer 13 .

[0030] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn. n is an integer greater than or equal to 1. Each block BLK is a collection of a plurality of nonvolatile memory cell transistors. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with one bit line and one word line.

[0031] The row decoder 11 selects one block BLK based on address information ADD received from the external memory controller 2. The row decoder 11 controls the writing and reading operations of data to and from the memory cell array 10 by applying desired voltages to each of a plurality of word lines.

[0032] The sense amplifier 12 applies a desired voltage to each of the plurality of bit lines according to the data DAT received from the memory controller 2. The sense amplifier 12 determines the data stored in the memory cell transistor based on the voltage of the bit line and transmits the determined data DAT to the memory controller 2.

[0033] The sequencer 13 controls the overall operation of the semiconductor memory device 1 based on the command CMD received from the memory controller 2 .

[0034] The combination of the semiconductor storage device 1 and the memory controller 2 described above constitutes one semiconductor device. Examples of the semiconductor device include a memory card such as an SD (registered trademark) card (secure digital card) or an SSD (Solid State Drive).

[0035] Next, the electrical structure of the memory cell array 10 will be described. Figure 2 1 is a diagram showing an equivalent circuit of the memory cell array 10, showing one block BLK. The block BLK includes a plurality of string groups SU. Figure 2 In the block BLK, there are four string groups SU0-SU3.

[0036] The string group SU is a collection of multiple NAND strings NS. One end of each NAND string NS is connected to any one of multiple bit lines BL0 to BLm. m is an integer greater than 1. The other end of each NAND string NS is connected to a source line SL. The NAND string NS includes multiple memory cell transistors MT, a first selection transistor ST1, and a second selection transistor ST2. Figure 2 In the example, the NAND string NS includes 15 memory cell transistors MT0 to MT14.

[0037] A plurality of memory cell transistors MT are connected in series. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data in a non-volatile manner. The memory cell transistor MT stores charge in the charge storage film according to the voltage applied to the control gate. The control gate of the memory cell transistor MT is connected to any one of the plurality of word lines WL. Figure 2 15 word lines WL0 to WL14 are shown in FIG. Memory cell transistors MT are connected to the row decoder 11 via corresponding word lines WL.

[0038] The first selection transistor ST1 is connected between the plurality of memory cell transistors MT and the corresponding bit lines BL. The drain of the first selection transistor ST1 is connected to the bit line BL. The source of the first selection transistor ST1 is connected to the plurality of memory cell transistors MT. The control gate of the first selection transistor ST1 is connected to the corresponding selection gate line SGD. Figure 2 The selection gate line SGD corresponding to the control gate of the first selection transistor ST1 is any one of the selection gate lines SGD0 to SGD3. The first selection transistor ST1 is connected to the row decoder 11 via the selection gate line SGD. When a specified voltage is applied to the selection gate line SGD, the first selection transistor ST1 connects the NAND string NS to the bit line BL.

[0039] The second selection transistor ST2 is connected between a plurality of memory cell transistors MT and a source line SL. The drain of the second selection transistor ST2 is connected to a plurality of memory cell transistors MT. The source of the second selection transistor ST2 is connected to the source line SL. The control gate of the second selection transistor ST2 is connected to the selection gate line SGS. The second selection transistor ST2 is connected to the row decoder 11 via the selection gate line SGS. When a specified voltage is applied to the selection gate line SGS, the second selection transistor ST2 connects the NAND string NS to the source line SL.

[0040] Next, the physical structure of the memory cell array 10 will be described. Figure 3 1 is a top view of a portion of the memory cell array 10. For example, a plurality of string groups SU are arranged along the X direction. Figure 3 2 strings SU0 and SU1 are shown in FIG. Each string SU extends in the Y direction. In the X direction, the plurality of string SUs are separated from each other by slits SLT filled with insulating material. Each string SU includes a plurality of columns 40 extending in the Z direction. Each column 40 is connected to a bit line BL via a contact plug BLC. The bit line BL extends in the X direction.

[0041] Figure 4 2 is a cross-sectional view of a portion of the memory cell array 10. The memory cell array 10 includes a semiconductor substrate 20, a laminate 30, a plurality of pillars 40, a plurality of contact plugs BLC, and a plurality of bit lines BL. Figure 4 One contact plug BLC and one bit line BL are shown in FIG.

[0042] The semiconductor substrate 20 extends in the X direction and the Y direction. An insulating layer 22 is provided on the semiconductor substrate 20. A driving circuit including a CMOS (Complementary MOS (Complementary Metal Oxide Semiconductor)) and the like is provided inside the insulating layer 22. A conductive layer 23 is provided on the insulating layer 22. The conductive layer 23 is formed in a plate shape substantially parallel to the X direction and the Y direction, and functions as a source line SL.

[0043] The laminate 30 is provided on the conductive layer 23. The laminate 30 includes one conductive layer 31, a plurality of conductive layers 32, a plurality of conductive layers 33, and a plurality of insulating layers 34. Figure 4 Two conductive layers 33 are shown in FIG. The conductive layers 31 , 32 , 33 and the insulating layer 34 are stacked along the Z direction.

[0044] The conductive layers 31, 32, and 33 are formed of tungsten, for example. The conductive layer 31 is the bottom conductive layer in the laminate 30. The conductive layer 31 functions as a selection gate line SGS. The conductive layer 33 is the top conductive layer in the laminate 30 and a conductive layer below it. The conductive layer 33 functions as a selection gate line SGD. A plurality of conductive layers 32 are located above the conductive layer 31 and below the conductive layer 33. A plurality of conductive layers 32 function as word lines WL0 to WL14. The conductive layers 31, 32, and 33 are formed in a plate shape along the X direction and the Y direction, respectively. A blocking insulating film may be provided at the interface between each of the conductive layers 31, 32, and 33 and the insulating layer 34, and at the interface between each of the conductive layers 31, 32, and 33 and the columnar body 40.

[0045] The insulating layer 34 is formed of, for example, silicon oxide. The insulating layer 34 is provided between the conductive layer 31 and the conductive layer 32, between the plurality of conductive layers 32, between the conductive layer 32 and the conductive layer 33, and between the plurality of conductive layers 33. The insulating layer 34 insulates the conductive layers 31, 32, and 33 from each other. The insulating layer 34 is formed in a plate shape along the X direction and the Y direction.

[0046] The columnar body 40 functions as, for example, one NAND string NS. The columnar body 40 is provided in the stacked body 30 along the Z direction. The columnar body 40 is provided from the upper surface 30b to the lower surface 30a of the stacked body 30 in the Z direction. The columnar body 40 includes a first columnar body 40A and a second columnar body 40B.

[0047] The first columnar body 40A is provided in the stacked body 30. The lower end 40c of the first columnar body 40A is in contact with the conductive layer 23. The portion where the first columnar body 40A intersects with the conductive layer 33 functions as the first selection transistor ST1. The portions where the first columnar body 40A intersects with the plurality of conductive layers 32 function as memory cell transistors MT, respectively. Figure 4 17 memory cell transistors MT0 to MT14 are shown in FIG. A portion where the second pillar 40B intersects the conductive layer 33 functions as a second selection transistor ST2 .

[0048] The width of the first columnar body 40A in the X direction and the Y direction gradually decreases as it goes from the upper end 40d toward the lower end 40c. When viewed from the Z direction, the first columnar body 40A is, for example, circular or elliptical.

[0049] The first columnar body 40A includes at least a channel film 44, a core 45, and a conductive layer 99. The core 45 is disposed on the central side of the first columnar body 40A more than the channel film 44 in the X direction and the Y direction. In the present embodiment, the X direction and the Y direction are examples of a "second direction" intersecting the first direction. The conductive layer 99 includes at least one of a metal layer and a silicide layer. In the first embodiment, the conductive layer 99 includes a metal layer 52, and is disposed on the central side of the first columnar body 40A more than the channel film 44 in the X direction and the Y direction. The metal layer 52 is disposed at the end of the first columnar body 40A facing the second columnar body 40B. The metal layer 52 is located between the core 45 and the second columnar body 40B in the Z direction.

[0050] The first columnar body 40A further includes a barrier film 41, a charge storage film 42, a tunnel film 43, and an overlying layer 51. The barrier film 41 is provided on the inner wall of a hole penetrating the conductive layer 31, the conductive layer 32, and the insulating layer 34 below the uppermost conductive layer 32 in the Z direction. The barrier film 41 is a film that can prevent charges from moving from the conductive layer 32 to the charge storage film 42 or the core 45.

[0051] The first columnar body 40A includes a charge storage film 42 disposed on the opposite side of the core 45 and the conductive layer 99 relative to the channel film 44. The charge storage film 42 is disposed on the inner wall of the barrier film 41. The charge storage film 42 is a film capable of storing charges according to the voltage applied to the selection gate line SGD. The tunnel film 43 is disposed on the inner wall of the charge storage film 42. The tunnel film 43 is a film that allows a cell current from the channel film 44 to flow to the charge storage film 42 through a tunneling effect. The channel film 44 is disposed on the inner wall of the tunnel film 43. The channel film 44 functions as a channel of a transistor constituting the NAND string NS.

[0052] The core 45 is arranged on the central side of the second columnar body 40B in the X direction and the Y direction relative to the channel film 49. The core 45 becomes a pillar for the barrier film 41, the charge storage film 42, the tunnel film 43, and the channel film 44 to be arranged across the Z direction. The core 45, the upper cladding layer 51, and the metal layer 52 are arranged in the region surrounded by the tunnel film 43 in the X direction and the Y direction. The upper cladding layer 51 is arranged on the core 45. The upper cladding layer 51 is a layer capable of suppressing the movement or diffusion of the metal element from the metal layer 52. The metal layer 52 is arranged on the upper cladding layer 51. The metal layer 52 forms a path for the unit current from the channel film 49 arranged above to flow to the channel film 44. The first columnar body 40A includes, in order from the radial inner side with the center of the core 45 as the radial center in the cross section intersecting the Z direction, the core 45, the cladding layer 51, any one of the metal layers 52, the channel film 44, the tunnel film 43, the charge storage film 42, and the barrier film 41.

[0053] The barrier film 41 is formed of an insulator such as silicon oxide, aluminum oxide, and zirconium oxide. The charge storage film 42 is formed of an insulator such as silicon nitride. The tunnel film 43 is formed of an insulator such as silicon oxide. The channel film 44 is formed of a semiconductor such as polycrystalline silicon in which impurities are doped. The impurities contained in the channel film 44 are, for example, any one selected from the group consisting of carbon, phosphorus, boron, and germanium. The core 45 is formed of an insulator such as silicon oxide. The overlying layer 51 is formed of a semiconductor such as amorphous silicon. The metal layer 52 is formed of a metal such as tungsten.

[0054] When viewed along the Z direction, the entire core 45 is covered by the upper cladding layer 51, and the entire upper cladding layer 51 is covered by the metal layer 52. The upper cladding layer 51 is in contact with the channel film 44 in any direction including the X direction and the Y direction and intersecting the Z direction. The metal layer 52 is in contact with the channel film 44 in any direction intersecting the Z direction. The thickness of the metal layer 52 in the Z direction is thinner than the thickness of the upper cladding layer 51 in the Z direction.

[0055] The second column 40B is disposed in the stacked body 30 and is parallel to the first column 40A in the Z direction. In the present embodiment, the second column 40B is located above the first column 40A. The lower end 40e of the second column 40B is in contact with the first column 40A. The upper end 40f of the second column 40B is connected to the bit line BL via the contact plug BLC. The second column 40B can electrically connect the contact plug BLC to the first column 40A. The width of the second column 40B in the X direction and the Y direction gradually becomes thinner as it moves from the upper end 40f toward the lower end 40e. When viewed from the Z direction, the second column 40B is, for example, circular or elliptical.

[0056] The second columnar body 40B includes at least the channel film 49 and the core 50 provided closer to the center of the second columnar body 40B than the channel film 49 in the X direction and the Y direction. The metal layer 52 is in contact with the channel film 44 and the channel film 49 .

[0057] The second columnar body 40B includes a barrier film 46, a charge storage film 47, a tunnel film 48, a channel film 49, and a core 50. The barrier film 46 is provided on the inner wall of a hole that penetrates the conductive layer 33 and the insulating layer 34 above the uppermost conductive layer 32 in the Z direction. The charge storage film 47 is provided on the inner wall of the barrier film 46. The tunnel film 48 is provided on the inner wall of the charge storage film 47. The channel film 49 is provided on the inner wall of the tunnel film 48. The core 50 is provided in a region surrounded by the tunnel film 48 in the X direction and the Y direction. That is, the second columnar body 40B includes the core 50, the channel film 49, the tunnel film 48, the charge storage film 47, and the barrier film 46 in order from the inside.

[0058] The barrier film 46 is a film that can prevent charges from moving from the conductive layer 33 to the charge storage film 42 or the core 45. The charge storage film 47 is a film that can store charges according to the voltage applied to the selection gate line SGD. The tunnel film 48 is a film that allows the cell current from the channel film 44 to flow to the charge storage film 47 through the tunneling effect. The channel film 49 functions as a channel of the transistor constituting the NAND string NS together with the channel film 44.

[0059] The core 50 serves as a support for arranging the barrier film 46 , the charge storage film 47 , the tunnel film 48 , and the channel film 49 in the Z direction.

[0060] The barrier film 46 is formed of, for example, silicon oxide, aluminum oxide, and zirconium oxide. The charge storage film 47 is, for example, silicon nitride. The tunnel film 48 is, for example, formed of silicon oxide. The channel film 49 is, for example, formed of polysilicon doped with impurities in a portion. In order to adjust the threshold current of the selection gate line SGD, impurities such as boron are appropriately injected into the channel film 49 in the region close to the metal layer 52 in the Z direction. The core 50 is, for example, formed of silicon oxide.

[0061] Figure 5 40A is an enlarged cross-sectional view of the boundary between the first columnar body 40A and the second columnar body 40B. The channel film 49 is provided on the inner wall of the hole that reaches below the upper end 40f and enters the metal layer 52. That is, the channel film 49 is in contact with the metal layer 52.

[0062] The metal layer 52 has an end face 52d (first face) facing the second columnar body 40B. The end face 52d has a recessed portion 95 that is recessed toward the core 45. The lower end portion of the channel film 49 is located in the recessed portion 95. As a result, the contact surface between the channel film 49 and the metal layer 52 is increased, and therefore, the contact resistance between the channel film 49 and the channel film 44 is reduced compared to the case where the lower end portion of the channel film 49 is not located in the recessed portion 95.

[0063] At the lower end of the second columnar body 40B, the charge storage film 47 is folded under the tunnel film 48. Also, at the lower end of the second columnar body 40B, the barrier film 46 is folded under the charge storage film 47.

[0064] When viewed from the Z direction, the width of the lower end portion 49x in contact with the metal layer 52 in the channel film 49 is smaller than the width of the end surface 52d on the upper side of the metal layer 52 including the portion in contact with the channel film 49. In the cross section of the first columnar body 40A including the end surface 52d, the metal layer 52, the channel film 44, the tunnel film 43, the charge storage film 42, and the barrier film 41 are arranged in order from the inside.

[0065] The first columnar body 40A has a first connection end 91 connected to the second columnar body 40B. The second columnar body 40B has a second connection end 92 connected to the first columnar body 40A. The channel film 49 has a first channel end 93a as one end in the X direction and the Y direction, and a second channel end 93b as the other end in the X direction and the Y direction. The length of the metal layer 52 in the first connection end 91 in the X direction and the Y direction is longer than the length between the first channel end 93a and the second channel end 93b in the second connection end 92 in the X direction and the Y direction.

[0066] When viewed along the Z direction, the charge storage film 47 and the tunnel film 48 overlap with the metal layer 52 and are surrounded by the metal layer 52 .

[0067] The contact plug BLC is a connection member formed of a conductive material in a columnar or inverted truncated cone shape.

[0068] Next, an example of a method for manufacturing the memory cell array 10 is described. The method for manufacturing the memory cell array 10 includes, for example, a pre-step, a first stacking step, a first hole forming step, a second stacking step, an opening forming step, a channel film forming step, a thinning step, a core forming step, a replacement step, a slit processing step, an upper cladding layer forming step, and a metal layer forming step. Figures 6 to 13 1 and 2 are cross-sectional views showing each manufacturing step of the memory cell array 10 .

[0069] In the previous step, the insulating layer 22 and the conductive layer 23 are formed on the semiconductor substrate 20. In the insulating layer 22, a driving circuit including a CMOS and the like is formed.

[0070] Figure 6 2 is a cross-sectional view showing the first lamination step. In the first lamination step, the insulating layer 34 and the replacement material 150 are alternately laminated on the conductive layer 23. A plurality of insulating layers 34 and a plurality of replacement materials 150 are alternately laminated to form a laminate 39. The replacement material 150 is, for example, a nitride film such as silicon nitride. An insulating layer 334 is formed on the uppermost insulating layer 34. The insulating layer 334 is, for example, tetraethyl orthosilicate (TEOS).

[0071] Figure 7 2 is a cross-sectional view showing the first hole forming step. In the first hole forming step, a hole H1 is processed in the laminate 39. The hole H1 extends from the upper surface to the lower surface of the laminate 39. The hole H1 is processed by photolithography and anisotropic etching. As anisotropic etching, for example, reactive ion etching (RIE) can be used.

[0072] Figure 8 2 is an enlarged cross-sectional view showing the second lamination step and the channel film forming step. In the second lamination step, the barrier film 41, the charge storage film 42, the tunnel film 43, and the cover insulating film (not shown) are sequentially laminated on the inner wall of the hole H1 and the upper surface of the insulating layer 334. The barrier film 41, the charge storage film 42, the tunnel film 43, and the cover insulating film each have a bottom and are formed in a cylindrical shape.

[0073] In the opening forming step, an opening is formed at the bottom of the barrier film 41, the charge storage film 42, the tunnel film 43, and the cover insulating film. The opening is formed, for example, by RIE. After the opening is formed, the cover insulating film is removed. The cover insulating film is removed, for example, by etching. In the opening, the upper surface of the conductive layer 23 is exposed.

[0074] In the channel film forming step, a channel film 68 is formed on the inner wall and the upper surface of the tunnel film 43. Since an opening is formed at the bottom of the tunnel film 43, the channel film 68 is connected from the upper surface of the laminate 39 to the upper surface of the conductive layer 23. Impurities are doped into the channel film 68 during the film formation. The impurities are supplied in the form of gas, for example, and doped into the channel film 68.

[0075] In the channel film forming step, for example, the first layer 481, the second layer 482, and the third layer 483 are formed in order from the inner surface of the tunnel film 43. When the first layer 481 and the third layer 483 are formed, impurities are not supplied to the first layer 481 and the third layer 483. The first layer 481 and the third layer 483 are, for example, non-doped amorphous silicon. When the second layer 482 is formed, impurities are supplied to the second layer 482. The second layer 482 is, for example, amorphous silicon doped with carbon.

[0076] Then, the first layer 481, the second layer 482, and the third layer 483 are heated. Amorphous silicon is crystallized into polycrystalline silicon by heating. The first layer 481 and the third layer 483 become, for example, non-doped polycrystalline silicon. The second layer 482 becomes, for example, polycrystalline silicon doped with carbon. By heating, a part of the impurities contained in the second layer 482 diffuses into the first layer 481 and the third layer 483.

[0077] Then, the film formed in the thinning step is thinned. In the thinning step, the surface of the channel film 68 is oxidized, and then the oxide film is etched. The surface oxidation of the channel film 68 is performed using, for example, hydrogen peroxide. The etching of the oxide film is performed using, for example, trimethyl-2-hydroxyethylammonium hydroxide (TMY). In the thinning step, for example, a portion of the channel film 68 is removed until the second layer 482. The channel film 68 is thinned by the thinning step compared to the film formation, and becomes the channel film 44.

[0078] Fig. 9 2 is a cross-sectional view showing a core forming step and a replacement step. In the core forming step, a core 45 is formed on the inner wall of the hole H1 in the thinned channel membrane 44. The core 45 is filled inside the region surrounded by the channel membrane 44 in the X direction and the Y direction. By forming the core 45, the first columnar body 40A is formed.

[0079] Then, the stacked body 39 is divided into a plurality of string groups SU by forming slits SLT in a slit processing step. Fig. 9 1 shows one of the plurality of string groups SU. In the replacement step, the replacement material 150 is removed by wet etching through the slit SLT. Then, the space obtained by removing the replacement material 150 is filled with a conductive material to form the conductive layers 31 and 32. By replacing the replacement material 150 with the conductive layers 31 and 32, the stacked body 39 becomes the stacked body 30.

[0080] Fig.10 and Fig.11 2 is a cross-sectional view showing the upper cladding layer forming step. In the upper cladding layer forming step, the upper portion of the core 45 is removed by etching. Thereafter, the recess formed above the core 45 is filled to form a semiconductor layer 61 on the channel film 44. The semiconductor layer 61 is, for example, amorphous silicon.

[0081] Then, the semiconductor layer 61 on the upper surface of the channel film 44, the channel film 44, the tunnel film 43, the charge storage film 42, and the barrier film 41 are removed to expose the insulating layer 334. The upper portion of the semiconductor layer 61 remaining below the upper surface of the insulating layer 334 and above the core 45 is removed. The semiconductor layer 61 is removed by etching. An upper cladding layer 51 that is recessed from the upper surface of the insulating layer 334 is formed above the core 45.

[0082] Fig.12 and Fig.13 : is a cross-sectional view showing a metal layer forming step. In the metal layer forming step, a metal layer 62 is formed with a fixed thickness on the upper surface of the insulating layer 334 and the upper surface of the upper cladding layer 51. The metal layer 62 is, for example, tungsten. The upper surface of the metal layer 62 above the upper cladding layer 51 reaches above the upper surface of the insulating layer 334. Thereafter, the upper portion of the metal layer 62 is removed until the insulating layer 334 is exposed. The metal layer 62 is removed, for example, by chemical mechanical polishing (CMP). A metal layer 52 surrounded by a channel film 44 is formed above the upper cladding layer 51.

[0083] Then, similarly to the first stacking step, insulating layers and replacement materials are alternately stacked on the insulating layer 334, the channel film 44, the tunnel film 43, the charge storage film 42, the barrier film 41, and the metal layer 52 exposed above. Similar to the first hole forming step, a hole is processed in the stacked body of the insulating layer and the replacement material above the metal layer 52. The width of the hole is made smaller than the width of the upper surface of the metal layer 52 in the X direction and the Y direction, so that the metal layer 52 is exposed at the entire bottom of the hole.

[0084] Then, similarly to the second stacking step, the barrier film 46, the charge storage film 47, and the tunnel film 48 are formed on the inner wall of the hole above the metal layer 52. Thereafter, similarly to the opening forming step, an opening is formed at the bottom of the barrier film 46, the charge storage film 47, the tunnel film 48, and the cover insulating film. The bottom surface of the opening is located below the upper surface of the metal layer 52 at the end of the third stacking step. That is, by forming the opening, a recess is formed on the upper surface of the metal layer 52 at the end of the third stacking step.

[0085] Then, in the same manner as the channel film forming step and the thinning step, the channel film 49 is formed on the inner wall of the tunnel film 48 and the concave portion of the metal layer 52. Thereafter, in the same manner as the core forming step, the core 50 is formed on the inner wall of the channel film 49. The core 50 is filled inside the region surrounded by the channel film 49 in the X direction and the Y direction. By forming the core 50, the second columnar body 40B is formed.

[0086] Through the above steps, the laminated body 30 and the columnar body 40 are formed. However, the method for manufacturing the semiconductor memory device 1 is not limited to the above example.

[0087] According to the semiconductor memory device 1 described above, power consumption can be reduced by including the metal layer 52 . Fig.14 FIG. 1 is an enlarged cross-sectional view of a boundary portion between a first columnar body 40A and a second columnar body 40B of a memory cell array of a conventional semiconductor memory device. Fig.14In the conventional structure shown, an overlying layer 51 having a width wider than these channel films is interposed between the bottom of the channel film 49 and the upper part of the channel film 44 in the X direction and the Y direction. Therefore, the contact resistance between the channel film 49 and the channel film 44 becomes high. In the semiconductor memory device 1, a metal layer 52 is interposed between the channel film 49 and the channel film 44. Therefore, the contact resistance between the channel film 49 and the channel film 44 can be reduced. By reducing the contact resistance in the memory cell array 10, the power consumption of the semiconductor memory device 1 can be reduced.

[0088] According to the semiconductor memory device 1, the upper end of the channel film 44 is in contact with the metal layer 52. Therefore, the inversion layer is easily formed when a cell current is applied to the channel film 44. The cell current flows smoothly from the channel film 49 to the channel film 44 due to the formation of the inversion layer.

[0089] According to the semiconductor memory device 1, when viewed from the Z direction, the width of the lower end portion 49x is smaller than the width of the end face 52d, so that the lower end portion 49x, that is, the entire bottom surface of the channel film 49, is in contact with the end face 52d, thereby reducing power consumption. The lower end portion 49x and the end face 52d are stably connected to prevent the cell current from being blocked.

[0090] In the semiconductor memory device 1, tunnel films 43, 48 and charge storage films 42, 47 are interposed between the channel films 44, 49 and the barrier films 41, 46. According to the semiconductor memory device 1, when a cell current is supplied to the channel film 49, charges can be stored in the charge storage films 42, 47 by the tunneling effect.

[0091] (Second embodiment)

[0092] Fig.15 1 is a cross-sectional view showing a partial area of ​​the memory cell array of the second embodiment. In the memory cell array of the second embodiment, the conductive layer 99 includes a silicide layer 54. The silicide layer 54 is disposed on the center side of the first columnar body 40A relative to the tunnel film 43 in the X direction and the Y direction. The silicide layer 54 is disposed on the overlying layer 51 and the channel film 44. The silicide layer 54, like the metal layer 52, forms a path for the cell current from the channel film 49 disposed above to flow to the channel film 44. The configuration of the memory cell array of the second embodiment, except for the configuration described below, is the same as the configuration of the memory cell array 10 of the first embodiment.

[0093] Fig.15It is a cross-sectional view of the boundary portion of the first columnar body 40A and the second columnar body 40B which is enlarged. The silicide layer 54 is disposed on the upper cladding layer 51. That is, when observed along the Z direction, the first columnar body 40A includes, from the inside, the core 45, the upper cladding layer 51, any one of the silicide layer 54, the channel film 44, the tunnel film 43, the charge storage film 42, and the barrier film 41. The silicide layer 54 is, for example, a transition metal such as titanium that is silicided. The silicide layer 54, like the metal layer 52, forms a path for the unit current from the channel film 49 disposed above to flow to the channel film 44.

[0094] When viewed from the Z direction, the width of the lower end portion 49x in contact with the silicide layer 54 in the channel film 49 is smaller than the width of the end face 54d including the portion in contact with the channel film 49 in the silicide layer 54. In the cross section of the first columnar body 40A including the end face 54d, the silicide layer 54, the tunnel film 43, the charge storage film 42, and the barrier film 41 are arranged in order from the inside.

[0095] The lengths of the silicide layer 54 in the first connection terminal 91 in the X direction and the Y direction are longer than the lengths between the first channel terminal 93a and the second channel terminal 93b in the X direction and the Y direction in the second connection terminal 92. In addition, the lengths of the silicide layer 54 in the first connection terminal 91 in the X direction and the Y direction are longer than the metal layer 52 by an amount substantially equal to the length of the channel film 44.

[0096] The manufacturing method of the memory cell array of the second embodiment has a silicide layer forming step, which replaces the metal layer forming step of the manufacturing method of the memory cell array 10 of the first embodiment. That is, the manufacturing method of the memory cell array of the second embodiment has, for example, a pre-step, and a first stacking step, a first hole forming step, a second stacking step, an opening forming step, a channel film forming step, a thinning step, a core forming step, a replacement step, a slit processing step, an upper layer forming step, and a silicide layer forming step. The silicide layer forming step is described below.

[0097] Fig.16 and Fig.17 2 is a cross-sectional view showing a silicide layer forming step. In the silicide layer forming step, a transition metal layer 71 is formed with a constant thickness on the upper surface of the insulating layer 334 and the upper surface of the upper cladding layer 51. The transition metal layer 71 is, for example, titanium, molybdenum, etc. The upper surface of the transition metal layer 71 above the upper cladding layer 51 reaches above the upper surface of the insulating layer 334.

[0098] Then, the transition metal layer 71 is subjected to, for example, a solid phase reaction to be silicided. At this time, the upper portion of the channel film 44 formed in the channel film forming step is also silicided. Fig.15The portion of the silicide layer 54 shown in the figure directly above the channel film 44 in the Z direction is a layer formed by silicideing the channel film 44 in the silicide layer forming step. Fig.15 and Fig.16 In the embodiment, the length of the silicide layer 54 directly above the channel film 44 in the Z direction is the same as the length of the silicide layer 54 directly above the core 45, but the length of the silicide layer 54 directly above the channel film 44 is changed according to the conditions when the silicide of the transition metal layer 71 is performed or the material of the channel film 44. In the silicide layer forming step, there may also be a case where the upper portion of the channel film 44 formed in the channel film forming step is silicided and the lower end of the silicide layer 54 directly above the channel film 44 in the Z direction is located higher than the lower end of the silicide layer 54 directly above the core 45.

[0099] Then, if Fig.17 As shown, the upper portion of the silicided transition metal layer 71 is removed until the insulating layer 334 is exposed. The silicided transition metal layer 71 is removed by, for example, annealing and wet etching. A silicide layer 54 surrounded by the channel film 44 is formed on the upper cladding layer 51.

[0100] According to the semiconductor memory device of the second embodiment described above, power consumption can be reduced by including the silicide layer 54. In the semiconductor memory device of the second embodiment, the silicide layer 54 is interposed between the channel film 49 and the channel film 44. Therefore, the contact resistance between the channel film 49 and the channel film 44 can be reduced. By reducing the contact resistance in the memory cell array, the power consumption of the semiconductor memory device 1 of the second embodiment can be reduced.

[0101] By configuring an overlying layer 51, and a metal layer 52 or a silicide layer 54 between the core 50 and the core 45 in the Z direction, the contact resistance in the memory cell array can be reduced compared to the previous configuration. By configuring the metal layer 52, the contact resistance can be further reduced compared to the case where the silicide layer 54 is configured. On the other hand, the silicide layer 54 is less likely to peel off from the overlying layer 51 or the core 50 than the metal layer 52. Therefore, by configuring the silicide layer 54, the cell current can be stabilized compared to the case where the metal layer 52 is configured. However, the contact resistance or the conductivity of the cell current changes according to the material and size of each component of the memory cell array. Which of the metal layer 52 and the silicide layer 54 is configured between the core 50 and the core 45 in the Z direction can be selected based on the material and size of each component of the memory cell array.

[0102] According to the semiconductor memory device of the second embodiment, the width of the lower end portion 49x is smaller than the width of the end face 54d, so that the lower end portion 49x, that is, the entire bottom surface of the channel film 49, is in contact with the end face 54d, thereby reducing power consumption. The lower end portion 49x and the end face 54d are stably connected to prevent the cell current from being blocked.

[0103] In the semiconductor memory device of the second embodiment, tunnel films 43, 48 and charge storage films 42, 47 are interposed between channel films 44, 49 and barrier films 41, 46. According to the semiconductor memory device of the second embodiment, when a cell current is supplied to the channel film 49, charges can be stored in the charge storage films 42, 47 by the tunneling effect.

[0104] (Notes) Below, some notes are provided for semiconductor storage devices.

[0105] [1] Have:

[0106] A laminated body formed by alternately laminating a plurality of conductive layers and a plurality of insulating layers along a first direction;

[0107] a first columnar body disposed within the laminate; and

[0108] a second columnar body disposed in the laminate and arranged in parallel with the first columnar body in the first direction; and

[0109] The second columnar body includes a channel membrane,

[0110] The first columnar body includes a channel film, a core provided on the central side of the first columnar body in the second direction relative to the channel film of the first columnar body, and a conductive layer provided between the channel film of the second columnar body and the core in the first direction in contact with the channel film of the second columnar body.

[0111] The conductive layer includes at least one of a metal layer and a silicide layer.

[0112] [2] The semiconductor memory device according to [1], wherein

[0113] The conductive layer includes a metal layer and is arranged on the central side of the first columnar body more closely than the channel membrane of the first columnar body in the second direction, is arranged at the end of the first columnar body facing the second columnar body, is located between the core and the second columnar body in the first direction, and is connected to the channel membrane of the first columnar body.

[0114] [3] The semiconductor memory device according to [1], wherein

[0115] The conductive layer includes a silicide layer, is disposed at an end of the first column facing the second column, is located between the core and the second column in the first direction, and is in contact with a channel film of the first column.

[0116] [4] The semiconductor memory device according to [1], wherein

[0117] The first column has a first connection end connected to the second column, and

[0118] The second columnar body has a second connection end connected to the first columnar body,

[0119] The channel film of the second columnar body has a first channel end as one end in the second direction and a second channel end as the other end in the second direction.

[0120] A length of the conductive layer in the first connection end in the second direction is longer than a length between the first channel end and the second channel end in the second connection end.

[0121] [5] The semiconductor memory device according to [1], wherein

[0122] The first columnar body includes a charge storage film provided on the opposite side of the channel film of the first columnar body from the core.

[0123] [6] The semiconductor memory device according to [1], wherein

[0124] An upper cladding layer including a semiconductor is included between the core of the first columnar body and the conductive layer.

[0125] [7] The semiconductor memory device according to [6], wherein

[0126] The thickness of the upper cladding layer in the first direction is greater than the thickness of the conductive layer in the first direction.

[0127] [8] The semiconductor memory device according to [1], wherein

[0128] The conductive layer has a first surface facing the second columnar body, the first surface has a concave portion concave toward the core, and

[0129] The channel film of the second columnar body includes a portion located in the recessed portion.

[0130] [9] The semiconductor memory device according to [1], wherein

[0131] The second columnar body includes a core provided on the central side of the second columnar body relative to the channel film of the second columnar body in the second direction, and an insulating film provided on the opposite side of the core of the second columnar body with respect to the channel of the second columnar body in the second direction.

[0132] A portion of the conductive layer is in contact with the insulating film in the first direction.

[0133]

[10] The semiconductor memory device according to [1], wherein

[0134] The first columnar body includes a charge storage film provided on the opposite side of the channel film of the first columnar body from the core of the first columnar body.

[0135] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0136] For example, the intersection of the conductive layer 32 and the pillar 40 may also be used as a dummy transistor not used to store charges, instead of being used as the memory cell transistor MT.

[0137]

Explanation of symbols

[0138] 1 Semiconductor storage device

[0139] 30 Layered

[0140] 40A 1st columnar body

[0141] 40B 2nd column

[0142] 41, 46 Barrier film

[0143] 42, 47 Charge storage film

[0144] 44, 49 channel membrane

[0145] 45, 50 cores

[0146] 52 Metal Layer

[0147] 54 Silicide layer

[0148] 93a Channel 1 terminal

[0149] 93b Channel 2 terminal

Claims

1. A semiconductor storage device comprising: A first laminated body is formed by alternately laminating a plurality of word lines and a plurality of first insulating layers along a first direction; A second laminated body is formed by alternately laminating a plurality of selection gate lines and a plurality of second insulating layers along the first direction and does not include a word line; a first columnar body disposed in the first laminated body; and a second columnar body disposed in the second laminate and arranged in parallel with the first columnar body in the first direction; and The first columnar body includes a first channel membrane, The second columnar body includes a second channel membrane, The first columnar body includes a first core disposed on a central side of the first columnar body relative to the first channel film in a second direction orthogonal to the first direction, and a conductive layer disposed between the second channel film and the first core in the first direction so as to be in contact with the second channel film. The conductive layer includes at least one of a metal layer and a silicide layer, The conductive layer is disposed closer to the center of the first column than the first channel film in the second direction, and is disposed at an end of the first column facing the second column, and is located between the first core and the second column in the first direction, and is in contact with the first channel film. The first columnar body includes a semiconductor layer between the first core and the conductive layer, and The semiconductor layer includes amorphous silicon.

2. The semiconductor memory device according to claim 1, wherein The first column has a first connection end connected to the second column, and The second columnar body has a second connection end connected to the first columnar body, The second channel film has a first channel end as one end in the second direction and a second channel end as the other end in the second direction. A length of the conductive layer in the first connection end in the second direction is longer than a length between the first channel end and the second channel end in the second connection end.

3. The semiconductor memory device according to claim 1, wherein The first columnar body includes a charge storage film provided on the opposite side of the first channel film from the first core.

4. The semiconductor memory device according to claim 1, wherein The conductive layer is a metal layer.

5. The semiconductor memory device according to claim 1, wherein The conductive layer is a silicide layer.

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