Drain-Shared Split LNA

Abstract

A receiver front end (300) having a low noise amplifier (LNA) is disclosed herein. A cascode having an input FET configured with a "common source" and an output FET configured with a "common gate" can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be made or broken between the source terminals of the input FETs of each LNA. A drain switch (260) is provided between the drain terminals of the input FETs to place the input FETs in parallel. This increases the g of the input stage of the amplifier. m , thereby improving the noise figure of the amplifier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 15 / 887,816, filed on February 2, 2018, entitled “Drain Shared Split LNA,” the disclosure of which is incorporated herein by reference in its entirety. Background Art (1) Technical field

[0004] Various embodiments described herein relate to amplifiers, and more particularly, to low noise amplifiers for use in communication devices. (2) Background technology

[0006] The front end of a communication receiver typically includes a low noise amplifier ("LNA"), which is responsible for providing the first stage of amplification of the signal received within the communication receiver. The operating specifications of the LNA are very important to the overall quality of the communication receiver. Any noise or distortion introduced by the LNA will result in degradation of the overall receiver performance. Therefore, the sensitivity of the receiver is largely determined by the quality of the front end, and in particular the quality of the LNA.

[0007] In some cases, the LNA is required to operate over a relatively wide frequency band and amplify signals having several different modulated baseband or modulated intermediate frequency (IF) signals. An example of a situation where the LNA is required to amplify a received signal having multiple modulated IF or baseband signals is a situation where an intra-band non-contiguous carrier aggregate (CA) signal is to be received. The CA signal may have two channels (or IF carriers) having frequencies that are not adjacent to each other but are within a frequency range that can be processed by a single LNA amplifier. For example, the CA signal may have two non-adjacent channels within a cellular frequency band defined by the Third Generation Partnership Project (3GPP). 3GPP is a well-known industry standards setting organization.

[0008] In the case where a receiver is required to receive CA signals, such as a cellular phone compliant with Release 11 of the 3GPP communications industry standard, the LNA typically amplifies the received signal and provides the amplified output signal to a passive splitter. FIG. 1 is a diagram of a portion of a cellular phone front end, in which an LNA 101 is coupled to a variable attenuator 103. A bypass switch 105 allows the variable attenuator to be selectively shunted. The signal is then coupled to a selector switch 107 in a single-pole, triple-throw mode, which allows the output of the LNA 101 to be selectively coupled to only a first downconverter and baseband circuitry (DBC) 109, a second DBC 111, or both the first DBC 109 and the second DBC 111.

[0009] When the mode selector switch 107 is in the first position (i.e., single channel mode 1), the output of the LNA 101 is directly coupled to the first DBC 109. In the second position (i.e., split mode), the output of the LNA 101 is coupled to the first DBC 109 and the second DBC 111 through the passive power splitter 113. In the third position (i.e., single channel mode 2), the output of the LNA 101 is coupled only to the second DBC 111.

[0010] There are some limitations caused by the architecture shown in Figure 1. The first limitation is the amount of isolation that can be achieved between the first DBC 109 and the second DBC 111. Typically, a well-made 3dB splitter can achieve about 18 to 20dB of isolation between the outputs at the center frequency that the splitter 113 is designed to operate. Signals cross-coupled from one DBC to other DBCs will generally result in interference and distortion that will result in an overall reduction in the sensitivity of the receiver.

[0011] In addition, passive splitters are typically designed to work optimally over a relatively narrow frequency range. That is, passive splitters are inherently narrowband devices. When the frequency of the signal coupled through splitter 113 deviates from the optimal frequency for which the splitter is designed, the output-to-output isolation will degrade. Due to the limitations of currently available splitters, and because receivers designed to process CA signals must operate over a relatively wide frequency range, it is difficult to achieve the desired isolation between DBCs 109, 111.

[0012] In addition, power splitters such as splitter 113 shown in FIG. 1 have significant losses. Since a 3dB power splitter splits the power in half, even an ideal splitter will result in a 3dB reduction in the power provided to DBC 109, DBC 111 in split mode compared to single channel mode. In addition, most splitters will have an additional insertion loss of 1.0 to 1.5dB. Insertion losses such as output-to-output isolation will generally become worse as the frequency of the applied signal deviates from the center frequency that the splitter is designed to operate.

[0013] Furthermore, more gain is required due to the losses encountered in the mode select switch 107 and splitter 113. This results in reduced linearity (as usually characterized by measuring the "third order intercept") and a degradation of the receiver's noise figure when operating in split mode.

[0014] Therefore, there is a need for a CA-capable receiver front end that can operate in a split mode with high output-to-output isolation without degrading the third-order intercept and noise figure, and with relatively low front-end losses. Summary of the invention

[0015] Disclosed herein is a receiver front end capable of receiving and processing in-band non-contiguous carrier aggregation (CA) signals using multiple low noise amplifiers (LNAs). According to some embodiments of the disclosed methods and apparatus, each of the multiple amplifiers is an LNA configured as a common source and common gate (i.e., a two-stage amplifier having two transistors, the first transistor being configured as a "common source" input transistor such as an input field effect transistor (FET), and the second transistor being configured as an output transistor (e.g., an output FET) in a "common gate" configuration. In other embodiments, the LNA may have additional transistors (i.e., more than two stages and / or stacked transistors). The output transistor of each LNA can be turned on or off (i.e., by using the gate of the output FET or opening a switch 254, 252 in the source of the input FET). The gates of the input FETs are coupled together to form a common input. However, in some embodiments, the gates of the two FETs can be separated to allow independent control of which output transistor is turned off (i.e., the FET does not conduct current from the drain terminal to the source). A first switch is provided that allows a connection to be made or broken between the source terminals of the input FETs of each LNA. In addition, a second switch enables a switchable gate-to-source and / or gate-to-ground capacitor to be selectively applied to the input FETs of at least one of the LNAs. In some embodiments, an additional switch is provided that enables a source-to-ground degeneration inductor to be disconnected from the source terminal of the input FET of the LNA whose output FET is turned off. Selectively turning the output FET on and off enables the amplifier to operate in both single mode and split mode. In addition, the use of the switch ensures that the input impedance to the amplifier is the same in both single mode and split mode. In addition, a drain switch is provided that couples the drain terminals of each input FET together during single mode. In split mode, the switch is opened to decouple the drain terminals.

[0016] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a diagram of a portion of a cellular telephone front end with an LNA coupled to a variable attenuator.

[0018] Figure 2 is a diagram of a front-end amplifier having a degenerate switch, a gate capacitor module, and using multiple LNAs operating in a single mode or a split mode.

[0019] Figure 3 is a simplified schematic diagram of another embodiment of an amplifier having a source split LNA and a drain switch and including a resistor that may be selectively placed in parallel across the inductor and capacitor in each output load matching circuit.

[0020] Figure 4 is a graph showing the improvement in noise figure achieved by using drain switches.

[0021] Figure 5 The noise figure and current I according to the input frequency are shown DD Graphs and tables of the relationships between .

[0022] Figure 6 A method according to one embodiment for amplifying a signal (eg, a CA signal) using more than one amplifier is shown.

[0023] Figure 7 is an illustration of another embodiment of a method including removing a parallel drain resistor during a single mode.

[0024] Like reference numbers and designations in the various drawings represent like elements. DETAILED DESCRIPTION

[0025] Figure 22 is an illustration of a front-end amplifier 200 of a communication receiver in which a plurality of low noise amplifiers (LNAs) 202, 204 are used to amplify signals. The signal to be amplified is coupled through a front-end signal input terminal 206. In a first mode, referred to as "single mode", one of the output FETs 208, 212 associated with the LNA 202, 204 is turned on (i.e., is actively amplifying a signal applied to the input of the LNA 202, 204). The amplified output of the activated LNA 202, 204 is coupled to output terminals 232, 234. The output FET 208, 212 of the other LNA 204, 202 is turned off (i.e., current is not allowed to flow from the drain to the source). In one embodiment of the disclosed method and apparatus, each LNA 202, 204 includes a pair of field effect transistors (FETs) 208, 210 and 212, 214. Each pair forms a two-stage LNA in a cascode architecture. However, those skilled in the art will appreciate that other types of transistors may be used, including but not limited to bipolar junction transistors. Furthermore, any type of FET may be used to implement the LNA, including but not limited to metal oxide semiconductors (MOSFETs), junction field effect transistors (JFETs), insulated gate FETs (IGFETs), metal semiconductor FETs (MESFETs), etc. While some types of transistors may be better suited for particular applications, the concepts associated with the disclosed methods and apparatus do not exclude the use of any particular type of transistor. Further, additional transistors may be included within an LNA (e.g., LNAs 202, 204), either as additional amplifier stages or stacked with those FETs 208, 212 shown. Furthermore, in some embodiments, the particular type of transistor and the number of such transistors may vary from one LNA 202, 204 to another or within each LNA 202, 204.

[0026] The LNA control signal applied to the control input terminal 216, 218 coupled to the gate of the output transistor (e.g., FET) of the LNA implemented by the FET 208, 212 controls whether the output FET 208, 212 of each LNA 202, 204 is turned on or off (i.e., conducts a large amount of current from the drain terminal to the source terminal). In one embodiment, the LNA control signal is generated by a control module such as an LNA controller 217. The LNA controller 217 can generate the LNA control signal based on information about the type of signal to be received by the amplifier 200, the content carried by the signal, or based on a user command to select one or more channels. The LNA controller 217 can be a general purpose processor that is capable of receiving commands and processing the commands to generate control signals to the LNA and related switches disclosed throughout the present disclosure. Alternatively, the LNA controller 217 is a dedicated processor specifically designed for generating control signals. Those skilled in the art will understand how to cause such a processor to receive a command to enter a first mode such as a split mode and determine the specific configuration of the switch control signals and LNA control signals to be generated. In some cases, the LNA controller 217 may be as simple as a logic block with a lookup table.Alternatively, in some embodiments, the LNA controller 217 may also rely on additional information in determining the state of the switch control signal and the LNA control signal.

[0027] In single mode, the LNA control signal to one of the LNAs 202, 204 turns on the output FETs 208, 212 of that LNA 202, 204. The LNA control to the other LNA 204, 202 turns off the output FETs 212, 208 of that LNA 202, 204. In split mode, the output FETs 208, 212 of both LNAs 202, 204 are turned on. Those skilled in the art will appreciate that Figure 2 Additional LNAs not shown in the drawings may similarly be coupled to expand the amplifier to select additional channels using additional modes of operation.

[0028] Output load matching circuits 220, 222 coupled to output ports 224, 226 of each LNA 202, 204 provide a means by which the output impedance can be matched to the load. In one case, an input matching circuit 228 is provided to match the input impedance of the amplifier to the source terminal. The input matching circuit 228 includes an input matching inductor 229 and an input DC blocking capacitor 233. In some embodiments, the output shunt capacitors 230, 231 provide a relatively low capacitive reactance to ground for signals within the frequency range of the input signal applied to the input of the LNA 202, 204, respectively. In some embodiments, a separate V DDThe supply voltage source is used to increase the isolation between the LNAs 202, 204. In other embodiments, the same supply terminal can be used to provide V to two or more of the LNAs. DD .

[0029] Figure 2 The isolation achieved by the front end 200 shown in FIG. 1 is enhanced by the fact that there is significant isolation between the output port 232 of the first LNA 202 and the output port 234 of the second LNA 204. In the amplifier 200, the isolation between the outputs of the front end will improve for signals separated by some intervening channels. That is, as the separation of frequencies increases, the level of gain-versus-frequency overlap of one narrowband tuned output with another narrowband tuned output will decrease. This reduction will enhance the isolation between the outputs. In lower gain operating modes, the output isolation will be improved.

[0030] One problem that needs to be addressed when using two LNAs in this manner is that the input impedance of the front-end amplifier 200 will vary depending on the mode in which the receiver is operating. That is, the input impedance presented in single mode will be significantly different from the impedance presented in split mode due to the difference in the gate-to-source capacitance Cgs of the FET transistor when the output FET of the LNA is on and when the output FET of the LNA is off. Large differences in input impedance will result in large input mismatches, which in turn have large adverse effects on almost every aspect of the amplifier 200. This effect can result in an increase in noise figure, a decrease in gain, and a degradation in linearity as measured, for example, by the third-order intercept (IP3). The Cgs of the input FETs 210, 214 of each LNA 202, 204 from a conducting state to a non-conducting state is proportional to the input impedance of the input FET 210, 214. gs The relatively large change in the input impedance of the amplifier 200 results in large changes in both the real and imaginary parts of the input impedance of the amplifier 200 when operating in the single mode and the split mode. A source switch 235 that can be closed in the single mode to couple the source of the first input FET 210 to the source of the second input FET 214 is provided to reduce this effect. Closing the switch 235 during the single mode to connect the sources of the two input FETs 210, 214 makes the input impedance presented in the split mode (i.e., when both output FETs 208, 212 of the two LNAs 202, 204 are on) closer to the input impedance presented during the single mode with the switch 235 open. However, this still represents a large impedance change compared to the split mode. In the split mode, the source switch 235 is opened. Opening the source switch 235 during the split mode improves the noise isolation between the output terminals 216, 218.

[0031] In addition to the source switch 235, in some embodiments, the front-end amplifier 200 has at least one gate capacitance module 240, which includes a gate capacitor 242 and a gate switch 244 connected in series between the first terminal and the second terminal of the module 240. When the second LNA 204 is turned off, the gate switch 244 can be switched to insert the gate capacitor 242 in parallel with the gate and source of the input FET 210, thereby providing additional input capacitance. By adding the additional capacitance of the gate capacitor 242, the input impedance during the single mode more closely matches the input impedance during the split mode. Therefore, in the case where both the gate switch 244 and the source switch 235 are closed during the single mode, the input impedance will very closely match the input impedance presented during the split mode (during the split mode, both switches 244, 235 are open). In the single mode, the gate switch 244 and the source switch 235 are closed. In the split mode, the gate switch 244 and the source switch 235 are opened.

[0032] In addition, the front-end amplifier 200 has at least a first degeneration switch 252 to disconnect a degeneration component such as the first degeneration inductor 238 from the second LNA 204 during the single mode. In some embodiments, the second degeneration switch 254 is placed between the source of the first FET 210 and the second degeneration component such as the second degeneration inductor 236 to allow the degeneration inductor 236 to be removed from the LNA 400. Therefore, it can be selected which inductor 236, 238 is removed during the single mode. It will be clear to those skilled in the art that either of the two degeneration switches 252, 254 can be provided separately, or the two switches 252, 254 can be provided together.

[0033] When the source switch 235 is closed, the degeneration inductors 236, 238 are disconnected. Thus, when the source switch 235 is open during the split mode, each LNA 202, 204 sees the inductance of only one degeneration inductor 236, 238 coupled to the respective source of the input FET 210, 214 associated with that LNA 202, 204. By opening one of the degeneration switches 252, 254 in the single mode, the active LNA 202, 214 operating in the single mode has an inductive load between the source and ground that is equal to the inductance of only one of the degeneration inductors 236, 238, thereby more closely matching the inductance presented during the split mode. Providing the second degeneration switch 254 provides flexibility as to which inductance is presented at the source of the activated input FET 210, 214 regardless of which output FET 208, 212 is turned on during the single mode.

[0034] In addition to the switches 235, 244, 252, 254, a drain switch 260 is provided to enable the drain terminal of the input FET 210 to be coupled to the drain terminal of the input FET 214 during the single mode. In an amplifier operating in the single mode without the drain switch 260, the input of one of the input FETs 210, 214 is essentially unused. Closing the drain switch 260 places the two input FETs 210, 214 in parallel. By placing the two input FETs 210, 214 in parallel, the unused input FETs 210, 214 are added to the g of the input stage of the front end amplifier 200. m (i.e., transconductance). Transconductance is the change in drain current divided by a small change in gate-to-source voltage when the drain-to-source voltage is constant. In this case, the drain current is the sum of the currents through each input FET 210, 214 (i.e., the current through the conducting FETs 208, 212). The amplifier's g m The increase in the noise figure of the amplifier increases. The switching frequency is f T ≈g m (2πC gs ). Therefore, due to C gs The value of remains basically unchanged, so the switching frequency (f T )With g m increases with the increase of .

[0035] When a signal is sent to the LNA 1 output, the LNA 1 control signal applied to the input 216 of FET 208 provides a bias to allow FET 208 to conduct. The LNA 2 control signal applied to the input of FET 212 is at ground potential to prevent FET 212 from conducting. By closing drain switch 260, the drain terminal of input FET 214 conducts in parallel with input FET 210, causing some of the current flowing through FET 208 to be shunted. It can be seen that since both input FETs 210, 214 are conducting (assuming R of drain switch 260 is on =(1 / 2) / (2 / 208) / ... T However, the input FET 214 requires additional DC bias current to generate g m , and thus the amplifier 200 will consume more power with both input FETs 210, 214 turned on. The bias of the input FETs 210, 214 can be set to optimize f TThus, amplifier 200 is flexible in its operation, allowing the user to determine how to balance the tradeoff between power consumption and noise figure in a single mode.

[0036] Since drain switch 260 is open (ie, non-conductive) during the split mode, drain switch 260 has minimal effect on the operation of amplifier 200 in the split mode. Since LNAs 202, 204 operate in common mode, C off The effect of (the capacitance of drain switch 260 when non-conductive) on the forward signal is minimal. However, if drain switch 260 is too large, then the drain switch may negatively affect the isolation of the outputs LNA Output 1 and LNA Output 2 in the split mode. In addition, a large drain switch 260 increases the shunt capacitance to the substrate on which the components of amplifier 200 are fabricated. Such an increase in shunt capacitance can increase the noise contribution from the cascode amplifier. Because the additional shunt capacitance added is typically relatively small for silicon-on-insulator (SOI) integrated circuits, the use of SOI integrated circuit systems mitigates this effect to some extent.

[0037] In addition, the size of the drain switch 260 may have an impact on the noise figure. If the drain switch 260 is too small, the R on The DC voltage drop across the input FET 214 (i.e., across the resistance of the switch when the switch is closed) results in a voltage V across the input FET 214. DS This results in a lower efficiency g m , which will have a negative impact on the noise figure. However, because R on is in g m It appears after the stage, so R on The contribution to the noise figure is not very significant.

[0038] Figure 3 2 is a simplified schematic diagram of another embodiment of an amplifier 300 having source-separated LNAs 202, 204 and drain switches 260. The amplifier 300 includes a resistor that can be selectively placed in parallel across the inductor and capacitor in each output load matching circuit 220, 222. Within each output load matching circuit 220, 222, switches 302, 304 and drain resistors 306, 308 are connected between the drain terminal of one of the output ports 224, 226 and V DD In single mode, the output impedance of amplifier 300 decreases because input FETs 210, 214 are placed in parallel when drain switch 260 is closed. Opening switches 302, 304 increases resistance by removing the parallel path through each drain resistor 306, 308.

[0039] Figure 4 is a graph showing the improvement in noise figure achieved by using the drain switch 260. The first curve 402 shows the difference between the voltage source V and the voltage source V during a single mode when the drain switch is turned on. DD The current drawn at each level I DD The associated noise figure (NF). Figure 3 In the embodiment shown, the current I DD is: (1) when the LNA1 control signal is set to turn on the output FET 208 of LNA1, the current I flowing through the first LNA 202 DD1 and any leakage current I flowing through the second LNA 204 DD2 or (2) when the LNA2 control signal is set to turn on the output FET 212 of LNA 2, the current I flowing through the second LNA 204 DD2 and any leakage current I flowing through the first LNA 202 DD1 The second curve 404 shows the single mode in which the drain switch is closed and the voltage source V DD The current drawn at each level I DD It can be seen that at point 406 on curve 402, at which the current I DD = 6 mA - the noise figure with the drain switch open is about 1.55 dB. In contrast, at point 408, the noise figure with the drain switch 260 closed is about 1.46 dB. The improvement in noise figure increases with I DD The current I DD At 16 mA, the noise figure when drain switch 260 is open is shown at point 410 to be approximately 1.53 dB. In contrast, the noise figure when drain switch 260 is closed, shown at point 412, is approximately 1.23 dB. It should be noted that these curves are plotted based on amplifier 300 with nominal values ​​for components and are meant only to give a relative proportion of the amount of improvement that can be achieved. An amplifier including components with specific values ​​and characteristics may differ from these values.

[0040] Figure 5 The noise figure and current I according to the input frequency are shown DD . Four curves 502, 504, 506, 508 are plotted over a frequency range from 2 GHz to 3 GHz. The first curve 502 represents a current I equal to 9.1 mA when the drain switch is turned on over a frequency range from 2 GHz to 3 GHz. DD The second curve 504 shows that when the drain switch 260 is closed, the current I DDThe third curve 506 shows the noise figure over the entire frequency range when the drain switch 260 is closed and the current I DD The fourth curve 508 shows the noise figure over the entire frequency range for a current I of 11.0 mA when the drain switch 260 is closed. DD The noise figure over the entire frequency range. It can be seen that with drain switch 260 closed, only 7.5 mA of I is used, compared to 9.1 mA when drain switch 260 is open. DD Almost the same noise figure can be achieved.

[0041] According to some embodiments of the disclosed methods and apparatus, switches 235, 244, 252, 254, 260, 302, 304 may be manufactured according to the techniques provided in U.S. Pat. No. 6,804,502 (the "502 patent"), which is incorporated herein by reference, and may be manufactured according to techniques disclosed in other related patents. Additional improvements in the performance of one or more of switches 235, 244, 252, 254, 260, 302, 304 may be achieved by implementing the techniques provided in U.S. Pat. No. 7,910,993 (the "993 patent"), which is incorporated herein by reference, and may be achieved by implementing techniques disclosed in other related patents. The use of such high performance switches reduces the nonlinearity of the switches and, therefore, reduces the adverse effects of such switches on the performance of the receiver. However, in many implementations, switches may be used that have performance characteristics (i.e., linearity, return loss, switching speed, ease of integration, etc.) that are not as good as the characteristics of switches made according to the techniques disclosed in the '502 and '993 patents. Thus, each or some of the switches disclosed above may be implemented using any combination of one or more transistors, including FETs, bipolar junction transistors (BJTs), or any other semiconductor switches. Alternatively, the switches may be implemented using electromechanical or MEM (micro-electromechanical systems) technology.

[0042] Furthermore, it will be appreciated by those skilled in the art that each of the switches 235, 244, 252, 254, 260, 302, 304 may be controlled by a control signal generated by the LNA controller 217 or other such controller to select the state of each switch according to the operating mode of the amplifier (i.e., whether in single mode or split mode). For simplicity, such control signals and inputs to the switches are not shown in the drawings, but are well within the purview of those skilled in the art.

[0043] method

[0044] Figure 6is an illustration of a method according to one embodiment of amplifying a signal (e.g., a CA signal) using more than one amplifier. A signal is applied to an input of an amplifier [step 601]. In some embodiments, the signal includes first and second non-adjacent channels. A first channel and a second channel are considered non-adjacent if there is at least a narrow frequency range between the end of a frequency range defined for the first channel and the beginning of a frequency range defined for the second channel. Typically, at least a third channel is defined within a frequency range between the end of the first channel and the beginning of the second channel. The frequency range of a channel is typically defined by an industry standard, but in some cases may be defined by a 3dB frequency range of a filter typically used to receive signals transmitted on the channel.

[0045] The method also includes selecting between the single mode or the split mode [step 603]. In one embodiment, the selection between the single mode and the split mode is performed by turning on the output FET 208 in the first LNA 202 and turning off the second output FET 121 in the second LNA 204 to select the single mode [step 605]. In one such embodiment, by providing a FET coupled to the output FET such as Figures 2 to 5 The first output FET 208 is shown to be turned on by applying the LNA control signal to the first control input terminal 216 of the gate of the FET 208. The second output FET 212 is turned off by applying the LNA control signal to the second control input terminal 218. Similarly, the selection of the split mode is performed by applying the LNA control signal to the control terminals 216, 218 to turn on both output FETs 208, 212 [step 607].

[0046] The method also includes coupling the source of the input FET of the first LNA 202, such as FET 210, with the source of the input FET of the second LNA 204, such as FET 212, during the single mode [step 609], and decoupling the two sources during the split mode [step 611]. In one such embodiment, the source switch 235 is closed in the single mode and is opened in the split mode. When the source switch 235 is closed, it couples the two sources of the input FETs 210, 212. In addition, the drain switch 260 is closed in the single mode [step 613] and is opened during the split mode [step 615].

[0047] Figure 7is an illustration of another embodiment of a method including removing parallel drain resistors 306, 308 during single mode [step 713]. In one embodiment, drain resistors are removed by opening switches 302, 304. Resistors 306, 308 are added during split mode by closing switches 302, 304 [step 715]. One such embodiment also includes selecting a resistance value of the drain resistor such that the output impedance is substantially the same during single mode and split mode.

[0048] Manufacturing Techniques and Options

[0049] It should be obvious to those of ordinary skill in the art that various embodiments of the claimed invention can be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice, and the claimed invention can be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures) or in hybrid or discrete circuit form. Any suitable substrate and process can be used - including but not limited to standard bulk silicon, silicon on insulator (SOI), silicon on sapphire (SOS), GaNHEMT, GaAs pHEMT and MESFET technology - to manufacture integrated circuit embodiments. However, in some cases, the claimed inventive concept may be particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics.

[0050] A number of embodiments of the invention claimed have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence-independent and may therefore be performed in an order different from the described order. In addition, some of the steps described above may be optional. The various activities described with respect to the methods confirmed above may be performed in a repetitive, serial or parallel manner. It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention claimed, which is limited by the scope of the appended claims, and other embodiments are within the scope of the claims.

Claims

1. An amplifier, comprising: (a) a plurality of low noise amplifiers (LNA), each of the low noise amplifiers comprising an input transistor and an output transistor; (b) at least two control input terminals, each of the control input terminals coupled to an output transistor of a respective one of the LNAs; as well as (c) at least one drain switch that connects the drain terminals of the input transistors of at least two of the LNAs to the source terminal of the output transistor during a first operating mode such that the drain current is the sum of the currents through each input transistor, and that disconnects the drain terminals during at least a second operating mode, wherein the output transistor of at least one of the LNAs is off during the first operating mode.

2. The amplifier of claim 1 , further comprising at least one source switch that connects source terminals of input transistors of at least two of the LNAs during the first operating mode and disconnects the source terminals during at least the second operating mode.

3. The amplifier according to claim 1, wherein: A signal coupled to the control input terminal turns the corresponding output transistor on and off.

4. The amplifier of claim 1 , further comprising a gate capacitance module having a first terminal coupled to a gate of an associated one of the input transistors and a second terminal coupled to a source of the associated input transistor.

5. The amplifier of claim 1 , further comprising a control module having at least one switch control signal output, wherein: Each drain switch has a switch control signal input to which a corresponding switch control signal output is coupled.

6. The amplifier according to claim 4, wherein: The gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

7. The amplifier according to claim 6, wherein The gate switch is open during the second operating mode and closed during the first operating mode.

8. The amplifier of claim 1, further comprising at least one gate capacitance module, each gate capacitance module having a first terminal coupled to a gate of an associated one of the input transistors and a second terminal coupled to ground.

9. The amplifier of claim 8, further comprising a control module having at least one switch control signal output, wherein: Each gate capacitance module has a switch control signal input to which a corresponding switch control signal output is coupled.

10. The amplifier according to claim 8, wherein Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

11. The amplifier according to claim 10, wherein The gate switch is open during the second operating mode and closed during the first operating mode.

12. The amplifier of claim 1, further comprising: (a) Degenerate parts; (b) a degenerative switch coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch coupled between a source of one of the input transistors and circuit ground.

13. The amplifier according to claim 12, wherein The degenerative component is a degenerative inductor.

14. The amplifier according to claim 12, wherein: When the drain switch is open, the degenerative switch is closed.

15. The amplifier of claim 12, further comprising at least a second degenerative component and a second degenerative switch, wherein the second degenerative component and the second degenerative switch are coupled in series between a source of a second one of the input transistors and ground, and the second degenerative switch is closed when the first degenerative switch is opened.

16. The amplifier of claim 12, further comprising a control module having a switch control signal output, wherein: The degenerative switch has a switch control signal input to which the switch control signal output is coupled.

17. The amplifier of claim 4, further comprising: (a) Degenerate parts; (b) a degenerative switch coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch coupled between a source of one of the input transistors and ground.

18. The amplifier of claim 17, wherein: The degenerate component is an inductor.

19. The amplifier according to claim 17, in, The gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module, wherein, when the drain switch is opened, the degenerate switch is closed, and Wherein, when the drain switch is closed, the gate switch is closed, and when the drain switch is opened, the gate switch is opened.

20. The amplifier of claim 17, further comprising at least a second degeneration inductor and a second degeneration switch, in, The gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module, wherein when the drain switch is closed, the gate switch is closed, and when the drain switch is opened, the gate switch is opened, and wherein the second degeneration inductor and the second degeneration switch are coupled in series between a source of a second input transistor in the input transistors and ground, and When the drain switch is open, both the degenerative switch and the second degenerative switch are closed, and when the drain switch is closed, at least one of the degenerative switch and the second degenerative switch is open.

21. The amplifier of claim 17, further comprising a control module having a switch control signal output, wherein: The degeneration switch has a switch control signal input to which one of the switch control signal outputs is coupled, and each gate capacitance module has a switch control signal input to which one of the switch control signal outputs is coupled.

22. A method for amplifying a signal in more than one amplifier, comprising: (a) coupling a signal to be amplified to the input of at least a first LNA and a second LNA, each LNA having an input transistor and an output transistor, each transistor having a first terminal, a second terminal and a third terminal; (b) coupling a second terminal of an output transistor of the first LNA to a third terminal of an input transistor of the first LNA; (c) coupling a second terminal of the output transistor of the second LNA to a third terminal of the input transistor of the second LNA; (d) turning on output transistors of the first LNA and the second LNA during a first mode; (e) during the first mode, opening a switch between a third terminal of an input transistor of the first LNA and a third terminal of an input transistor of the second LNA; (f) turning off one of the output transistors of the first LNA or the second LNA during a second mode; as well as (g) closing a switch between a second input transistor of the second LNA and a third terminal of a first input transistor of the first LNA in the second mode to connect the second input transistor and the third terminal of the first input transistor to the second terminal of the output transistor that is not blocked, so that a drain current is a sum of currents through the first input transistor and the second input transistor.

23. The method according to claim 22, further comprising: (a) opening a switch between second terminals of the input transistor during the first mode; as well as (b) Closing a switch between the second terminals of the input transistor in the second mode.

24. The method of claim 22, further comprising, during the second mode, closing a gate switch to place a capacitor between a first terminal of an input transistor of the first LNA and a second terminal of an input transistor of the first LNA.

25. The method of claim 24, further comprising opening the gate switch during the first mode to remove the capacitor from between a first terminal of an input transistor of the first LNA and a second terminal of an input transistor of the first LNA.

26. The method according to claim 25, wherein: The capacitance of the capacitor is selected such that an input impedance seen by observing the LNA activated in the second mode is substantially the same during the first mode as during the second mode.

27. The method according to claim 25, wherein: The input transistor and the output transistor are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

28. The method of claim 22, further comprising closing a gate switch during the second mode to place a capacitor between a first terminal of an input transistor of the first LNA and ground.

29. The method of claim 28, further comprising opening a switch to disconnect a capacitor from between a first terminal of an input transistor of the first LNA and ground during the first mode.

30. The method of claim 29, wherein: The capacitance of the capacitor is selected such that an input impedance seen by observing the LNA activated in the second mode is substantially the same during the first mode as during the second mode.

31. The method of claim 29, wherein: The input transistor and the output transistor are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

32. The method of claim 22, further comprising opening a first degeneration switch to disconnect a second terminal of one of input transistors of the first and second LNAs from ground when changing from the first mode to the second mode.

33. The method of claim 32, further comprising, during the second mode, closing a gate switch to place a capacitor between a first terminal of an input transistor of the first LNA and a second terminal of an input transistor of the first LNA.

34. The method of claim 32, further comprising, during the first mode, opening a switch to disconnect a capacitor from between a first terminal of an input transistor of the first LNA and a second terminal of an input transistor of the first LNA.

35. The method of claim 32, further comprising, during the second mode, closing a gate switch to place a capacitor between a first terminal of an input transistor of the first LNA and the ground.

36. The method of claim 32, further comprising, during the first mode, opening a switch to disconnect a capacitor from between a first terminal of an input transistor of the first LNA and ground.

37. An amplifier comprising: (a) a plurality of low noise amplifiers (LNA), each of the low noise amplifiers comprising an input transistor and an output transistor; (b) at least two control input terminals, each of the control input terminals coupled to an output transistor of a respective one of the LNAs; as well as (c) at least one drain switch, the at least one drain switch having a first terminal and a second terminal, the first terminal being directly connected to a source of a first output transistor among the output transistors and a drain of a first input transistor among the input transistors, and the second terminal being directly connected to a source of a second output transistor among the output transistors and a drain of a second input transistor among the input transistors, the at least one drain switch connecting drain terminals of the first input transistor and the second input transistor of at least two of the LNAs in a first operating mode and disconnecting the drain terminals in at least a second operating mode, wherein in the first operating mode, the output transistor of a first LNA among at least two LNAs among the plurality of low noise amplifiers LNAs is off, and the output transistor of a second LNA among the at least two LNAs is on.

38. An amplifier comprising: (a) a first low noise amplifier LNA, the first low noise amplifier LNA comprising an input transistor and an output transistor, each transistor having a control input, a source and a drain, wherein the drain of the input transistor is coupled in series to the source of the output transistor at a common connection point; (b) a second LNA comprising an input transistor and an output transistor, each transistor having a control input, a source and a drain, wherein the drain of the input transistor is coupled in series to the source of the output transistor at a common connection point; and (c) a drain switch that connects a common connection point of the first LNA and the second LNA in a single operation mode in which one of the output transistors is turned off, and disconnects the common connection point of the first LNA and the second LNA in a split operation mode.

39. The amplifier of claim 38, further comprising a source switch that connects sources of the first and second LNAs in the single operation mode and disconnects sources of the first and second LNAs in the split operation mode.

40. The amplifier of claim 38, further comprising a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and to disconnect the capacitance in the split operation mode.

41. The amplifier of claim 40, wherein The capacitance of the switchable gate capacitance module is selected such that an input impedance of the first LNA is substantially the same in the single operation mode and the split operation mode.

42. The amplifier of claim 38, further comprising a first switchable degenerate component coupled to a source of an input transistor of the first LNA and a second switchable degenerate component coupled to a source of an input transistor of the second LNA, wherein: The first and second switchable degenerative components are configured to couple a degeneration inductance to respective sources of input transistors of the first and second LNAs in the split operation mode, and to disconnect the degeneration inductance of at least one of the first and second switchable degenerative components in the single operation mode.

43. The amplifier of claim 38, further comprising a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein: The first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to corresponding drains of output transistors of the first LNA and the second LNA, respectively.

44. The amplifier of claim 38, wherein: In the single operation mode in which one of the output transistors is off, the other of the output transistors is on and the current through the on output transistor is the sum of the currents through the input transistors of the first and second LNAs.

45. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; as well as (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode.

46. ​​The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (c) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

47. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (c) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

48. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; (c) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (d) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

49. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (c) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

50. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; as well as (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

51. The amplifier of claim 38, further comprising: (a) a source switch that connects sources of input transistors of the first LNA and the second LNA in the single operation mode and disconnects sources of input transistors of the first LNA and the second LNA in the split operation mode; as well as (b) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

52. The amplifier of claim 38, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (c) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

53. The amplifier of claim 38, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

54. The amplifier of claim 38, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

55. The amplifier of claim 38, further comprising: (a) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degenerative inductance to the respective sources of the input transistors of the first and second LNAs in the split operation mode and to disconnect the degenerative inductance of at least one of the first and second switchable degenerative components in the single operation mode; and (b) a first load matching circuit coupled to a drain of an output transistor of the first LNA and a second load matching circuit coupled to a drain of an output transistor of the second LNA, wherein the first load matching circuit and the second load matching circuit are configured to selectively couple a first drain resistor and a second drain resistor to the respective drains of the output transistors of the first LNA and the second LNA, respectively.

56. An amplifier, comprising: (a) a first low noise amplifier LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; (b) a second LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; as well as (c) a drain switch that connects a common connection point of the first LNA and the second LNA during a single operation mode in which one of the output transistors is off, such that a drain current is the sum of currents through each input transistor, and disconnects the common connection point of the first LNA and the second LNA during a split operation mode.

57. An amplifier, comprising: (a) a plurality of low noise amplifiers LNA, each of the low noise amplifiers comprising an input transistor and an output transistor, the input transistor having a drain coupled in series to a source of the output transistor at a common connection point; (b) at least one drain switch that connects a common connection point of at least two of the LNAs in a single operation mode so that a drain current is the sum of currents through each input transistor, and disconnects the common connection point in a split operation mode, wherein the output transistor of a first LNA of at least two of the plurality of low noise amplifiers LNAs is off in the single operation mode and the output transistor of a second LNA of the at least two LNAs is on in the split operation mode.

Images