A three-table structure avalanche photodiode and manufacturing method thereof

Abstract

The present invention relates to an avalanche photodiode with a three-table structure and a manufacturing method thereof, wherein the avalanche photodiode comprises a Fe-InP substrate, an InP buffer layer, a P-type InGaAsP contact layer, a third table, a second table and a first table arranged from bottom to top; the third table comprises a P-type InP corrosion cutoff layer, a P-type InGaAsP gradient layer, a P-type InGaAs light absorption layer, an i-type InGaAs light absorption layer, a P-type AlGaInAs gradient layer, a P-type InP charge layer and an i-type InAlAs multiplication layer arranged from bottom to top; the second table comprises an N-type InP charge layer and an N-type InP fringe electric field buffer layer arranged from bottom to top; the first table comprises an N-type InGaAs contact layer. The avalanche photodiode and the manufacturing method thereof are conducive to improving the reliability and high-speed and high-bandwidth performance of the avalanche photodiode.

Description

Technical Field

[0001] The invention relates to the technical field of photodiodes, and in particular to a three-table structure avalanche photodiode and a manufacturing method thereof. Background Art

[0002] InP-based avalanche photodiodes have the advantages of high sensitivity and large responsiveness. As the core part of optical receivers, they are widely used in optical communication systems. When traditional planar avalanche photodiodes are manufactured, the size of the device's photosensitive surface is determined by the Zn diffusion window, and the curvature effect of the diffusion window makes the electric field intensity at the edge higher than that in the center of the photosensitive surface, which can easily cause edge breakdown at the edge of the diffusion window, affecting the normal operation of the device and reducing reliability.

[0003] The existing method of suppressing edge breakdown generally adopts diffusion or ion implantation again on the outer ring of the photosensitive surface to form a guard ring with a specific depth and diffusion concentration to improve the edge electric field. Another method is to first grow the charge layer and the layers below it, etch to form a mesa, and then use MOCVD to secondary epitaxially grow the InP layer above to improve the edge electric field and suppress premature breakdown. Summary of the invention

[0004] The object of the present invention is to provide a three-table structure avalanche photodiode and a manufacturing method thereof, which are beneficial to improving the reliability and high-speed, high-bandwidth performance of the avalanche photodiode.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a three-table structure avalanche photodiode, comprising an Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a third table (4), a second table (5) and a first table (6) arranged from bottom to top;

[0006] The third mesa comprises a P-type InP etching stop layer (41), a P-type InGaAsP gradient layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradient layer (45), a P-type InP charge layer (46) and an i-type InAlAs multiplication layer (47) arranged from bottom to top;

[0007] The second mesa comprises an N-type InP charge layer (51) and an N-type InP edge electric field buffer layer (52) arranged from bottom to top;

[0008] The first mesa comprises an N-type InGaAs contact layer (61).

[0009] Furthermore, each epitaxial layer is lattice matched with the substrate.

[0010] Furthermore, a P electrode (8) and an N electrode (9) are respectively arranged above the P-type InGaAsP contact layer and the N-type InGaAs contact layer.

[0011] Furthermore, a SiO2 passivation layer (7) is provided above and on the side walls of the three-terrace structure.

[0012] Furthermore, an anti-reflection film (10) is provided on the back side of the Fe-InP substrate, and when the avalanche photodiode is working, light is incident from the back side of the substrate.

[0013] Furthermore, the area of ​​the photosensitive surface of the avalanche photodiode is the area of ​​the first table.

[0014] The present invention also provides a method for manufacturing a three-table structure avalanche photodiode, comprising the following steps:

[0015] S1. On a Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a P-type InP etching stop layer (41), a P-type InGaAsP gradient layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradient layer (45), a P-type InP charge layer (46), an i-type InAlAs multiplication layer (47), an N-type InP charge layer (51), an N-type InP fringe electric field buffer layer (52) and an N-type InGaAs contact layer (61) are sequentially epitaxially grown to form an epitaxial wafer;

[0016] S2. Using SiO2 mask, photolithography, wet etching process, forming a first mesa on the epitaxial wafer;

[0017] S3. After forming the first mesa, a mask is formed by a photolithography process, and a second mesa is formed by wet etching;

[0018] S4. After forming the second mesa, a mask is formed by a photolithography process, and a third mesa is formed by dry etching and wet etching;

[0019] S5. removing the remaining SiO2 mask on the epitaxial wafer, and then depositing SiO2 by PECVD to grow a SiO2 passivation layer (7) on the top and sidewalls of the three-table structure;

[0020] S6. Open windows above the N-type InGaAs contact layer in the first table and the P-type InGaAsP contact layer in the third table, and evaporate N metal and P metal, respectively, to form an N electrode (9) and a P electrode (8);

[0021] S7. After the electrode is prepared, the epitaxial wafer is thinned and an anti-reflection film with a thickness of one-quarter of the working wavelength of the avalanche photodiode is evaporated on the back of the Fe-InP substrate.

[0022] Furthermore, in step S2, a SiO2 mask is deposited on the epitaxial wafer using PECVD; then the required pattern of the first mesa is transferred to the SiO2 mask by photolithography and etching, and then the N-type InGaAs contact layer is corroded using a H3PO4:H202:H20 mixed solution to obtain the first mesa.

[0023] Furthermore, in the step S3, the epitaxial wafer obtained by obtaining the first mesa is subjected to a photolithography process again, and a pattern required for the second mesa is transferred to the photoresist using a photoresist mask, and then the InP is etched using an HCl solution, and the remaining photoresist is removed to obtain the second mesa;

[0024] Furthermore, in step S4, the epitaxial wafer obtained by the second mesa is further subjected to a photolithography process, and the pattern required for the third mesa is transferred to the photoresist using a photoresist mask. First, ICP or RIE dry etching is used to etch from the i-type InAlAs multiplication layer to the InP etching stop layer from top to bottom, and then the remaining InP etching stop layer is removed using an HCl solution. After removing the remaining photoresist, the third mesa is obtained.

[0025] Compared with the prior art, the present invention has the following beneficial effects: by adopting a process combining wet etching and dry etching, a three-table structure avalanche photodiode is manufactured, without the need to adopt processes such as diffusion, ion implantation, MOCVD secondary epitaxy, etc., which can effectively suppress the edge electric field breakdown phenomenon and improve the reliability of the avalanche photodiode. In addition, the photosensitive surface is determined by the size of the first table, which can effectively reduce the parasitic capacitance of the avalanche photodiode, improve the high-speed performance, and thus improve the high-speed and high-bandwidth performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a three-mesa structure avalanche photodiode according to an embodiment of the present invention.

[0027] Figure 2 Schematic diagram of the epitaxial structure of a three-table structure avalanche photodiode in an embodiment of the present invention.

[0028] Figure 3 It is a cross-sectional schematic diagram of a three-table structure avalanche photodiode epitaxial wafer after masking SiO2 in an embodiment of the present invention.

[0029] Figure 4 It is a cross-sectional schematic diagram of transferring the first mesa pattern onto SiO2 in the three-mesa structure avalanche photodiode in an embodiment of the present invention.

[0030] Figure 5 It is a cross-sectional schematic diagram of the first mesa obtained after etching of the three-mesa structure avalanche photodiode in an embodiment of the present invention.

[0031] Figure 6 It is a cross-sectional schematic diagram of the second mesa obtained after etching of the three-mesa structure avalanche photodiode in an embodiment of the present invention.

[0032] Figure 7 Schematic diagram of the cross section of the third mesa obtained after etching of the three-mesa structure avalanche photodiode in the embodiment of the present invention.

[0033] Figure 8 It is a cross-sectional schematic diagram of a three-table structure avalanche photodiode after table passivation and electrode evaporation in an embodiment of the present invention.

[0034] Fig. 9 It is a cross-sectional schematic diagram of a three-table structure avalanche photodiode after substrate thinning and anti-reflection film fabrication in an embodiment of the present invention.

[0035] Fig.10 4 is a manufacturing flow chart of a three-table structure avalanche photodiode according to an embodiment of the present invention.

[0036] In the figure: 1-substrate, 2-InP buffer layer, 3-P-type InGaAsP contact layer, 4-third terrace, 41-P-type InP corrosion stop layer, 42-P-type InGaAsP gradient layer, 43-P-type InGaAs light absorption layer, 44-i-type InGaAs light absorption layer, 45-P-type AlGaInAs gradient layer, 46-P-type InP charge layer, 47-i-type InAlAs multiplication layer, 5-second terrace, 51-N-type InP charge layer, 52-N-type InP fringe electric field buffer layer, 6-first terrace, 61-N-type InGaAs contact layer, 7-SiO2 passivation layer, 8-P electrode, 9-N electrode, 10-antireflection film, 11-SiO2 mask, 12-photoresist. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the present invention provides a three-table structure avalanche photodiode, comprising a Fe-InP substrate 1, an InP buffer layer 2, a P-type InGaAsP contact layer 3, a third table 4, a second table 5 and a first table 6 arranged from bottom to top. A P electrode 8 and an N electrode 9 are arranged above the P-type InGaAsP contact layer and the N-type InGaAs contact layer, respectively. A SiO2 passivation layer 7 is arranged above and on the sidewalls of the three-table structure. An anti-reflection film 10 is arranged on the back of the Fe-InP substrate. When the avalanche photodiode is working, light is incident from the back of the substrate.

[0039] Since there is a large band gap between the light absorption layer InGaAs and InP, the discontinuity of the energy band will produce a potential barrier, hindering the movement of electrons and holes and affecting the high-frequency response of the device. Therefore, according to the different carriers, optimizing the InGaAsP or AlGaInAs gradient layer with different components can effectively reduce the potential barrier and improve the high-frequency response of the device.

[0040] like Figure 2 As shown, the third mesa includes a P-type InP corrosion stop layer 41, a P-type InGaAsP gradient layer 42, a P-type InGaAs light absorption layer 43, an i-type InGaAs light absorption layer 44, a P-type AlGaInAs gradient layer 45, a P-type InP charge layer 46 and an i-type InAlAs multiplication layer 47 arranged from bottom to top; the second mesa includes an N-type InP charge layer 51 and an N-type InP edge electric field buffer layer 52 arranged from bottom to top; the first mesa includes an N-type InGaAs contact layer 61.

[0041] Among them, each epitaxial layer (InP buffer layer 2, P-type InGaAsP contact layer 3, P-type InP corrosion stop layer 41, P-type InGaAsP gradient layer 42, P-type InGaAs light absorption layer 43, i-type InGaAs light absorption layer 44, P-type AlGaInAs gradient layer 45, P-type InP charge layer 46, i-type InAlAs multiplication layer 47, N-type InP charge layer 51, N-type InP fringe electric field buffer layer 52 and N-type InGaAs contact layer 61) is lattice matched with the substrate, that is, the lattice constant of each epitaxial layer material is consistent with the lattice constant of the substrate, that is, all materials are matched, not mismatched.

[0042] The area of ​​the photosensitive surface of the avalanche photodiode is the area of ​​the first table.

[0043] The present invention also provides a method for manufacturing the above-mentioned three-table structure avalanche photodiode, such as Fig.10 As shown, the following steps are included:

[0044] S1. On a Fe-InP substrate 1, an InP buffer layer 2, a P-type InGaAsP contact layer 3, a P-type InP corrosion stop layer 41, a P-type InGaAsP gradient layer 42, a P-type InGaAs light absorption layer 43, an i-type InGaAs light absorption layer 44, a P-type AlGaInAs gradient layer 45, a P-type InP charge layer 46, an i-type InAlAs multiplication layer 47, an N-type InP charge layer 51, an N-type InP fringe electric field buffer layer 52 and an N-type InGaAs contact layer 61 are sequentially epitaxially grown to form an epitaxial wafer.

[0045] S2. Using SiO2 mask, photolithography, and wet etching process, a first table is formed on the epitaxial wafer. Specifically, a layer of SiO2 mask is deposited on the epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD), such as Figure 3 Then, the required pattern of the first mesa is transferred to the SiO2 mask by photolithography and etching to form the first mesa etching window, as shown in FIG. Figure 4 After removing the photoresist with a stripping solution, the N-type InGaAs contact layer is etched with a H3PO4:H202:H20 mixed solution to obtain the first mesa, as shown in FIG. Figure 5 shown.

[0046] S3. After forming the first mesa, a mask is formed by photolithography, and a second mesa is formed by wet etching. Specifically, the epitaxial wafer obtained by the first mesa is subjected to photolithography again, and the pattern required for the second mesa is transferred to the photoresist using a photoresist mask, and then the InP is etched using an HCl solution, and the remaining photoresist is removed to obtain the second mesa, such as Figure 6 shown.

[0047] S4. After forming the second mesa, a mask is formed by photolithography, and a third mesa is formed by dry etching and wet etching. Specifically, the epitaxial wafer obtained by the second mesa is further subjected to photolithography, and the pattern required for the third mesa is transferred to the photoresist using a photoresist mask. First, ICP or RIE dry etching is used to etch from the i-type InAlAs multiplication layer to the InP etching stop layer from top to bottom, and then the remaining InP etching stop layer is removed using HCl solution. After removing the remaining photoresist, the third mesa is obtained, as shown in FIG. Figure 7 shown.

[0048] S5. Use buffered oxide etchant (BOE) to remove the residual SiO2 mask on the epitaxial wafer after the mesa etching, then use PECVD to deposit SiO2, and grow a SiO2 passivation layer 7 on the top and side walls of the three-mesa structure to protect the top and side walls of the mesa, reduce the surface leakage current, and improve the device reliability, such as Figure 8 shown.

[0049] S6. Open windows on the N-type InGaAs contact layer in the first mesa and the P-type InGaAsP contact layer in the third mesa, and evaporate N metal and P metal respectively to form N electrode 9 and P electrode 8.

[0050] S7. After the electrode is prepared, the epitaxial wafer is thinned, and an antireflection film with a thickness of one quarter of the working wavelength of the avalanche photodiode is evaporated on the back of the Fe-InP substrate, such as Fig. 9 shown.

[0051] The three-table avalanche photodiode and the manufacturing method thereof of the present invention do not require Zn diffusion, ion implantation and other processes. The three-table structure is used to optimize the edge electric field, suppress premature edge breakdown, increase the reliability of the device, and optimize the epitaxial structure design to enable it to have excellent characteristics of high speed and high bandwidth.

[0052] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

Claims

1. A three-table avalanche photodiode, characterized in that: It comprises an Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a third table (4), a second table (5) and a first table (6) which are arranged from bottom to top; The third mesa comprises a P-type InP etching stop layer (41), a P-type InGaAsP gradient layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradient layer (45), a P-type InP charge layer (46) and an i-type InAlAs multiplication layer (47) arranged from bottom to top; The second mesa comprises an N-type InP charge layer (51) and an N-type InP edge electric field buffer layer (52) arranged from bottom to top; The first mesa comprises an N-type InGaAs contact layer (61); Each epitaxial layer is lattice matched to the substrate; A P electrode (8) and an N electrode (9) are respectively arranged above the P-type InGaAsP contact layer and the N-type InGaAs contact layer; A SiO2 passivation layer (7) is arranged above and on the side walls of the three-table structure; The back of the Fe-InP substrate is provided with an anti-reflection film (10), and when the avalanche photodiode is working, light is incident from the back of the substrate; The area of ​​the photosensitive surface of the avalanche photodiode is the area of ​​the first table; The method for manufacturing the three-table structure avalanche photodiode comprises the following steps: S1. On a Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a P-type InP corrosion stop layer (41), a P-type InGaAsP gradient layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradient layer (45), a P-type InP charge layer (46), an i-type InAlAs multiplication layer (47), an N-type InP charge layer (51), an N-type InP fringe electric field buffer layer (52) and an N-type InGaAs contact layer (61) are sequentially epitaxially grown to form an epitaxial wafer; S2. A first mesa is formed on the epitaxial wafer by using a SiO2 mask, photolithography, and wet etching process; in the step S2, a SiO2 mask is deposited on the epitaxial wafer by using PECVD; then the required pattern of the first mesa is transferred to the SiO2 mask by photolithography and etching, and then the N-type InGaAs contact layer is etched by using a H3PO4:H202:H20 mixed solution to obtain a first mesa; S3. After forming the first mesa, a mask is formed by photolithography, and a second mesa is formed by wet etching; in the step S3, the epitaxial wafer obtained by the first mesa is subjected to photolithography again, and the pattern required for the second mesa is transferred to the photoresist using a photoresist mask, and then the InP is etched using an HCl solution, and the remaining photoresist is removed to obtain the second mesa; S4. After forming the second mesa, a mask is formed by photolithography, and a third mesa is formed by dry etching and wet etching; in the step S4, the epitaxial wafer obtained by the second mesa is further subjected to photolithography, and the pattern required for the third mesa is transferred to the photoresist using a photoresist mask, and firstly, ICP or RIE dry etching is used to etch from the i-type InAlAs multiplication layer to the InP etching stop layer from top to bottom, and then the remaining InP etching stop layer is removed by HCl solution, and the third mesa is obtained after removing the remaining photoresist; S5. Removing the residual SiO2 mask on the epitaxial wafer, and then depositing SiO2 by PECVD, growing a SiO2 passivation layer (7) on the top and side walls of the three-table structure; S6. Open windows above the N-type InGaAs contact layer in the first mesa and the P-type InGaAsP contact layer in the third mesa, and evaporate N metal and P metal to form an N electrode (9) and a P electrode (8); S7. After the electrode preparation is completed, the epitaxial wafer is thinned and a layer of anti-reflection film with a thickness of one-quarter of the working wavelength of the avalanche photodiode is evaporated on the back of the Fe-InP substrate.

Images