Peaking inductor embedded in T-coil

Abstract

The present invention relates to a peaking inductor embedded in a T-coil, and discloses a structure including a peaking inductor and a T-coil, and a method associated with forming such a structure. A back-end process interconnect structure includes a first metallization level, a second metallization level, and a third metallization level disposed between the first metallization level and the second metallization level. The T-coil includes a first inductor having a first coil disposed in the first metallization level and a second inductor having a second coil disposed in the second metallization level. The peaking inductor includes a coil disposed in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end process interconnect structure in a stacked arrangement.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to structures including peaking inductors and T-coils, and methods associated with forming such structures. Background Art

[0002] Inductors represent an on-chip passive device that is commonly used in many types of monolithic integrated circuits designed to operate at high frequencies. Inductors can be manufactured in the metallization levels of the back-end-of-line (BEOL) interconnect structures on a chip. Inductors can be characterized by a quality factor, which is a quality factor that represents a measure of the relationship between energy loss and energy storage. A high value of the quality factor reflects low energy loss to the substrate of the chip. However, increasing the quality factor comes at the expense of increasing the size of the inductor. The design of an on-chip inductor often must balance the space occupied by the inductor on the chip with the value of the quality factor of the inductor as a compromise.

[0003] Chips may integrate on-chip inductors with T-coils in circuit designs to provide inductive peaking. These circuit designs often make fairly inefficient use of available space in the BEOL interconnect structure. In particular, completely separate and laterally extended areas are often used in chip layout to place the on-chip peaking inductor and to place the T-coil. The T-coil and on-chip peaking inductor also have separate keep out zones, which further exacerbates the inefficient use of available space on the chip.

[0004] There is a need for improved structures including peaking inductors and T-coils, and methods associated with forming such structures. Summary of the invention

[0005] In one embodiment of the present invention, a structure includes a back-end process interconnect structure having a first metallization level, a second metallization level, and a third metallization level disposed between the first metallization level and the second metallization level. The structure also includes a T-coil having a first inductor and a second inductor, the first inductor having a first coil disposed in the first metallization level and the second inductor having a second coil disposed in the second metallization level. A peaking inductor includes a coil disposed in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end process interconnect structure in a stacked arrangement.

[0006] In one embodiment of the present invention, a method includes forming a first inductor having a T-coil of a first coil disposed in a first metallization level of a back-end process interconnect structure, forming a second inductor having a second coil disposed in a second metallization level of the back-end process interconnect structure, and forming a peaking inductor having a coil disposed in a third metallization level of the back-end process interconnect structure. The third metallization level is disposed between the first metallization level and the second metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end process interconnect structure in a stacked arrangement. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0008] Figure 1 A circuit diagram showing a circuit including an inductor and a T-coil according to an embodiment of the present invention.

[0009] Figure 2 show Figure 1 A three-dimensional diagram of an inductor and a T-coil, wherein the interlayer dielectric layer is omitted for simplicity of explanation.

[0010] Figure 3 Display the approximate Figure 2 A cross-sectional view taken along line 3-3.

[0011] Figure 4 Display the approximate Figure 2 A cross-sectional view taken along line 4-4.

[0012] Figure 5 Display the approximate Figure 2 A cross-sectional view taken along line 5-5. DETAILED DESCRIPTION

[0013] Please refer to Figure 1 According to an embodiment of the present invention, the circuit 10 includes a plurality of inductors 12, 14, 16 disposed on a chip, and the chip also includes one or more integrated circuits manufactured by a front-end-of-line (FEOL) process. The inductors 12, 14, 16 are located within an interconnect structure 30 of the chip ( Figure 2-4), the interconnection structure can be formed by a back-end-of-line (BEOL) process. Inductors 12 and 14 are included in the circuit 10 as a connecting component of a T-coil. The turns or windings of the inductors 12 and 14 included in the T-coil are stacked in an upright direction with the turns or windings of the inductor 16, as described later, to provide a composite structure having windings in a stacked arrangement. The stacked arrangement of the windings of the inductors 12, 14, and 16 provides a more compact structure compared to a non-stacked arrangement.

[0014] Terminal 11 of inductor 12, terminal 13 of inductor 14, and terminal 15 of inductor 16 are coupled to a common node 18. Circuit 10 may also include electrostatic discharge devices 20, 22, input / output pad 24, design component 26, and transmission line termination resistor 29. Design component 26 may be a driver or gain stage, such as an amplifier. Inductor 16 may have terminal 17 coupled to design component 26. Input / output pad 24 is coupled to terminal 25 of inductor 12, electrostatic discharge devices 20, 22 are coupled to common node 18, and transmission line termination resistor 29 (e.g., a 50 ohm metal resistor) is coupled to terminal 27 of inductor 14. Signals may be sent from input / output pad 24 in a signal path through circuit 10 to design component 26. Electrostatic discharge devices 20, 22 may be used to protect sensitive device structures of design component 26 from receiving high currents of an electrostatic discharge event occurring at input / output pad 24. The electrostatic discharge devices 20, 22 may be diodes of a diode string, for example. The inductors 12, 14 of the T-coil may have the characteristics of parasitic capacitance, although not an actual physical circuit component, which is represented by the symbol C T exist Figure 1 Indicated schematically.

[0015] Inductor 16 can be used, for example, for bandwidth extension in high-speed transceiver designs and is also referred to herein as a peaking inductor. The T-coil inductors 12, 14 can be used in high-speed transceiver designs to compensate for the capacitance of ESD devices 20, 22, for example, to maintain return loss and reduce insertion loss.

[0016] Please refer to Figure 2-5According to an embodiment of the present invention, the inductors 12, 14 and the inductor 16 of the T-coil can be stacked in a composite structure arranged in an upright spacing in multiple metallization levels of the back-end process (BEOL) interconnect structure (generally represented by the reference numeral 30). The inductors 12, 14, 16 of the composite structure together include multiple coils, which are stacked in interlayer dielectric layers 62, 66, 70, 74, 78 belonging to multiple metallization levels. Each inductor 12, 14, 16 can include one or more coils, which are stacked in one or more of the metallization levels and can be connected in parallel and / or in series. In one embodiment, the inductors 12, 14, 16 of the composite structure can include five coils arranged in five different metallization levels. In one embodiment, the coils of the inductors 12, 14, 16 are arranged in different metallization levels, and there is only a single coil in each metallization level. The coil of inductor 12, the coil of inductor 14, and the coil of inductor 16 are stacked in a stacked arrangement in the different metallization levels of the BEOL interconnect structure 30. The stacking is provided by the relative lateral positioning of the inductors 12, 14, 16 in the different metallization levels of the BEOL interconnect structure 30 and the relative sizes of the inductors 12, 14, 16.

[0017] In this representative embodiment, the inductor 16 is included in a metallization level (M) located at the BEOL interconnect structure 30. x+1 ) is provided in a plurality of turns or windings 36 in a coil within an interlayer dielectric layer 70, and the inductor 16 also includes a metallization level (M) at the BEOL interconnect structure 30. x+2 ) is provided in a coil within an interlayer dielectric layer 74. The inductor 12 of the T-coil includes a plurality of turns or windings 38 disposed in a coil within an interlayer dielectric layer 74 of the BEOL. x+3 ) is provided in a coil within an interlayer dielectric layer 78. The inductor 14 of the T-coil includes a plurality of turns or windings 40 disposed in a coil within an interlayer dielectric layer 78 of the BEOL interconnect structure 30. x-1 ) in the coil within the interlayer dielectric layer 61, and at the metallization level (M) located at the BEOL interconnect structure 30. x ) of the coil in the interlayer dielectric layer 66. At the lowest metallization level (M x-1 ) may have additional metallization levels (not shown) below, and at the highest metallization level (M x+3 ) There may be additional metallization levels (not shown) above the integrated circuit. Additional conductive features (not shown) in the different metallization levels interconnect the devices of the integrated circuit, and the additional conductive features may provide circuit-to-circuit connections or may establish contacts with input and output terminals.

[0018] Each set of windings 32, 34, 36, 38, 40 may be viewed as being wound or spiraled inwardly from the terminal terminals of the outermost winding to the terminal terminals of the innermost winding, which are disposed in a central region 60 of the composite structure, which is filled with dielectric material from the interlayer dielectric layers 62-78 of the BEOL interconnect structure 30. In this representative embodiment, the coil provided by each set of windings 32, 34, 36, 38, 40 may have a rectangular layout with straight line segments disposed about a common centerline and defining angles where the segments intersect to provide directional changes. The height and width dimensions of the individual windings in each set of windings 32, 34, 36, 38, 40 may be different, so that their respective cross-sectional areas may be different. For example, the cross-sectional area of ​​winding 40 may be greater than the cross-sectional area of ​​winding 32 or the cross-sectional area of ​​winding 34.

[0019] Inductor 12 has a perimeter 41 established by outermost winding 40, and innermost winding 40 arranged and configured to facilitate establishing a stand-up interconnection with inductor 14. Inductor 16 has a perimeter 39 established by outermost winding 36 and / or outermost winding 38, and innermost windings 36, 38 arranged and configured to allow the stand-up interconnection between inductors 12, 14 of the T-coil to pass without crossing or connecting between the stand-up interconnection and the innermost windings 36, 38. Inductor 14 has a perimeter 35 established by one or both of outermost windings 32, 34.

[0020] The perimeter 41 of inductor 12 may surround an area generally defined by a width dimension W1 and a length dimension across the width dimension. The perimeter 35 of inductor 14 may surround an area generally defined by a width dimension W3 and a length dimension across the width dimension. In one embodiment, the dimensions of inductor 12 may be substantially equal to the dimensions of inductor 14 to provide substantially equal areas. The perimeter 39 of inductor 16 may surround an area generally defined by a width dimension W2 and a length dimension across the width dimension. The area of ​​inductor 12 and the area of ​​inductor 14 may each be greater than the area of ​​inductor 16. The area of ​​inductor 12 may be equal to the area of ​​inductor 14.

[0021] The footprint represented by the respective areas of each inductor 12, 14, 16 may be projected in an upright direction relative to the substrate 28. In one embodiment, the lateral dimensions of the inductor 16 at its perimeter 39 may be smaller than the lateral dimensions of the inductors 12, 14 at their respective perimeters 35, 41, and the lateral arrangement may laterally position the area occupied by the inductor 16 within or inside the respective areas occupied by the inductors 12, 14 to provide a stacked arrangement from an upright perspective. In an alternative embodiment, the lateral dimensions of the inductor 16 at its perimeter 39 may be substantially equal to the lateral dimensions of the inductors 12, 14 at their respective perimeters 35, 41, and the lateral arrangement may position the area occupied by the inductor 16 to laterally coincide with the respective areas occupied by the inductors 12, 14 to provide a fully stacked arrangement. This stacked arrangement of the inductor 16 with the inductors 12, 14 efficiently utilizes the available space in the BEOL interconnect structure 30.

[0022] In one embodiment, perimeter 39 of inductor 16 is disposed entirely within or bounded by perimeter 41 of inductor 12, such that the surrounding area of ​​inductor 16 is smaller than the surrounding area of ​​inductor 12. In one embodiment, perimeter 39 of inductor 16 is disposed entirely within or bounded by perimeter 35 of inductor 14, such that the surrounding area of ​​inductor 16 is smaller than the surrounding area of ​​inductor 14. In one embodiment, perimeter 39 of inductor 16 is disposed entirely within or bounded by perimeter 41 of inductor 12 and disposed entirely within perimeter 35 of inductor 14, such that the surrounding area of ​​inductor 16 is smaller than the surrounding area of ​​inductor 12 and smaller than the surrounding area of ​​inductor 14. Although disposed in different metallization levels of BEOL interconnect structure 30, the different coils used herein may have a confined and stacked arrangement.

[0023] The winding 36 of the inductor 16 is connected in series with the winding 38 of the inductor 16 by a vertical connection, which is formed by a via level (V x+1 ) in the via 42, the via level (V x+1 ) is located vertically at the metallization level (M) of the BEOL interconnect structure 30 x+1 ) and metallization level (M x+2 ). The via 42 is located between the via level (V x+1 ) in the via opening of the interlayer dielectric layer 72. The winding 38 is connected to the terminal 17 ( Figure 1 ) spirals inwardly from a terminal of the inductor 16 to a via 42, and the winding 36 spirals outwardly from the via 42 to the other terminal of the inductor 16. The latter terminal of the inductor 16 is connected to the center tap 44 by a vertical connection provided at the via level (V x) in the via 46, the via level (V x ) is located vertically at the metallization level (M) of the BEOL interconnect structure 30 x+1 ) and metallization level (M x ). The via 46 is located between the via level (V x ) in a via opening of an interlayer dielectric layer 68. The center tap 44 may be provided at a metallization level (M x-1 ), whose entities represent the common node 18 of the circuit 10 ( Figure 1 ) and connected to the winding 32 of the inductor 14.

[0024] The inductor 12 of the T-coil terminates at a terminal 25 ( Figure 1 ). A winding 40 of the inductor 12 spirals inwardly from this terminal to another terminal of the inductor 12 disposed near the center of the inductor 12. x+3 ) is connected to the inductor 12 via a vertical interconnection at the metallization level (M x ) is connected to the winding 34 in the inductor 16. In the representative embodiment, the vertical interconnection is provided by a stacked series of vias 48, 50, 52 that extend through the winding 38 for providing the coil of the inductor 16 and the winding 36 for providing the coil of the inductor 16 in the central region 60 of the composite structure. The via 48 is provided at the via level (V x+2 ), the via level (V x+2 ) is located vertically at the metallization level (M) of the BEOL interconnect structure 30 x+2 ) and metallization level (M x+3 ), the via 50 is disposed at the via level (V x+1 ), and the via 52 is arranged at the via level (V x ) in the metallization level (M) comprising the winding 36 of the inductor 16. x+2 ) is disposed between vias 48, 50 and is located at a metallization level (M) including winding 34 of inductor 16. x+1 ) is disposed between vias 46 and 48. Via 48 is located in a vertical direction extending through the via level (V x+2 ) in the via opening of the interlayer dielectric layer 76, the via 50 is located in the vertical direction extending through the via level (V x+1 ) in the via opening of the interlayer dielectric layer 72, and the via 52 is located in the vertical direction extending through the via level (V x ) in the via opening of the interlayer dielectric layer 68.

[0025] The vias 48, 50, 52, and in particular the via 50, are offset relative to the via 42 to facilitate the formation of vertical interconnections between the inductors 12, 14, 16. The vertical interconnections provided by the vias 48, 50, 52 extend through the metallization level (M) from the upper coil (e.g., the winding 40 of the inductor 16). x+2 )、(M x+1 ) to the metallization level below (M x ) without being connected to the windings 36 , 38 of either middle coil of the inductor 16 .

[0026] The center tap 44 is at the metallization level (M x-1 ) is connected to the terminals of the winding 32 of the inductor 14. At the metallization level (M x ) is connected in parallel with the winding 32 of the inductor 14 and the winding 34 of the inductor 14 by a vertical connection, which is provided at the via level (V x-1 ) is provided in the via 54 in the interlayer dielectric layer 64, the via level (V x-1 ) is located vertically at the metallization level (M) of the BEOL interconnect structure 30 x ) and metallization level (M x-1 ). In one embodiment, the via 54 may be a strip-shaped via. The coupling windings 32 and 34 of the inductor 14 spiral outward from the terminal coupled to the center tap 44 to another terminal 27 ( Figure 1 In an alternative embodiment, the metallization layer (M x-1 ) of the winding 32 of the inductor 14, so that the inductor 14 only includes the winding 34, and the center tap 44 is located at the metallization level (M x ) and connected to winding 34.

[0027] The inductors 12, 14 and the inductor 16 of the T-coil may have various arrangements, such as the arrangement in the representative embodiment, in which the inductor 16 is sandwiched between the inductors 12, 14 of the T-coil, the inductor 16 is disposed above the inductors 12, 14 of the T-coil, or the inductor 16 is disposed below the inductors 12, 14 of the T-coil. In one embodiment, the inductor 16 may include only a single coil winding, rather than a multi-coil winding. In one embodiment, the windings 32, 34 of the inductor 16 may be disposed in different metallization levels and connected in parallel, rather than in series. In one embodiment, the windings 32, 34 of the inductor 14 may be connected in series, rather than in parallel. In one embodiment, the inductor 14 may include multiple coils that may be connected in parallel or in series.

[0028] The windings 32, 34, 36, 38, 40 disposed in the different metallization levels of the BEOL interconnect structure 30 and the vias 42, 46, 48, 50, 52 disposed in the different via levels of the BEOL interconnect structure 30 may be formed by a damascene process, wherein trenches and via openings are formed in associated interlayer dielectric layers by photolithography and etching processes and filled with one or more conductors (e.g., one or more metals) that are deposited and planarized. The main conductors of the windings 32, 34, 36, 38, 40 and the vias 42, 46, 48, 50, 52 may be composed of a metal, such as copper, cobalt, or ruthenium, deposited by, for example, electroless or electrolytic deposition using a seed layer. A conductive barrier / liner layer may be disposed between the main conductor and the surface of the interlayer dielectric layer. The barrier / liner layer may be composed of one or more conductive materials, such as titanium nitride, tantalum nitride, tantalum, titanium, tungsten, tungsten nitride, cobalt, ruthenium, or a layered stack of these conductive materials (e.g., a titanium and titanium nitride bilayer), which is deposited by, for example, physical vapor deposition or chemical vapor deposition. The interlayer dielectric layers 62-78 may be composed of one or more dielectric materials, such as silicon dioxide or silicon nitride.

[0029] In one embodiment, field effect transistors may be connected to inductor 12, inductor 14, and / or inductor 16 to provide the ability to adjust the corresponding inductance value. In one embodiment, any or all of windings 32, 34, 36, 38, 40 may be composed of magnetically conductive materials to enhance the inductance of the associated inductor 12, 14, 16, thereby allowing for further size reduction. In one embodiment, interlayer dielectric layers 62-78 associated with one or more of the metallization levels of inductors 12, 14, 16 may include air gaps having a lower dielectric constant than solid dielectric materials, thereby reducing capacitive coupling. In one embodiment, inductors 12, 14 may be configured as Pi coils rather than T coils.

[0030] The composite structure including the inductors 12, 14 and 16 of the T-coil has a reduced size because the inductor 16 is embedded within the inductors 12, 14, as opposed to a laterally extended arrangement of the T-coil and the peaking inductor that inefficiently utilizes the available space on the chip. To further improve the efficient utilization of the available space on the chip, the inductors 12, 14 and 16 of the T-coil of the composite structure also share a common keep-out zone around their upright stacked coils, rather than having a laterally extended arrangement of the keep-out zones of the inductors 12, 14 of the T-coil and a separate keep-out zone of the inductor 16. Because they are integrated into the composite structure, the magnetic coupling between the inductors 12, 14 and 16 of the T-coil is accounted for at the device level rather than at the layout level. The size of the inductor 16 can be increased, for example to increase the quality factor, without the same concerns about inefficient utilization of the available space on the chip that occurs when the T-coil and the peaking inductor have a laterally spaced arrangement.

[0031] The method described above is used in the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is provided in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In any case, the chip is then integrated with other chips, discrete circuit components and / or other signal processing devices as part of an intermediate product or a final product.

[0032] Terms such as "upright", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "upright" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0033] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0034] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0035] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device structure, comprising: A back-end process interconnect structure includes a first metallization level, a second metallization level, and a third metallization level disposed between the first metallization level and the second metallization level; a T-coil including a first inductor having a first coil disposed in the first metallization level and a second inductor having a second coil disposed in the second metallization level; as well as a peaking inductor having a first coil disposed in the third metallization level, The first coil of the first inductor, the second coil of the second inductor, and the first coil of the peaking inductor are stacked in a stacked arrangement in the back-end process interconnect structure.

2. The semiconductor device structure according to claim 1, wherein: The back end process interconnect structure includes an upstanding interconnect extending from the first coil of the first inductor to the second coil of the second inductor.

3. The semiconductor device structure according to claim 2, wherein: The vertical interconnect passes through the third metallization level without connecting to the first coil of the peaking inductor.

4. The semiconductor device structure according to claim 2, wherein: The T-coil and the peaking inductor include a central region filled with a dielectric material of the back end process interconnect structure, and the upright interconnect extends through the central region.

5. The semiconductor device structure according to claim 2, wherein: The vertical interconnect includes a first via in a first via level between the first metallization level and the third metallization level, and the vertical interconnect includes a second via in a second via level between the second metallization level and the third metallization level.

6. The semiconductor device structure according to claim 1, wherein: The first metallization level is arranged above the third metallization level, the second metallization level is arranged below the third metallization level, the back-end process interconnection structure includes a fourth metallization level arranged below the second metallization level, and the second inductor includes a third coil arranged in the fourth metallization level, and the third coil is coupled in parallel with the second coil.

7. The semiconductor device structure according to claim 1, wherein: The first metallization level is disposed above the third metallization level, the second metallization level is disposed below the third metallization level, the back-end process interconnect structure includes a fourth metallization level disposed between the first metallization level and the second metallization level, and the peaking inductor includes a second coil disposed in the third metallization level, the second coil being coupled in series with the first coil of the peaking inductor.

8. The semiconductor device structure according to claim 1, wherein: The first inductor, the second inductor, and the peaking inductor are connected to a common node.

9. The semiconductor device structure of claim 8, further comprising: designing a component coupled to the common node through the peaking inductor; an input / output pad coupled to the common node through the first inductor; as well as A terminal resistor is coupled to the common node through the second inductor.

10. The semiconductor device structure of claim 9, further comprising: The electrostatic discharge device is coupled to the common node.

11. The semiconductor device structure according to claim 1, wherein: The first coil of the first inductor has a first perimeter surrounding a first area, the second coil of the second inductor has a second perimeter surrounding a second area, and the first coil of the peaking inductor has a third perimeter surrounding a third area, the third area is smaller than the first area, and the third area is smaller than the second area.

12. The semiconductor device structure according to claim 1, wherein: The first coil of the first inductor has a first periphery surrounding a first region, the second coil of the second inductor has a second periphery surrounding a second region, the first coil of the peaking inductor has a third periphery surrounding a third region, and the third periphery of the first coil of the peaking inductor is limited by the first periphery of the first coil of the first inductor.

13. The semiconductor device structure according to claim 11, wherein: The third perimeter of the first coil of the peaking inductor is bounded by the second perimeter of the second coil of the second inductor.

14. A method of forming a semiconductor device structure, the method comprising: forming a first inductor having a T-coil having a first coil disposed in a first metallization level of a back end process interconnect structure; forming a second inductor of the T-coil having a second coil disposed in a second metallization level of the back end process interconnect structure; as well as forming a peaking inductor having a coil disposed in a third metallization level of the back end process interconnect structure, The third metallization level is disposed between the first metallization level and the second metallization level, and the first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end process interconnect structure in a stacked arrangement.

15. The method of claim 14, further comprising: A first vertical interconnect is formed in the back-end process interconnect structure, the first vertical interconnect extending from the first coil of the first inductor to the second coil of the second inductor.

16. The method of claim 15, wherein: The first vertical interconnect passes through the third metallization level without being connected to the coil of the peaking inductor.

17. The method of claim 15, wherein: The first vertical interconnect includes a first via in a first via level between the first metallization level and the third metallization level, and the first vertical interconnect includes a second via in a second via level between the second metallization level and the third metallization level.

18. The method of claim 15, further comprising: A second vertical interconnect is formed in the back-end process interconnect structure, the second vertical interconnect extending from the second coil of the second inductor to the coil of the peaking inductor.

19. The method of claim 15, wherein: The first coil of the first inductor has a first periphery surrounding a first region, the second coil of the second inductor has a second periphery surrounding a second region, the coil of the peaking inductor has a third periphery surrounding a third region, and the third periphery of the coil of the peaking inductor is limited by the first periphery of the first coil of the first inductor.

20. The method of claim 19, wherein: The third perimeter of the coil of the peaking inductor is bounded by the second perimeter of the second coil of the second inductor.

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