A semiconductor structure

Abstract

The application provides a semiconductor structure, and relates to the technical field of semiconductor production, which comprises a first wafer and a second wafer stacked into one body; wherein the first wafer comprises a capacitor region and a non-capacitor region; the second wafer comprises an array region and a control region; the capacitor region corresponds to the array region, and the non-capacitor region corresponds to the control region; and the first wafer and the second wafer are electrically connected. The semiconductor structure in the technical scheme provided by the application is stacked by two wafers, and compared with the prior art, the density and production speed of the semiconductor structure on the wafer can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor structure. Background Technology

[0002] DRAM (Dynamic Random Access Memory) and other semiconductor devices are mostly planar in structure. By improving process technology, circuit design, programming algorithms, and manufacturing processes, semiconductor devices can be scaled down to smaller sizes. However, as the feature size of semiconductor devices approaches its lower limit, planar processes and manufacturing technologies become challenging and costly.

[0003] As electronic devices and memory devices become smaller and thinner, there are higher requirements for the size and thickness of memory chips.

[0004] In addition, when using planar processes and manufacturing techniques to produce memory chips such as DRAM, the production cycle is longer and the production speed is slower due to the limitations of the process sequence.

[0005] Therefore, how to increase the density and production speed of semiconductor chips such as memory chips on wafers is a problem that needs to be solved.

[0006] It should be noted that the information in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor structure that at least to some extent improves the density and production speed of semiconductor structures on wafers.

[0008] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0009] According to an embodiment of the present invention, a semiconductor structure is provided, comprising a first wafer and a second wafer stacked together; wherein the first wafer includes a capacitor region and a non-capacitor region; the second wafer includes an array region and a control region; the capacitor region and the array region correspond to each other, and the non-capacitor region and the control region correspond to each other; the first wafer and the second wafer are electrically connected.

[0010] In one embodiment, the capacitor region of the first wafer includes a capacitor structure, and the non-capacitor region includes a first conductive interconnect structure.

[0011] In one embodiment, the array region of the second wafer includes an active region, and the control region of the second wafer includes a second conductive interconnect structure and a control structure, wherein the second conductive interconnect structure and the control structure are electrically connected.

[0012] In one embodiment, the capacitor structure includes: a second electrode located in the capacitor region; a dielectric layer disposed on the second electrode; and a first electrode disposed on the dielectric layer.

[0013] In one embodiment, the capacitor region is provided with an isolation layer, and the second electrode is disposed on the isolation layer.

[0014] In one embodiment, the capacitor structure includes: a first electrode located in the capacitor region; a dielectric layer disposed on the first electrode; and a second electrode disposed on the dielectric layer.

[0015] In one embodiment, the capacitor region is provided with an isolation layer, and the first electrode is disposed on the isolation layer.

[0016] In one embodiment, a first electrode of the first wafer is electrically connected to an active region of the second wafer, and a first conductive interconnect structure of the first wafer is electrically connected to a second conductive interconnect structure of the second wafer.

[0017] In one embodiment, the first conductive interconnect structure of the first wafer includes a top conductive layer, a first conductive plug, and a second conductive plug; the first conductive plug connects the top conductive layer and a second electrode, and the second conductive plug connects the top conductive layer and the second conductive interconnect structure; the number of the first conductive plug is at least 1, and the number of the second conductive plug is at least 1.

[0018] In one embodiment, the first conductive interconnect structure of the first wafer includes a top conductive layer, a first conductive plug, a second conductive plug, and a middle interconnect structure; the second conductive plug includes a first second conductive plug and a second second conductive plug; the first conductive plug connects the top conductive layer and a second electrode, the first second conductive plug connects the top conductive layer and the middle interconnect structure, and the second second conductive plug connects the middle interconnect structure and the second conductive interconnect structure; the number of the first conductive plug is at least 1, the number of the first second conductive plug is at least 1, and the number of the second second conductive plug is at least 1.

[0019] In one embodiment, the central interconnect structure includes at least one central conductive layer, and more than one central conductive layer is connected to each other by a third conductive plug; the number of the third conductive plug is at least one.

[0020] In one embodiment, the second conductive interconnect structure contains at least two lower conductive layers connected to each other by a fourth conductive plug; the number of the fourth conductive plug is at least one.

[0021] In one embodiment, the first electrode of the first wafer is electrically connected to the active region of the second wafer via a fifth conductive plug, wherein the number of the fifth conductive plug is at least one.

[0022] In one embodiment, the first wafer includes a first substrate, the capacitor structure is located in the first substrate, and the first conductive interconnect structure is connected to the first substrate; the first substrate contains a first dielectric material.

[0023] In one embodiment, the first substrate is a doped substrate.

[0024] In one embodiment, the capacitor region further includes a capacitor connection member connected to the second electrode of the capacitor structure.

[0025] In one embodiment, the capacitor connection member is connected to either the first conductive interconnect structure or the second conductive interconnect structure.

[0026] In one embodiment, a second dielectric material, which is the same as the first dielectric material, is included around the first conductive interconnect structure of the first wafer.

[0027] In one embodiment, a second dielectric material is included around the first conductive interconnect structure of the first wafer, and the second dielectric material is different from the first dielectric material.

[0028] In one embodiment, the orthographic projections of the lower conductive layers in the second conductive interconnect structure overlap.

[0029] In one embodiment, the materials of the first dielectric layer and the second dielectric layer include one or any combination of oxides, nitrides, silicides, carbides or amorphous carbon.

[0030] In one embodiment, the materials of the first conductive interconnect structure and the second conductive interconnect structure include one or any combination of copper, aluminum, tin or tungsten.

[0031] In one embodiment, the first conductive interconnect structure includes a first conductive layer exposed on the surface of the first wafer that contacts the second wafer; the second conductive interconnect structure includes a second conductive layer exposed on the surface of the second wafer that contacts the first wafer; the first conductive layer is connected to the second conductive layer.

[0032] In one embodiment, the control structure includes a transistor structure, the transistor structure including a source, a drain, and a gate.

[0033] In one embodiment, the active region has a buried gate structure, a fifth conductive plug, and a bit line plug; the bit line plug is located above the middle of the active region, the fifth conductive plug is located above both ends of the active region, and the fifth conductive plug is exposed on the surface of the second wafer that contacts the first wafer.

[0034] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0035] In an exemplary embodiment of the present invention, the semiconductor structure is formed by stacking two wafers. Compared with the prior art, this increases the density of the semiconductor structure on the wafer, allowing the first wafer and the second wafer to be produced simultaneously, thereby increasing the production speed of the semiconductor structure.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0038] Figure 1 The schematic diagram shows a cross-sectional view of a semiconductor structure in one embodiment of the present invention;

[0039] Figure 2a The schematic diagram shows a cross-sectional view of the capacitor region in one embodiment of the present invention;

[0040] Figure 2b A schematic cross-sectional view of the capacitor region is shown in another embodiment of the present invention;

[0041] Figure 3 A schematic cross-sectional view of the second wafer in an embodiment of the present invention is shown.

[0042] Figure 4 A schematic cross-sectional view of the first wafer in an embodiment of the present invention is shown.

[0043] Figure 5a A schematic cross-sectional view of the capacitor region is shown in another embodiment of the present invention;

[0044] Figure 5b A schematic cross-sectional view of the capacitor region is shown in another embodiment of the present invention;

[0045] Figure 6 A schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown.

[0046] Figure 7a A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention;

[0047] Figure 7b A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention;

[0048] Figure 7c A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention;

[0049] Figure 7d A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention;

[0050] Figure 8 A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention;

[0051] Figure 9 A schematic cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0053] Although this specification uses relative terms such as "up" and "down" to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as the orientation of the examples shown in the accompanying drawings. It is understood that if the modules of the icon are flipped so that they are upside down, the component described as "up" will become the component described as "down." Other relative terms, such as "high," "low," "top," "bottom," "left," and "right," have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" placed on the other structure, or that the structure is "indirectly" placed on the other structure through another structure.

[0054] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0055] In DRAM structures of related technologies, the production process is lengthy because multiple different processes are used on the same wafer during fabrication, and the fabrication of different parts cannot be performed simultaneously. Furthermore, when DRAM structures are manufactured using planar processes, the number of devices per unit area of ​​wafer is relatively small.

[0056] Stacked wafer structures, formed by stacking semiconductor wafers, can function as single devices, thereby achieving performance improvements with a smaller footprint compared to conventional planar processes.

[0057] Here, we will use a DRAM chip as an example of a semiconductor chip for illustration, but semiconductor chips are not limited to DRAM chips.

[0058] This disclosure provides a semiconductor structure with a stacked wafer structure. This allows two or more wafers to be produced simultaneously on different production lines, and the semiconductor structure is formed through bonding and subsequent processes, thus shortening production time. The exemplary embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0059] Figure 1 A schematic cross-sectional view of a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, with reference to... Figure 1 The semiconductor structure 400 provided in this embodiment of the invention includes a first wafer and a second wafer stacked together. The first wafer includes a capacitor region and a non-capacitor region. For example... Figure 3 As shown, the second wafer has an array region 320 and a control region 330. (As...) Figure 1 As shown, the array region 320 corresponds to the capacitor region, and the first wafer and the second wafer are electrically connected.

[0060] In this scheme, a semiconductor structure with a stacked wafer structure is formed. Compared with the semiconductor structure fabricated on a planar structure, this scheme can increase the density of the semiconductor structure on the wafer.

[0061] Furthermore, the two wafers that make up the stacked structure can be produced simultaneously and then bonded. Compared with the semiconductor structure fabricated by performing various processes sequentially on a single wafer in a planar structure, this saves production time and improves production efficiency.

[0062] like Figure 2aAs shown, the capacitor region has a capacitor structure 220, which includes a first electrode 223 and a second electrode 221. The first electrode 223 of the capacitor structure is electrically connected to the array region 320.

[0063] The array region of the second wafer includes an active region, and the control region of the second wafer includes a second conductive interconnect structure and a control structure, and the second conductive interconnect structure and the control structure are electrically connected.

[0064] like Figure 3 As shown, the active region includes a buried gate structure 321, a fifth conductive plug, and a bit line plug 322. The bit line plug 322 is located above the center of the active region, and the fifth conductive plug is located above both ends of the active region, including a fifth conductive plug 424 and a fifth conductive plug 425. The fifth conductive plug is exposed on the surface of the second wafer that contacts the first wafer. A bit line 323 is disposed above the bit line plug 322.

[0065] The fifth conductive plug is electrically connected to the first electrode of the capacitor. The number of fifth conductive plugs is the same as the number of capacitors, and each fifth conductive plug corresponds one-to-one with a capacitor.

[0066] The control structure includes a transistor structure 331, which includes a source, a drain, and a gate.

[0067] The first electrode 223 of the first wafer is electrically connected to the active region of the second wafer, and the first conductive interconnect structure of the first wafer is electrically connected to the second conductive interconnect structure of the second wafer.

[0068] In an exemplary embodiment of this disclosure, the capacitor structure on the first wafer is surrounded by a first dielectric material, which is a substrate material.

[0069] like Figure 4 As shown, the first wafer 200 includes a first substrate 210, and a capacitor structure is located in the first substrate 210. The first substrate 210 contains a first dielectric material. The first substrate 210 may be a doped substrate.

[0070] The first conductive interconnect structure of the first wafer is surrounded by a second dielectric material, which may be the same as or different from the first dielectric material.

[0071] The material of the second substrate 310 of the second wafer is the same as that of the first substrate 210 of the first wafer, both of which can be silicon substrate material.

[0072] In an exemplary embodiment of this disclosure, the non-capacitive region includes a first conductive interconnect structure. The first conductive interconnect structure may be entirely located within the non-capacitive region. This structure can reduce the thickness of the semiconductor structure.

[0073] Alternatively, one can use, such as Figure 4 As shown, a portion of the top metal layer of the first conductive interconnect structure is located in the capacitive region, and another portion is located in the non-capacitive region.

[0074] like Figure 8 As shown, in the semiconductor structure 700, the first conductive interconnect structure of the first wafer includes a top conductive layer 410, a first conductive plug 411, and a second conductive plug 4113; the first conductive plug 411 connects the top conductive layer 410 and the second electrode 221, and the second conductive plug 4113 connects the top conductive layer 410 and the second conductive interconnect structure; the number of the first conductive plugs is the same as the number of capacitor structures, and the number of the second conductive plugs is at least 1.

[0075] like Figure 6 and Figure 7a As shown, the first conductive interconnect structure of the first wafer includes a top conductive layer 410, a first conductive plug 411, a second conductive plug 4112, and a middle interconnect structure; the second conductive plug includes a first second conductive plug 4114 and a second second conductive plug 431; the first conductive plug 411 connects the top conductive layer and the second electrode, the first second conductive plug 4114 connects the top conductive layer and the middle interconnect structure, and the second second conductive plug 431 connects the middle interconnect structure and the second conductive interconnect structure; the number of the first conductive plug is at least 1, the number of the first second conductive plug is at least 1, and the number of the second second conductive plug is at least 1.

[0076] like Figure 7a As shown, in the semiconductor structure 600, the central interconnect structure includes a central conductive layer 430. For example... Figure 1 and Figure 6 As shown, the central interconnect structure may include two central conductive layers, which are connected by a third conductive plug 431; the number of the third conductive plug is at least one.

[0077] like Figure 1 and Figure 3 As shown, the second conductive interconnect structure contains at least two lower conductive layers, namely lower conductive layer 333 and lower conductive layer 334, which are connected to each other via a fourth conductive plug 336; the number of the fourth conductive plug is at least one. The lower conductive layer 333 and the control structure 332 are connected via the fourth conductive plug 332.

[0078] In the above scheme, since the size, number, and position of each conductive interconnect layer in the first and second conductive interconnect structures inside the wafer can be adjusted, for example, the orthogonal projections between the lower conductive layers in the second conductive interconnect structure can be set to overlap, thus providing a larger layout space inside the semiconductor structure and increasing the density of the semiconductor structure on the wafer.

[0079] In another embodiment, such as Figure 7b As shown, in the semiconductor structure 6100, the first conductive interconnect structure is connected to the first substrate 210. The first substrate 210 can be a silicon wafer substrate or other semiconductor material substrate. The second electrode of the capacitor structure 220 is connected to the first substrate 210, and the top conductive layer 410 of the first conductive interconnect structure is connected to the first substrate 210.

[0080] The first substrate 210 can be a doped substrate. The purpose of doping is to increase the conductivity of the first substrate 210. There are no restrictions on the ions used for doping, such as boron ions, arsenic ions, phosphorus ions, etc. The timing of the doping step is not limited. It can be performed during the formation of the first wafer, such as doping the first substrate 210 before forming the capacitor structure 220, or it can be doped on the first substrate 210 by defining the doping region on the stacked wafer formed after bonding using a photolithography process.

[0081] Subsequently, utilizing the conductivity of the doped first substrate 210 itself, the second electrode of the capacitor structure 220 is connected to facilitate the application of the same potential. For example, the first substrate 210 is connected to zero potential through the top conductive layer 410, ensuring that all capacitor structures 220 in the first substrate 210 can store the same amount of charge. This process can significantly reduce process steps, save costs, and conserve space occupied by the semiconductor structure.

[0082] In an exemplary embodiment of this disclosure, the capacitor region further includes a capacitor connection member connected to the second electrode of the capacitor structure. The capacitor connection member may be connected to either a first conductive interconnect structure or a second conductive interconnect structure.

[0083] like Figure 7c As shown, in the semiconductor structure 6200, the capacitor connection member 412 is connected to the top conductive layer 410 of the first conductive interconnect structure. By directly connecting the second electrode of the capacitor structure using the capacitor connection member, the conventional method of connecting the second electrode through conductive plugs is eliminated, which can reduce the space occupied by the conductive interconnect structure in the vertical direction and increase the density of the first conductive interconnect structure.

[0084] like Figure 7d As shown, in the semiconductor structure 6300, the capacitor connection member 225 is connected to the lower conductive layer 333 of the second conductive interconnect structure.

[0085] In the bonded stacked wafers, the capacitor connection component is connected to the second conductive interconnect structure, which can avoid forming a capacitor connection component connecting the second electrode on the top of the capacitor, increase the density of the semiconductor structure, and thus reduce the volume occupied by the semiconductor structure.

[0086] In exemplary embodiments of this disclosure, the materials of the first dielectric layer and the second dielectric layer may be one or any combination of oxides, nitrides, silicides, carbides or amorphous carbon.

[0087] In an exemplary embodiment of this disclosure, the materials of the first conductive interconnect structure and the second conductive interconnect structure can be one of copper, aluminum, tin, or tungsten, or any combination thereof.

[0088] After etching away the non-capacitor regions of the first wafer, a notch appears on the first wafer. By depositing dielectric material, conductive plug material, and conductive layer material layer by layer at this notch, a second metal interconnect layer and a first metal interconnect layer can be formed, realizing the connection between the control region and the outside of the wafer.

[0089] In one embodiment, such as Figure 2a As shown, the first wafer 200 includes a first substrate 210, and the capacitor structure 220 includes: a first electrode 223 located in the capacitor region; a dielectric layer 222 disposed on the first electrode; and a second electrode 221 disposed on the dielectric layer 222.

[0090] like Figure 2a As shown, the cross-section of the first electrode and the dielectric layer is U-shaped. The first electrode is formed in the first substrate, the dielectric layer is formed on the inner wall of the first electrode, and the second electrode is a cylindrical structure located on the inner wall of the dielectric.

[0091] In another embodiment, such as Figure 2b As shown, the capacitor structure 220 includes: an isolation layer 224 located in the capacitor region; a first electrode 223 disposed on the isolation layer; a dielectric layer 222 disposed on the first electrode; and a second electrode 221 disposed on the dielectric layer 222.

[0092] like Figure 2b As shown, the isolation layer is a bottomless cylindrical structure, the cross-section of the first electrode and the dielectric layer is U-shaped, the first electrode is formed on the inner wall of the isolation layer, the dielectric layer is formed on the inner wall of the first electrode, and the second electrode is a cylindrical structure located on the inner wall of the dielectric.

[0093] The formation of the first wafer 200 and the formation of the second wafer 300 can be carried out simultaneously on different machines, which can save the production time of semiconductor structures.

[0094] After the first wafer 200 and the second wafer 300 are bonded together, a semiconductor structure 400 is formed. The bonding process enables the first wafer 200 and the second wafer 300 to be combined and form a stacked wafer structure with high-density interconnection.

[0095] In another embodiment, the layout of the capacitor region is similar to... Figure 2b The layout of the capacitor regions differs.

[0096] like Figure 5a As shown, the capacitor structure 520 includes a first electrode 522 located in the capacitor region; a dielectric layer 521 disposed on the first electrode; and a second electrode 523 disposed on the dielectric layer.

[0097] like Figure 5a As shown, the cross-section of the second electrode and the dielectric layer is U-shaped. The second electrode is formed on the inner wall of the isolation layer, and the dielectric layer is formed on the inner wall of the second electrode. The first electrode is a cylindrical structure located on the inner wall of the dielectric.

[0098] In another embodiment, such as Figure 5b As shown, the capacitor structure 520 includes an isolation layer 510 located in the capacitor region; a first electrode 522 disposed on the isolation layer; a dielectric layer 521 disposed on the first electrode; and a second electrode 523 disposed on the dielectric layer.

[0099] like Figure 5b As shown, the isolation layer is a bottomless cylindrical structure, the cross-section of the second electrode and the dielectric layer is U-shaped, the second electrode is formed on the inner wall of the isolation layer, the dielectric layer is formed on the inner wall of the second electrode, and the first electrode is a cylindrical structure located on the inner wall of the dielectric.

[0100] like Figure 5b The capacitor region shown is similar to... Figure 2b Compared to the capacitor region shown, the opening direction of the U-shaped electrodes in the capacitor structure is different, thus including, as Figure 5b The capacitor region semiconductor structure 500, such as Figure 6 As shown, including as Figure 2b The capacitor region semiconductor structure 400 Figure 1 As shown, semiconductor structure 500 is different from semiconductor structure 400.

[0101] like Figure 9 As shown, in a semiconductor structure 800, the first conductive interconnect structure includes a first conductive layer 720 exposed on the surface of the first wafer that contacts the second wafer; the second conductive interconnect structure includes a second conductive layer 710 exposed on the surface of the second wafer that contacts the first wafer; the first conductive layer 720 is connected to the second conductive layer 710.

[0102] When using conductive interconnects to connect wafers, the process window for the connection can be increased, and the manufacturing difficulty can be reduced.

[0103] like Figure 1 As shown, the bottom layer of the first conductive interconnect structure is the second conductive plug 431, and the top layer of the second conductive interconnect structure is the lower conductive layer 333. The second conductive plug 431 and the lower conductive layer 333 are connected.

[0104] In addition, there is a case where the bottom layer of the first conductive interconnect structure is a conductive layer and the top layer of the second conductive interconnect structure is a conductive plug. In this case, the bottom layer of the first conductive interconnect structure is connected to the top layer of the second conductive interconnect structure.

[0105] The semiconductor structure provided by the exemplary embodiment of the present invention is a stacked structure formed by bonding a first wafer and a second wafer. Compared with the prior art, it increases the density of the semiconductor structure on the wafer, allowing the first wafer and the second wafer to be produced simultaneously, thereby increasing the production speed of the semiconductor structure.

[0106] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0107] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, This includes a first wafer and a second wafer stacked together; wherein, The first wafer includes a capacitor region and a non-capacitor region; The second wafer includes an array region and a control region; The capacitor region corresponds to the array region, and the non-capacitor region corresponds to the control region; The first wafer and the second wafer are electrically connected.

2. The semiconductor structure according to claim 1, characterized in that, The capacitor region of the first wafer includes a capacitor structure, and the non-capacitor region includes a first conductive interconnect structure.

3. The semiconductor structure according to claim 2, characterized in that, The array region of the second wafer includes an active region, and the control region of the second wafer includes a second conductive interconnect structure and a control structure, wherein the second conductive interconnect structure and the control structure are electrically connected.

4. The semiconductor structure according to claim 3, characterized in that, The capacitor structure includes: The second electrode is located in the capacitor region; A dielectric layer disposed on the second electrode; The first electrode is disposed on the dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that, The capacitor region is provided with an isolation layer, and the second electrode is disposed on the isolation layer.

6. The semiconductor structure according to claim 3, characterized in that, The capacitor structure includes: The first electrode located in the capacitor region; Dielectric layer disposed on the first electrode; The second electrode is disposed on the dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that, The capacitor region is provided with an isolation layer, and the first electrode is disposed on the isolation layer.

8. The semiconductor structure according to claim 4 or 6, characterized in that, The first electrode of the first wafer is electrically connected to the active region of the second wafer, and the first conductive interconnect structure of the first wafer is electrically connected to the second conductive interconnect structure of the second wafer.

9. The semiconductor structure according to claim 8, characterized in that, The first conductive interconnect structure of the first wafer includes a top conductive layer, a first conductive plug, and a second conductive plug; The first conductive plug connects to the top conductive layer and the second electrode, and the second conductive plug connects to the top conductive layer and the second conductive interconnect structure. The number of the first conductive plug is at least 1, and the number of the second conductive plug is at least 1.

10. The semiconductor structure according to claim 8, characterized in that, The first conductive interconnect structure of the first wafer includes a top conductive layer, a first conductive plug, a second conductive plug, and a middle interconnect structure; The second conductive plug includes a first second conductive plug and a second second conductive plug; The first conductive plug connects to the top conductive layer and the second electrode; the first and second conductive plugs connect to the top conductive layer and the middle interconnect structure; and the second conductive plugs connect to the middle interconnect structure and the second conductive interconnect structure. The number of the first conductive plug is at least 1, the number of the first and second conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

11. The semiconductor structure according to claim 10, characterized in that, The central interconnect structure includes at least one central conductive layer, and the multiple central conductive layers are connected by a third conductive plug. The number of the third conductive plugs is at least one.

12. The semiconductor structure according to claim 11, characterized in that, The second conductive interconnect structure contains at least two lower conductive layers, which are connected by a fourth conductive plug. The number of the fourth conductive plugs is at least one.

13. The semiconductor structure according to claim 12, characterized in that, The first electrode of the first wafer is electrically connected to the active region of the second wafer through a fifth conductive plug, and the number of the fifth conductive plug is at least one.

14. The semiconductor structure according to claim 12, characterized in that, The first wafer includes a first substrate, the capacitor structure is located in the first substrate, and the first conductive interconnect structure is connected to the first substrate; The first substrate contains a first dielectric material.

15. The semiconductor structure according to claim 14, characterized in that, The first substrate is a doped substrate.

16. The semiconductor structure according to claim 15, characterized in that, The capacitor region also includes a capacitor connection component, which is connected to the second electrode of the capacitor structure.

17. The semiconductor structure according to claim 16, characterized in that, The capacitor connection component is connected to either the first conductive interconnect structure or the second conductive interconnect structure.

18. The semiconductor structure according to claim 17, characterized in that, The first conductive interconnect structure of the first wafer is surrounded by a second dielectric material, which is the same as the first dielectric material.

19. The semiconductor structure according to claim 18, characterized in that, The first conductive interconnect structure of the first wafer is surrounded by a second dielectric material, which is different from the first dielectric material.

20. The semiconductor structure according to claim 19, characterized in that, The orthographic projections of the lower conductive layers in the second conductive interconnect structure overlap.

21. The semiconductor structure according to claim 20, characterized in that, The materials of the first dielectric layer and the second dielectric layer include one or any combination of oxides, nitrides, silicides, carbides or amorphous carbon.

22. The semiconductor structure according to claim 21, characterized in that, The materials of the first conductive interconnect structure and the second conductive interconnect structure include one or any combination of copper, aluminum, tin or tungsten.

23. The semiconductor structure according to claim 22, characterized in that, The first conductive interconnect structure includes a first conductive layer, which is exposed on the surface of the first wafer that contacts the second wafer; The second conductive interconnect structure includes a second conductive layer exposed on the surface of the second wafer that contacts the first wafer; The first conductive layer is connected to the second conductive layer.

24. The semiconductor structure according to claim 23, characterized in that, The control structure includes a transistor structure, which includes a source, a drain, and a gate.

25. The semiconductor structure according to claim 24, characterized in that, The active region includes a buried gate structure, a fifth conductive plug, and a bit line plug. The bit line plug is located above the center of the active region, and the fifth conductive plug is located above both ends of the active region. The fifth conductive plug is exposed on the surface of the second wafer that is in contact with the first wafer.

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