Power supply control device

Abstract

The present invention provides a power supply control device, which can maintain the other transistor turned on even when a short circuit fault occurs in one of the two transistors. In the power supply control device, power supply via two branch routes branching from a common power supply route is controlled. N-channel FETs (50, 60) are respectively configured in the two branch routes. A boost circuit (80) outputs a voltage from a common output end and applies a voltage to the gate of the FET (50, 60) via a circuit resistor (83). Charging resistors (52, 62) are respectively configured in the two application routes for applying voltage from the output end of the boost circuit (80) to the gate of the FET (50, 60). Diodes (54, 64) are connected between the two ends of each of the charging resistors (52, 62). The cathode of the diode (54, 64) is configured on the boost circuit (80) side.

Description

Technical Field

[0001] The invention relates to a power supply control device. Background Art

[0002] A power supply control device for controlling the power supply from a DC power supply to a load is mounted on the vehicle (for example, refer to Patent Document 1). In the power supply control device described in Patent Document 1, two N-channel FETs (Field Effect Transistors) are connected in parallel. The two FETs function as switches. The control circuit controls the power supply to the load by switching the two FETs on or off. When the two FETs are turned on, the DC power supply supplies power to the load via the two FETs. When the two FETs are turned off, the power supply to the load is stopped.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-239293 Summary of the invention

[0006] Problems to be solved by the invention

[0007] The N-channel FET is switched on when the gate voltage value based on the source potential is adjusted to a voltage value above a certain on-threshold value. The N-channel FET is switched off when the gate voltage value based on the source potential is adjusted to a voltage value less than a certain off-threshold value. The on-threshold value is above the off-threshold value, and the off-threshold value exceeds 0V. In the power supply control device in Patent Document 1, when the FET is turned on, current is input to the drain and current is output from the source.

[0008] As a structure of the control circuit of the power supply control device described in Patent Document 1, there is a structure in which a drive circuit applies a voltage to the gates of two FETs from a common output terminal. In addition, as one of the failures of the FET, there is a short-circuit failure in which the gate and the source are short-circuited, and the drain and the source are short-circuited. Assume that the two FETs are turned on. In the structure in which the drive circuit applies a voltage to the gates of the two FETs from a common output terminal, when a short-circuit failure occurs in one FET, the voltage value between the source and the gate in the other FET is reduced to 0V, that is, reduced to a voltage value less than the disconnection threshold and maintained at 0V.

[0009] Therefore, when a short circuit occurs in one FET, the other FET is switched to off and remains off. In this case, the current is concentrated on the FET that has a short circuit. When an excessive current flows in the FET, the temperature of the FET rises to an abnormal temperature, which may cause various problems. For example, the temperature of the peripheral equipment of the FET also rises, which may cause adverse conditions in the operation of the peripheral equipment.

[0010] The present invention has been made in view of such circumstances, and an object of the present invention is to provide a power supply control device capable of maintaining the other transistor on even when a short-circuit failure occurs in one of two transistors.

[0011] Technical solutions to solve problems

[0012] A power supply control device according to one aspect of the present invention controls power supply via two branch routes branching from a common power supply route, and the power supply control device comprises: two transistors, respectively arranged on the two branch routes, the higher the voltage value of the control end based on the potential of the current output end of the output current, the smaller the resistance value between the current input end of the input current and the current output end; a first resistor; a voltage application unit, which outputs a voltage from a common output end and applies a voltage to the control ends of the two transistors via the first resistor; two second resistors, respectively arranged on two application routes for applying a voltage from the output end of the voltage application unit to the control ends of the two transistors; and two diodes, connected between the two ends of each of the two second resistors, with the cathode arranged on the voltage application unit side.

[0013] Effects of the Invention

[0014] According to the above aspect, even when a short-circuit failure occurs in one of the two transistors, the other transistor can be maintained on. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a block diagram showing a main part configuration of a power supply system in this embodiment.

[0016] Figure 2 This is a block diagram showing the main structure of the driving circuit.

[0017] Figure 3 This is a diagram for explaining the switching of the FET to the on state.

[0018] Figure 4 This is a diagram for explaining conditions to be satisfied in the power supply control device.

[0019] Figure 5 This is a diagram for explaining the effect of the power supply control device.

[0020] Figure 6 This is a diagram for explaining the switching of the FET to the off state. DETAILED DESCRIPTION

[0021] [Description of Embodiments of the Invention]

[0022] First, embodiments of the present invention will be listed and described. At least a part of the embodiments described below may be arbitrarily combined.

[0023] (1) An aspect of the present invention relates to a power supply control device that controls power supply via two branch routes branching from a common power supply route, and the power supply control device comprises: two transistors, respectively arranged on the two branch routes, wherein the higher the voltage value of the control terminal based on the potential of the current output terminal of the output current, the smaller the resistance value between the current input terminal of the input current and the current output terminal; a first resistor; a voltage application unit that outputs a voltage from a common output terminal and applies a voltage to the control terminals of the two transistors via the first resistor; two second resistors, respectively arranged on two application routes for applying a voltage from the output terminal of the voltage application unit to the control terminals of the two transistors; and two diodes connected between the two ends of each of the two second resistors, with the cathodes arranged on the voltage application unit side.

[0024] In one of the above-mentioned methods, the transistor is, for example, an N-channel FET. In this case, the gate, the drain, and the source correspond to the control terminal, the current input terminal, and the current output terminal, respectively. In the two transistors, when the voltage value of the control terminal based on the potential of the current output terminal is higher, the resistance value between the current input terminal and the current output terminal is smaller, and the two transistors are turned on. In this state, it is assumed that a short-circuit fault occurs in one transistor, in which the control terminal and the current output terminal are short-circuited, and the current input terminal and the current output terminal are short-circuited. In this case, the larger the resistance value of the second resistor configured in the application route for applying a voltage to the control terminal of the transistor having the short-circuit fault, the higher the voltage value of the control terminal of the normal transistor. Therefore, when a resistor with a larger resistance value is used as the second resistor, even when a short-circuit fault occurs in one transistor, the other transistor remains turned on.

[0025] In the two transistors, input capacitors are formed between the control terminal and the current output terminal, respectively. When a voltage is applied to the control terminal of the transistor via the second resistor, the input capacitor is charged and the voltage value of the control terminal rises. As a result, the resistance value between the current input terminal and the current output terminal decreases, and the transistor is switched to on. When the input capacitor is discharged, the voltage value of the control terminal decreases. As a result, the resistance value between the current input terminal and the current output terminal increases, and the transistor is switched to off. Since the input capacitor is discharged via a diode instead of a second resistor having a larger resistance value, the power accumulated in the input capacitor is quickly released, and the transistor can be quickly switched to off.

[0026] (2) A power supply control device according to one embodiment of the present invention comprises two third resistors connected in series with the two diodes respectively, and two series circuits including diodes and third resistors are respectively connected between the two ends of the two second resistors, and the two second resistors respectively have a resistance value greater than the resistance value of the third resistor connected to themselves between the two ends.

[0027] In the above embodiment, the resistance value of the third resistor is smaller than the resistance value of the second resistor. Therefore, the input capacitance of each transistor releases power via the series circuit including the diode and the third resistor.

[0028] (3) In a power supply control device according to one embodiment of the present invention, a voltage value Vp of a voltage outputted from the output terminal by the voltage applying unit, a voltage value Vi of a current input terminal of a first transistor included in the two transistors, a resistance value R1 of the first resistor, and a resistance value R2 of the second resistor arranged in an application route for applying a voltage to a control terminal of a second transistor included in the two transistors satisfy the following formula:

[0029] (Vp-Vi)·R2 / (R1+R2)≥Vg

[0030] Wherein, Vg is the voltage value between the current output terminal and the control terminal required to switch the first transistor on.

[0031] In one of the above-mentioned methods, when the current input terminal of the first transistor is directly connected to the current input terminal of the second transistor, in the second transistor, when the control terminal and the current output terminal are short-circuited, and the current input terminal and the current output terminal are short-circuited, in the second transistor, the voltage value of the control terminal based on the fixed potential is Vi. Therefore, in the first transistor, the voltage value of the control terminal based on the fixed potential is represented by ((Vp-Vi)·R2 / (R1+R2)+Vi). Here, since (Vp-Vi)·R2 / (R1+R2)≥Vg is satisfied, the voltage value of the control terminal based on the fixed potential is greater than (Vg+Vi). As a result, in the first transistor, the voltage value of the control terminal based on the potential of the current output terminal is greater than Vg, and the first transistor is reliably maintained to be turned on.

[0032] [Details of the embodiments of the present invention]

[0033] Hereinafter, a specific example of a power supply control device according to an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0034] As a specific example of the present embodiment, a power supply system including a power supply control device will be described.

[0035] <Power System Configuration>

[0036] Figure 1 1 is a block diagram showing the main structure of the power supply system 1. The power supply system 1 is preferably mounted on a vehicle and includes a power supply control device 2, a DC power supply 3, and a load 4. The power supply control device 2 is connected to the positive electrode of the DC power supply 3 and one end of the load 4. The negative electrode of the DC power supply 3 and the other end of the load 4 are grounded. The grounding is achieved, for example, by connecting to the body of the vehicle. The ground potential is a fixed potential.

[0037] The power supply control device 2 performs electrical connection between the DC power supply 3 and the load 4, and disconnects the electrical connection between the DC power supply 3 and the load 4. The DC power supply 3 is, for example, a battery. The load 4 is an electrical device mounted on the vehicle. When power is supplied to the load 4, the load 4 operates. When power supply to the load 4 is stopped, the load 4 stops operating.

[0038] The power supply control device 2 is input with a working signal indicating the operation of the load 4 and a stop signal indicating the stop of the operation of the load 4. When the working signal is input, the power supply control device 2 electrically connects the DC power supply 3 to the load 4. As a result, the DC power supply 3 supplies power to the load 4, and the load 4 operates. When the stop signal is input, the power supply control device 2 cuts off the electrical connection between the DC power supply 3 and the load 4. As a result, the power supply to the load 4 stops, and the load 4 stops operating. In this way, the power supply control device 2 controls the power supply to the load 4.

[0039] <Structure of Power Supply Control Device 2>

[0040] The power supply control device 2 has N-channel FETs 50 and 60, series resistors 51 and 61, charging resistors 52 and 62, discharging resistors 53 and 63, diodes 54 and 64, a drive circuit 70, a current detection circuit 71, and a microcomputer (hereinafter referred to as a microcomputer) 72. In FET 50, an input capacitor Cd1 is connected between the gate and the drain, and an input capacitor Cs1 is connected between the gate and the source. The input capacitors Cd1 and Cs1 are formed in the process of manufacturing FET 50, and are also called parasitic capacitances. Similarly, in FET 60, an input capacitor Cd2 is connected between the gate and the drain, and an input capacitor Cs2 is connected between the gate and the source. The input capacitors Cd2 and Cs2 are formed in the process of manufacturing FET 60, and are also called parasitic capacitances.

[0041] The drains of FET50 and 60 are connected to the positive electrode of the DC power supply 3. The sources of FET50 and 60 are connected to one end of the series resistors 51 and 61, respectively. The other ends of the series resistors 51 and 61 are connected to one end of the load 4. The gate of FET50 is connected to one end of the charging resistor 52. The other end of the charging resistor 52 is connected to the drive circuit 70. One end of the charging resistor 52 is also connected to one end of the discharge resistor 53. The other end of the discharge resistor 53 is connected to the anode of the diode 54. The cathode of the diode 54 is connected to the other end of the charging resistor 52. In this way, the discharge resistor 53 and the diode 54 are connected in series. The series circuit including the discharge resistor 53 and the diode 54 is connected between the two ends of the charging resistor 52. The resistance value of the charging resistor 52 is larger than the resistance value of the discharge resistor 53.

[0042] Similarly, the gate of FET 60 is connected to one end of charging resistor 62. The other end of charging resistor 62 is connected to driving circuit 70. One end of charging resistor 62 is also connected to one end of discharge resistor 63. The other end of discharge resistor 63 is connected to the anode of diode 64. The cathode of diode 64 is connected to the other end of charging resistor 62. In this way, discharge resistor 63 and diode 64 are connected in series. The series circuit including discharge resistor 63 and diode 64 is connected between the two ends of charging resistor 62. The resistance value of charging resistor 62 is larger than the resistance value of discharge resistor 63.

[0043] The charging resistors 52 and 62 correspond to the second resistor, respectively. The discharging resistors 53 and 63 correspond to the third resistor, respectively.

[0044] The drive circuit 70 is also connected to the drains of the FETs 50 and 60 and the microcomputer 72. The drive circuit 70 is also grounded. One end and the other end of the series resistor 51 are respectively connected to the current detection circuit 71. The current detection circuit 71 is also connected to the microcomputer 72.

[0045] In each of FET50 and FET60, current is input from DC power supply 3 to the drain, and current is output from the source to load 4. In each of FET50 and FET60, the higher the gate voltage value based on the potential of the source, the smaller the resistance value between the drain and the source.

[0046] In the FETs 50 and 60 , the drain, source and gate correspond to the current input terminal, the current output terminal and the control terminal, respectively.

[0047] In each of FET50 and FET60, when the voltage value of the gate based on the potential of the source is above a certain on-threshold value, the resistance value between the drain and the source is sufficiently small. At this time, FET50 and FET60 are each turned on, and current flows through the drain and the source in each of FET50 and FET60. When FET50 and FET60 are switched on, the DC power supply 3 and the load 4 are electrically connected, and the DC power supply 3 supplies power to the load 4. At this time, a part of the current output from the positive electrode of the DC power supply 3 flows in the order of FET50, the series resistor 51 and the load 4. The remaining part of the current output from the positive electrode of the DC power supply 3 flows in the order of FET60, the series resistor 61 and the load 4.

[0048] In each of FET50 and 60, when the voltage value of the gate based on the potential of the source is less than a certain disconnection threshold, the resistance value between the drain and the source is sufficiently large. At this time, FET50 and 60 are each disconnected, and in each of FET50 and 60, the current does not flow through the drain and the source. When FET50 and 60 are switched to disconnection, the electrical connection between the DC power supply 3 and the load 4 is cut off, and the power supply to the load 4 is stopped. The on threshold is above the off threshold, and the off threshold exceeds 0V.

[0049] As described above, the power supply control device 2 controls power supply to the load 4 via two branch routes branched from the common power supply route on which the positive electrode of the DC power supply 3 is arranged. The FET 50 is arranged on one branch route, and the FET 60 is arranged on the other branch route.

[0050] The microcomputer 72 outputs a binary signal consisting of a high-level voltage and a low-level voltage to the drive circuit 70. When the microcomputer 72 switches the voltage output to the drive circuit 70 from the low-level voltage to the high-level voltage, the drive circuit 70 boosts the output voltage of the DC power supply 3 to a preset target voltage. The drive circuit 70 applies the boosted voltage (target voltage) to the gate of the FET 50 via the charging resistor 52, and applies it to the gate of the FET 60 via the charging resistor 62. The boosted voltage is a voltage value based on the ground potential.

[0051] When the drive circuit 70 applies the boosted voltage to the gate of the FET 50, the input capacitors Cd1 and Cs1 are charged. As a result, the gate voltage value based on the source potential increases in the FET 50. When the gate voltage value based on the source potential becomes equal to or higher than the on threshold, the FET 50 is switched on.

[0052] Similarly, when the drive circuit 70 applies the boosted voltage to the gate of the FET 60, the input capacitors Cd2 and Cs2 are charged. As a result, the gate voltage value based on the potential of the source increases in the FET 60. When the gate voltage value based on the potential of the source is greater than the on threshold, the FET 60 is switched on.

[0053] When the microcomputer 72 switches the voltage output to the drive circuit 70 from the high level voltage to the low level voltage, the cathodes of the diodes 54 and 64 are grounded. As a result, the input capacitors Cd1 and Cs1 of the FET 50 release the stored power via the discharge resistor 53 and the diode 54. Furthermore, the input capacitors Cd2 and Cs2 of the FET 60 also release the stored power via the discharge resistor 63 and the diode 64.

[0054] When the input capacitors Cs1 and Cd1 are discharged, the gate voltage value based on the source potential decreases in the FET 50. When the gate voltage value based on the source potential is less than the OFF threshold, the FET 50 is switched OFF.

[0055] Similarly, when the input capacitors Cs2 and Cd2 are discharged, the gate voltage value based on the source potential decreases in the FET 60. When the gate voltage value based on the source potential is less than the off threshold, the FET 60 is switched off.

[0056] As described above, the drive circuit 70 switches the FETs 50 and 60 on or off by adjusting the voltage value of the gate with reference to the potential of the source in the FETs 50 and 60 .

[0057] When the FET 50 is turned on, current flows through the series resistor 51. When the FET 60 is turned on, current flows through the series resistor 61. The current detection circuit 71 detects the current value of the current flowing through the series resistor 51. The current detection circuit 71 outputs current information indicating the detected current value to the microcomputer 72. The current information is, for example, a voltage value proportional to the current value detected by the current detection circuit 71, that is, the current value of the current flowing through the series resistor 51.

[0058] The microcomputer 72 inputs the operation signal and the stop signal. When the operation signal is input, the microcomputer 72 switches the voltage output to the drive circuit 70 to a high level voltage. As a result, the drive circuit 70 switches the FETs 50 and 60 to on, and the DC power supply 3 supplies power to the load 4. As a result, the load 4 operates. When the stop signal is input, the microcomputer 72 switches the voltage output to the drive circuit 70 to a low level voltage. As a result, the drive circuit 70 switches the FETs 50 and 60 to off, and stops the power supply to the load 4 from the DC power supply 3. As a result, the load 4 stops operating.

[0059] When the FETs 50 and 60 are turned on, the microcomputer 72 determines whether the current value of the current flowing through the FETs 50 and 60 is greater than or equal to the reference current value based on the current value indicated by the current information input from the current detection circuit 71. When the microcomputer 72 determines that the current value of the current flowing through the FETs 50 and 60 is greater than or equal to the reference current value, the voltage output to the drive circuit 70 is switched to a low-level voltage, and the drive circuit 70 switches the FETs 50 and 60 off. This prevents an overcurrent from flowing through the FETs 50 and 60.

[0060] <Structure of Driving Circuit 70>

[0061] Figure 2: is a block diagram showing the main part structure of the driving circuit 70. The driving circuit 70 includes a boost circuit 80, a charging switch 81, a discharging switch 82, and a circuit resistor 83. The boost circuit 80 is connected to the positive electrode of the DC power supply 3 and one end of the charging switch 81. The other end of the charging switch 81 is connected to one end of the discharging switch 82. The other end of the discharging switch 82 is grounded. The connection node between the charging switch 81 and the discharging switch 82 is connected to one end of the circuit resistor 83. The other end of the circuit resistor 83 is connected to the other ends of the charging resistors 52 and 62.

[0062] Figure 3 : This is an explanatory diagram of the switching of FET50 and 60 toward on. When the voltage output from the microcomputer 72 to the drive circuit 70 is switched from a low-level voltage to a high-level voltage, the boost circuit 80 operates, the charging switch 81 is switched on, and the discharge switch 82 is switched off. The boost circuit 80 is also called a charge pump circuit, and boosts the output voltage of the DC power supply 3 to a target voltage. The boost circuit 80 applies the boosted voltage (target voltage) to the gate of the FET50 via the circuit resistor 83 and the charging resistor 52, and applies the boosted voltage to the gate of the FET60 via the circuit resistor 83 and the charging resistor 62.

[0063] When the boost circuit 80 applies the boosted voltage to the gate of the FET 50, the current flows to the input capacitors Cd1 and Cs1 of the FET 50 via the circuit resistor 83 and the charging resistor 52. As a result, the input capacitors Cd1 and Cs1 are charged, and in the FET 50, the voltage value of the gate based on the potential of the source rises to a voltage value above the on-threshold. As a result, the FET 50 is switched on. The smaller the resistance value of the charging resistor 52, the faster the charging speed of the input capacitor Cs1, and the smaller the capacitance value of the input capacitor Cs1, the faster the charging speed of the input capacitor Cs1. Similarly, the smaller the resistance value of the charging resistor 52, the faster the charging speed of the input capacitor Cd1, and the smaller the capacitance value of the input capacitor Cd1, the faster the charging speed of the input capacitor Cd1. Therefore, the smaller the resistance value of the charging resistor 52, the faster the speed at which the FET 50 switches from off to on.

[0064] When the boost circuit 80 applies the boosted voltage to the gate of the FET 60, the current flows to the input capacitors Cd2 and Cs2 of the FET 60 via the circuit resistor 83 and the charging resistor 62. As a result, the input capacitors Cd2 and Cs2 are charged, and in the FET 60, the voltage value of the gate based on the potential of the source rises to a voltage value above the on threshold. As a result, the FET 60 is switched on. The smaller the resistance value of the charging resistor 62, the faster the charging speed of the input capacitor Cs2, and the smaller the capacitance value of the input capacitor Cs2, the faster the charging speed of the input capacitor Cs2. Similarly, the smaller the resistance value of the charging resistor 62, the faster the charging speed of the input capacitor Cd2, and the smaller the capacitance value of the input capacitor Cd2, the faster the charging speed of the input capacitor Cd2. Therefore, the smaller the resistance value of the charging resistor 62, the faster the speed at which the FET 60 switches from off to on.

[0065] As described above, the boost circuit 80 outputs the boosted voltage from the common output terminal, and applies the boosted voltage to the gates of the FETs 50 and 60 via the circuit resistor 83. Charging resistors 52 and 62 are respectively arranged in two application routes for applying the boosted voltage from the output terminal of the boost circuit 80 to the gates of the FETs 50 and 60. As described above, the diode 54 is connected between the two ends of the charging resistor 52, and the diode 64 is connected between the two ends of the charging resistor 62. The cathodes of the diodes 54 and 64 are arranged on the boost circuit 80 side. The circuit resistor 83 is equivalent to the first resistor. The boost circuit 80 functions as a voltage applying unit.

[0066] Figure 4 It is an explanatory diagram of the conditions satisfied in the power supply control device 2. In the following, the voltage value of the voltage (target voltage) output from the output terminal of the boost circuit 80 is recorded as Vp. The voltage value of the drain of FET50, 60 is recorded as Vi. The resistance value of the circuit resistor 83 is recorded as Rd. The resistance values ​​of the charging resistors 52, 62 are recorded as Rn1, Rn2, respectively. The on-threshold of FET50, that is, the voltage value between the source and the gate required to switch FET50 to on is recorded as Vg1. The on-threshold of FET60, that is, the voltage value required to switch FET60 to on is recorded as Vg2. The voltage values ​​Vp and Vi are voltage values ​​with the ground potential as a reference.

[0067] As one of the failures of each of the FETs 50 and 60 , there is a short-circuit failure in which the gate and the source are short-circuited and the drain and the source are short-circuited.

[0068] In the power supply control device 2 , when a short-circuit fault occurs in the FET 60 and both charging and discharging of the input capacitors Cd1 and Cs1 of the FET 50 are stopped, the following formula (1) is satisfied.

[0069] ((Vp-Vi)·Rn2 / (Rd+Rn2))≥Vg1…(1)

[0070] Similarly, in the case of a short-circuit failure in the FET 50 , when both charging and discharging of the input capacitors Cd2 and Cs2 of the FET 60 are stopped, the following formula (2) is satisfied.

[0071] ((Vp-Vi)·Rn1 / (Rd+Rn1))≥Vg2…(2)

[0072] The resistance value Rd corresponds to the resistance value R1. The resistance values ​​Rn1 and Rn2 correspond to the resistance value R2. The voltage values ​​Vg1 and Vg2 correspond to the voltage value Vg.

[0073] When equation (1) is satisfied, even when a short-circuit fault occurs in FET 60 while FET 50 is turned on, FET 50 is not switched off but remains on. When equation (2) is satisfied, even when a short-circuit fault occurs in FET 50 while FET 60 is turned on, FET 60 is not switched off but remains on. The following describes the reason why FET 50 and 60 are kept on.

[0074] Figure 5 1 is an explanatory diagram of the effect of the power supply control device 2. In the following, the voltage value of the connection node between the charging resistors 52, 62 and the circuit resistor 83 is recorded as Vd. The voltage value Vd is also a voltage value based on the ground potential. Assume that when the boost circuit 80 outputs the boosted voltage from the output terminal, a short circuit fault occurs in the FET 60. At this time, the charging switch 81 is turned on and the discharging switch 82 is turned off.

[0075] When a short-circuit fault occurs in FET60, current flows from the output end of the boost circuit 80 in the order of the charging switch 81, the circuit resistor 83, the charging resistor 62, the gate of FET60, and the source of FET60. Then, the input capacitors Cd1 and Cs1 of FET50 are discharged or charged. When the discharge or charging of the input capacitors Cd1 and Cs1 is completed, all the current flowing in the circuit resistor 83 flows in the charging resistor 62, and the current does not flow in the charging resistor 52. At this time, in FET50, the voltage value of the gate with respect to the ground potential is consistent with the voltage value Vd.

[0076] The voltage value Vd when both discharge and charge of the input capacitors Cd1 and Cs1 are stopped is expressed by the following formula (3).

[0077] Vd=((Vp-Vi)·Rn2 / (Rd+Rn2))+Vi……(3)

[0078] Formula (3) can also be expressed as follows.

[0079] Vd=(Vp-Vi) / ((Rd / Rn2)+1)+Vi

[0080] Therefore, the larger the resistance value Rn2 of the charging resistor 62 is, the higher the voltage value Vd is. When the voltage value Vd is higher than the voltage value Vi and the difference between the voltage values ​​Vd and Vi is equal to or greater than the voltage value Vg1, the FET 50 is turned on.

[0081] When formula (1) is satisfied, the following formula (4) is satisfied.

[0082] Vd≥Vg1+Vi……(4)

[0083] Furthermore, by using equations (1) and (3) and eliminating the voltage value Vp, equation (4) is obtained.

[0084] When equation (1) is satisfied, voltage value Vd is higher than voltage value Vi, and the difference between voltage values ​​Vd and Vi is greater than voltage value Vg1. As a result, FET 50 is kept on. When equation (1) is satisfied, FET 50 is kept on even when a short-circuit fault occurs in FET 60.

[0085] Similarly, when a short-circuit fault occurs in FET50, current flows from the output end of the boost circuit 80 in the order of the charging switch 81, the circuit resistor 83, the charging resistor 52, the gate of FET50, and the source of FET50. Then, the input capacitors Cd2 and Cs2 of FET60 are discharged or charged. When the discharge or charging of the input capacitors Cd2 and Cs2 is completed, all the current flowing in the circuit resistor 83 flows in the charging resistor 52, and the current does not flow in the charging resistor 62. At this time, in FET60, the voltage value of the gate with respect to the ground potential is consistent with the voltage value Vd.

[0086] The voltage value Vd when the input capacitors Cd2 and Cs2 stop discharging and charging is expressed by the following formula (5).

[0087] Vd=((Vp-Vi)·Rn1 / (Rd+Rn1))+Vi……(5)

[0088] Formula (5) can also be expressed as follows.

[0089] Vd=(Vp-Vi) / ((Rd / Rn1)+1)+Vi

[0090] Therefore, the larger the resistance value Rn1 of the charging resistor 52 is, the higher the voltage value Vd is. When the voltage value Vd is higher than the voltage value Vi and the difference between the voltage values ​​Vd and Vi is equal to or greater than the voltage value Vg2, the FET 60 is turned on.

[0091] When formula (2) is satisfied, the following formula (6) is satisfied.

[0092] Vd≥Vg2+Vi……(6)

[0093] Furthermore, by using equations (2) and (5) and eliminating the voltage value Vp, equation (6) is obtained.

[0094] When equation (2) is satisfied, voltage value Vd is higher than voltage value Vi, and the difference between voltage values ​​Vd and Vi is greater than voltage value Vg2. As a result, FET 60 is maintained on. When equation (2) is satisfied, FET 60 is maintained on even when a short-circuit fault occurs in FET 50.

[0095] As described above, in the power supply control device 2, when a resistor with a larger resistance value is used as the charging resistor 52, 62, even if a short-circuit fault occurs in one of the FETs 50 and 60, the other FET is not switched off but maintained on. As a result, current is prevented from concentrating on the FET in which the short-circuit fault occurs, that is, excessive current is prevented from flowing in the FET in which the short-circuit fault occurs. In addition, since equations (1) and (2) are satisfied, when a short-circuit fault occurs in one of the FETs 50 and 60, the other FET is reliably maintained on.

[0096] Figure 6 1 and 2 are diagrams for explaining the switching of the FETs 50 and 60 to the OFF state. When the voltage output from the microcomputer 72 to the drive circuit 70 is switched from a high level voltage to a low level voltage, the booster circuit 80 stops operating, the charging switch 81 is switched to the OFF state, and the discharging switch 82 is switched to the ON state.

[0097] As described above, when the FETs 50 and 60 are turned on, the input capacitors Cd1, Cs1, Cd2, and Cs2 are charged. When the discharge switch 82 is turned on, the input capacitors Cd1, Cs1, Cd2, and Cs2 are discharged.

[0098] As described above, the resistance value of the discharge resistor 53 is smaller than the resistance value of the charging resistor 52. Therefore, when the input capacitors Cd1 and Cs1 of the FET 50 are discharged, the current flows from one end of the gate side of the input capacitors Cd1 and Cs1 in the order of the discharge resistor 53, the diode 54, the circuit resistor 83, and the discharge switch 82. During the period when the input capacitors Cd1 and Cs1 are discharged, the power stored in the input capacitors Cd1 and Cs1 decreases with the passage of time. As a result, in the FET 50, the voltage value of the gate based on the potential of the source decreases to a voltage value less than the disconnection threshold, and the FET 50 is switched to disconnection.

[0099] The smaller the resistance value of the discharge resistor 53, the faster the discharge speed of the input capacitor Cd1, and the smaller the capacitance value of the input capacitor Cd1, the faster the discharge speed of the input capacitor Cd1. Similarly, the smaller the resistance value of the discharge resistor 53, the faster the discharge speed of the input capacitor Cs1, and the smaller the capacitance value of the input capacitor Cs1, the faster the discharge speed of the input capacitor Cs1. Therefore, the smaller the resistance value of the discharge resistor 53, the faster the speed at which the FET50 switches from on to off. As described above, the resistance value of the discharge resistor 53 is smaller than the resistance value of the charging resistor 52. Therefore, the speed at which the FET50 switches from on to off is faster than the speed at which the FET50 switches from off to on.

[0100] In addition, as described above, the resistance value of the discharge resistor 63 is smaller than the resistance value of the charging resistor 62. Therefore, when the input capacitors Cd2 and Cs2 of the FET 60 are discharged, the current flows from one end of the gate side of the input capacitors Cd2 and Cs2 in the order of the discharge resistor 63, the diode 64, the circuit resistor 83, and the discharge switch 82. During the discharge of the input capacitors Cd2 and Cs2, the power stored in the input capacitors Cd2 and Cs2 decreases with the passage of time. As a result, in the FET 60, the voltage value of the gate based on the potential of the source is reduced to a voltage value less than the disconnection threshold, and the FET 60 is switched to disconnection.

[0101] The smaller the resistance value of the discharge resistor 63, the faster the discharge speed of the input capacitor Cd2, and the smaller the capacitance value of the input capacitor Cd2, the faster the discharge speed of the input capacitor Cd2. Similarly, the smaller the resistance value of the discharge resistor 63, the faster the discharge speed of the input capacitor Cs2, and the smaller the capacitance value of the input capacitor Cs2, the faster the discharge speed of the input capacitor Cs2. Therefore, the smaller the resistance value of the discharge resistor 63, the faster the speed at which the FET60 switches from on to off. As described above, the resistance value of the discharge resistor 63 is smaller than the resistance value of the charging resistor 62. The speed at which the FET60 switches from on to off is faster than the speed at which the FET60 switches from off to on.

[0102] As described above, in the power supply control device 2, since the series circuit including the discharge resistor 53 and the diode 54 is connected between the two ends of the charging resistor 52, the power accumulated in the input capacitors Cd1 and Cs1 is quickly released, and the FET 50 can be quickly switched off. Similarly, since the series circuit including the discharge resistor 63 and the diode 64 is connected between the two ends of the charging resistor 62, the power accumulated in the input capacitors Cd2 and Cs2 is quickly released, and the FET 60 can be quickly switched off. As described above, when the microcomputer 72 determines that the current value of the current flowing through the FETs 50 and 60 is greater than the reference current value, the voltage output to the drive circuit 70 is switched to a low-level voltage, and the drive circuit 70 switches the FETs 50 and 60 to be switched off. In this way, overcurrent is prevented from flowing through the FETs 50 and 60.

[0103] When the current value is greater than the reference current value, that is, when a large amount of heat is generated in the FETs 50 and 60, it is preferable that the period during which the current flows through the FETs 50 and 60 is short. When the period during which the current flows through the FETs 50 and 60 is short, the temperature rise of the FETs 50 and 60 is suppressed. In the power supply control device 2, since the FETs 50 and 60 are quickly switched off, the period during which the current flows through the FETs 50 and 60 is short, and the temperature rise of the FETs 50 and 60 is suppressed.

[0104] In addition, in the power supply control device 2, since the discharge resistor 53 and the diode 54 can be connected in series, the diode 54 can also be arranged on the FET50 side of the discharge resistor 53. In this case, the cathode of the diode 54 is also arranged on the boost circuit 80 side. Similarly, since the discharge resistor 63 and the diode 64 can be connected in series, the diode 64 can also be arranged on the FET60 side of the discharge resistor 63. In this case, the cathode of the diode 64 is also arranged on the boost circuit 80 side.

[0105] The power supply control device 2 may not include the series resistor 51. In this case, the source of the FET 50 is connected to one end of the load 4. Similarly, the power supply control device 2 may not include the series resistor 61. In this case, the source of the FET 60 is connected to one end of the load 4.

[0106] Furthermore, the FETs 50 and 60 can function as transistors in which the resistance between the current input terminal and the current output terminal decreases as the voltage value of the control terminal based on the potential of the current output terminal increases. Therefore, transistors other than FETs, such as IGBTs (Insulated Gate Bipolar Transistors), can be used to replace the FETs 50 and 60. The gate, collector, and emitter of the IGBT correspond to the gate, drain, and source of the FET, respectively.

[0107] In addition, the circuit resistor 83 only needs to be arranged in a common portion of the application route for applying a voltage from the output end of the boost circuit 80 to the gates of the FETs 50 and 60. Therefore, the circuit resistor 83 may be arranged, for example, between the output end of the boost circuit 80 and the charging switch 81. In this case, the connection node between the charging switch 81 and the discharging switch 82 is connected to one end of the charging resistors 52 and 62 on the boost circuit 80 side.

[0108] As described above, when the DC power supply 3 supplies power to the load 4, the current flows in the common power supply route, and the common power supply route branches into two branch routes. Various elements may also be configured in the common power supply route. For example, a resistor may also be configured in the common power supply route. In this case, the output voltage value of the DC power supply 3 is different from the voltage value of the drain of the FET 50 and 60. Furthermore, in the power supply control device 2, series resistors 51 and 61 are respectively configured in the two branch routes. However, the structure of the power supply control device 2 may also be a structure in which one or both of the series resistors 51 and 61 are not configured. When the series resistor 51 is not configured, the source of the FET 50 is directly connected to one end of the load 4. In this case, instead of the current detection circuit 71, for example, a current sensor that can detect current without using a resistor is used. When the series resistor 61 is not configured, the source of the FET 60 is directly connected to one end of the load 4. In addition, other elements may be configured instead of each series resistor 51 and 61.

[0109] As the structure of the power supply control device 2, a structure in which a common power supply route branches and the number of branch routes for transistor configuration is 2 is described. However, the structure of the power supply control device 2 can be expanded to a structure in which the number of branch routes is 3 or more. In this case, a circuit identical to the circuit composed of the charging resistor 52, the discharging resistor 53 and the diode 54 is configured in the application route in which the drive circuit 70 applies a voltage to the control terminal of each transistor. In each circuit, the resistance value of the charging resistor is greater than the resistance value of the discharging resistor. By considering the state in which a short-circuit fault occurs in each transistor, a conditional expression identical to a conditional expression such as formula (1) or formula (2) can be set. However, the structure in which the number of branch routes is 3 or more includes a structure in which the number of branch routes is 2.

[0110] The disclosed embodiments should be considered in all respects as illustrative and non-restrictive. The scope of the present invention is indicated by the claims rather than the above content, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0111] Description of Reference Numerals

[0112] 1 Power System

[0113] 2 Power supply control device

[0114] 3 DC power supply

[0115] 4 Load

[0116] 50, 60 FET (first transistor, second transistor)

[0117] 51, 61 series resistance

[0118] 52, 62 Charging resistor (second resistor)

[0119] 53, 63 discharge resistor (third resistor)

[0120] 54, 64 diodes

[0121] 70 drive circuit

[0122] 71 Current detection circuit

[0123] 72 Microcomputer

[0124] 80 boost circuit (voltage applying section)

[0125] 81 Charging switch

[0126] 82 Discharge switch

[0127] 83 Circuit resistance (first resistance)

[0128] Cd1, Cs1, Cd2, Cs2 input capacitors.

Claims

1. A power supply control device for controlling power supply to a load via two branch routes branched from a common power supply route arranged at a positive electrode of a DC power supply, The power supply control device comprises: Two transistors are respectively arranged on the two branch routes, and the higher the gate voltage value based on the potential of the source of the output current is, the smaller the resistance value between the drain of the input current and the source is; a driving circuit connected to the drains of the two transistors and having a boost circuit, a charging switch, a discharging switch and a first resistor, outputting a voltage from a common output terminal and applying a voltage to the gates of the two transistors via the first resistor; two charging resistors, respectively arranged at two application routes for applying voltage from the output end of the driving circuit to the gates of the two transistors; and Two diodes are connected between the two ends of the two charging resistors, and the cathodes are arranged on the boost circuit side. One end of the charging resistor is respectively connected to the gate of the transistor, the boost circuit is connected to the positive electrode of the DC power supply and one end of the charging switch, the other end of the charging switch is connected to one end of the discharging switch, the other end of the discharging switch is grounded, the connection node between the charging switch and the discharging switch is connected to one end of the first resistor, and the other end of the first resistor is connected to the other ends of the two charging resistors. The power supply control device further includes two discharge resistors connected in series with the two diodes, respectively. Two series circuits including a diode and a discharge resistor are respectively connected between the two ends of the two charging resistors. The two charging resistors each have a resistance value greater than the resistance value of the discharge resistor connected to the two ends. The boost circuit boosts the output voltage of the DC power supply and outputs the boosted voltage from the common output terminal. The sources of the two transistors are connected to a series resistor, respectively, and current is output from the sources of the two transistors to the load via the series resistor. The power supply control device further includes a current detection circuit for detecting the current flowing in the series resistor, and when it is determined that the current value flowing through the transistor is greater than a reference current value based on the current value represented by the current information input from the current detection circuit, the transistor is switched off by the drive circuit.

2. The power supply control device according to claim 1, wherein: The voltage value Vp of the voltage output from the output terminal of the boost circuit, the voltage value Vi of the drain of the first transistor included in the two transistors, the resistance value R1 of the first resistor, and the resistance value R2 of the charging resistor arranged in the application route for applying voltage to the gate of the second transistor included in the two transistors satisfy the following formula: (Vp-Vi)·R2 / (R1+R2)≥Vg Wherein, Vg is the voltage value between the source and the gate required to switch the first transistor on.

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