Semiconductor device and method for manufacturing the same

Abstract

Semiconductor devices such as vertical cavity surface emitting lasers and methods of manufacturing the same are disclosed. The semiconductor device includes a contact extension and a conductive bonding material, such as a fusible metal alloy or a conductive composite. In some cases, the semiconductor device also includes a structured contact. These components allow the semiconductor device to be manufactured with minimal deformation. For example, an array of vertical cavity surface emitting lasers that exhibits little to no bending can be manufactured. In some cases, the semiconductor device with minimal deformation exhibits enhanced performance.

Description

Background Art

[0001] Semiconductor devices may include components with intrinsic stresses. For example, an epitaxially grown layer may exhibit lattice parameters that are mismatched with the substrate on which the epitaxially grown layer is grown. This misalignment results in strains that occur, for example, near the interface between the two components. In addition, in some cases, the coefficients of thermal expansion of various components within the semiconductor device may be significantly different from each other, resulting in thermal stresses during the manufacture or operation of the semiconductor device. These effects may cause measurable deformations (e.g., bending) in the semiconductor device. The deformation may be significant in an array or wafer of semiconductor devices. Deformation may be particularly problematic for applications that require a substantially flat (deformation-free) array of semiconductor devices.

[0002] Strain compensating layers are known in the art. However, strain compensating layers, such as dielectric strain compensating layers, may be difficult to implement in some cases. Therefore, alternative solutions are needed. Summary of the invention

[0003] The present disclosure describes semiconductor devices (such as discrete semiconductor devices or semiconductor device arrays) that exhibit little to no deformation and methods of manufacturing the same. For example, in one aspect, a semiconductor device includes: a substrate having opposing first and second sides; and an epitaxial layer having opposing first and second sides. A first side of the epitaxial layer abuts a first side of the substrate.

[0004] The semiconductor device also includes: a substrate contact adjacent to the second side of the substrate; an epitaxial contact adjacent to the second side of the epitaxial layer; and a submount. The submount is mounted to the submount contact by a conductive material. In some cases, the submount contact is an epitaxial contact. In some cases, the submount contact is a substrate contact.

[0005] The semiconductor device also includes an obverse sub-base contact. In some cases, the obverse sub-base contact is an epitaxial contact that is not associated with the sub-base contact. In some cases, the obverse sub-base contact is a substrate contact that is not associated with the sub-base contact. The semiconductor device also includes a contact extension adjacent to the obverse sub-base contact.

[0006] In some implementations, a semiconductor device includes a structured extension adjacent to a submount contact.

[0007] In some embodiments, the contact extensions are composed of the same material as the front submount contacts, and the contact extensions are characterized by microstructures that are substantially similar to the front submount contacts.

[0008] In some embodiments, the contact extensions are composed of the same material as the front submount contacts, and the contact extensions are characterized by substantially different microstructures than the front submount contacts.

[0009] In another aspect, a semiconductor device array includes: a substrate having a first side and a second side opposite to each other; and an epitaxial layer having a first side and a second side opposite to each other. The first side of the epitaxial layer is adjacent to the first side of the substrate. The first side of the substrate and the first side of the epitaxial layer are characterized by intrinsic stress within the vicinity of the first side of the substrate and the first side of the epitaxial layer.

[0010] The semiconductor device array also includes: a substrate contact that abuts the second side of the substrate; an epitaxial contact that abuts the second side of the epitaxial layer; and a submount. The submount is mounted to the submount contact by a conductive material. The submount contact is either an epitaxial contact or a substrate contact. The conductive adhesive material is characterized by a melting temperature below which the conductive adhesive material is substantially solid.

[0011] The semiconductor device array also includes a front sub-mount contact. In some cases, the front sub-mount contact is an epitaxial contact that is not associated with the sub-mount contact. In some cases, the front sub-mount contact is a substrate contact that is not associated with the sub-mount contact. The semiconductor device array also includes: a contact extension that is adjacent to the front sub-mount contact; and a plurality of isolation components that are located within the epitaxial layer. The isolation components divide individual semiconductor devices within the semiconductor device array.

[0012] In some implementations, the contact extensions are operable to counteract intrinsic stress within the first side of the substrate and near the first side of the epitaxial layer such that the semiconductor device array adopts a substantially planar form above a melting temperature of the conductive bonding material.

[0013] In some embodiments, the conductive adhesive material is operable to secure the array of semiconductor devices in a substantially planar form below the melting temperature of the conductive adhesive material.

[0014] In some embodiments, the semiconductor device array further includes a structured extension adjacent to the submount contact.

[0015] In another aspect, the present invention describes a method for manufacturing a semiconductor device. The method may include:

[0016] o mounting a component on a component holder, the component comprising a substrate having opposing first and second sides; and an epitaxial layer having opposing first and second sides, the first side of the epitaxial layer abutting the first side of the substrate, and the second side of the substrate abutting the component holder;

[0017] o depositing an epitaxial contact onto the second side of the epitaxial layer;

[0018] o depositing contact extensions onto the epitaxial contacts;

[0019] ○ Mounting the assembly, epitaxial contact, and contact extension onto the suction cup such that the epitaxial layer, epitaxial contact, and contact extension are adjacent to the suction cup;

[0020] ○ Remove the component, extension contact, contact extension and suction cup from the component holder;

[0021] o removing a portion of the substrate from the second side of the substrate;

[0022] o depositing a substrate contact onto the second side of the substrate;

[0023] o positioning the substrate contact, the assembly, the epitaxial contact, the contact extension, and the suction cup on a submount such that the submount is adjacent to the second side of the substrate and the substrate contact, the submount being positioned by conductive material between portions of the substrate contact and the submount;

[0024] o heating the submount, substrate contacts, assembly, epitaxial contacts, contact extensions, chuck, and conductive material to an elevated temperature at or above the melting temperature of the conductive material;

[0025] o Cooling the submount, substrate contacts, components, epitaxial contacts, contact extensions, chucks, and conductive materials to a temperature below the elevated temperature;

[0026] ○ Removing the submount, substrate contacts, components, epitaxial contacts, contact extensions, and conductive materials from the chuck; and

[0027] o Cutting the sub-mounts, substrate contacts, components, epitaxial contacts, contact extensions, and conductive materials into a plurality of semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices.

[0028] In some embodiments, the method for manufacturing a semiconductor device further includes depositing a structured extension onto the substrate contact.

[0029] In some embodiments, mounting the component, epitaxial contacts, and contact extensions onto the chuck includes depositing an organic compound between the chuck and the epitaxial layer, epitaxial contacts, and contact extensions.

[0030] In some embodiments, depositing the contact extension includes depositing the contact extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0031] In some embodiments, depositing the structured extension includes depositing the structured extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0032] In some embodiments, depositing the epitaxial contacts and / or the substrate contacts includes depositing the contacts by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0033] In another aspect, a method for manufacturing a semiconductor device may include:

[0034] o mounting a component on a component holder, the component comprising a substrate having opposing first and second sides; and an epitaxial layer having opposing first and second sides, the first side of the epitaxial layer abutting the first side of the substrate, and the second side of the epitaxial layer abutting the component holder;

[0035] o depositing a substrate contact onto the second side of the epitaxial layer;

[0036] ○ depositing contact extensions onto substrate contacts;

[0037] ○ Mount the component, substrate contact and contact extension on the suction cup so that the substrate, substrate contact and contact extension are adjacent to the suction cup;

[0038] ○ Remove the component, substrate contacts, contact extensions and suction cups from the component holder;

[0039] o depositing an epitaxial contact onto the second side of the epitaxial layer;

[0040] o positioning the epitaxial contact, the assembly, the substrate contact, the contact extension, and the suction cup on a submount such that the submount is adjacent to the second side of the epitaxial layer and the epitaxial contact, the submount being positioned by conductive material between the epitaxial contact and a portion of the submount;

[0041] o heating the submount, epitaxial contacts, assembly, substrate contacts, contact extensions, chuck, and conductive material to an elevated temperature at or above the melting temperature of the conductive material;

[0042] o Cooling the submount, epitaxial contacts, components, substrate contacts, contact extensions, chucks, and conductive materials to a temperature below the elevated temperature;

[0043] ○ Removing the submount, epitaxial contacts, components, substrate contacts, contact extensions, and conductive materials from the chuck; and

[0044] o Cutting the sub-mounts, epitaxial contacts, components, substrate contacts, contact extensions, and conductive materials into a plurality of semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices.

[0045] In some embodiments, the method includes depositing a structured extension onto the epitaxial contact.

[0046] In some embodiments, mounting the component, substrate contact, and contact extension onto the chuck includes depositing an organic compound between the chuck and the substrate, substrate contact, and contact extension.

[0047] In some embodiments, depositing the contact extension includes depositing the contact extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0048] In some embodiments, depositing the structured extension includes depositing the structured extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0049] In some embodiments, depositing the epitaxial contacts and / or the substrate contacts includes depositing the contacts by electrodeposition, physical vapor deposition, or chemical vapor deposition.

[0050] Other aspects, features, and advantages will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1A An exemplary semiconductor device array is depicted, where the semiconductor devices are shown as an array of top-emitting vertical cavity surface emitting lasers.

[0052] Figure 1B Another exemplary semiconductor device array is depicted, where the semiconductor devices are shown as an array of bottom emitting vertical cavity surface emitting lasers.

[0053] Figure 1C Depicted Figure 1A An enlarged region within the exemplary semiconductor device array depicted in FIG.

[0054] Figure 1D and Figure 1E Depicted Figure 1B An enlarged region within the exemplary semiconductor device array depicted in FIG.

[0055] Figure 2 A method for manufacturing a semiconductor device or semiconductor device array (such as Figure 1A An exemplary method of a semiconductor device array as depicted in FIG.

[0056] Figure 3 A method for manufacturing a semiconductor device or semiconductor device array (such as Figure 1B An exemplary method of a semiconductor device array as depicted in FIG. DETAILED DESCRIPTION

[0057] Figure 1A and Figure 1BAn exemplary semiconductor device array 100A and an exemplary semiconductor device array 100B are depicted, respectively. The semiconductor device array 100A is a top-emitting vertical cavity surface emitting laser, and the semiconductor device array 100B is a bottom-emitting vertical cavity surface emitting laser. The following components disclosed herein can be applied to both types of vertical cavity surface emitting lasers, as well as other semiconductor devices or semiconductor device arrays.

[0058] The following description refers to an array of semiconductor devices designed to operate as a single device or module (such as a wafer of semiconductor devices or smaller multiple semiconductor devices), and the description is applicable to individual or discrete semiconductor devices separated (e.g., diced) from the array of semiconductor devices.

[0059] Figure 1A and Figure 1B The same components are included and are referred to simultaneously in the following description. Although they are positioned differently relative to other components, some components are described using common component names. Their common component names indicate their positions relative to common components (whose positions do not change in both semiconductor device arrays 100A, 100B). For example, the submount contact is Figure 1A The substrate contacts in the embodiment depicted in FIG. 1 , and Figure 1B A common component name (submount contact in this example) is used in both embodiments to refer to the location of the substrate contact; that is, adjacent to the submount in the first embodiment and not adjacent to the submount in the second embodiment; thus, in any embodiment, the submount contact location is adjacent to the submount.

[0060] The semiconductor device arrays 100A and 100B each include a substrate 102 having opposite first and second sides 104 and 106, and an epitaxial layer 108 having opposite first and second sides 110 and 112. The substrate 102 and the epitaxial layer 108 may each be composed of, for example, a crystalline, polycrystalline, or amorphous semiconductor or insulating material such as gallium arsenide, aluminum gallium arsenide, indium antimonide, or silicon.

[0061] The composition and thickness of substrate 102 and epitaxial layer 108 depend on the intended application of the semiconductor device and may therefore vary in different embodiments. For example, substrate 102 may be composed of gallium arsenide 10 to 200 microns thick, and epitaxial layer 108 may be composed of aluminum gallium arsenide 1 to 20 microns thick.

[0062] Typically, the epitaxial layer 108 is epitaxially grown as a crystalline layer on the first side 104 of the substrate 102 to a thickness that is substantially less than the substrate 102. In such a case, the substrate 102 is also crystalline and composed of a material having a similar, but not identical, lattice parameter as the epitaxial layer 108. Because the lattice parameters are not identical, stresses may occur within the vicinity of the first side 104 of the substrate 102 and the first side 110 of the epitaxial layer 108, causing both the substrate 102 and the epitaxial layer 108 to deviate from a plane (e.g., bend).

[0063] Each of the semiconductor device arrays 100A, 100B further includes a substrate contact 114 adjacent to the second side 106 of the substrate 102, an epitaxial contact 116 adjacent to the second side 112 of the epitaxial layer 108, and a submount 118. Generally, the substrate contact 114 and the epitaxial contact 116 are operable to direct current to components within the semiconductor device, such as an active region (e.g., including quantum wells) configured to generate light 126 within the epitaxial layer 108. For example, the submount may be a printed circuit board, a lead frame, or a metal layer intended for further processing.

[0064] Submount 118 is mounted to a submount contact using a conductive material 120 such as a fusible metal alloy (e.g., indium tin solder) or a conductive composite (e.g., silver epoxy). The submount contact is adjacent to submount 118 and may be substrate contact 114 or epitaxial contact 116, depending on the embodiment. For example, the submount contact may be Figure 1A 1. The substrate contact 114 for a top emitting vertical cavity surface emitting laser as depicted in FIG. 1. In another example, the submount contact is as shown in FIG. Figure 1B An epitaxial contact 116 for a bottom emitting vertical cavity surface emitting laser is depicted in FIG.

[0065] Each of the semiconductor device arrays 100A, 100B further includes a front sub-mount contact. Figure 1A As depicted in FIG. 1 , when the epitaxial contact 116 is not associated with a sub-mount contact, the front sub-mount contact is the epitaxial contact 116. Figure 1B As depicted in , the front submount contact is the substrate contact 114 when the substrate contact 114 is not associated with a submount contact.

[0066] Both the submount contact and the front submount contact (and thus the substrate contact 114 and the epitaxial contact 116) may be composed of a conductive metal. The conductive metal may include an element selected from the group consisting of: gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony, and tin. Both the submount contact and the front submount contact may be deposited by chemical vapor deposition (e.g., metal organic vapor deposition), physical vapor deposition (e.g., electron beam physical vapor deposition), and / or electrodeposition (e.g., damascene plating). In some cases, the front submount contact and / or the submount contact may include a metal barrier film (e.g., tantalum, tantalum nitride) and / or a dielectric barrier (silicon nitride).

[0067] Each of the semiconductor device arrays 100A, 100B further includes a contact extension 122 adjacent to the front submount contact. Figure 1A The contact extension 122 is depicted abutting the epitaxial contact 116 , which is a front side submount contact, as in this and similar embodiments. Figure 1B The contact extension 122 is depicted abutting the substrate contact 114 , which, in this and similar embodiments, is a front side submount contact.

[0068] In some cases, contact extension 122 is composed of a conductive metal. The conductive metal may include an element selected from the group consisting of: gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony, and tin. Thus, contact extension 122 may be operable to direct current via electrical connection 128 to components within semiconductor device array 100A, 100B, such as an active region (e.g., including quantum wells) configured to generate light 126 within epitaxial layer 108, such as Figure 1C However, the contact extension 122 need not be operable to direct current to the component. For example, the substrate contact 114 may include a plate 130 for the electrical connector 128, such as Figure 1D Thus, the contact extension 122 may be electrically isolated from the substrate contact 114 or even insulated in some embodiments.

[0069] In some embodiments, contact extension 122 can be composed of the same material as the front sub-mount contact and can be deposited onto the front sub-mount contact by chemical vapor deposition, physical vapor deposition, and / or electrodeposition. Thus, contact extension 122 can be composed of the same material as the front sub-mount contact and can be characterized by a microstructure that is substantially similar to that of the front sub-mount contact.

[0070] However, in some embodiments, contact extension 122 is comprised of the same material as the front sub-mount contact and can be deposited by a different method than the front sub-mount contact. For example, in some cases, the front sub-mount contact is comprised of gold deposited by physical vapor deposition (e.g., electron beam physical vapor deposition), and the contact extension is comprised of gold deposited by electrodeposition. Thus, contact extension 122 can be characterized by a microstructure that is substantially different from that of the front sub-mount contact. For example, contact extension 122 can employ a substantially crystalline or polycrystalline microstructure, and the front sub-mount contact can employ a substantially amorphous microstructure.

[0071] Furthermore, in some embodiments, contact extension 122 is comprised of a different material than the front submount contact and can be deposited by different means than the front submount contact. For example, in some cases, the front submount contact is comprised of gold deposited by physical vapor deposition (e.g., electron beam physical vapor deposition) and the contact extension is comprised of copper deposited by electrodeposition. Thus, contact extension 122 can be characterized by a composition and microstructure that is substantially different than the front submount contact.

[0072] The contact extension 122 is operable to counteract intrinsic stresses within the first side 104 of the substrate 102 and the first side 110 of the epitaxial layer 108, so that the semiconductor device array 100A, 100B adopts a substantially planar form above the melting temperature of the conductive adhesive material 120. In some embodiments, the contact extension can be composed of gold from 1 micron to 30 microns thick. However, the operability of the contact extension 122 depends on many factors, such as its composition, area, thickness, thermal expansion coefficient, and stress within the substrate 102 and the epitaxial layer 108, as described above. In addition, the intrinsic stresses within the contact extension 122 caused by various processing parameters can be tailored to counteract the above-mentioned intrinsic stresses. For example, stresses within the microstructure of the contact extension 122 can be introduced by adjusting processing parameters (e.g., solution pH, impurities, particle size) during electrodeposition.

[0073] Although the contact extensions 122 are operable to counteract intrinsic stress at elevated temperatures (i.e., at or above the melting temperature of the conductive adhesive 120), this effect must be locked in at cooler temperatures. Thus, the conductive adhesive material 120 is operable to secure the semiconductor device array 100A, 100B in a substantially planar form below its melting temperature.

[0074] In some embodiments (such as Figure 1A and Figure 1BIn the embodiment depicted in FIG. 1 , each of the semiconductor device arrays 100A, 100B further includes a structured extension 124 adjacent to the sub-base contact. The structured extension 124 is configured to improve the adhesion of the conductive adhesive material 120 to the sub-base contact. In some cases, the structured extension 124 can also be configured to counteract the above-mentioned intrinsic stress via the same method as the contact extension 122.

[0075] Both the contact extension 122 and the structured extension 124 are configured together with the conductive adhesive material 120 to enable the semiconductor device array 100A, 100B to adopt a substantially planar form at a temperature above the melting temperature of the conductive adhesive material 120. The conductive adhesive material 120 and the structured extension 124 can then operate to fix the semiconductor device array 100A, 100B in a substantially planar form at a temperature below the melting temperature of the conductive adhesive material 120. In some cases, the structured extension 124 may include a crenelated extension 132 configured to increase the contact area between the structured extension 124 and the conductive adhesive material 120, such as Figure 1E As depicted in .

[0076] The semiconductor device arrays 100A, 100B also include a plurality of isolation features (not depicted) within the epitaxial layer 108. The plurality of isolation features divide the semiconductor devices within the semiconductor device arrays 100A, 100B. For example, the isolation features within the epitaxial layer 108 may include a dielectric material such as aluminum oxide. In some cases, the isolation features may include portions of the epitaxial layer characterized by damage caused by ion bombardment. In some cases, the isolation features within the epitaxial layer include removed portions of the epitaxial layer. The removed portions define mesa structures, each of which divides one of the semiconductor devices within the semiconductor device array.

[0077] Figure 2 The method for manufacturing Figure 1A 2. An exemplary method 200 for mounting a semiconductor device array as depicted in FIG. 202 is provided by mounting an assembly on an assembly holder, such as a vacuum chuck. The assembly includes a substrate 102 having opposing first and second sides 104, 106, and an epitaxial layer 108 having opposing first and second sides 110, 112. The first side 110 of the epitaxial layer 108 abuts the first side 104 of the substrate 102, and the second side 106 of the substrate 102 abuts the assembly holder. As described above, the epitaxial layer 108 may be epitaxially grown on the substrate 102 according to methods apparent to one of ordinary skill in the art.

[0078] At 204, epitaxial contact 116 is deposited onto second side 112 of epitaxial layer 108. As described above, epitaxial contact 116 may be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, epitaxial contact 116 may be 1000 angstroms to 2000 angstroms, but in other cases, epitaxial contact 116 may be 5 microns thick or more.

[0079] At 206, contact extension 122 is deposited onto epitaxial contact 116. As described above, contact extension 122 can be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, contact extension 122 can be 1 micron or up to 20 microns, or even 30 microns thick. In some cases, epitaxial contact 116 serves as a seed layer for contact extension 122.

[0080] At 208, the component, epitaxial contact 116, and contact extension 122 are mounted onto a chuck (e.g., a vacuum chuck) such that the epitaxial layer 108, epitaxial contact 116, and contact extension 122 are adjacent to the chuck. In some cases, the component, epitaxial contact 116, and contact extension 122 are mounted onto the chuck using an organic compound positioned between the chuck and the epitaxial layer 108, epitaxial contact 116, and contact extension 122. The organic compound may be a wax, resin, or other moldable material designed to minimize damage to the aforementioned components.

[0081] At 210, the component, the extension contacts 116, the contact extensions 122, and the suction cup are removed from the component holder.

[0082] At 212, a portion of the substrate 102 is removed from the second side 106 of the substrate 102. The portion of the substrate 102 may be removed by standard means, such as grinding, lapping, or polishing. For example, the substrate 102 may be 700 microns thick and may be subjected to grinding, lapping, or polishing until it is, for example, 100 to 200 microns thick.

[0083] At 214, substrate contact 114 is deposited onto second side 106 of substrate 102. As described above, substrate contact 114 may be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, substrate contact 114 is 1000 angstroms to 2000 angstroms, but in other cases, substrate contact 114 is 5 microns or more. In some cases, structured extension 124 is deposited onto substrate contact. Structured extension 124 may be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, structured extension 124 is 1 micron or up to 20 microns, or even 30 microns thick. In some cases, substrate contact 114 serves as a seed layer for structured extension 124. In some cases, structured extension 124 may be blunt-toothed or otherwise structured to increase the surface area of ​​the structured extension.

[0084] At 216, substrate contact 114, assembly, epitaxial contact 116, contact extension 122, and chuck are positioned onto submount 118 such that submount 118 is adjacent to second side 106 of substrate 102 and substrate contact 114. Submount 118 is positioned with conductive material 120 between substrate contact 114 and portions of submount 118.

[0085] At 218, the submount 118, substrate contact 114, assembly, epitaxial contact 116, contact extension 122, chuck, and conductive material 120 are heated to an elevated temperature at or above the melting temperature of the conductive material 120 for a duration that depends on the conductive adhesive material 120. For example, the foregoing components may be heated to 200° C., 300° C., or even 350° C. for 15 minutes, an hour, or even several hours. In some cases, the foregoing components may be heated in an inert atmosphere (e.g., N2, Ar) or a reducing atmosphere (e.g., 95:5 N2:H).

[0086] At 220 , the submount 118 , substrate contact 114 , assembly, epitaxial contact 116 , contact extension 122 , chuck, and conductive material 120 are cooled to a temperature below the elevated temperature.

[0087] At 222, the submount 118, substrate contacts 116, components, epitaxial contacts 116, contact extensions 122, and conductive material 120 are removed from the chuck.

[0088] At 224 , submount 118 , substrate contacts 114 , components, epitaxial contacts 116 , contact extensions 122 , and conductive material 120 are separated (eg, diced) into a plurality of discrete semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices.

[0089] Figure 3 The method for manufacturing Figure 1B . At 302, a component is mounted on a component holder. The component includes a substrate 102 having an opposing first side 104 and a second side 106, and an epitaxial layer 108 having an opposing first side 110 and a second side 112. The first side 110 of the epitaxial layer 108 abuts the first side 104 of the substrate 102, and the second side 112 of the epitaxial layer 108 abuts the component holder. As described above, the epitaxial layer 108 can be epitaxially grown on the substrate 102.

[0090] At 304, a substrate contact 114 is deposited onto the second side 110 of the epitaxial layer 108. As described above, the substrate contact 114 can be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, the substrate contact 114 is 1000 angstroms to 2000 angstroms, but in other cases, the substrate contact 114 is 5 microns thick or more.

[0091] At 306, contact extension 122 is deposited onto substrate contact 114. As described above, contact extension 122 can be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, contact extension 122 is 1 micron or up to 20 microns, or even 30 microns thick. In some cases, substrate contact 114 acts as a seed layer for contact extension 122.

[0092] At 308, the component, substrate contact 114, and contact extension 122 are mounted on a chuck (e.g., a vacuum chuck) such that the substrate 102, substrate contact 114, and contact extension 122 are adjacent to the chuck. In some cases, the component, substrate contact 114, and contact extension 122 are mounted on the chuck using an organic compound positioned between the chuck and the substrate 102, substrate contact 114, and contact extension 122. The organic compound may be a wax, resin, or other moldable material designed to minimize damage to the aforementioned components.

[0093] At 310, the component, substrate contacts 114, contact extensions 122, and suction cup are removed from the component holder.

[0094] At 312, epitaxial contact 116 is deposited onto second side 112 of epitaxial layer 108. As described above, epitaxial contact 116 may be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, epitaxial contact 116 is 1000 angstroms to 2000 angstroms, but in other cases, epitaxial contact 116 is 5 microns or more. In some cases, structured extension 124 is deposited onto epitaxial contact 116. Structured extension 124 may be deposited via chemical vapor deposition, physical vapor deposition, and / or electrodeposition. In some cases, structured extension 124 is 1 micron or up to 20 microns, or even 30 microns thick. In some cases, epitaxial contact 116 serves as a seed layer for structured extension 124. In some cases, structured extension 124 may be blunt-toothed or otherwise structured to increase the surface area of ​​the structured extension.

[0095] At 314, epitaxial contact 116, assembly, substrate contact 114, contact extension 122, and suction cup are positioned onto submount 118 such that submount 118 is adjacent to second side 112 of epitaxial layer 108 and epitaxial contact 116. Submount 118 is positioned with conductive material 120 between epitaxial contact 116 and portions of submount 118.

[0096] At 316, submount 118, epitaxial contacts 116, assembly, substrate contacts 114, contact extensions 122, chuck, and conductive material 120 are heated to an elevated temperature at or above the melting temperature of conductive material 120 for a duration that depends on conductive adhesive material 120. For example, the foregoing components may be heated to 200° C., 300° C., or even 350° C. for 15 minutes, an hour, or even several hours. In some cases, the foregoing components may be heated in an inert atmosphere (e.g., N2, Ar) or a reducing atmosphere (e.g., 95:5 N2:H).

[0097] At 318 , the submount, epitaxial contacts 116 , assembly, substrate contacts 114 , contact extensions 122 , chuck, and conductive material 120 are cooled to a temperature below the elevated temperature.

[0098] At 320, the submount 118, epitaxial contacts 116, assembly, substrate contacts 114, contact extensions 122, and conductive material 120 are removed from the chuck.

[0099] At 322 , submount 118 , epitaxial contacts 116 , components, substrate contacts 114 , contact extensions 122 , and conductive material 120 are separated (eg, diced) into a plurality of discrete semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices.

[0100] Other modifications may be made to the foregoing embodiments. For example, the foregoing exemplary procedures may include additional steps, such as applying, developing, and removing photoresist; thermal treatment (e.g., annealing); planarization; and welding. In addition, the semiconductor device described above may include additional components, such as additional electrical connections, current and / or light-defining apertures, etc. In addition, the features described above in different embodiments may be combined in the same embodiment. Therefore, other embodiments also fall within the scope of the claims.

Claims

1. A semiconductor device comprising: a substrate having a first side and a second side opposite to each other; an epitaxial layer having a first side and a second side opposite to each other, the first side of the epitaxial layer being adjacent to the first side of the substrate; a substrate contact adjacent the second side of the substrate; an epitaxial contact adjacent the second side of the epitaxial layer; a sub-mount mounted to a sub-mount contact by a conductive material, the sub-mount contact being the epitaxial contact or the substrate contact; a front sub-mount contact, the front sub-mount contact being the epitaxial contact or the substrate contact not associated with the sub-mount contact; as well as a contact extension abutting the front submount contact; wherein the contact extension is operable to counteract intrinsic stress near the first side of the substrate and the first side of the epitaxial layer, thereby making the semiconductor device planar above a melting temperature of the conductive material; and wherein intrinsic stress within the contact extension is caused by processing parameters during electrodeposition of the contact extension, and wherein the intrinsic stress within the contact extension is adjusted to offset intrinsic stress near the first side of the substrate and the first side of the epitaxial layer. 2 . The semiconductor device of claim 1 , further comprising a structured extension adjacent to the submount contact.

3. The semiconductor device according to claim 1, wherein The contact extension is composed of the same material as the front submount contact and the contact extension is characterized by the same microstructure as the front submount contact.

4. The semiconductor device according to claim 1, wherein The contact extension is composed of the same material as the front submount contact and is characterized by a different microstructure than the front submount contact.

5. The semiconductor device according to claim 4, wherein: The contact extension is characterized by a crystalline or polycrystalline microstructure, and the front submount contact is characterized by an amorphous microstructure.

6. The semiconductor device according to claim 1, wherein The contact extension is composed of a conductive metal.

7. The semiconductor device according to claim 6, wherein: The conductive metal includes an element selected from the group consisting of gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony, and tin.

8. The semiconductor device according to claim 1, wherein The conductive material includes a fusible metal alloy or a conductive composite.

9. The semiconductor device according to claim 1, wherein: The front submount contact is composed of a conductive material, wherein the conductive material includes an element selected from the group consisting of: gold, copper, silver, aluminum, platinum, palladium, rhodium, indium, iridium, gallium, bismuth, antimony and tin.

10. The semiconductor device according to claim 2, wherein: The structured extension includes a serrated extension configured to increase a contact area between the structured extension and the conductive material.

11. The semiconductor device according to claim 1, wherein The contact extension has a thickness of 1 micrometer to 30 micrometers.

12. The semiconductor device according to claim 1, wherein The substrate is composed of gallium arsenide and is 10 microns to 200 microns thick, the epitaxial layer is composed of aluminum gallium arsenide and is 1 micron to 20 microns thick, the epitaxial contact is composed of gold and is 0.1 micron to 5 microns thick, the substrate contact is composed of gold and is 0.1 micron to 5 microns thick, and the contact extension is 1 micron to 25 microns thick.

13. The semiconductor device according to claim 12, wherein: The substrate is 100 microns thick, the epitaxial layer is 10 microns thick, the epitaxial contact is 0.1 microns thick, the substrate contact is 0.1 microns thick, and the contact extension is 20 microns thick.

14. The semiconductor device according to claim 1, wherein The semiconductor device is a vertical cavity surface emitting laser.

15. The semiconductor device according to claim 14, wherein: The epitaxial layer includes a distributed Bragg reflector and an active region, and the substrate, the epitaxial layer, the epitaxial contact, the substrate contact, and the submount are operable to generate light.

16. The semiconductor device according to claim 14, wherein: The vertical cavity surface emitting laser is a top emitting vertical cavity surface emitting laser.

17. The semiconductor device according to claim 14, wherein: The vertical cavity surface emitting laser is a bottom emitting vertical cavity surface emitting laser.

18. A semiconductor device array, the array comprising: a substrate having a first side and a second side opposite to each other; an epitaxial layer having opposing first and second sides, the first side of the epitaxial layer being adjacent to the first side of the substrate, wherein the first side of the substrate and the first side of the epitaxial layer are characterized by intrinsic stresses proximate the first side of the substrate and the first side of the epitaxial layer; a substrate contact adjacent the second side of the substrate; an epitaxial contact adjacent the second side of the epitaxial layer; a sub-mount mounted to a sub-mount contact by a conductive material, the sub-mount contact being the epitaxial contact or the substrate contact; The conductive material is characterized by a melting temperature, the conductive material being solid below the melting temperature; a front sub-mount contact, the front sub-mount contact being the epitaxial contact or the substrate contact not associated with the sub-mount contact; a contact extension abutting the front submount contact; wherein the contact extension is operable to counteract intrinsic stress near the first side of the substrate and the first side of the epitaxial layer, thereby making the semiconductor device planar above a melting temperature of the conductive material; and wherein intrinsic stress within the contact extension is caused by processing parameters during electrodeposition of the contact extension, and wherein the intrinsic stress within the contact extension is adjusted to counteract intrinsic stress near the first side of the substrate and the first side of the epitaxial layer; and A plurality of isolation components are located in the epitaxial layer, and the plurality of isolation components divide the semiconductor devices in the semiconductor device array.

19. The semiconductor device array according to claim 18, wherein: The conductive material is operable to fix the array of semiconductor devices in a planar form below the melting temperature of the conductive material.

20. The semiconductor device array of claim 18, further comprising a structured extension adjacent to the submount contact.

21. The semiconductor device array according to claim 20, wherein: The conductive material and the structured extensions are operable to fix the array of semiconductor devices in a planar form below the melting temperature of the conductive material.

22. The semiconductor device array according to claim 21, wherein: The structured extension includes a serrated extension configured to increase a contact area between the structured extension and the conductive material.

23. The semiconductor device array according to claim 18, wherein: The contact extension is composed of the same material as the front submount contact and the contact extension is characterized by the same microstructure as the front submount contact.

24. The semiconductor device array according to claim 18, wherein: The contact extension is composed of the same material as the front submount contact and is characterized by a different microstructure than the front submount contact.

25. The semiconductor device array according to claim 24, wherein: The contact extension is characterized by a crystalline or polycrystalline microstructure and the front submount contact is characterized by an amorphous microstructure.

26. The semiconductor device array according to claim 18, wherein: The isolation features within the epitaxial layer include a dielectric material.

27. The semiconductor device array according to claim 26, wherein: The dielectric material is aluminum oxide.

28. The semiconductor device array according to claim 18, wherein: The isolation feature in the epitaxial layer A portion of the epitaxial layer is included that is characterized by damage caused by ion bombardment.

29. The semiconductor device array according to claim 18, wherein: The plurality of isolation features within the epitaxial layer include removed portions of the epitaxial layer, the removed portions forming mesa structures, wherein each mesa structure partitions one of the semiconductor devices within the array of semiconductor devices.

30. The semiconductor device array according to claim 18, wherein: The intrinsic stress near the first side of the substrate and the first side of the epitaxial layer is due to a lattice parameter misalignment between the substrate and the epitaxial layer and / or a thermal expansion coefficient misalignment between the substrate and the epitaxial layer.

31. The semiconductor device array according to claim 18, wherein: The semiconductor device is a vertical cavity surface emitting laser.

32. The semiconductor device array according to claim 31, wherein: The vertical cavity surface emitting laser is a top emitting vertical cavity surface emitting laser.

33. The semiconductor device array according to claim 31, wherein: The vertical cavity surface emitting laser is a bottom emitting vertical cavity surface emitting laser.

34. A method of manufacturing a semiconductor device, the method comprising: mounting a component to a component holder, the component comprising a base plate having opposing first and second sides; and an epitaxial layer having opposing first and second sides, the first side of the epitaxial layer abutting the first side of the substrate and the second side of the substrate abutting the component holder; depositing an epitaxial contact onto the second side of the epitaxial layer; depositing a contact extension onto the epitaxial contact; mounting the assembly, the epitaxial contact, and the contact extension onto a suction cup such that the epitaxial layer, the epitaxial contact, and the contact extension are adjacent to the suction cup; removing the component, the extension contact, the contact extension, and the suction cup from the component holder; removing a portion of the substrate from the second side of the substrate; depositing a substrate contact onto the second side of the substrate; positioning the substrate contact, the assembly, the epitaxial contact, the contact extension, and the suction cup on a submount such that the submount is adjacent to the second side of the substrate and the substrate contact, the submount being positioned by conductive material between portions of the substrate contact and the submount; heating the submount, the substrate contact, the assembly, the epitaxial contact, the contact extension, the chuck, and the conductive material to an elevated temperature at or above a melting temperature of the conductive material; cooling the submount, the substrate contact, the assembly, the epitaxial contact, the contact extension, the chuck, and the conductive material to a temperature below the elevated temperature; removing the submount, the substrate contact, the assembly, the epitaxial contact, the contact extension, and the conductive material from the chuck; as well as cutting the submount, the substrate contacts, the assembly, the epitaxial contacts, the contact extensions, and the conductive material into a plurality of semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices; wherein the contact extension is operable to counteract intrinsic stress near the first side of the substrate and the first side of the epitaxial layer, thereby making the semiconductor device planar above a melting temperature of the conductive material; and wherein the intrinsic stress within the contact extension is caused by processing parameters during electrodeposition of the contact extension, and wherein the intrinsic stress within the contact extension is adjusted to offset intrinsic stress near the first side of the substrate and the first side of the epitaxial layer.

35. The method of claim 34, further comprising depositing a structured extension onto the substrate contact.

36. The method of claim 34, wherein: Mounting the assembly, the epitaxial contact, and the contact extension onto a chuck includes depositing an organic compound between the chuck and the epitaxial layer, the epitaxial contact, and the contact extension.

37. The method of claim 34, wherein: Depositing the contact extension includes depositing the contact extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

38. The method of claim 35, wherein: Depositing the structured extension includes depositing the structured extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

39. The method of claim 34, wherein: Depositing the epitaxial contact and / or the substrate contact includes depositing the contacts by electrodeposition, physical vapor deposition or chemical vapor deposition.

40. A method of manufacturing a semiconductor device, the method comprising: mounting a component to a component holder, the component comprising a base plate having opposing first and second sides; and an epitaxial layer having opposing first and second sides, the first side of the epitaxial layer abutting the first side of the substrate and the second side of the epitaxial layer abutting the component holder; depositing a substrate contact onto the second side of the epitaxial layer; depositing a contact extension onto the substrate contact; mounting the assembly, the substrate contact, and the contact extension onto a suction cup such that the substrate, the substrate contact, and the contact extension are adjacent to the suction cup; removing the component, the substrate contact, the contact extension, and the suction cup from the component holder; depositing an epitaxial contact onto the second side of the epitaxial layer; positioning the epitaxial contact, the assembly, the substrate contact, the contact extension, and the suction cup on a submount such that the submount is adjacent to the second side of the epitaxial layer and the epitaxial contact, the submount being positioned by conductive material between the epitaxial contact and portions of the submount; heating the submount, the epitaxial contacts, the assembly, the substrate contacts, the contact extensions, the chuck, and the conductive material to an elevated temperature at or above a melting temperature of the conductive material; cooling the submount, the epitaxial contacts, the assembly, the substrate contacts, the contact extensions, the chuck, and the conductive material to a temperature below the elevated temperature; removing the submount, the epitaxial contacts, the assembly, the substrate contacts, the contact extensions, and the conductive material from the suction cup; as well as cutting the submount, the epitaxial contacts, the assembly, the substrate contacts, the contact extensions, and the conductive material into a plurality of semiconductor devices, an array of semiconductor devices, or a plurality of arrays of semiconductor devices; wherein the contact extension is operable to counteract intrinsic stress near the first side of the substrate and the first side of the epitaxial layer, thereby making the semiconductor device planar above a melting temperature of the conductive material; and wherein the intrinsic stress within the contact extension is caused by processing parameters during electrodeposition of the contact extension, and wherein the intrinsic stress within the contact extension is adjusted to offset intrinsic stress near the first side of the substrate and the first side of the epitaxial layer.

41. The method of claim 40, further comprising: A structured extension is deposited onto the epitaxial contact.

42. The method of claim 40, wherein: Mounting the assembly, the substrate contact, and the contact extension onto a chuck includes depositing an organic compound between the chuck and the substrate, the substrate contact, and the contact extension.

43. The method of claim 40, wherein: Depositing the contact extension includes depositing the contact extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

44. The method of claim 41, wherein: Depositing the structured extension includes depositing the structured extension by electrodeposition, physical vapor deposition, or chemical vapor deposition.

45. The method of claim 40, wherein: Depositing the epitaxial contact and / or the substrate contact includes depositing the contacts by electrodeposition, physical vapor deposition or chemical vapor deposition.

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