Semiconductor equipment and imaging equipment

Abstract

A semiconductor device suitable for a highly integrated structure is provided. The semiconductor device has: a transistor having a gate portion, a first diffusion layer, and a second diffusion layer; a first conductive portion; a second conductive portion electrically insulated from the first conductive portion; a first memory element located between the first diffusion layer and the first conductive portion and electrically connected to the first diffusion layer and the first conductive portion; and a second memory element located between the second diffusion layer and the second conductive portion and electrically connected to the second diffusion layer and the second conductive portion.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a transistor and a memory element, and an imaging device including the semiconductor device. Background Art

[0002] For semiconductor integrated circuits including CMOS (complementary metal oxide semiconductor) transistors, higher integration and higher operating speed thereof have been studied. In recent years, from the viewpoint of low power consumption, switching from volatile memory to nonvolatile memory has been studied, and for example, development of MRAM (magnetoresistive random access memory) has been proposed (for example, see PTL 1).

[0003] Reference List

[0004] Patent Literature

[0005] PTL 1: International Publication No. WO 2007 / 066407 Summary of the invention

[0006] Incidentally, it is expected that a semiconductor device including the semiconductor integrated circuit will be more highly integrated. Therefore, it is desirable to provide a semiconductor device having a structure suitable for higher integration, and an imaging device including the semiconductor device.

[0007] A semiconductor device as an embodiment of the present disclosure includes: a transistor including a gate portion, a source portion, and a drain portion; a first conductive portion; a second conductive portion electrically insulated from the first conductive portion; a first storage element located between the source portion and the first conductive portion and electrically coupled to each of the source portion and the first conductive portion; and a second storage element located between the drain portion and the second conductive portion and electrically coupled to each of the drain portion and the second conductive portion. Further, an imaging device as an embodiment of the present disclosure includes the semiconductor device described above.

[0008] In the semiconductor device and imaging device as an embodiment of the present disclosure, the first storage element is coupled to the source portion of the transistor, and the second storage element is coupled to the drain portion of the transistor. Thus, for example, the entire occupied area is smaller than when the first storage element and the second storage element are coupled to the source portion.

[0009] The semiconductor device and the imaging device as the embodiments of the present disclosure are suitable for higher integration. It should be noted that the effects of the present disclosure are not limited thereto, and may be any of the effects described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] [ Figure 1A ] Figure 1A is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present disclosure.

[0011] [ Figure 1B ] Figure 1B It is shown Figure 1A 1 is a plan view of a configuration example of a semiconductor device shown in FIG.

[0012] [ Figure 1C ] Figure 1C It is shown Figure 1A Another plan view of the configuration example of the semiconductor device shown in FIG.

[0013] [ Figure 1D ] Figure 1D yes Figure 1A A circuit diagram of a semiconductor device is shown in FIG.

[0014] [ Figure 2 ] Figure 2 It is shown Figure 1A A cross-sectional view of an embodiment of a configuration of a storage portion of a storage element is shown in FIG.

[0015] [ Figure 3 ] Figure 3 It is shown Figure 2 A cross-sectional view of an embodiment of the configuration of each layer of the storage portion is shown.

[0016] [ Figure 4A ] Figure 4A It describes writing the first information into Figure 1A An explanatory diagram of a method in a first storage element of a semiconductor device shown in FIG.

[0017] [ Figure 4B ] Figure 4B It describes writing the second information into Figure 1A An explanatory diagram of a method in a first storage element of a semiconductor device shown in FIG.

[0018] [ Figure 4C ] Figure 4C It describes writing the first information into Figure 1A 0 is an explanatory diagram of a method in a second storage element of a semiconductor device shown in FIG.

[0019] [ Figure 4D ] Figure 4D It describes writing the second information into Figure 1A 0 is an explanatory diagram of a method in a second storage element of a semiconductor device shown in FIG.

[0020] [ Figure 5A ] Figure 5A is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment of the present disclosure.

[0021] [ Figure 5B ] Figure 5B It is shown Figure 5A1 is a plan view of a configuration example of a semiconductor device shown in FIG.

[0022] [ Figure 5C ] Figure 5C It is shown Figure 5A Another plan view of the configuration example of the semiconductor device shown in FIG.

[0023] [ Fig. 6A ] Fig. 6A is a perspective view showing a configuration example of a semiconductor device according to a third embodiment of the present disclosure.

[0024] [ Figure 6B ] Figure 6B It is shown Fig. 6A 2 is a cross-sectional view of a configuration example of a semiconductor device shown in FIG.

[0025] [ Figure 6C ] Figure 6C It is shown Fig. 6A 0 is a cross-sectional view of a modified example of the semiconductor device shown in FIG.

[0026] [ Fig. 7A ] Fig. 7A is a perspective view schematically showing an imaging device as an application example of a semiconductor device including the present disclosure.

[0027] [ Figure 7B ] Figure 7B It is shown Fig. 7A A cross-sectional view of a configuration example of an imaging device is shown in FIG.

[0028] [ Fig. 8A ] Fig. 8A is a cross-sectional view showing a configuration example of a semiconductor device as a reference example.

[0029] [ Figure 8B ] Figure 8B is shown as Fig. 8A 2 is a plan view of a semiconductor device of a reference example shown in FIG.

[0030] [ Fig.9A ] Fig.9A is an explanatory diagram for describing a method of writing second information into a first storage element of a semiconductor device as another modification example of the present disclosure.

[0031] [ Fig. 9B ] Fig. 9B is an explanatory diagram for describing a method of writing first information into a first storage element of a semiconductor device as another modification example of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0033] 1. First Embodiment (Semiconductor Device Including Two Memory Elements on Backside of Semiconductor Substrate)

[0034] 2. Second Embodiment (Semiconductor Device Including Two Memory Elements on the Front Side of Semiconductor Substrate)

[0035] 3. Third Embodiment (Semiconductor Device Including Two Memory Elements on the Backside of Fin-Shaped Semiconductor Layer)

[0036] 4. Application examples (imaging devices including semiconductor devices and sensor devices bonded together)

[0037] 5. Other variations

[0038] <1. First Embodiment>

[0039] [Configuration of Semiconductor Device 1]

[0040] Figure 1A 1 shows a cross-sectional configuration of a semiconductor device 1 as a first embodiment of the present disclosure. Figure 1B and Figure 1C 1 shows a planar configuration of the semiconductor device 1. It should be noted that Figure 1B 1 shows a planar configuration of the semiconductor device 1 when viewed from a main surface 10A side of a semiconductor substrate 10 described later, and Figure 1C 1 shows a planar configuration of the semiconductor device 1 when viewed from the back side 10B of the semiconductor substrate 10 described later. Figure 1A Along with Figure 1B and Figure 1C The cross-sectional views shown in each figure correspond to the section line IA-IA. Figure 1D is a circuit diagram of the semiconductor device 1 .

[0041] like Figures 1A to 1D As shown in , the semiconductor device 1 includes a transistor 20, a bit line BL1 as a first conductive portion, a bit line BL2 as a second conductive portion electrically insulated from the bit line BL1, a storage element 30A as a first storage element, and a storage element 30B as a second storage element. The transistor 20 includes a gate electrode 21 as a gate portion, a diffusion layer 22S as a source portion, and a diffusion layer 22D as a drain portion. The storage element 30A is located between the diffusion layer 22S and the bit line BL1, and is electrically coupled to each of the diffusion layer 22S and the bit line BL1. The storage element 30B is located between the diffusion layer 22D and the bit line BL2, and is electrically coupled to each of the diffusion layer 22D and the bit line BL2. Further, for example, the gate electrode 21, the bit line BL1, and the bit line BL2 each include a highly conductive material such as copper (Cu) and extend along the Y-axis direction (see Figure 1B ).

[0042] The semiconductor device 1 further includes a selection line SL2 as a third conductive portion and a selection line SL1 as a fourth conductive portion. The selection line SL2 is disposed opposite to the storage element 30A and electrically coupled to the diffusion layer 22S as viewed from the diffusion layer 22S. The selection line SL1 is disposed opposite to the storage element 30B and electrically coupled to the diffusion layer 22D as viewed from the diffusion layer 22D. Further, for example, like the gate electrode 21, the bit line BL1, and the bit line BL2, the selection line SL2 and the selection line SL1 also include a highly conductive material such as copper (Cu) and extend along the Y-axis direction (see FIG. 2 ). Figure 1C ).

[0043] For example, the semiconductor device 1 is a device in which a multilayer wiring forming portion 40, an interlayer insulating layer 27, an interlayer insulating layer 26, a semiconductor substrate 10, and an insulating layer 60 are stacked in order on a supporting substrate 50. The transistor 20 is arranged close to the main surface (front side) 10A of the semiconductor substrate 10. The storage element 30A and the storage element 30B are arranged on the back side 10B of the semiconductor substrate 10 by inserting the insulating layer 60 between the semiconductor substrate 10 and the storage elements 30A and 30B. It should be noted that the number of transistors 20 arranged on the semiconductor substrate 10 is not particularly limited. The number of transistors 20 may be one, or may be two or more.

[0044] The semiconductor substrate 10 includes an element region R1 in which a portion of the transistor 20 is disposed and an isolation region R2 surrounding the element region R1. In the isolation region R2 of the semiconductor substrate 10, for example, an element isolation layer 11 formed by STI (shallow trench isolation) is disposed. For example, the element isolation layer 11 is an insulating layer including a silicon oxide film (SiO2), and one surface thereof is exposed in the main surface 10A of the semiconductor substrate 10.

[0045] For example, a portion of the semiconductor substrate 10 occupying the element region R1 includes single crystal silicon having a channel region and a pair of diffusion layers 22S and 22D constituting a portion of the transistor 20 formed thereon.

[0046] The back surface 10B of the semiconductor substrate 10 is covered with an insulating layer 60. The memory elements 30A and 30B are provided on the surface of the insulating layer 60 opposite to the surface thereof in contact with the back surface 10B, that is, on the upper surface 60S of the insulating layer 60.

[0047] The element region R1 is further provided with a contact plug P1 as a first connection portion and a contact plug P2 as a second connection portion, and the contact plug P1 and the contact plug P2 each extend to penetrate the insulating layer 60. For example, the contact plug P1 and the contact plug P2 include a material mainly containing a low-resistance metal such as Cu (copper), W (tungsten), or aluminum (Al). Further, around the low-resistance metal, a barrier metal layer including a single substance Ti (titanium) or Ta (tantalum) or an alloy thereof may be provided. The contact plug P1 and the contact plug P2 are each surrounded by the insulating layer 60 and electrically isolated from each other. The lower end of the contact plug P1 contacts the silicide region 25S described later, and the upper end of the contact plug P1 contacts the storage element 30A. The lower end of the contact plug P2 contacts the silicide region 25D described later, and the upper end of the contact plug P2 contacts the storage element 30B. Therefore, the memory element 30A is electrically coupled to the silicide region 25S of the source region through the contact plug P1, and the memory element 30B is electrically coupled to the silicide region 25D of the drain region through the contact plug P2. It should be noted that, for example, the contact plugs P1 and P2 are shaped to gradually become larger in the occupied area from the silicide regions 25S and 25D toward the memory elements 30A and 30B.

[0048] For example, the transistor 20 is a transistor for selecting between the memory elements 30A and 30B and is a planar transistor including a gate electrode 21 and a pair of diffusion layers 22S and 22D serving as a source region and a drain region. The gate electrode 21 is coupled to the word line WL of the memory elements 30A and 30B.

[0049] The gate electrode 21 is provided on the main surface 10A of the semiconductor substrate 10. However, a gate insulating film 23 including a silicon oxide film or the like is provided between the gate electrode 21 and the semiconductor substrate 10. For example, a side wall 24 including a stacked film of a silicon oxide film 24A and a silicon nitride film 24B is provided on the side surface of the gate electrode 21.

[0050] For example, the pair of diffusion layers 22S and 22D include silicon with impurities diffused therein. Specifically, the diffusion layer 22S corresponds to the source region, and the diffusion layer 22D corresponds to the drain region. The pair of diffusion layers 22S and 22D are arranged across the channel region of the semiconductor substrate 10 opposite to the gate electrode 21. The corresponding portions of the diffusion layers 22S and 22D are provided with silicide regions 25S and 25D including metal silicides such as NiSi (nickel silicide) or CoSi (cobalt silicide). The silicide regions 25S and 25D reduce the contact resistance between the connection layers 28A to 28D described later and the diffusion layers 22S and 22D. One surface of each silicide region in the silicide regions 25S and 25D is exposed to the main surface 10A of the semiconductor substrate 10, and the other surface thereof opposite to the one surface is covered with an insulating layer 60. Further, it is desirable that the diffusion layers 22S and 22D and the silicide regions 25S and 25D are all smaller in thickness than the element isolation layer 11 .

[0051] The word line WL and the selection lines SL1 and SL2 are embedded in the interlayer insulating layer 27. Further, the connection layers 28A to 28C are arranged to penetrate the interlayer insulating layers 26 and 27. Here, the gate electrode 21 is coupled to the word line WL via the connection layer 28C. The silicide region 25S of the diffusion layer 22S used as the source region is coupled to the selection line SL2 via the connection layer 28A as the source electrode. Further, the silicide region 25D of the diffusion layer 22D used as the drain region is coupled to the selection line SL1 via the connection layer 28B as the drain electrode. The connection layer 28A is a specific embodiment corresponding to the "third connection portion" of the present disclosure, and the connection layer 28B is a specific embodiment corresponding to the "fourth connection portion" of the present disclosure. It should be noted that the selection line SL2 is coupled to the via V1 of the wiring line group 40A described later, and the selection line SL1 is coupled to the via V1 of the wiring line group 40B described later.

[0052] For example, the multilayer wiring forming part 40 includes a stack of an interlayer insulating layer 41, an interlayer insulating layer 42, an interlayer insulating layer 43, and an interlayer insulating layer 44 in ascending order of distance from the transistor 20 by means of the wiring line groups 40A and 40B arranged therein. The wiring line groups 40A and 40B have a structure in which a metal layer M1, a metal layer M2, a metal layer M3, and a metal layer M4 are stacked. Here, the metal layer M1 is embedded in the interlayer insulating layer 41, the metal layer M2 is embedded in the interlayer insulating layer 42, the metal layer M3 is embedded in the interlayer insulating layer 43, and the metal layer M4 is embedded in the interlayer insulating layer 44. The wiring line groups 40A and 40B further include vias V1 to V4. The metal layer M1 and the metal layer M2 are coupled to each other by the via V2 penetrating the interlayer insulating layer 42. Likewise, the metal layer M2 and the metal layer M3 are coupled to each other through the via V3 penetrating the interlayer insulating layer 43, and the metal layer M3 and the metal layer M4 are coupled to each other through the via V4 penetrating the interlayer insulating layer 44. As described above, the wiring line group 40A is coupled to the silicide region 25S of the diffusion layer 22S used as the source region through the via V1, the selection line SL2, and the connection layer 28A. Further, the wiring line group 40B is coupled to the silicide region 25D of the diffusion layer 22D used as the drain region through the via V1, the selection line SL1, and the connection layer 28B. It should be noted that Figure 1A The configuration of the multilayer wiring forming section 40 shown in FIG. 4 is an embodiment and is not limiting.

[0053] The multilayer wiring forming part 40 is bonded to the support substrate 50. For example, the support substrate 50 is a substrate including single crystal silicon. It should be noted that the material of the support substrate 50 is not particularly limited. Instead of single crystal silicon, the support substrate 50 may include another material such as SiO2 or glass.

[0054] As described above, the insulating layer 60 is provided to cover the semiconductor substrate 10. The insulating layer 60 may have a stacked structure of a first layer, a second layer, and a third layer, the first layer including, for example, a high-K (high dielectric constant) film that can be formed at a low temperature, that is, Hf oxide, Al2O3, Ru (ruthenium) oxide, Ta oxide, an oxide containing Al, Ru, Ta, or Hf, and Si, a nitride containing Al, Ru, Ta, or Hf, and Si, an oxynitride containing Al, Ru, Ta, or Hf, and Si, etc., the second layer including, for example, SiO2, and the third layer including a material having a relative dielectric constant (low-K) lower than that of SiO2.

[0055] The storage element 30A and the storage element 30B have a stacked structure, that is, in which, for example, a conductive layer 31 as a lower electrode, a storage portion 32, and a conductive layer 33 as an upper electrode are stacked in this order. The conductive layer 31 of the storage element 30A is coupled to the silicide region 25S through the contact plug P1. The conductive layer 31 of the storage element 30B is coupled to the silicide region 25D through the contact plug P2.

[0056] The back interlayer film 71 is provided around the storage element 30A and the storage element 30B. Examples of the material of the back interlayer film 71 include SiO2, a low-K (low dielectric constant) film, etc. The upper surface of the conductive layer 33 in the storage element 30A contacts the lower surface of the bit line BL1, and the upper surface of the conductive layer 33 in the storage element 30B contacts the lower surface of the bit line BL2. The insulating layer 72 is filled around the bit line BL1 and the bit line BL2.

[0057] For example, the storage unit 32 in the storage element 30 is preferably a spin-injection magnetization-reversal storage element (STT-MTJ: spin transfer torque-magnetic tunnel junction) that stores information by reversing the magnetization direction of a storage layer described later by spin injection. The STT-MTJ can achieve high-speed reading and writing, and is therefore expected to be a non-volatile memory that replaces volatile memory.

[0058] For example, the conductive layer 31 and the conductive layer 33 include metal materials such as Cu, Ti, W, or Ru. The conductive layer 31 and the conductive layer 33 preferably mainly include Cu, Al, or W, that is, metals other than the constituent materials of the bottom layer 32A or the cap layer 32E described later. Further, the conductive layer 31 and the conductive layer 33 may also include Ti, TiN (titanium nitride), Ta, TaN (tantalum nitride), W, Cu, or Al, or a stacked structure thereof.

[0059] Figure 2 An embodiment of the configuration of the storage unit 32 is shown. The storage unit 32 has a configuration in which, for example, there are a bottom layer 32A, a magnetization fixed layer 32B, an insulating layer 32C, a storage layer 32D, and a cap layer 32E stacked in ascending order of distance from the conductive layer 31. That is, the storage element 30 has a bottom fixed structure including the magnetization fixed layer 32B, the insulating layer 32C, and the storage layer 32D in the order from bottom to top in the stacking direction. Information is stored by changing the orientation of the magnetization M32D of the storage layer 32D using uniaxial anisotropy. Information "0" or "1" is defined by the relative angle (parallel or antiparallel) between the magnetization M32D of the storage layer 32D and the magnetization M32B of the magnetization fixed layer 32B.

[0060] The bottom layer 32A and the cap layer 32E include a metal film such as Ta or Ru, or a stacked film thereof.

[0061] The magnetization fixed layer 32B is a reference layer used as a reference (magnetization direction) of the storage information of the storage layer 32D, and includes a ferromagnetic substance having a magnetic moment that fixes the direction of the magnetization M32B in a direction perpendicular to the film surface. For example, the magnetization fixed layer 32B includes Co-Fe-B.

[0062] It is desirable to change the direction of the magnetization M32B of the magnetization fixed layer 32B by reading and writing, however, it does not always need to be fixed in a specified direction. One of the reasons for this is that the direction of the magnetization M32B of the magnetization fixed layer 32B only needs to be less likely to change compared to the direction of the magnetization M32D of the storage layer 32D. For example, the magnetization fixed layer 32B only needs to have a higher coercive force and a larger magnetic film thickness or have a larger magnetic damping constant than the storage layer 32D. In order to fix the direction of the magnetization M32B, for example, it is sufficient to set an antiferromagnetic substance such as PtMn or IrMn in contact with the magnetization fixed layer 32B. Alternatively, the direction of the magnetization M32B can be directly fixed by magnetically coupling the magnetic substance in contact with the antiferromagnetic substance and the magnetization fixed layer 32B through a non-magnetic substance such as Ru.

[0063] The insulating layer 32C is an intermediate layer used as a tunnel barrier layer (tunnel insulating layer) and includes, for example, aluminum oxide or magnesium oxide (MgO). Among them, the insulating layer 32C preferably includes magnesium oxide. This can increase the magnetoresistance change rate (MR ratio) and improve the efficiency of spin injection, thereby making it possible to reduce the current density for reversing the orientation of the magnetization M32D of the storage layer 32D.

[0064] The memory layer 32D includes a ferromagnetic substance having a magnetic moment that allows the direction of the magnetization M32D to be freely changed to a direction perpendicular to the film surface. For example, the memory layer 32D includes Co-Fe-B.

[0065] Figure 3An embodiment of the configuration of each layer in the storage section 32 is shown in more detail. The bottom layer 32A has a configuration in which, for example, a Ta layer having a thickness of 3 nm and a Ru film having a thickness of 25 nm are stacked in ascending order of distance from the conductive layer 31. The magnetization fixed layer 32B has a configuration in which, for example, a Pt layer having a thickness of 5 nm, a Co layer having a thickness of 1.1 nm, a Ru layer having a thickness of 0.8 nm, and a (Co20Fe80)80B20 layer having a thickness of 1 nm are stacked in ascending order of distance from the conductive layer 31. The insulating layer 32C has a configuration in which, for example, a Mg layer having a thickness of 0.15 nm, a MgO layer having a thickness of 1 nm, and a Mg layer having a thickness of 0.15 nm are stacked in ascending order of distance from the conductive layer 31. For example, the storage layer 32D has a thickness t of 1.2 to 1.7 nm and includes a (Co20Fe80)80B20 layer. The cap layer 32E has a configuration in which, for example, there are a Ta layer having a thickness of 1 nm, a Ru layer having a thickness of 5 nm, and a Ta layer having a thickness of 3 nm stacked in ascending order of distance from the conductive layer 31 .

[0066] The semiconductor device 1 further includes a controller CTRL ( Figure 1D ). The controller CTRL controls the potential of each of the selection line SL1, the selection line SL2, the bit line BL1, the bit line BL2, and the word line WL.

[0067] [Operation of Semiconductor Device 1]

[0068] In the semiconductor device 1, information is written into the storage layer 32D of the storage element 30A and the storage layer 32D of the storage element 30B according to the order of magnitude relationship between the respective potentials of the selection line SL1, the selection line SL2, the bit line BL1, the bit line BL2, and the word line WL. The potential of each of the selection line SL1, the selection line SL2, the bit line BL1, the bit line BL2, and the word line WL is controlled by the controller CTRL ( Figure 1D ).

[0069] Specifically, for example, Figure 4A As shown in FIG. 1 , the controller CTRL sets the potential of the bit line BL1 to a first potential (eg, low), and sets the potential of the selection line SL1 to a second potential (eg, high) higher than the first potential. This causes the electrons e -Flows in the direction of the arrow, and thereby writes the first information "1" into the storage layer 32D of the storage element 30A. At this time, the controller CTRL sets the potential of the gate potential 21 (i.e., the word line WL) to the second potential, and keeps the potential of the bit line BL2 and the potential of the selection line SL2 at a third potential that is independent of the potential of the bit line BL1, the potential of the selection line SL1, and the potential of the word line WL. That is, the controller CTRL causes the potential of the bit line BL2 and the potential of the selection line SL2 to enter a floating state. The controller CTRL can cause the high impedance circuit (Hi-Z circuit) included therein to perform floating control on the potential of the bit line BL2 and the potential of the selection line SL2.

[0070] For example, Figure 4B As shown in FIG. 1 , the controller CTRL sets the potential of the bit line BL1 to the second potential and sets the potential of the selection line SL1 to the first potential. This causes the electrons e - Flows in the direction of the arrow, and thereby writes the second information "0" into the storage layer 32D of the storage element 30A. In addition, in this case, the controller CTRL sets the potential of the gate electrode 21 (i.e., the word line WL) to the second potential, and keeps the potential of the bit line BL2 and the potential of the selection line SL2 at a third potential that is independent of the potential of the bit line BL1, the potential of the selection line SL1, and the potential of the word line WL. That is, the controller CTRL causes the potential of the bit line BL2 and the potential of the selection line SL2 to enter a floating state.

[0071] For example, Figure 4C As shown in FIG. 1 , the controller CTRL sets the potential of the bit line BL2 to the first potential and the potential of the selection line SL2 to the second potential. This causes the electrons e - Flow in the direction of the arrow, and thereby write the first information "1" into the storage layer 32D of the storage element 30B. In this case, the potential of the gate potential 21 (i.e., the word line WL) is set to the second potential, and the potential of the bit line BL1 and the potential of the selection line SL1 are kept at a fourth potential that is independent of the potential of the bit line BL2, the potential of the selection line SL2, and the potential of the word line WL. That is, the controller CTRL keeps the potential of the bit line BL1 and the potential of the selection line SL1 in a floating state.

[0072] For example, Figure 4D As shown in FIG. 1 , the controller CTRL sets the potential of the bit line BL2 to the second potential and sets the potential of the selection line SL2 to the first potential. This causes the electrons e -Flows in the direction of the arrow, and thereby writes the second information "0" into the storage layer 32D of the storage element 30B. In addition, in this case, the potential of the gate electrode 21 (i.e., the word line WL) is set to the second potential, and the potential of the bit line BL1 and the potential of the selection line SL1 are kept at the fourth potential. That is, the controller CTRL keeps the potential of the bit line BL1 and the potential of the selection line SL1 in a floating state.

[0073] According to the order of magnitude relationship between the respective potentials of the selection line SL1, the selection line SL2, the bit line BL1, the bit line BL2, and the word line WL, a current is applied in a direction perpendicular to the film surface of the memory portion 32, which causes a spin torque magnetization reversal to occur. Thus, writing of information is performed by making the orientation of the magnetization M32D of the memory layer 32D parallel or antiparallel to the magnetization M32B of the magnetization fixed layer 32B and thereby changing the resistance value of the memory portion 32 to high or low.

[0074] At the same time, a magnetic layer (not shown) used as an information reference is provided on the storage layer 32D with a thin insulating film interposed therebetween and a ferromagnetic tunnel current flowing via the insulating layer 32C is used so that information stored in the storage section 32 can be read out. Further, reading can also be performed by using a magnetoresistance effect.

[0075] [Function and Effect of Semiconductor Device 1]

[0076] In the semiconductor device 1, the storage element 30A is coupled to the source region of the transistor 20, and the storage element 30B is coupled to the drain region of the transistor 20. Thus, compared with the case where the storage element 30A and the storage element 30B are coupled to, for example, the source region, the area occupied by the entire semiconductor device 1 is smaller. Fig. 8A and Figure 8B In the semiconductor device 1001 of the reference example shown, two storage elements 1030A and 1030B located at the same level are coupled to the source region. In this case, a larger element region R1001 is required. It should be noted that Fig. 8A is a cross-sectional view showing a configuration example of a semiconductor device 1001 as a reference example. Figure 8B FIG. 1 shows a planar configuration example of the semiconductor device 1001. As viewed from the direction of the arrow, Fig. 8A Along with Figure 8B The cross section shown corresponds to the section line VIIIA-VIIIA.

[0077] In contrast, according to the semiconductor device 1 of the present embodiment, the transistor 20 and the storage elements 30A and 30B can be compactly arranged in the narrower element region R1. This makes it possible to accommodate more transistors 20 and more storage elements 30A and 30B in the limited area of ​​the semiconductor device 1 as a whole, thereby achieving higher integration. Further, for example, if the storage element 30A is used for reading and writing at normal times, and the storage element 30B is used for reading and writing in the event of any abnormality in the storage element 30A, redundancy can be achieved. That is, the operational reliability of the semiconductor device 1 can be improved. Moreover, in the semiconductor device 1 of the present embodiment, the storage elements 30A and 30B are arranged on the back side 10B of the semiconductor substrate 10, and therefore, it is possible to prevent the heat generated in the process of producing the transistor 20 or the wiring layer, for example, from affecting the storage elements 30A and 30B.

[0078] <2. Second Embodiment>

[0079] [Configuration of Semiconductor Device 2]

[0080] Figure 5A 2 shows a cross-sectional configuration of a semiconductor device 2 as a second embodiment of the present disclosure. Figure 5B and Figure 5C 2 shows a planar configuration of the semiconductor device 2. It should be noted that Figure 5B 1 shows a planar configuration of the semiconductor device 2 viewed from the main surface 10A side of the semiconductor substrate 10, and Figure 5C FIG. 2 shows a planar configuration of the semiconductor device 2 viewed from the back surface 10B side of the semiconductor substrate 10. As viewed from the direction of the arrow, Figure 5A Along with Figure 5B and Figure 5C The cross-sectional view corresponds to the section line VA-VA shown in FIG.

[0081] In the semiconductor device 1 of the first embodiment described above, the memory element 30A and the memory element 30B are provided on the back surface 10B side of the semiconductor device 10 opposite to the main surface 10A on which the transistor 20 is provided in such a manner that the insulating layer 60 is interposed between the semiconductor substrate 10 and the memory elements 30A and 30B. In contrast, in the semiconductor device 2 according to the present embodiment, the memory element 30A and the memory element 30B are provided on the side of the main surface 10A of the semiconductor substrate 10 on which the transistor 20 is provided. In the following description and FIG. 5A to FIG. 5C Components corresponding to those of the semiconductor device 1 according to the first embodiment described above will be denoted by the same reference numerals.

[0082] Compared with the semiconductor device 1, in the semiconductor device 2 of the present embodiment, the corresponding positions where the storage element 30A and the selection line SL2 are provided are interchanged, and the corresponding positions where the storage element 30B and the selection line SL1 are provided are interchanged. Specifically, the selection line SL2 and the selection line SL1 are provided on the upper surface 60S of the insulating layer 60, the lower surface of the selection line SL2 is in contact with the contact plug P1, and the lower surface of the selection line SL1 is in contact with the contact plug P2. At the same time, the storage element 30A and the storage element 30B are embedded in the interlayer insulating layer 27, the storage element 30A is in contact with the lower surface of the connection layer 28A, and the storage element 30B is in contact with the lower surface of the connection layer 28B. Further, in the semiconductor device 2, the bit line BL1 is provided in the wiring line group 40A of the semiconductor device 1 instead of the metal layer M4, and the bit line BL2 is provided in the wiring line group 40B of the semiconductor device 1 instead of the metal layer M4. That is, the bit line BL1 and the bit line BL2 are disposed on the support substrate 50 , and upper surfaces thereof are in contact with the lower surface of the via hole V4 and embedded in the interlayer insulating layer 44 .

[0083] [Function and Effect of Semiconductor Device 2]

[0084] In addition, in this semiconductor device 2, an effect similar to that of the semiconductor device 1 according to the first embodiment described above is obtained. That is, in the semiconductor device 2, the storage element 30A is coupled to the source region of the transistor 20, and the storage element 30B is coupled to the drain region of the transistor 20. Thus, for example, compared with the case where the storage element 30A and the storage element 30B are coupled to the source region, the area occupied by the entire semiconductor device 2 is smaller, which makes it possible to accommodate more transistors 20 and more storage elements 30A and 30B in a narrower area, thereby enabling higher integration. Further, in the semiconductor device 2, the storage element 30A and the storage element 30B are arranged on one side of the main surface 10A on which the transistor 20 is arranged, and therefore, it is sufficient to arrange only the contact plugs P1 and P2 and the wiring lines such as the selection lines SL1 and SL2 on the back side 10B side. That is, the formation process on the back side 10B side can be simplified. Furthermore, in the semiconductor device 2 , the memory element 30A and the memory element 30B are embedded in the interlayer insulating layer 27 provided with the transistor 20 ; therefore, it is easier to reduce the overall thickness than in the semiconductor device 1 of the first embodiment described above.

[0085] <3. Third Embodiment>

[0086] [Configuration of Semiconductor Device 3]

[0087] Fig. 6A : is a perspective view showing the configuration of a semiconductor device 3 as a third embodiment of the present disclosure. Figure 6BThe configuration of the semiconductor device 3 is shown, and as viewed from the direction of the arrow, the Fig. 6A The cross section of the section line VIB-VIB shown in corresponds to the cross section of the section line VIB-VIB shown in . The semiconductor device 3 has a configuration similar to that of the semiconductor device 1, but, instead of the transistor 20, the semiconductor device 3 includes a transistor 80. The transistor 80 is embedded in an element forming layer 80A provided between the supporting substrate 50 and the semiconductor substrate 13 including, for example, silicon. The semiconductor substrate 13 has a front side 13A facing the element forming layer 80A and a back side 13B positioned opposite to the front side 13A. The transistor 80 is provided on the front side 13A of the semiconductor substrate 13. The storage elements 30A and 30B are provided on the back side 13B. In this embodiment, for the sake of description, components similar to those of the semiconductor device 1 according to the first embodiment described above are represented by the same reference numerals.

[0088] For example, transistor 80 is a fin field effect transistor (fin FET), including: fin 81, including Si; gate electrode 82G, source electrode 82S; and drain electrode 82D. Compared with a planar transistor on a bulk substrate, by using a fin FET, it becomes possible to suppress short channel characteristics. Gate electrode 82G also serves as word line WL of storage element 30A and storage element 30B.

[0089] The fin 81 has a flat plate shape and includes a plurality of fins arranged to stand on a semiconductor substrate 13 including, for example, silicon. For example, the plurality of fins 81 extend in the X-axis direction and are arranged in the Y-axis direction. Note that Fig. 6A and Figure 6B Only a single fin 81 is shown. For example, a cross section of the fin 81 perpendicular to the X-axis direction (i.e., a YZ cross section) has a trapezoidal shape. The gate electrode 82G, the source electrode 82S, and the drain electrode 82D each extend across the fin 81 in the Y-axis direction intersecting the extension direction of the fin 81. The gate electrode 82G, the source electrode 82S, and the drain electrode 82D each cover the surface of the fin 81 except the back side, i.e., the surface of the fin 81 in contact with the semiconductor substrate 13. Here, the upper end of the source electrode 82S is coupled to the selection line SL2, and the upper end of the drain electrode 82D is coupled to the selection line SL1. It should be noted that in Fig. 6A In the figure, illustrations of the selection lines SL1 and SL2 are omitted to prevent the drawing from being complicated.

[0090] Further, the fin 81 includes impurity diffusion regions 83S and 83D serving as a source region and a drain region near its back surface. The impurity diffusion region 83S is coupled to the memory element 30A through the contact plug P1, and the impurity diffusion region 83D is coupled to the memory element 30B through the contact plug P2.

[0091] [Function and Effect of Semiconductor Device 3]

[0092] Furthermore, in this semiconductor device 3 , effects similar to those of the semiconductor device 1 of the above-described first embodiment can be expected.

[0093] Further, in the present embodiment, the transistor 80, ie, a fin FET having a high current driving capability is mounted, and the transistor 80 is used as a transistor for selecting between the memory element 30A and the memory element 30B. This enables high-speed reading and writing of information.

[0094] [Configuration of Semiconductor Device 3A as Modification Example]

[0095] Figure 6C is a cross-sectional view showing the configuration of a semiconductor device 3A as a modification of the present embodiment and Figure 6B Corresponding. Fig. 6A and Figure 6B In the semiconductor device 3 of the third embodiment shown, the storage element 30A and the storage element 30B are provided on the back surface 13B side of the semiconductor substrate 13. In contrast, in the semiconductor device 3A as the present modification, the storage elements 30A and 30B are provided on the front surface 13A side of the semiconductor substrate 13. In addition, in this semiconductor device 3A, effects similar to those of the semiconductor device 3 of the third embodiment described above can be expected.

[0096] <4. Application Examples>

[0097] Fig. 7A There is shown a schematic configuration of an imaging device 101 in which the sensor device 100 and the semiconductor device 200 are bonded together. As the semiconductor device 200, the semiconductor devices 1 to 3 of the above-described first to third embodiments can be used.

[0098] For example, the imaging device 101 is a stacked image sensor device in which the sensor device 100 is stacked on the semiconductor device 200. The pixel portion 110 is formed in the sensor device 100. The semiconductor device 200 is provided with a logic circuit 210 and a memory portion 220.

[0099] In the pixel section 110 of the sensor device 100, unit pixels are arranged two-dimensionally and a back-side illumination imaging element (imaging element 110S, see Figure 2 ), a transfer transistor that transfers the charge obtained by the imaging element 110S through photoelectric conversion to the floating diffusion (FD) portion, a reset transistor that resets the potential of the FD portion, an amplification transistor that outputs a signal corresponding to the potential of the FD portion, etc.

[0100] The semiconductor device 200 is provided with a logic circuit 210 such as a control circuit that controls the operation of the imaging element 110S, and a nonvolatile storage element (storage elements 30A and 30B) included in the storage section 220. It should be noted that, for example, in addition to the logic circuit 210 and the storage section 220, the semiconductor device 200 may be equipped with a circuit having an image processing function, an ADC (Analog-Digital Converter) circuit that converts an analog signal output from a unit pixel provided from the pixel section into a digital signal and outputs the digital signal, and the like.

[0101] Figure 7B Shows Fig. 7A . The sensor device 100 in the imaging device 101 is provided with the imaging element 110S described above. For example, the imaging element 110S is an element in which a planarization layer 114, a color filter 115, and a microlens 116 are stacked in this order on a semiconductor substrate 113 in such a manner that a photodiode 113A and a transistor 113B are embedded therein. In the sensor device 100, a protective layer 117 is provided on the microlens 116 of the imaging element 110S, and a glass substrate 118 is provided on the protective layer 117. Further, the sensor device 100 includes a conductive film 111 containing Cu in its lowest layer (which faces the surface of the semiconductor device 200), and an insulating layer 112 occupying the periphery of the conductive film 111. The lower surface of the conductive film 111 is coupled to a connection layer P3 provided in the uppermost layer of the semiconductor device 200. For example, the connection layer P3 includes copper or the like, and an insulating layer 73 occupies the periphery thereof.

[0102] Since any of the semiconductor devices 1 to 3 of the above-described first to third embodiments is applied as the semiconductor device 200, Fig. 7A and Figure 7B The imaging device 101 shown in FIG. 1 allows higher integration to be achieved.

[0103] The present disclosure has been described above with reference to the embodiments and the like; however, the present disclosure is not limited to the above-described embodiments and may be modified in various ways.

[0104] For example, the above embodiment has been described with reference to the specific configurations of the transistors 20 and 80 and the memory elements 30A and 30B; however, it is not necessary to include all components, and may further include other components.

[0105] Further, the above first embodiment has been described with reference to an example in which the transistor 20 is an NMOS transistor; however, the present disclosure is not limited thereto and, for example, a PMOS transistor is applied. Fig.9A and Fig. 9BThe semiconductor device 1A shown in FIG. 1 includes a PMOS transistor 20A. In this case, for example, Fig.9A As shown in FIG. 1 , the potential of the bit line BL1 is set to a first potential (eg, low), and the potential of the selection line SL1 is set to a second potential (eg, high) higher than the first potential. This causes the electrons e - Flows in the direction of the arrow, and writes the second information "0" into the storage layer 32D of the storage element 30A. Fig. 9B As shown in FIG. 1 , if the potential of the bit line BL1 is set to the second potential and the potential of the selection line SL1 is set to the first potential, the electrons e - Flows in the direction of the arrow, and writes the first information “1” into the memory layer 32D of the memory element 30A.

[0106] Moreover, in the above-mentioned embodiments and the like, a storage element having a bottom fixed structure is described; however, the present technology may employ a storage element having a top fixed structure. As used herein, the top fixed structure refers to a structure in which a storage layer, an insulating layer, and a magnetization fixed layer are stacked in order from bottom to top in a stacking direction. It should be noted that in the case where the storage element has a top fixed structure, its behavior is opposite to that in the case where the storage element has a bottom fixed structure (the high and low written in the storage element are reversed).

[0107] It should be noted that the effects described here are only embodiments and the description thereof is non-limiting. Any other effects may also be achieved. Further, the present technology may have the following configurations.

[0108] (1) A semiconductor device comprising:

[0109] A transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

[0110] a first conductive portion;

[0111] a second conductive portion, electrically insulated from the first conductive portion;

[0112] a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

[0113] A second storage element is located between the second diffusion layer and the second conductive portion and is electrically coupled to each of the second diffusion layer and the second conductive portion.

[0114] (2) The semiconductor device according to (1), further comprising:

[0115] A third conductive portion, viewed from the first diffusion layer, is disposed opposite to the first memory element and is electrically coupled to the first diffusion layer; and

[0116] The fourth conductive portion is disposed opposite to the second memory element as viewed from the second diffusion layer and is electrically coupled to the second diffusion layer.

[0117] (3) The semiconductor device according to (1) or (2), wherein the gate portion, the first conductive portion, and the second conductive portion all extend along the first direction.

[0118] (4) The semiconductor device according to (2), wherein the gate portion and the first to fourth conductive portions all extend along the first direction.

[0119] (5) The semiconductor device according to any one of (1) to (4), further comprising a semiconductor substrate having a first surface on which the gate portion is provided and a second surface positioned opposite to the first surface, wherein

[0120] The first diffusion layer constitutes a portion of the semiconductor substrate close to the first surface; and

[0121] The second diffusion layer constitutes another portion of the semiconductor substrate close to the first surface.

[0122] (6) The semiconductor device according to (5), further comprising:

[0123] a first insulating layer covering the second surface of the semiconductor substrate; and

[0124] The first connecting portion and the second connecting portion each penetrate the first insulating layer; wherein,

[0125] The first memory element and the second memory element are each arranged opposite to the second surface as viewed from the first insulating layer;

[0126] The first storage element is electrically coupled to the first diffusion layer through the first connection portion; and

[0127] The second storage element is electrically coupled to the second diffusion layer through the second connection portion.

[0128] (7) The semiconductor device according to (6), further comprising:

[0129] a second insulating layer covering the first surface of the semiconductor substrate;

[0130] The third conductive portion and the fourth conductive portion are each disposed opposite to the second surface when viewed from the second insulating layer;

[0131] a third connection portion penetrating the second insulating layer and electrically coupling the first diffusion layer and the third conductive portion to each other; and

[0132] The fourth connecting portion penetrates the second insulating layer and electrically couples the second diffusion layer and the fourth conductive portion to each other.

[0133] (8) The semiconductor device according to (7), further comprising a controller that performs the following control:

[0134] The first information is written into the first memory element by setting the potential of the first conductive portion to a first potential, setting the potential of the fourth conductive portion to a second potential higher than the first potential, setting the potential of the gate portion to a second potential, and setting the potential of the second conductive portion and the potential of the third conductive portion to a third potential that is independent of the potential of the first conductive portion, the potential of the fourth conductive portion, and the potential of the gate portion; and

[0135] The potential of the first conductive portion is set to the second potential, the potential of the fourth conductive portion is set to the first potential, the potential of the gate portion is set to the second potential, and the potentials of the second conductive portion and the third conductive portion are set to the third potential, thereby writing the second information into the first storage element.

[0136] (9) The semiconductor device according to (8), wherein the controller includes a potential control circuit capable of maintaining the potential of the second conductive portion and the potential of the third conductive portion at the third potential.

[0137] (10) The semiconductor device according to (7), further comprising a controller that performs the following control:

[0138] The first information is written into the second storage element by setting the potential of the second conductive portion to a first potential, setting the potential of the third conductive portion to a second potential higher than the first potential, setting the potential of the gate portion to a second potential, and setting the potential of the first conductive portion and the potential of the fourth conductive portion to a fourth potential that is independent of the potential of the second conductive portion, the potential of the third conductive portion, and the potential of the gate portion; and

[0139] The potential of the second conductive portion is set to the second potential, the potential of the third conductive portion is set to the first potential, the potential of the gate portion is set to the second potential, and the potential of the first conductive portion and the potential of the fourth conductive portion are set to the fourth potential, thereby writing the second information into the second storage element.

[0140] (11) The semiconductor device according to (10), wherein the controller includes a potential control circuit capable of maintaining the potential of the first conductive portion and the potential of the fourth conductive portion at a fourth potential.

[0141] (12) The semiconductor device according to any one of (5) to (11), further comprising:

[0142] a first insulating layer covering a first surface of the semiconductor substrate;

[0143] The first connecting portion and the second connecting portion each penetrate the first insulating layer;

[0144] A third conductive portion is disposed opposite to the first surface as viewed from the first insulating layer and is electrically coupled to the first diffusion layer through the first connecting portion; and

[0145] The fourth conductive portion is disposed opposite to the first surface as viewed from the first insulating layer and is electrically coupled to the second diffusion layer through the second connecting portion.

[0146] (13) The semiconductor device according to (12), further comprising:

[0147] a second insulating layer covering the second surface of the semiconductor substrate; and

[0148] The third connecting portion and the fourth connecting portion each penetrate the second insulating layer; wherein,

[0149] The first conductive portion is disposed opposite to the second insulating layer as viewed from the first memory element and is electrically coupled to the first diffusion layer through the third connecting portion; and

[0150] The second conductive portion is disposed opposite to the second insulating layer as viewed from the second memory element and is electrically coupled to the second diffusion layer through the fourth connecting portion.

[0151] (14) The semiconductor device according to (1), further comprising a fin portion including a semiconductor material and extending in a second direction intersecting the first direction, wherein

[0152] The first storage element and the second storage element are each coupled to a back side of the fin; and

[0153] The gate portion, the first diffusion layer, and the second diffusion layer extend in a first direction and cover the surface except for the back surface of the fin portion.

[0154] (15) An imaging device comprising:

[0155] Semiconductor equipment; and

[0156] Imaging elements, stacked on semiconductor devices;

[0157] Semiconductor equipment includes:

[0158] A transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

[0159] a first conductive portion;

[0160] a second conductive portion, electrically insulated from the first conductive portion;

[0161] a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

[0162] A second storage element is located between the second diffusion layer and the second conductive portion and is electrically coupled to each of the second diffusion layer and the second conductive portion.

[0163] This application claims priority from Japanese Patent Application JP2018-39217 filed in the Japan Patent Office on Mar. 6, 2018, the entire contents of which are hereby incorporated by reference.

[0164] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and changes may be made according to design requirements and other factors as long as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A semiconductor device comprising: A transistor including a gate portion, a first diffusion layer, and a second diffusion layer; a first silicide region in contact with the first diffusion layer; a second silicide region in contact with the second diffusion layer; a first conductive portion; a second conductive portion, electrically insulated from the first conductive portion; a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion; a first insulating layer covering the second surface of the semiconductor substrate; as well as The first connecting portion and the second connecting portion each penetrate the first insulating layer, wherein The first storage element is electrically coupled to the first silicide region through the first connection portion; and The second storage element is electrically coupled to the second silicide region through the second connection portion, wherein The semiconductor device further comprises: a third conductive portion, which is disposed opposite to the first memory element and electrically coupled to the first diffusion layer as viewed from the first diffusion layer; and a fourth conductive portion, which is disposed opposite to the second storage element and electrically coupled to the second diffusion layer when viewed from the second diffusion layer, The semiconductor device further includes a controller that performs the following control: The potential of the first conductive portion is set to a first potential, the potential of the fourth conductive portion is set to a second potential higher than the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to a third potential that is independent of the potential of the first conductive portion, the potential of the fourth conductive portion, and the potential of the gate portion, thereby writing the first information into the first storage element; and the potential of the first conductive portion is set to the second potential, the potential of the fourth conductive portion is set to the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to the third potential, thereby writing the second information into the first storage element, or The potential of the second conductive part is set to a first potential, the potential of the third conductive part is set to a second potential higher than the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to a fourth potential that is independent of the potential of the second conductive part, the potential of the third conductive part, and the potential of the gate part, thereby writing the first information into the second storage element; and the potential of the second conductive part is set to the second potential, the potential of the third conductive part is set to the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to the fourth potential, thereby writing the second information into the second storage element.

2. The semiconductor device according to claim 1, wherein The gate portion, the first conductive portion, and the second conductive portion all extend along a first direction.

3. The semiconductor device according to claim 1, wherein: The gate portion and the first conductive portion to the fourth conductive portion all extend along a first direction.

4. The semiconductor device according to claim 1, further comprising a semiconductor substrate having a first surface and a second surface positioned opposite to the first surface, the gate portion being disposed on the first surface, wherein The first diffusion layer constitutes a portion of the semiconductor substrate close to the first surface; and The second diffusion layer constitutes another portion of the semiconductor substrate close to the first surface.

5. The semiconductor device according to claim 4, wherein: The first storage element and the second storage element are each arranged to be opposite to the second surface when viewed from the first insulating layer; The first storage element is electrically coupled to the first diffusion layer through the first connection portion; and The second storage element is electrically coupled to the second diffusion layer through the second connection portion.

6. The semiconductor device according to claim 5, further comprising: a second insulating layer, covering the first surface of the semiconductor substrate; a third conductive portion and a fourth conductive portion, wherein the third conductive portion and the fourth conductive portion are each disposed opposite to the second surface when viewed from the second insulating layer; a third connecting portion penetrating the second insulating layer and electrically coupling the first diffusion layer and the third conductive portion to each other; as well as The fourth connection portion penetrates the second insulating layer and electrically couples the second diffusion layer and the fourth conductive portion to each other.

7. The semiconductor device according to claim 1, wherein: The controller includes a potential control circuit capable of maintaining the potential of the second conductive portion and the potential of the third conductive portion at the third potential.

8. The semiconductor device according to claim 1, wherein The controller includes a potential control circuit capable of maintaining the potential of the first conductive portion and the potential of the fourth conductive portion at the fourth potential.

9. The semiconductor device according to claim 1, further comprising a fin, the fin comprising a semiconductor material and extending in a second direction intersecting the first direction, wherein The first storage element and the second storage element are each coupled to a back side of the fin; and The gate portion, the first diffusion layer, and the second diffusion layer extend in the first direction and cover a surface other than the back surface of the fin portion.

10. A semiconductor device comprising: A transistor including a gate portion, a first diffusion layer, and a second diffusion layer; a first silicide region in contact with the first diffusion layer; a second silicide region in contact with the second diffusion layer; a first conductive portion; a second conductive portion, electrically insulated from the first conductive portion; a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion; a first insulating layer covering a first surface of the semiconductor substrate; A first connecting portion and a second connecting portion, each of which penetrates the first insulating layer; The first storage element is electrically coupled to the first silicide region through the first connection portion; and The second storage element is electrically coupled to the second silicide region through the second connection portion, wherein The semiconductor device further comprises: a third conductive portion, which is disposed opposite to the first surface as viewed from the first insulating layer and is electrically coupled to the first diffusion layer; and a fourth conductive portion, viewed from the first insulating layer, disposed opposite to the first surface and electrically coupled to the second diffusion layer, The semiconductor device further includes a controller that performs the following control: The potential of the first conductive portion is set to a first potential, the potential of the fourth conductive portion is set to a second potential higher than the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to a third potential that is independent of the potential of the first conductive portion, the potential of the fourth conductive portion, and the potential of the gate portion, thereby writing the first information into the first storage element; and the potential of the first conductive portion is set to the second potential, the potential of the fourth conductive portion is set to the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to the third potential, thereby writing the second information into the first storage element, or The potential of the second conductive part is set to a first potential, the potential of the third conductive part is set to a second potential higher than the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to a fourth potential that is independent of the potential of the second conductive part, the potential of the third conductive part, and the potential of the gate part, thereby writing the first information into the second storage element; and the potential of the second conductive part is set to the second potential, the potential of the third conductive part is set to the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to the fourth potential, thereby writing the second information into the second storage element.

11. The semiconductor device according to claim 10, further comprising: a second insulating layer, covering the second surface of the semiconductor substrate; and The third connecting portion and the fourth connecting portion each penetrate the second insulating layer; wherein, The first conductive portion is disposed opposite to the second insulating layer as viewed from the first memory element and is electrically coupled to the first diffusion layer through the third connecting portion; and The second conductive portion is disposed opposite to the second insulating layer as viewed from the second memory element and is electrically coupled to the second diffusion layer through the fourth connecting portion.

12. An imaging device comprising: Semiconductor equipment; and An imaging element stacked on the semiconductor device; The semiconductor device comprises: A transistor including a gate portion, a first diffusion layer, and a second diffusion layer; a first silicide region in contact with the first diffusion layer; a second silicide region in contact with the second diffusion layer; a first conductive portion; a second conductive portion, electrically insulated from the first conductive portion; a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion; a first insulating layer covering the second surface of the semiconductor substrate; and The first connecting portion and the second connecting portion each penetrate the first insulating layer, wherein The first storage element is electrically coupled to the first silicide region through the first connection portion; and The second storage element is electrically coupled to the second silicide region through the second connection portion, wherein The semiconductor device further comprises: a third conductive portion, which is disposed opposite to the first memory element and electrically coupled to the first diffusion layer as viewed from the first diffusion layer; and a fourth conductive portion, which is disposed opposite to the second storage element and electrically coupled to the second diffusion layer when viewed from the second diffusion layer, The semiconductor device further includes a controller that performs the following control: The potential of the first conductive portion is set to a first potential, the potential of the fourth conductive portion is set to a second potential higher than the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to a third potential that is independent of the potential of the first conductive portion, the potential of the fourth conductive portion, and the potential of the gate portion, thereby writing the first information into the first storage element; and the potential of the first conductive portion is set to the second potential, the potential of the fourth conductive portion is set to the first potential, the potential of the gate portion is set to the second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to the third potential, thereby writing the second information into the first storage element, or The potential of the second conductive part is set to a first potential, the potential of the third conductive part is set to a second potential higher than the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to a fourth potential that is independent of the potential of the second conductive part, the potential of the third conductive part, and the potential of the gate part, thereby writing the first information into the second storage element; and the potential of the second conductive part is set to the second potential, the potential of the third conductive part is set to the first potential, the potential of the gate part is set to the second potential, and the potential of the first conductive part and the potential of the fourth conductive part are set to the fourth potential, thereby writing the second information into the second storage element.

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