Semiconductor Memory Device and Memory System Having the Same

Abstract

A semiconductor memory device and a memory system including the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array, and the memory cell array includes a memory block, a local parity check memory block, and a register block. The memory block stores a plurality of partial local data respectively in response to a plurality of column selection signals, or stores a first partial global parity check in response to a global parity check column selection signal. The local parity check memory block stores a local parity check of local data in response to the plurality of column selection signals, or stores a second partial global parity check in response to the global parity check column selection signal. The register block generates a global parity check including the first partial global parity check and the second partial global parity check. Each piece of local data includes partial local data, and the global parity check is a parity check of the plurality of pieces of local data and the local parity check.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0038816, filed on Apr. 3, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Devices and systems consistent with example embodiments relate to semiconductor memory devices and memory systems including such semiconductor memory devices. Background Art

[0004] A semiconductor memory device may include a memory cell array. Generally, the semiconductor memory device may perform an ECC (error correcting code) encoding operation on data applied to the memory cell array and an ECC decoding operation on data output from the memory cell array. Summary of the Invention

[0005] One aspect is to provide a semiconductor memory device and a memory system including the semiconductor memory device, which can perform error correcting code (ECC) encoding and decoding operations on data of at least two different data units.

[0006] Aspects of the inventive concept should not be limited by the above description, and other aspects not mentioned will be clearly understood by those of ordinary skill in the art from the example embodiments described herein.

[0007] According to an aspect of an example embodiment, there is provided a semiconductor memory device including a memory cell array, the memory cell array including: a plurality of memory blocks configured to store a plurality of partial local data respectively in response to a plurality of column selection signals, or store a first partial global parity in response to a global parity column selection signal; a local parity storage block configured to store a plurality of local parities of the plurality of local data in response to the plurality of column selection signals, or store a second partial global parity in response to a global parity column selection signal; and a register block configured to generate a global parity including the plurality of first partial global parities and the second partial global parity, wherein each of the plurality of local data includes the plurality of partial local data, and the global parity is a parity of the plurality of local data and the plurality of local parities.

[0008] According to another aspect of the exemplary embodiment, a storage system is provided, including: a controller configured to output a command / address, send input data, and receive output data; and a memory configured to receive the command / address and the input data and send the output data, wherein the memory includes a memory cell array, and the memory cell array includes: a plurality of memory blocks configured to store a plurality of partial local data respectively in response to a plurality of column selection signals, or store a first partial global parity in response to a global parity column selection signal; a local parity storage block configured to store a plurality of local parities of the plurality of local data in response to the plurality of column selection signals, or store a second partial global parity in response to the global parity column selection signal; and a register block configured to generate a global parity including the plurality of first partial global parities and the second partial global parity, wherein each of the plurality of local data includes a plurality of partial local data, and the global parity is a parity of the plurality of local data and the plurality of local parities. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B is a block diagram of a semiconductor memory device according to an exemplary embodiment;

[0010] Figure 2 is a block diagram showing a configuration of a memory bank according to an exemplary embodiment;

[0011] Figure 3 is a diagram showing a configuration of k memory blocks and a local parity storage block of each memory bank according to an exemplary embodiment;

[0012] Figure 4 is a diagram showing an error correcting code (ECC) encoder according to an exemplary embodiment;

[0013] Figure 5 is a diagram showing a parity operation of a parity generator according to an exemplary embodiment;

[0014] Figure 6 is a diagram showing a configuration of an ECC decoder according to an exemplary embodiment;

[0015] Figure 7 is a diagram showing a syndrome operation of a syndrome generator according to an exemplary embodiment;

[0016] Figure 8 is a circuit diagram showing a configuration of a register according to an exemplary embodiment;

[0017] Figure 9is a diagram illustrating an operation of a semiconductor memory device when a command / address including an active command is applied according to an exemplary embodiment;

[0018] Figure 10 is a diagram illustrating an operation of a semiconductor memory device when a command / address including a write command is applied according to an exemplary embodiment;

[0019] Figure 11 is a diagram illustrating an operation of semiconductor memory device 100 when a command / address including a write command is applied according to an exemplary embodiment;

[0020] Figure 12 is a diagram illustrating an operation of a semiconductor memory device when a command / address including a precharge command is applied according to an exemplary embodiment;

[0021] Figures 13 to 15 is a diagram illustrating a global ECC decoding operation of a semiconductor memory device according to an exemplary embodiment; and

[0022] Figure 16 is a block diagram illustrating a storage system according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, a semiconductor memory device and a storage system including the semiconductor memory device according to an exemplary embodiment will be described with reference to the accompanying drawings.

[0024] Figure 1A and Figure 1B is a block diagram of a semiconductor memory device according to an exemplary embodiment.

[0025] The semiconductor memory device 100 may include a command / address generator 10, a refresh address counter 12, a row address generator 14, a selector 16, a row decoder 18, a bank selection signal generator 20, a column address generator 22, a column decoder 24, a memory cell array 26, a data write path unit 28, an error correction code (ECC) encoder 30, an ECC decoder 32, a data read path unit 34, and an error address storage 36. For example, the memory cell array 26 may include four banks 26a, 26b, 26c, and 26d. For example, the row decoder 18 may include four row decoders 18a, 18b, 18c, and 18d, and for example, the column decoder 24 may include four column decoders 24a, 24b, 24c, and 24d. That is, one row decoder 18 and one column decoder 24 may be included in each bank. Different from what is shown, one ECC encoder 30, one ECC decoder 32, and one error address storage 36 may also be included in each bank.

[0026] Figure 1A andFigure 1B The functions of the respective blocks shown in the figure will be described below.

[0027] When a command / address CA is applied, the command / address generator 10 may decode a command signal included in the command / address CA to generate an activate command ACT, a write command WR, a read command RD, a precharge command PRE, or a refresh command REF, and generate an address signal included in the command / address CA as a bank address signal BADD, a row address signal RADD, and a column address signal CADD. For example, the command / address generator 10 may generate the bank address signal BADD and the row address signal RADD together with the activate command ACT, and generate the column address signal CADD together with the write command WR or the read command RD.

[0028] The refresh address counter 12 may generate a refresh row address refa in response to the refresh command REF.

[0029] The row address generator 14 may receive the row address signal RADD in response to the activate command ACT and generate a row address ra.

[0030] The selector 16 may generate the refresh row address refa as a final row address raf in response to the refresh command REF, and generate the row address ra as the final row address raf in response to the activate command ACT.

[0031] Each of the row decoders 18a, 18b, 18c, and 18d may decode the final row address raf in response to the activate command ACT and a corresponding bank select signal baa, bab, bac, or bad, and activate one of a plurality of corresponding word line select signals wla, wlb, wlc, or wld. In addition, each of the row decoders 18a, 18b, 18c, and 18d may decode the final row address raf in response to the refresh command REF and a corresponding bank select signal baa, bab, bac, or bad, and activate at least one of a plurality of corresponding word line select signals wla, wlb, wlc, or wld. In addition, each of the row decoders 18a, 18b, 18c, and 18d may decode a faulty row address fra in response to the refresh command REF and a faulty bank address fba, and activate a faulty word line select signal of one of a plurality of corresponding word line select signals wla, wlb, wlc, or wld of a faulty bank of one of the four banks 26a, 26b, 26c, and 26d.

[0032] The bank select signal generator 20 may decode the bank address signal BADD and generate bank select signals baa, bab, bac, and bad.

[0033] The column address generator 22 can receive a column address signal CADD in response to a write command WR or a read command RD, and generate a column address ca.

[0034] Each of column decoders 24a, 24b, 24c, and 24d can decode the column address ca in response to a write command WR or a read command RD and corresponding bank select signals baa, bab, bac, or bad, and activate one of a plurality of corresponding column select signals csla, cslb, cslc, or csld. In addition, each of column decoders 24a, 24b, 24c, and 24d can activate a global parity column select signal (not shown) of a plurality of corresponding column select signals csla, cslb, cslc, or csld in response to a precharge command PRE and corresponding bank select signals baa, bab, bac, or bad. In addition, each of column decoders 24a, 24b, 24c, and 24d can activate all of a plurality of corresponding column select signals csla, cslb, cslc, or csld of a defective bank in sequence in response to a refresh command REF and a defective bank address fba, and activate a defective column select signal (not shown) in response to a refresh command REF, a defective bank address fba, and a defective column address fca.

[0035] Each of banks 26a, 26b, 26c, and 26d can include a plurality of memory cells (not shown), and store data di in a memory cell selected by one of a plurality of corresponding word line select signals wla, wlb, wlc, or wld and one of a plurality of corresponding column select signals csla, cslb, cslc, or csld, or output data do stored in the selected memory cell. In addition, each of banks 26a, 26b, 26c, and 26d can perform a refresh operation on memory cells selected by at least one of a plurality of corresponding word line select signals wla, wlb, wlc, or wld.

[0036] The data write path unit 28 can sequentially receive data DQ applied from the outside of the semiconductor memory device 100 in a serial manner the same number of times as the burst length, and the data write path unit 28 outputs local data DI in a parallel manner. For example, when the number of data input / output (I / O) terminals (pins or solder balls) of the semiconductor memory device 100 is n (e.g., 16) and the burst length is set to k (e.g., 8), the data write path unit 28 can sequentially receive n-bit data DQ k times in a serial manner, and generate n×k-bit (e.g., 128-bit) local data DI in a parallel manner.

[0037] The ECC encoder 30 can perform a local ECC encoding operation on the local data DI, generate a local parity check for the local data DI, and generate the local data DI including the local parity check as the data di. For example, the ECC encoder 30 can perform a local ECC encoding operation on n×k bits (e.g., 128 bits) of local data DI, generate m bits (e.g., 8 bits) of local parity check for the n×k bits of local data DI, and generate (n×k)+m bits (e.g., 136 bits) of data di.

[0038] The ECC decoder 32 can perform a local ECC decoding operation on the local data do to detect whether there is an error in the data do, and generate the local data DO. In addition, when an error is detected, the ECC decoder 32 can generate an error signal ER. For example, the ECC decoder 32 can perform a local ECC decoding operation on (n×k)+m bits (e.g., 136 bits) of data do, generate a syndrome for the local data do, and use the syndrome to detect whether there is an error.

[0039] The data read path unit 34 can receive the data DO and sequentially generate the data DQ in a serial manner the same number of times as the number corresponding to the burst length. For example, when the number of data I / O terminals (pins or solder balls) of the semiconductor memory device 100 is n (e.g., 16) and the burst length is set to k (e.g., 8), the data read path unit 34 can receive n×k bits (e.g., 128 bits) of data DO and sequentially generate n bits of data DQ k times in a serial manner.

[0040] The error address memory 36 can store the bank select signals baa to bad, the final row address raf, and the column address ca as the faulty bank address fba, the faulty row address fra, and the faulty column address fca in response to the error signal ER. In addition, the error address memory 36 can generate the faulty bank address fba, the faulty row address fra, and the faulty column address fca in response to a refresh command REF.

[0041] Figure 2 is a block diagram showing the configuration of a bank according to an exemplary embodiment. Each of the banks 26a, 26b, 26c, and 26d can include k memory blocks BLK1 to BLKk, a local parity check memory block BLKP, and a register block REGBLK.

[0042] Reference Figure 2, each of the k (e.g., 8) memory blocks BLK1 to BLKk in each of the memory banks 26a, 26b, 26c, and 26d can receive, store, and output n-bit (e.g., 16-bit) partial data in response to one of the j (e.g., 64) corresponding column select signals csla1 to cslaj, cslb1 to cslbj, cslc1 to cslcj, or csld1 to csldj, and can receive, store, and output n-bit partial global parity in response to the corresponding global parity column select signals cslagp, calbgp, cslcgp, or csldgp.

[0043] The local parity memory block BLKP in each of the memory banks 26a, 26b, 26c, and 26d can receive, store, and output m-bit (e.g., 8-bit) local parity in response to one of the j corresponding column select signals csla1 to cslaj, cslb1 to cslbj, cslc1 to cslcj, or csld1 to csldj, and can receive, store, and output m-bit (e.g., 8-bit) partial global parity in response to the corresponding global parity column select signals cslagp, calbgp, cslcgp, or csldgp.

[0044] That is, in response to one of the j corresponding column select signals csla1 to cslaj, cslb1 to cslbj, cslc1 to cslcj, or csld1 to csldj, each of the memory banks 26a, 26b, 26c, and 26d can receive, store, and output (n×k)-bit (e.g., 128-bit) local data and m-bit local parity, or can receive, store, and output (n×k)+m-bit (e.g., 136-bit) global parity in response to the corresponding global parity column select signals cslagp, calbgp, cslcgp, or csldgp.

[0045] The register block REGBLK in each of the memory banks 26a, 26b, 26c, and 26d can store the (n×k)+m-bit global parity output from the k memory blocks BLK1 to BLKk and the local parity memory block BLKP in the corresponding memory bank 26a, 26b, 26c, or 26d, compare the (n×k)+m-bit global parity with the (n×k)-bit local data and m-bit local parity, and generate and output the generated (n×k)+m-bit global parity to the k memory blocks BLK1 to BLKk and the local parity memory block BLKP in the corresponding memory bank 26a, 26b, 26c, or 26d.

[0046] Figure 3FIG. is a diagram showing a configuration of k memory blocks BLK1 to BLKk and a local parity memory block BLKP of each bank according to an exemplary embodiment. Each of the k memory blocks BLK1 to BLKk may include thirty-two partial memory blocks PBLK1 to PBLK32 arranged in a bit line direction and thirty-one sense amplifier blocks SA12 to SA3132. The thirty-one sense amplifier blocks SA12 to SA3132 may be respectively disposed between pairs of adjacent partial memory blocks PBLK1 and PBLK2, PBLK2 and PBLK3 (not shown), …, and PBLK31 (not shown) and PBLK32. Each of the thirty-two partial memory blocks PBLK1 to PBLK32 may include sixty-five sub-memory blocks SMCA1 to SMCA65 arranged in a word line direction. Each of the thirty-one sense amplifier blocks SA12 to SA3132 may include sixty-five partial sense amplifier blocks PSA1 to PSA65. Each of the sixty-five partial sense amplifier blocks PSA1 to PSA65 may be shared between two adjacent sub-memory blocks SMCA1, SMCA2, …, or SMCA65 in a bit line direction. Each of the sixty-five sub-memory blocks SMCA1 to SMCA65 may receive and output 16-bit partial local data or 16-bit partial global parity in response to one of a plurality of corresponding word line selection signals wl1 to wli, wl21 to wl2i, …, or wl321 to wl32i and a corresponding column selection signal csla1, csla2, …, or cslagp. Each of the sixty-five partial sense amplifier blocks PSA1 to PSA65 may amplify and receive 16-bit partial local data or 16-bit partial global parity applied to one of two corresponding adjacent sub-memory blocks SMCA1, SMCA2, …, or SMCA65, or amplify and output 16-bit partial local data or 16-bit partial global parity output from one of two corresponding sub-memory blocks SMCA1, SMCA2, …, or SMCA65.

[0047] The local parity check memory block BLKP may include thirty-two partial memory blocks PBLK1’ to PBLK32’ arranged in the bit line direction and thirty-one sense amplifier blocks SA12’ to SA3132’. The thirty-one sense amplifier blocks SA12’ to SA3132 may be respectively arranged between pairs of adjacent partial memory blocks PBLK1’ and PBLK2’, PBLK2’ and PBLK3’ (not shown), …, and PBLK31’ (not shown) and PBLK32’. Each of the thirty-two partial memory blocks PBLK1’ to PBLK32’ may include sixty-five sub-memory blocks SMCA1’ to SMCA65’ arranged in the word line direction, and each of the thirty-one sense amplifier blocks SA12’ to SA3132 may include sixty-five partial sense amplifier blocks PSA1’ to PSA65’. Each of the sixty-five partial sense amplifier blocks PSA1’ to PSA65’ may be shared between two adjacent sub-memory blocks SMCA1’, SMCA2’, …, or SMCA65’ in the bit line direction. Each of the sixty-five sub-memory blocks SMCA1’ to SMCA65’ may receive and output 8-bit local parity check or 8-bit partial global parity check in response to one of a plurality of corresponding word line selection signals wl1 to wli, wl21 to wl2i, …, or wl321 to wl32i and a corresponding column selection signal csla1, csla2, …, or cslagp. Each of the sixty-five partial sense amplifier blocks PSA1’ to PSA65’ may amplify and receive the 8-bit local parity check or 8-bit partial global parity check applied to one of a pair of two corresponding adjacent sub-memory blocks SMCA1’, SMCA2’, …, or SMCA65’, or amplify and output the 8-bit local parity check or 8-bit partial global parity check output from one of a pair of two corresponding sub-memory blocks SMCA1’, SMCA2’, …, or SMCA65.

[0048] In Figure 3 it, word lines WL11 to WL1i, WL21 to WL2i, …, and WL321 to WL32i indicate word lines selected in response to word line selection signals wl11 to wl1i, wl21 to wl2i, …, and wl321 to wl32i respectively, and bit line BL represents a representative bit line.

[0049] The register block REGBLK may include nine partial register blocks PREG1 to PREG9. Each of the eight partial register blocks PREG1 to PREG8 may include sixteen registers REG. The remaining one partial register block PREG9 may include eight registers REG.

[0050] The partial register block PREG1 can be commonly connected to sixty-five partial sense amplifier blocks PSA1 to PSA65, each of the thirty-one sense amplifier blocks SA12, SA23, …, and SA3132 included in the memory block BLK1. Sixteen registers REG of the partial register block PREG1 can store 16-bit partial local data or 16-bit partial global parity. The partial register block PREG2 can be commonly connected to sixty-five partial sense amplifier blocks PSA1 to PSA65, each of the thirty-one sense amplifier blocks SA12, SA23, …, and SA3132 included in the memory block BLK2. Sixteen registers REG of the partial register block PREG2 can store 16-bit partial local data or 16-bit partial global parity. Similarly, each of the partial register blocks PREG3 to PREG8 can be commonly connected to sixty-five corresponding partial sense amplifier blocks PSA1 to PSA65, each of the thirty-one sense amplifier blocks SA12, SA23, …, and SA3132 included in the corresponding memory blocks BLK3, BLK4, …, or BLK8. Sixteen corresponding registers REG of each of the partial register blocks PREG3 to PREG8 can store corresponding 16-bit partial local data or corresponding 16-bit global parity. The partial register block PREG9 can be commonly connected to sixty-five corresponding partial sense amplifier blocks PSA1’ to PSA65’, each of the thirty-one sense amplifier blocks SA12, SA23, …, and SA3132 included in the memory block BLKP. Eight registers REG of the partial register block PREG9 can store 8-bit local parity or 8-bit partial global parity.

[0051] Figure 4 FIG. is a diagram showing an ECC encoder 30 according to an exemplary embodiment. The ECC encoder 30 may include a parity generator 42.

[0052] Refer to Figure 4 , the parity generator 42 may receive local data DI applied from the data write path unit 28 and generate data di including the local data and local parity. For example, the parity generator 42 may generate 8-bit local parity using a first H matrix H and 128-bit local data.

[0053] Figure 5 FIG. is a diagram showing a parity operation of the parity generator 42 according to an exemplary embodiment.

[0054] Refer to Figure 5, the first H matrix H can be an 8×136 matrix, and the matrix R of 128-bit local data and 8-bit local parity can be a 136×1 matrix. In the first H matrix H, the codes h11 to h81, h12 to h82, …, h1128 to h8128, 10…0, 01…0, …, and 00…1 of the 136 column vectors C1 to C136 can have different codes including “0” and / or “1” respectively, except for the code with all “0”. In addition, for example, the first H matrix H can be generated using the polynomial code “111001111” according to the cyclical redundancy check (CRC) generating polynomial, and the cyclical redundancy check generating polynomial is X 8 +X 7 +X 6 +X 3 +X 2 +X+1. That is to say, after adding the 8-bit code “00000000” with all “0” to each of the 2 128 different 128-bit data words including the codewords h11 to h1128, h21 to h2128, …, and h81 to h8128 in the row vectors R1 to R8 of the first H matrix H, each of the 2 128 different 136-bit data words can be divided by the polynomial code to obtain an 8-bit remainder. The corresponding 8-bit remainder can be added after each of the 2 128 different 128-bit data words to generate 2 128 different 136-bit codewords. The first H matrix H can include the codewords among the 2 128 different 136-bit codewords, where the 8-bit remainders are represented as “10000000”, “01000000”, …, and “0000001” (with “1” in the diagonal direction), and the minimum Hamming distance dmin between any two codewords in the codewords h11 to h112810000000, h21 to h212801000000, …, and h81 to h812800000001 of the row vectors R1 to R8 is 3. The first H matrix H can detect each 1-bit error, 2-bit errors with two isolated 1-bit errors, and multiple-bit errors within 8 consecutive bits.

[0055] Reference Figure 4 and Figure 5The parity generator 42 can perform an exclusive OR (XOR) operation on each of the 128-bit codewords h11 to h128, h21 to h2128, …, and h81 to h8128 included in the row vectors R1 to R8 of the first H matrix H and the 128-bit local data r1 to r128 of the 136×1 matrix, and perform a modulo-2 operation on the result of the XOR operation to generate 8-bit local parities P1 to P8.

[0056] That is, the 8-bit local parities P1 to P8 can be represented by the following equations:

[0057] P1 = h11 ^ r1 + h12 ^ r2 + … + h1128 ^ r128

[0058] P2 = h21 ^ r1 + h22 ^ r2 + … + h2128 ^ r128

[0059] …

[0060] P8 = h81 ^ r1 + h82 ^ r2 + … + h8128 ^ r128,

[0061] where “^” represents the XOR operator and “+” represents the modulo-2 operator.

[0062] Figure 6 is a diagram showing the configuration of the ECC decoder 32 according to an exemplary embodiment. The ECC decoder 32 may include a syndrome generator 44 and an error detector 46.

[0063] Figure 6 The functions of the illustrated blocks will be described below.

[0064] The syndrome generator 44 can receive the 128-bit local data and the 8-bit local parity do output from the memory cell array 26 and generate an 8-bit syndrome.

[0065] Figure 7 is a diagram showing the syndrome operation of the syndrome generator 44 according to an exemplary embodiment.

[0066] Refer to Figure 7 , in the second H matrix H’, the codes h11’ to h81’, h12’ to h82’, …, and h1136’ to h8136’ of the 136 column vectors C1’ to C136’ can have different codes including “0” and / or “1” respectively, except for the codes having all “0”. In addition, for example, the second H matrix H’ can be generated according to the CRC generation polynomial, using the polynomial code “111001111” for the CRC generation polynomial which is X 8 + X 7 + X6 +X 3 +X 2 +X + 1. That is, the second H matrix H' may include codewords among the codewords obtained by dividing two different data words by a polynomial code and having a remainder of 0, where the minimum Hamming distance dmin between any two codewords is 3. Similar to the first H matrix H, the second H matrix H' can detect each 1-bit error, 2-bit errors with two isolated 1-bit errors, and multiple-bit errors with 8 consecutive bits. 136 That is, the 8-bit syndrome S1 to S8 can be represented by the following equations:

[0067] That is, the 8-bit syndrome S1 to S8 can be represented by the following equations:

[0068] S1 = h11' ^ r1' + h12' ^ r2' +... + h1128' ^ r128' +... + h1136' ^ p8'

[0069] S2 = h21' ^ r1' + h22' ^ r2' +... + h2128' ^ r128' +... + h2136' ^ p8'

[0070] ...

[0071] S8 = h81' ^ r1' + h82' ^ r2' +... + h8128' ^ r128' +... + h8136' ^ p8',

[0072] where "^" represents the XOR operator and "+" represents the modulo 2 operator.

[0073] Reference Figure 6 , when all 8-bit syndromes S1 to S8 are "0", the error detector 46 can generate a non-error signal NE indicating non-error, when the 8-bit syndromes S1 to S8 are included in the code of 136 column vectors C1' to C136' of the second H matrix H', generate a correctable error signal ER indicating a correctable error, or when the 8-bit syndromes S1 to S8 are not present in the code of 136 column vectors C1' to C136' of the second H matrix H', generate an uncorrectable error signal UE indicating an uncorrectable error.

[0074] Figure 8 is a circuit diagram showing the configuration of a register REG according to an exemplary embodiment. The register REG may include an XOR gate XORG, a first switch SW1 and a second switch SW2, a latch L including a first inverter I1 and a second inverter I2, an NMOS transistor N, and a third inverter I3.

[0075] Figure 8The functions of the respective components shown will be described as follows.

[0076] The XOR gate XORG can perform an XOR operation on data d and data d'.

[0077] The first switch SW1 can be turned on in response to a write command WR, a precharge command PRE, or a refresh command REF, and send the output signal of the XOR gate XORG to the node n. The precharge command PRE can be a word line precharge command for precharging the word line.

[0078] The latch L can invert and latch the signal at the node n.

[0079] The NMOS transistor N can reset the node n to the ground voltage level (data "0") in response to an activation command ACT. In addition, the NMOS transistor N can reset the node n to the ground voltage level at an initial stage (before the first switch SW1 is turned on) in response to a refresh command REF.

[0080] The third inverter I3 can invert the signal output from the latch L and generate data d'.

[0081] The second switch SW2 can be turned on in response to a precharge command PRE or a refresh command REF.

[0082] Figures 9 to 12 FIG. is a diagram showing the global ECC encoding operation of the semiconductor memory device 100 according to an exemplary embodiment. Figures 9 to 12 FIG. shows the global ECC encoding operation of the semiconductor memory device 100 when 128-bit local data and 8-bit local parity d11d12...d19 are stored in a memory cell (not shown) (the memory cell is selected in response to the word line selection signal wl11 of the sub memory cells SMCA1 and SMCA1' of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP of the memory bank 26a of the semiconductor memory device 100), 128-bit local data and 8-bit local parity d21d22...d29 are stored in a memory cell (not shown) (the memory cell is selected in response to the word line selection signal wl11 of the sub memory cells SMCA2 and SMCA2'), and 136-bit global parity D11D12...D19 are stored in the sub memory cells SMCA65 and SMCA65'.

[0083] Figure 9 FIG. is a diagram showing the operation of the semiconductor memory device 100 when a command / address ca1 including an activation command ACT is applied as the command / address CA.

[0084] Reference Figures 1A to 3 AndFigure 8 and Figure 9 When the command / address ca1 is applied, the semiconductor memory device 100 can decode the command signal COM included in the command / address ca1, generate an activation command ACT, activate the bank select signal baa using the bank address signal BADD included in the command / address ca1, and activate the word line select signal wl11 using the row address signal RADD included in the command / address ca1.

[0085] When the activation command ACT is generated, part of the register blocks PREG1 to PREG9 of the register block REGBLK of the bank 26a can be reset in response to the activation command ACT. That is, all 136-bit data of the part of the register blocks PREG1 to PREG9 of the register block REGBLK can be reset to "0".

[0086] Figure 10 FIG. is a diagram showing the operation of the semiconductor memory device 100 when the command / address ca2 including the write command WR is applied as the command / address CA.

[0087] Refer to Figures 1A to 3 and Figures 8 to 10, when the command / address ca2 is applied, the semiconductor memory device 100 can decode the command signal COM included in the command / address ca2 to generate a write command WR, and activate the column selection signal csla1 using the column address signal CADD included in the command / address ca2. In this case, first, in response to the word line selection signal wl11 and the column selection signal csla1, the previously stored 128-bit local data and the previously stored data of 8-bit local parity d11d12…d19 in the selected memory cells (not shown) of the sub-memory blocks SMCA1 and SMCA1’ included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP can be sent to the register block REGBLK. The register block REGBLK can perform an XOR operation on the data with all “0” and the previously stored data d11d12…d19, and generate the previously stored data d11d12…d19. Next, in response to the word line selection signal wl11 and the column selection signal csla1, the new data including the new 128-bit local data and 8-bit local parity d111d121…d191 can be stored in the selected memory cells (not shown) of the sub-memory blocks SMCA1 and SMCA1’ included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP. At the same time, the new data d111d121…d191 can be sent to the register block REGBLK. The register block REGBLK can perform an XOR operation on the previously stored data d11d12…d19 and the new data d111d121…d191, and generate the intermediate global parity D21D22…D29.

[0088] That is, when the write command WR is generated, the register block REGBLK can perform an XOR operation on the previously stored data d11d12…d19 stored in the selected memory cells (not shown) and the new data d111d121…d191 to be stored in the selected memory cells (not shown), and generate the intermediate global parity D21D22…D29.

[0089] Figure 11 FIG. is a diagram showing the operation of the semiconductor memory device 100 when the command / address ca3 including the write command WR is applied as the command / address CA.

[0090] Reference Figures 1A to 3 And Figures 8 to 11, when the command / address ca3 is applied, the semiconductor memory device 100 can decode the command signal COM included in the command / address ca3, generate a write command WR, and activate the column selection signal csla2 using the column address signal CADD included in the command / address ca3. In this case, first, in response to the word line selection signal wl11 and the column selection signal csla2, the previously stored 128-bit local data and the previous data of 8-bit local parity d21d22…d29 stored in the selected memory cells (not shown) of the sub-memory blocks SMCA2 and SMCA2’ included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP can be sent to the register block REGBLK. The register block REGBLK can perform an XOR operation on the intermediate global parity D21D22…D29 and the previous data d21d22…d29, and generate the intermediate global parity D31D32…D39. Next, in response to the word line selection signal wl11 and the column selection signal csla2, the new data including the new 128-bit data and 8-bit local parity d211d221…d291 can be stored in the selected memory cells (not shown) of the sub-memory blocks SMCA2 and SMCA2’ included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP. At the same time, the new data d211d221…d291 can be sent to the register block REGBLK. The register block REGBLK can perform an XOR operation on the intermediate global parity D31D32…D39 and the new data d211d221…d291, and generate the intermediate global parity D41D42…D49.

[0091] Figure 12 FIG. is a diagram showing the operation of the semiconductor memory device 100 when the command / address ca4 including the precharge command PRE is applied as the command / address CA.

[0092] Reference Figures 1A to 3 and Figures 8 to 12, when a command / address ca4 is applied, the semiconductor memory device 100 may decode a command signal COM included in the command / address ca4 and generate a precharge command PRE. In this case, first, in response to a word line selection signal wl11 and a global parity column selection signal cslagp, previous global parities D11D12…D19 stored in selected memory cells (not shown) of sub-memory blocks SMCA65 and SMCA65’ of memory blocks BLK1 to BLK8 and a local parity memory block BLKP may be sent to a register block REGBLK. The register block REGBLK may perform an XOR operation on an intermediate global parity D31D32…D39 and the previous global parity D11D12…D19 and generate a new global parity D41D42…D49. Next, in response to the word line selection signal wl11 and the global parity column selection signal cslagp, the new global parity D41D42…D49 generated by the register block REGBLK may be stored in the selected memory cells (not shown) of sub-memory blocks SMCA65 and SMCA65’ of memory blocks BLK1 to BLK8 and the local parity memory block BLKP.

[0093] As described above, in the global ECC encoding operation of the semiconductor memory device according to the exemplary embodiment, the register block REGBLK may perform an XOR operation on previous data, new data, and the previous global parity using a simple even parity (SEP) method and generate a new global parity.

[0094] As another example, the global ECC encoding operation according to the exemplary embodiment may be performed in a manner different from that described above with reference to Figures 9 to 12 description. Refer to Figure 9 and Figure 12, when generating an activation command ACT, part of the register blocks PREG1 to PREG9 of the register block REGBLK of the memory bank 26a can be reset in response to the activation command ACT. In addition, in response to the word line selection signal wl11 and the global parity column selection signal cslagp, the previous global parity D11D12…D19 stored in the selected memory cells (not shown) of the sub-memory blocks SMCA65 and SMCA65’ of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP can be sent to the register block REGBLK. That is, when generating an activation command ACT, the previous global parity D11D12…D19 can be stored in part of the register blocks PREG1 to PREG9 of the register block REGBLK. In this case, when generating a precharge command PRE, the previous global parity D11D12…D19 may not need to be sent to the register block REGGBLK, and the data stored in the register block REGGBLK is the new global parity. Therefore, in response to the word line selection signal wl11 and the global parity column selection signal cslagp, the new global parity stored in the register block REGBLK can be stored in the selected memory cells (not shown) of the sub-memory blocks SMCA65 and SMCA65’ of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP.

[0095] Figures 13 to 15 FIG. is a diagram illustrating a global ECC decoding operation of the semiconductor memory device 100 according to an exemplary embodiment. Figures 13 to 15 FIG. is a diagram illustrating a global ECC decoding operation of the semiconductor memory device 100 when a defective memory bank address fba indicating the memory bank 26a, a defective row address fra indicating the word line selection signal wl11, and a defective column address fca indicating the column selection signal csla1 are stored in the error address memory 36. That is, Figures 13 to 15 FIG. is a diagram illustrating Figure 12 FIG. is a diagram illustrating the operation of the semiconductor memory device 100 in the case where an error is detected in the data d111d121…d191 stored in the sub-memory blocks SMCA1 and SMCA1’ of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP in response to the word line selection signal wl11 and the column selection signal csla1.

[0096] Refer to Figures 1A to 3 , Figure 12 and Figure 13, when the command / address ca5 is applied, the semiconductor memory device 100 can decode the command signal COM included in the command / address ca5 and generate a refresh command REF. First, in response to the refresh command REF, all the data of partial register blocks PREG1 to PREG9 of the register block REGBLK can be reset to "0". That is, all 136 registers REG of the register block REGBLK can be reset to "0". In addition, the error address memory 36 can generate a defective bank address fba and a defective row address fra in response to the refresh command REF. The row decoder 18a of the bank 26a can activate the word line selection signal wl11 in response to the defective bank address fba and the defective row address fra. In addition, the column decoder 24a of the bank 26a can activate the column selection signal csla1 in response to the refresh command REF and the defective bank address fba. In response to the word line selection signal wl11 and the column selection signal csla1, the previous 128-bit local data and the previous data of the 8-bit local parity d111d121…d191 stored in the selected memory cells (not shown) of the sub-memory blocks SMCA1 and SMCA1' included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP can be stored in the register block REGBLK. The register block REGBLK can perform an XOR operation on the data with all "0"s and the previous data d111d121…d191 and generate the previous data d111d121…d191.

[0097] Reference Figures 1A to 3 and Figures 12 to 14 , the column decoder 24a can activate the column selection signal csla2. In response to the word line selection signal wl11 and the column selection signal csla2, the previous 128-bit local data and the previous data of the 8-bit local parity d211d221…d291 stored in the selected memory cells (not shown) of the sub-memory blocks SMCA2 and SMCA2' included in the memory blocks BLK1 to BLK8 and the local parity memory block BLKP can be stored in the register block REGBLK. The register block REGBLK can perform an XOR operation on the previous data d111d121…d191 and the previous data d211d221…d291 and generate the intermediate global parity D51D52…D59.

[0098] Although not shown, the column decoder 24a may sequentially activate subsequent column selection signals csla3 to csla64. In response to the word line selection signal wl11 and the corresponding column selection signals csla3, csla4, …, or csla64, the corresponding previous 128-bit local data and previous 8-bit local parity stored in the selected memory cells (not shown) of the corresponding sub-memory blocks SMCA3 and SMCA3’, SMCA4 and SMCA4’, …, or SMCA64 and SMCA64’ of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP may be sequentially stored in the register block REGBLK. The register block REGBLK may sequentially perform an XOR operation on the intermediate global parity D51D52…D59 and the previous data, and generate the intermediate global parity D61D62…D69.

[0099] In addition, the column decoder 24a may activate the global parity column selection signal cslagp. In response to the word line selection signal wl11 and the global parity column selection signal cslagp, the previous global parity D41D42…D49 stored in the selected memory cells (not shown) of the sub-memory blocks SMCA65 and SMCA65’ of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP may be stored in the register block REGBLK. The register block REGBLK may perform an XOR operation on the intermediate global parity D61D62…D69 and the previous global parity D41D42…D49, and generate the error location data D71D72…D79.

[0100] When performing the above operations, error location data indicating the location of an error having one “1”, two isolated “1”s, or multiple “1”s within eight consecutive bits of the data d111d121…d191 may be detected. That is, the 136 bits of the error location data D71D72…D79 may include one “1”, two isolated “1”s, or multiple “1”s within eight consecutive bits.

[0101] Next, refer to Figures 1A to 3 and Figures 12 to 15, the error address register 36 can generate a fault column address fca, and the column decoder 24a can activate a column select signal csla1. In response to the word line select signal wl11 and the column select signal csla1, the previous fault data including 128-bit local data stored in the selected memory cells (not shown) of the sub-memory blocks SMCA1 and SMCA1' of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP and 8-bit global parity d111d121…d191 can be stored in the register block REGBLK. The register block REGBLK can perform an XOR operation on the error location data D71D72…D79 and the previous fault data d111d121…d191, and generate 128-bit local data and 8-bit local parity d111’d121…d191 in which the error is corrected. That is, the data D72…D79 of the error location data D71D72…D79 can all be “0”, and the data D71 can be “1000000000000000”. In this case, there may be an error in the most significant bit (MSB) of the data d111 of the previous fault data d111d121…d191, and the error can be corrected by inverting the MSB of the data d111.

[0102] Next, in response to the word line select signal wl11 and the column select signal csla1, the data d111’d121…d191 stored in the register block REGBLK can be stored in the selected memory cells (not shown) of the sub-memory blocks SMCA1 and SMCA1' of the memory blocks BLK1 to BLK8 and the local parity memory block BLKP. Thus, the global ECC decoding operation can be completed.

[0103] Although not shown, when performing the above global ECC decoding operation, the positions of 2-bit errors having two isolated bits or the positions of multi-bit errors within 8 consecutive bits in the data d111d121…d191 can be detected and corrected.

[0104] Although the semiconductor memory device according to the above embodiment performs the global ECC decoding operation when generating a refresh command REF, the semiconductor memory device can perform the global ECC decoding operation when generating an error check and erase command ECS.

[0105] In addition, when generating a refresh command REF, the semiconductor memory device according to the above embodiment can perform a refresh operation on the memory banks 26b, 26c, or 26d other than the faulty memory bank 26a during the global ECC decoding operation of the faulty memory bank 26a.

[0106] The semiconductor memory device according to the above exemplary embodiment can use the CRC method to detect whether there is an error during local ECC encoding and decoding operations, and use the SEP method to detect and correct the error location during global ECC encoding and decoding operations.

[0107] However, different from the above, the semiconductor memory device can be configured to detect and correct at least 1-bit error during local ECC encoding and decoding operations, and detect and correct at least 2-bit errors during global ECC encoding and decoding operations.

[0108] In addition, although the semiconductor memory device according to the above exemplary embodiment includes four memory banks, this is only an example. In some exemplary embodiments, the semiconductor memory device can be configured to include less than four memory banks, or more than four memory banks, that is, the semiconductor memory device can be configured to include at least one memory bank.

[0109] Figure 16 is a block diagram showing a storage system 1000 according to an exemplary embodiment. The storage system 1000 may include a controller 200 and a memory 300.

[0110] Reference Figure 16 , the controller 200 can send a command / address CA and receive and output data DQ. The memory 300 can receive the command / address CA and receive and output data DQ.

[0111] In Figure 16 the memory 300 can be the semiconductor memory device 100 described above with reference to Figures 1A to 15 or a memory module in which a plurality of semiconductor memory devices 100 are arranged.

[0112] According to an exemplary embodiment, the semiconductor memory device and the storage system including the semiconductor memory device can perform ECC encoding operations and ECC decoding operations on data of at least two different data units (e.g., local data units and global data units). Therefore, the reliability of the operations of the semiconductor memory device and the storage system including the semiconductor memory device can be improved.

[0113] Although various exemplary embodiments have been described with reference to the drawings, those skilled in the art should understand that various modifications can be made without departing from the scope of the present disclosure and without changing its essential features. Therefore, the above embodiments should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising: A plurality of memory blocks configured to store a plurality of partial local data respectively in response to a plurality of column selection signals, and store a first partial global parity in response to a global parity column selection signal; A local parity storage block configured to store a plurality of local parities of the plurality of local data in response to the plurality of column selection signals, and store a second partial global parity in response to the global parity column selection signal; and A register block configured to generate a global parity including a plurality of first partial global parities and the second partial global parity, Wherein each of the plurality of local data includes the plurality of partial local data, and the global parity is a parity of the plurality of local data and the plurality of local parities, and Wherein each of the local parity storage block and the plurality of memory blocks includes: A plurality of first sub - storage blocks configured to store the partial local data or the local parity respectively in response to a plurality of word line selection signals and the plurality of column selection signals; and A second sub - storage block configured to store the first partial global parity or the second partial global parity in response to the plurality of word line selection signals and the global parity column selection signal.

2. The semiconductor memory device according to claim 1, further comprising: A command and address generator configured to receive commands and addresses externally applied, decode command signals included in the commands and addresses, generate an activation command, a write command or a pre - charge command, and generate a row address or a column address using address signals included in the commands and addresses; And An error - correcting code (ECC) encoder configured to receive new local data and generate a new local parity of the new local data when the write command is applied, Wherein when the write command is applied, the memory cell array outputs, in response to a corresponding word line selection signal among the plurality of word line selection signals and a corresponding column selection signal among the plurality of column selection signals, the previous local data and the previous local parity stored in a selected first sub - storage block of each of the plurality of first sub - storage blocks in the plurality of memory blocks and the local parity storage block to the register block. The plurality of word line selection signals are generated in response to the row address, the plurality of column selection signals are generated in response to the column address, and the memory cell array receives the new local data and the new local parity and stores the new local data and the new local parity in the memory cell array, and the register block generates an intermediate global parity using the previous local data, the previous local parity, the new local data, and the new local parity.

3. The semiconductor memory device according to claim 2, wherein, The ECC encoder generates the new local parity using the new local data and a cyclic redundancy check (CRC) generation polynomial, where the cyclic redundancy check generation polynomial is X 8 + X 7 + X 6 + X 3 + X 2 + X + 1.

4. The semiconductor memory device according to claim 2, wherein, When the activation command is applied, the register block is reset.

5. The semiconductor memory device according to claim 2, wherein When the precharge command is applied, the second sub-storage blocks of the plurality of storage blocks and the local parity storage block output the stored previous global parity in response to corresponding word line selection signals among the plurality of word line selection signals and the global parity column selection signal, and wherein the register block performs a global ECC encoding operation that generates a new global parity using the intermediate global parity and the previous global parity and outputs the new global parity to the second sub-storage blocks of the plurality of storage blocks and the local parity storage block in response to the corresponding word line selection signal and the global parity column selection signal.

6. The semiconductor memory device according to claim 2, wherein, The command and address generator decodes the command signal and also generates a read command, or a refresh command or an error check and erase command, wherein the semiconductor memory device further includes: an ECC decoder configured to receive the previous local data and the previous local parity stored in the selected first sub-storage block when the read command is applied, determine whether an error exists in the previous local data and the previous local parity, and generate an error signal when it is determined that the error exists; and an error address storage configured to store the row address and the column address as a faulty row address and a faulty column address in response to the error signal.

7. The semiconductor memory device according to claim 6, wherein, The ECC decoder uses the previous local data, the previous local parity, and a CRC generation polynomial to detect the error, where the CRC generation polynomial is X 8 + X 7 + X 6 + X 3 + X 2 + X + 1.

8. The semiconductor memory device according to claim 6, wherein When the refresh command or the error check and erase command is applied, the register block is reset.

9. The semiconductor memory device according to claim 6, wherein, When the refresh command or the error check and erase command is applied, the first sub-storage blocks and the second sub-storage blocks of each of the local parity storage block and the plurality of storage blocks output a plurality of stored previous local data, previous local parity, and previous global parity to the register block in sequence in response to corresponding word line selection signals among the plurality of word line selection signals, the plurality of column selection signals, and the global parity column selection signal, the plurality of word line selection signals are generated in response to the faulty row address, the plurality of column selection signals and the global parity column selection signal are sequentially activated, and the selected first sub-storage blocks of the first sub-storage blocks of each of the local parity storage block and the plurality of storage blocks output the previous local data and the previous local parity including an error to the register block in response to corresponding word line selection signals among the plurality of word line selection signals and corresponding column selection signals among the plurality of column selection signals, the plurality of word line selection signals are generated in response to the faulty row address, the plurality of column selection signals are generated in response to the faulty column address, and store the previous local data and the previous local parity in which the error is corrected in the selected first sub-storage block, and Among them, the register block performs a global ECC decoding operation. The global ECC decoding operation uses sequentially applied, a plurality of previous local data, the previous local parity, and the previous global parity to generate error location data including an error location, and uses the error location data, the previous local data including the error, and the previous local parity to output the previous local data and the previous local parity in which the error is corrected.

10. The semiconductor memory device according to claim 9, wherein, The memory cell array includes a predetermined number of banks. Among them, each of the predetermined number of banks includes the plurality of memory blocks, the local parity check memory block, and the register block, and Among them, when the refresh command is applied, one of the predetermined number of banks performs a global ECC decoding operation, and another of the predetermined number of banks performs a refresh operation.

11. The semiconductor memory device according to claim 1, further comprising: A command and address generator configured to receive commands and addresses externally applied, decode command signals included in the commands and addresses, generate an activation command, a write command, or a precharge command, and generate a row address or a column address using address signals included in the commands and addresses; And An error correction code ECC encoder configured to receive new local data and generate a new local parity of the new local data when the write command is applied. Among them, when the activation command is applied, the register block is reset, the second sub-memory blocks of the plurality of memory blocks and the local parity check memory block output the previous global parity in response to corresponding word line selection signals among the plurality of word line selection signals and the global parity check column selection signal. The plurality of word line selection signals are generated in response to the row address, and the register block stores the previous global parity. And Among them, when the write command is applied, the selected first sub-memory blocks of the plurality of first sub-memory blocks of each of the plurality of memory blocks and the local parity check memory block output the previous local data and the previous local parity stored in the selected first sub-memory blocks to the register block in response to corresponding word line selection signals among the plurality of word line selection signals and corresponding column selection signals among the plurality of column selection signals. The plurality of word line selection signals are generated in response to the row address, the plurality of column selection signals are generated in response to the column address, and the selected first sub-memory blocks receive the new local data and the new local parity and store the new local data and the new local parity in the selected first sub-memory blocks. And the register block uses the previous global parity, the previous local data, the previous local parity, the new local data, and the new local parity to generate an intermediate global parity.

12. The semiconductor memory device according to claim 11, wherein, When the precharge command is applied, in response to a corresponding word line selection signal among the plurality of word line selection signals and the global parity column selection signal, the register block performs a global ECC encoding operation of outputting a new global parity to the plurality of memory blocks and the second sub-memory block of the local parity memory block.

13. The semiconductor memory device according to claim 1, wherein, The register block generates the global parity using a simple even parity (SEP) method and includes a plurality of partial register blocks. Each of the plurality of partial register blocks includes: an XOR gate configured to perform an XOR operation on a latch signal and an input signal and generate an output signal; and a latch configured to latch the output signal.

14. A memory system includes: a controller configured to output commands and addresses, send input data, and receive output data; and a memory configured to receive the commands and addresses and the input data and send the output data, wherein the memory includes a memory cell array that includes: a plurality of memory blocks configured to store multiple pieces of partial local data respectively in response to a plurality of column selection signals and store a first part of the global parity in response to a global parity column selection signal; a local parity memory block configured to store multiple local parities of the multiple pieces of local data in response to the plurality of column selection signals and store a second part of the global parity in response to the global parity column selection signal; and a register block configured to generate a global parity including a plurality of first parts of the global parity and the second part of the global parity, wherein each of the multiple pieces of local data includes the multiple pieces of partial local data, and the global parity is a parity of the multiple pieces of local data and the multiple local parities, wherein each of the multiple first memory blocks and the local parity memory block includes: a plurality of first sub-memory blocks configured to store the partial local data or the local parity respectively in response to a plurality of word line selection signals and the plurality of column selection signals; and a second sub-memory block configured to store the first part of the global parity or the second part of the global parity in response to the plurality of word line selection signals and the global parity column selection signal.

15. The storage system according to claim 14, wherein, The memory further includes: a command and address generator configured to receive commands and addresses applied from outside the memory, decode command signals included in the commands and addresses, generate an activation command, a write command, or a precharge command, and generate a row address or a column address using the address signals included in the commands and addresses; and an error correction code (ECC) encoder configured to receive new local data and generate a new local parity of the new local data when the write command is applied, and Wherein, when the write command is applied, the memory cell array outputs, in response to the corresponding word line selection signal among the plurality of word line selection signals and the corresponding column selection signal among the plurality of column selection signals, the previous local data and the previous local parity stored in the selected first sub-block of each of the plurality of memory blocks and the local parity check memory block, the plurality of word line selection signals are generated in response to the row address, the plurality of column selection signals are generated in response to the column address, and the memory cell array receives the new local data and the new local parity and stores the new local data and the new local parity in the memory cell array, and the register block generates an intermediate global parity using the previous local data, the previous local parity, the new local data, and the new local parity.

16. The storage system according to claim 15, wherein, When the precharge command is applied, the second sub-blocks of the plurality of memory blocks and the local parity check memory block output, in response to the corresponding word line selection signal among the plurality of word line selection signals and the global parity check column selection signal, the previous global parity stored in the second sub-block, and wherein, the register block performs a global ECC encoding operation, the global ECC encoding operation generates a new global parity using the intermediate global parity and the previous global parity and outputs the new global parity to the second sub-blocks of the plurality of memory blocks and the local parity check memory block in response to the corresponding word line selection signal and the global parity check column selection signal.

17. The storage system according to claim 16, wherein, The command and address generator decodes the command signal and also generates a read command, or a refresh command or an error check and erase command, wherein, the memory further includes: an ECC decoder, configured to receive, when the read command is applied, the previous local data and the previous local parity stored in the selected first sub-block, determine whether there is an error in the previous local data and the previous local parity, and generate an error signal when it is determined that the error exists; and an error address storage, configured to store the row address and the column address as a faulty row address and a faulty column address in response to the error signal.

18. The storage system according to claim 17, wherein, When the refresh command or the error check and erase command is applied, the plurality of first sub - memory blocks and the second sub - memory blocks of each of the local parity check memory block and the plurality of memory blocks output, in response to corresponding word - line selection signals among the plurality of word - line selection signals, the plurality of column selection signals, and the global parity check column selection signal, the plurality of previous local data, the previous local parity check, and the previous global parity check stored in the plurality of first sub - memory blocks and the second sub - memory blocks to the register block. The plurality of word - line selection signals are generated in response to the faulty row address, the plurality of column selection signals and the global parity check column selection signal are sequentially activated, and the selected first sub - memory block of the plurality of first sub - memory blocks of each of the local parity check memory block and the plurality of memory blocks outputs the previous local data and the previous local parity check including an error to the register block in response to the corresponding word - line selection signal among the plurality of word - line selection signals and the corresponding column selection signal among the plurality of column selection signals. The plurality of word - line selection signals are generated in response to the faulty row address, the plurality of column selection signals are generated in response to the faulty column address, and store the previous local data and the previous local parity check in which the error is corrected into the selected first sub - memory block, and wherein, the register block performs a global ECC decoding operation. The global ECC decoding operation uses the sequentially applied plurality of previous local data, the previous local parity check, and the previous global parity check to generate error location data including the error location, and uses the error location data and the previous local data and the previous local parity check including the error to output the previous local data and the previous local parity check in which the error is corrected.

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