Display control device and display panel module

Abstract

The present invention relates to a display control apparatus and a display panel module. Power consumption generated by interleaved driving of a display panel is reduced. A driving stop period is inserted between driving of odd-numbered fields and driving of even-numbered fields in interleaved driving. Furthermore, when driving signals output from a source driving section are supplied to the display panel in a time-division manner per sub-pixel, a switching control signal of a source line switch allocated to a source line of a driving signal corresponding to each sub-pixel is changed in such a manner that the number of switching times of the source line switch is reduced.

Description

[0001] This application is a divisional application of the patent application No. 2017105947675, the title of which is "Display control device and display panel module". TECHNICAL FIELD

[0002] The present application relates to a display control device which can perform interlaced driving of a display panel, for example, and relates to a technology effective for a display panel module in which the display control device is loaded. BACKGROUND

[0003] There is an interlaced driving method in display driving by a display control device which performs gate line control and source line driving of a display panel. This alternately displays odd fields and even fields of gate lines to work, and 1 frame is constituted by 2 fields of odd fields and even fields. This interlaced driving method is a technology which increases the number of drawings without increasing the amount of data (transmission rate or bandwidth) in image data transmission compared with a non-interlaced driving method which sequentially selects gate lines to display an image. There is a description in Patent Literature 1 for such an interlaced driving method for a liquid crystal display panel.

[0004] Prior Art Documents

[0005] Patent Literature

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2015-111400 SUMMARY

[0007] Problems to be Solved by the Invention

[0008] The interlaced driving method does not increase the transmission rate or bandwidth of image data, but the number of drawings must be increased, and there is a tendency to increase power consumption due to this. In a high-definition display panel of FHD (Full High Definition) or more in recent years, the increase in the total power consumption of the system becomes a problem, and in the display control device, low power consumption is also an urgent task, and in particular, the present inventors have intensively studied a technology for reducing power consumption in the interlaced driving method.

[0009] An object of the present application is to reduce power consumption generated by interlaced driving of a display panel.

[0010] The objects and new features of the present application described above and other objects and new features will become apparent from the description and drawings.

[0011] Solutions to the Problems

[0012] Briefly describing the outline of representative inventions among the inventions disclosed in this application, they are as follows. Also, the reference symbols and the like in the drawings described in parentheses in this item are an example for easy understanding.

[0013] That is, a driving stop period is inserted between the driving of the odd field and the driving of the even field in the interlaced driving. Further, when driving signals for driving sub-pixels are supplied to the display panel in a time-division manner per sub-pixel, the switching control signal of the source line switch allocated to the source line of the driving signal corresponding to each sub-pixel is changed in such a manner that the number of switching of the source line switch is reduced. Further specific schemes according to this viewpoint are as follows.

[0014] 〔1〕<Interval Interlaced Mode>

[0015] The display control device 1 has a gate line control section 10 for selecting and controlling the gate lines (Gl ~ Gn) of the display panel 3 in synchronization with the display timing, a source drive section 9 for applying driving signals to the source lines (Sl_R ~ Sx_B) arranged in cross to the gate lines of the display panel, and a control section 6 for controlling the gate line control section and the source drive section. The gate line control section outputs an odd gate line control signal (GSl) for the first odd gate line of the display panel and an even gate line control signal (GS2) for the first even gate line, respectively. The control section performs control for alternately activating the odd gate line control signal and the even gate line control signal in order of the gate lines in response to designation of the non-interlaced mode, performs control for alternately generating an odd field period (ACTodd) for sequentially activating the odd gate line control signal and deactivating the even gate line control signal, and an even field period (ACTevn) for sequentially activating the even gate line control signal and deactivating the odd gate line control signal in response to designation of the interlaced mode, and performs control for setting a gate stop period (STP) for deactivating both of the gate line control signals between the alternately generated odd field period and even field period in response to designation of the interval interlaced mode.

[0016] Thus, in the interval interlaced mode, in the gate stop period (STP) arranged between the alternately generated odd field period and even field period, both of the gate line control signals are deactivated, and therefore, it is possible to reduce the power consumption per unit time of the display control device.

[0017] 〔2〕<Interrupting supply of operating power to the source drive section during the gate stop period>

[0018] In item 1, the control section performs control for interrupting the supply of operating power to the source drive section corresponding to the gate stop period.

[0019] Thus, it is possible to further reduce power consumption per unit time in the interval stagger mode.

[0020] 〔3〕<In the inactive period of the gate line control signal in the stagger mode or the interval stagger mode, cut off the supply of the operating power to the source drive section>

[0021] In item 1, regardless of which of the stagger mode or the interval stagger mode is designated, the control section performs the following control: cut off the supply of the operating power to the source drive section in correspondence with the period during which the even-numbered gate line control signal is made inactive during the odd-numbered field period, and cut off the supply of the operating power to the source drive section in correspondence with the period during which the odd-numbered gate line control signal is made inactive during the even-numbered field period.

[0022] Thus, it is possible to further reduce power consumption per unit time in the interval stagger mode.

[0023] 〔4〕<Gate rest period variable>

[0024] In item 1, there is also a rest period setting register 5 that re-writably sets gate rest period data (STPP), and the control section controls the length of the rest period in accordance with the gate rest period data set by the rest period setting register.

[0025] Accordingly, it is possible to variably set the gate rest period as needed.

[0026] 〔5〕<Gate line control signal>

[0027] In item 1, the odd-numbered gate line control signal is an odd-numbered shift clock signal (ODD CLK1, ODD CLK2) for sequentially shifting back a stage to control a plurality of phases of odd-numbered shift data for selecting an odd-numbered gate line, the even-numbered gate line control signal is an even-numbered shift clock signal (EVN CLK1, EVN CLK2) for sequentially shifting back a stage to control a plurality of phases of even-numbered shift data for selecting an even-numbered gate line, and the inactive of the gate line control signal means that the clock change of the shift clock signal is stopped.

[0028] Accordingly, it is possible to perform selection control of the gate line by shift control using the shift data of the shift clock signal, and it is possible to simply make the gate line control signal inactive by stopping the clock change of the shift clock signal.

[0029] 〔6〕<Output synchronization signal enabled across the display period of each gate line>

[0030] In item 1, the source driving unit outputs the driving signal of the corresponding sub-pixel from the driving terminal (S1 to Sx) in a time-division manner for each sub-pixel during each display period (Hodd, Hevn) of a gate line. The gate line control unit outputs an output synchronization signal (ODD_SW1 to ODD_SW3, EVN_SW1 to EVN_SW3) corresponding to the output period for each sub-pixel output from the driving terminal in a time-division manner. Regardless of whether the non-interleaved mode, interleaved mode, or interleaved mode is specified, the control unit performs control that uses the last output synchronization signal of each display period (Hodd, Hevn) of a gate line as the initial output synchronization signal for the display period of the next gate line, and maintains this control in the gate line control unit.

[0031] Accordingly, when the drive signal is supplied to the display panel in a time-division manner for each sub-pixel, the number of source line switches assigned to the source line of the drive signal corresponding to each sub-pixel can be reduced. That is, by maintaining the output synchronization signal last output during each display period of a gate line as the initial output synchronization signal for the display period of the next gate line, the number of charging and discharging cycles of the source line switch switching control signal can be reduced.

[0032] [7] <Output synchronization signal when interleaving mode or interval interleaving mode is specified>

[0033] In item 6, the control unit performs the following control in response to the designation of either the interleaving mode or the interval interleaving mode: during the odd-numbered field, it maintains the output synchronization signal last output corresponding to the display period (Hodd) of each odd-numbered gate line as the initial output synchronization signal for the next odd-numbered gate line, and during the even-numbered field, it maintains the output synchronization signal last output corresponding to the display period (Hevn) of each even-numbered gate line as the initial output synchronization signal for the next even-numbered gate line.

[0034] Therefore, in either the interleaved pattern or the spaced interleaved pattern, the same effect as item 6 is achieved.

[0035] [8] <Interlaced Pattern>

[0036] The display panel module includes a display panel 3 and a display control device 1. The display control device includes a gate line control unit 10 that selects and controls the gate lines (G1-Gn) of the display panel synchronously with the display timing; a source drive unit 9 that applies drive signals in parallel to source lines (S1_R-Sx_B) arranged intersecting the gate lines of the display panel; and a control unit 6 that controls the gate line control unit and the source drive unit. The gate line control unit outputs an odd-numbered gate line control signal (GS1) for the odd-numbered gate lines and an even-numbered gate line control signal (GS2) for the even-numbered gate lines of the display panel. The control unit, in response to the designation of a non-interleaved mode, controls the alternating activation of the odd-numbered gate line control signal and the even-numbered gate line control signal on a gate line-by-gate line basis. In response to the designation of an interleaved mode, it controls the alternating generation of an odd-field period (ACTodd) that sequentially activates the odd-numbered gate line control signal and deactivates the even-numbered gate line control signal, and an even-field period (ACTevn) that sequentially activates the even-numbered gate line control signal and deactivates the odd-numbered gate line control signal. In response to the designation of an interleaved mode, it controls the setting of a gate rest period (STP) between the alternately generated odd-field period and even-field period, deactivating the gate line control signals of both.

[0037] Therefore, it achieves the same effect as item 1.

[0038] [9] <Disrupting the supply of operating power to the source drive unit during gate rest>

[0039] In item 8, the control unit controls the supply of operating power to the source drive unit to be cut off in accordance with the gate rest period.

[0040] Therefore, the same effect as item 2 is achieved.

[0041]

[10] <During the inactivity period of the gate line control signal in interleaved mode or spaced interleaved mode, the power supply to the source drive is cut off>

[0042] In item 8, regardless of whether the interleaving mode or the interval interleaving mode is specified, the control unit performs control to cut off the supply of operating power to the source drive unit during the odd field period corresponding to the period when the even gate line control signal is inactive, and to cut off the supply of operating power to the source drive unit during the even field period corresponding to the period when the odd gate line control signal is inactive.

[0043] Therefore, it achieves the same effect as item 3.

[0044]

[11] <Gate rest period can be variable>

[0045] In item 8, there is also a rest period setting register 5 that can be rewritten to set the gate rest period data (STPP), and the control unit controls the length of the rest period according to the gate rest period data set in the rest period setting register.

[0046] Therefore, it achieves the same effect as item 4.

[0047]

[12] <Gate line control signal>

[0048] In item 8, the display panel has an odd-numbered gate driver 21 that selects the odd-numbered gate line corresponding to the shift position of the shifted data in the odd-numbered shift register, and an even-numbered gate driver 22 that selects the even-numbered gate line corresponding to the shift position of the shifted data in the even-numbered shift register. The odd-numbered gate line control signal is an odd-numbered shift clock signal (ODD_CLK1, ODD_CLK2) used to sequentially shift and control multiple phases of the odd-numbered shifted data in the odd-numbered shift register to the next stage. The even-numbered gate line control signal is an even-numbered shift clock signal (EVN_CLK1, EVN_CLK2) used to sequentially shift and control multiple phases of the even-numbered shifted data in the even-numbered shift register to the next stage. The deactivation of the gate line control signal means that the clock change of the shift clock stops.

[0049] Therefore, it achieves the same effect as item 5.

[0050]

[13] <Output synchronization signal enabled during display across each gate line>

[0051] In item 8, the source driving unit outputs pixel data of its multiple pixels from the driving terminals (S1 to Sx) in a time-division manner for each sub-pixel during each display period of a gate line. The gate line control unit outputs an output synchronization signal (ODD_SW1 to ODD_SW3, EVN_SW1 to EVN_SW3) corresponding to the output period for each sub-pixel output in a time-division manner from the driving terminals. The display panel has a source line switching circuit 23 that distributes the driving signals output from the driving terminals in a time-division manner to the source lines (S1_R, S1_G, S1_B to Sx_R, Sx_G, Sx_B) of the sub-pixels, and the source line switching circuit uses the output synchronization signal as a switching control signal for each sub-pixel. Regardless of whether the non-interleaved mode, interleaved mode, or interleaved mode is specified, the control unit performs control such that the output synchronization signal last output during each display period (Hodd, Hevn) of a gate line is used as the initial output synchronization signal for the display period of the next gate line.

[0052] Therefore, it achieves the same effect as item 6.

[0053]

[14] <Output synchronization signal in the case of specified interleaving mode or interval interleaving mode>

[0054] In item 13, the control unit performs the following control in response to the designation of either the interleaving mode or the interval interleaving mode: during the odd-numbered field, it maintains the output synchronization signal last output corresponding to the display period (Hodd) of each odd-numbered gate line as the initial output synchronization signal for the next odd-numbered gate line, and during the even-numbered field, it maintains the output synchronization signal last output corresponding to the display period (Hevn) of each even-numbered gate line as the initial output synchronization signal for the next even-numbered gate line.

[0055] Therefore, it achieves the same effect as item 7.

[0056]

[15] <Distribution control of source epipolar lines for sub-pixel data supplied in a time-division manner>

[0057] The display control device (1) includes a gate line control unit 10 for selecting and controlling the gate lines (G1 to Gn) of the display panel 3 in synchronization with the display timing, a source drive unit (9) for applying drive signals to source lines (S1_R to Sx_B) arranged intersecting the gate lines of the display panel, and a control unit 6 for controlling the gate line control unit and the source drive unit. The gate line control unit outputs an odd-numbered gate line control signal (GS1) for the odd-numbered gate lines of the display panel and an even-numbered gate line control signal (GS2) for the even-numbered gate lines. The control unit, in response to the designation of a non-interleaved mode, controls the sequential alternating activation of the odd-numbered gate line control signals and the even-numbered gate line control signals on a gate line-by-gate line basis. In response to the designation of an interleaved mode, it controls the alternating generation of odd-numbered field periods (ACTodd) where the odd-numbered gate line control signals are activated sequentially and the even-numbered gate line control signals are muted, and even-numbered field periods (ACTevn) where the even-numbered gate line control signals are activated sequentially and the odd-numbered gate line control signals are muted. The source drive unit outputs the drive signals for its multiple pixels from the drive terminals (S1 to Sx) in a time-division manner for each sub-pixel of a gate line during each display period (Hodd, Hevn). The gate line control unit outputs an output synchronization signal (ODD_SW1 to ODD_SW3, EVN_SW1 to EVN_SW3) corresponding to its output period for each sub-pixel output from the drive terminals in a time-division manner. In response to the designation of a non-interleaved mode or an interleaved mode, the control unit performs control during the odd-numbered field to maintain the output synchronization signal last output corresponding to the display period (Hodd) of each odd-numbered gate line as the initial output synchronization signal for the next odd-numbered gate line, and during the even-numbered field to maintain the output synchronization signal last output corresponding to the display period (Hevn) of each even-numbered gate line as the initial output synchronization signal for the next even-numbered gate line.

[0058] Accordingly, in both non-interleaved and interleaved modes, when the drive signal is supplied to the display panel in a time-division manner for each sub-pixel, the number of source line switches assigned to the source line of the drive signal corresponding to each sub-pixel can be reduced. That is, by maintaining the output synchronization signal last output during each display period of one gate line as the initial output synchronization signal for the display period of the next gate line, the number of charging and discharging cycles of the source line switch switching control signal can be reduced.

[0059]

[16] <Distribution control of source epipolar lines for sub-pixel data supplied in a time-division manner>

[0060] The display panel module includes a display panel 3 and a display control device 1. The display control device includes a gate line control unit 10 that selects and controls the gate lines (G1-Gn) of the display panel synchronously with the display timing; a source drive unit 9 that applies drive signals in parallel to source lines (S1_R-Sx_B) arranged intersecting the gate lines of the display panel; and a control unit 6 that controls the gate line control unit and the source drive unit. The gate line control unit outputs an odd-numbered gate line control signal (GS1) for the odd-numbered gate lines and an even-numbered gate line control signal (GS2) for the even-numbered gate lines of the display panel. The control unit, in response to the designation of a non-interleaved mode, controls the sequential alternating activation of the odd-numbered gate line control signals and the even-numbered gate line control signals on a gate line-by-gate line basis. In response to the designation of an interleaved mode, it controls the alternating generation of odd-numbered field periods (ACTodd) where the odd-numbered gate line control signals are activated sequentially and the even-numbered gate line control signals are muted, and even-numbered field periods (ACTevn) where the even-numbered gate line control signals are activated sequentially and the odd-numbered gate line control signals are muted. The source drive unit outputs the drive signals for its multiple pixels from the drive terminals (S1 to Sx) in a time-division manner for each sub-pixel of a gate line during each display period (Hodd, Hevn). The gate line control unit outputs an output synchronization signal (ODD_SW1 to ODD_SW3, EVN_SW1 to EVN_SW3) corresponding to its output period for each sub-pixel output from the drive terminals in a time-division manner. The display panel has a source line switching circuit 23 that distributes pixel data output from the driving terminal in a time-division manner to the source lines (S1_R, S1_G, S1_B ~ Sx_R, Sx_G, Sx_B) of the sub-pixels. The source line switching circuit uses the output synchronization signal as a switching control signal for each sub-pixel. The control unit performs control during the odd-numbered field to maintain the output synchronization signal last output corresponding to the display period (Hood) of each odd-numbered gate line as the initial output synchronization signal for the next odd-numbered gate line, and during the even-numbered field to maintain the output synchronization signal last output corresponding to the display period (Hevn) of each even-numbered gate line as the initial output synchronization signal for the next even-numbered gate line.

[0061] Therefore, it can achieve the same effect as item 15.

[0062] Invention Effects

[0063] The effects obtained by means of representative inventions disclosed in this application will be briefly explained as follows.

[0064] That is, it can reduce the power consumption caused by the interleaved driving of the display panel. Attached Figure Description

[0065] Figure 1 This is a block diagram illustrating an example of a display control device.

[0066] Figure 2A This is a block diagram showing an example of a display panel.

[0067] Figure 2B This is a block diagram illustrating an example of an odd-numbered gate driver.

[0068] Figure 2C This is a block diagram illustrating an example of an even-numbered gate driver.

[0069] Figure 3 This is a block diagram illustrating the generation logic of gate line control signals and output synchronization signals in a display control device.

[0070] Figure 4 This is a block diagram illustrating an example of a switching circuit in a display panel.

[0071] Figure 5 This is a block diagram showing an example of a source drive unit in a display control device.

[0072] Figure 6 This is a diagram illustrating the operation under the staggered mode.

[0073] Figure 7 This is a diagram illustrating the operation under the staggered interval mode.

[0074] Figure 8 In the context of Figure 7 The diagram illustrates the operation of the interleaved mode when the gate rest period is set to be longer.

[0075] Figure 9 A diagram illustrating the operation under the alternating right and wrong mode.

[0076] Figure 10 This is a time diagram illustrating the switching control signal waveform of a switching circuit that distributes the source lines of the drive signals supplied to the display panel in a time-division manner in non-interleaved mode.

[0077] Figure 11 It is a time diagram illustrating the switching control signal waveform of the switching circuit that is distributed to the source line of the drive signal supplied to the display panel in a time-division manner in an odd field of interleaved mode or interval interleaved mode.

[0078] Figure 12 It is a time diagram illustrating the switching control signal waveform of the switching circuit that is distributed to the source line of the drive signal supplied to the display panel in a time-division manner in an even field of interleaved mode or interval interleaved mode.

[0079] Figure 13 It is relative to Figure 10 Timing diagram of a comparative example without considering reducing the number of switching operations of the switching circuit.

[0080] Figure 14 It is relative to Figure 12 Timing diagram of a comparative example without considering reducing the number of switching operations of the switching circuit.

[0081] Explanation of reference numerals in the attached figures

[0082] 1 Display control equipment

[0083] 2. Main unit

[0084] 3 Display Panel (DPML)

[0085] 4. System Interface Circuit (SYSIF)

[0086] 5. Register Circuit (REGC)

[0087] 6. Control Unit (TMGG)

[0088] 6B Amplifier Control Logic

[0089] 6A Control Logic

[0090] 7. Buffer Memory (BUFMRY)

[0091] 8. Grayscale Voltage Generation Circuit (GLYSCL)

[0092] 9. Source Drive Unit (SRCDRV)

[0093] 10 Gate line control section

[0094] 10A, 10B gate buffers

[0095] 11. Oscillator Circuit (OSC)

[0096] 12 Power Supply Circuit (PSC)

[0097] 20 Display Department

[0098] 21. Odd-number gate driver (GDRV1)

[0099] 22 Even-numbered gate drivers (GDRV2)

[0100] 23 Source Line Switching Circuit

[0101] 30. Signal Generation Logic (GSGNR)

[0102] 31 Shielding Control Logic (MSKCNT)

[0103] 32 AND gate

[0104] 40_1~40_x Level shifters

[0105] 41_1~41_x Grayscale voltage selection circuit

[0106] 42_1~42_x Source Amplifier

[0107] 43-line latch circuit

[0108] Input data for P1~Px

[0109] VP0~VP255 Grayscale voltage

[0110] V1~Vx drive signals

[0111] PXL display element (subpixel)

[0112] G1~Gn gate lines

[0113] S1_R~Sx_B Source Line

[0114] S1~Sx drive terminals

[0115] V1~Vx drive signals

[0116] SW1, SW2, SW3 Source line switches

[0117] GS1 (ODD_CLK1, ODD_CLK2) are odd-numbered gate line control signals.

[0118] GS2 (EVN_CLK1, EVN_CLK2) Even-numbered gate line control signals

[0119] ODD_SW1~ODD_SW3, EVN_SW1~EVN_SW3 output synchronization signals

[0120] ACTodd during odd-numbered periods

[0121] ACTevn Even-numbered periods

[0122] STP gate rest period

[0123] IMD Interleaved Mode Data

[0124] IVLIMD Interleaved Mode Data

[0125] STPP data during the hiatus

[0126] OCLK1, OCLK2 shift clocks

[0127] OMSK1 and OMSK2 shielded signals

[0128] ECLK1, ECLK2 shift clocks

[0129] EMSK1 and EMSK2 shielded signals

[0130] Hodd's horizontal display during the odd-numbered gate line

[0131] Hevn horizontal display period of the even-numbered gate line

[0132] Hevn_MSK Non-display period of the even-numbered gate line

[0133] Hodd_MSK Non-display period of the odd-numbered gate line

[0134] EX Waveform sustaining section. Detailed Implementation

[0135] exist Figure 1 The image illustrates a display control device according to one embodiment of the present invention. The display control device 1 is mounted on a glass substrate of a display panel (DPNL) 3, represented by a liquid crystal display panel, to form a display panel module (MDL). The display panel module (MDL) is mounted in electronic devices such as tablet computers and smartphones. The display control device 1 is connected to a host device 2, such as an application processor, and receives display data and display commands from the host device 2 executing the application program, and performs display drive control for displaying images on the display panel 3. The display panel 3 is, for example, as shown in the image. Figure 2A The example includes a display unit 20 and gate drivers 21 and 22. In the display unit 20, multiple display elements (sub-pixels) PXL, represented by a liquid crystal display element, are arranged in a matrix along the X and Y directions (one is representatively shown in the figure). On the X-direction, the corresponding gate lines G1 to Gn (n is any even number) are connected to the selection terminal (gate) of the selection transistor Tr in the display element PXL. On the Y-direction, the corresponding source lines S1_R to Sx_B (x is an integer greater than 2) are connected to the data input terminal of the selection transistor Tr in the display element. A common potential Vcom is applied to the reference terminals of the parallel capacitor elements C1 and C2 of the display element PXL. The parallel capacitor elements C1 and C2 represent the capacitive component C1 of the liquid crystal element and the charge storage capacitor C2 connected in parallel with it. The display element PXL is arranged in sub-pixel units; for example, one color pixel consists of three sub-pixels PXL: R (red), G (green), and B (blue). Therefore, the source lines S1_R to Sx_B are set in sub-pixel units. The subscripts R, G, and B accompanying the reference symbols of the source lines indicate the type of sub-pixel.

[0136] existFigure 2A In the example, the gate drivers 21 and 22 are configured to drive the display element PXL in an interleaved manner, and are divided left and right as odd gate drivers (GDRV1) 21 for driving the odd gate lines G1, G3 to Gn-1 and even gate drivers (GDRV2) 22 for driving the even gate lines G2, G4 to Gn. The mounting space of the gate drivers is not biased to either the left or right. Figure 2B This is a block diagram schematically illustrating the structure of the odd-number gate driver 21. The odd-number gate driver 21 comprises multiple stages 2121, 2123, ... 212 connected in series, each equipped with master / slave latches. n-1 It consists of shift register 211. Multiple stages 2121, 2123, ... 212 n-1 These are connected to the odd-numbered gate lines G1, G3 to Gn-1, respectively. The odd-numbered gate driver 21 uses, for example, a two-phase shift clock (ODD_CKL1, ODD_CLK2) to synchronize the shifted data from the primary stage 2121 to the final stage 212, in sync with the display timing. n-1 By shifting sequentially, gate lines G1, G3 to Gn-1 can be selected in sequence. Figure 2C This is a block diagram schematically showing the structure of the even-number gate driver 22. Similar to the odd-number gate driver 21, the even-number gate driver 22 consists of multiple stages 2222, 2224, ... 222 connected in series, each equipped with master / slave latches. n It consists of shift registers 221. Multiple stages 2221, 2223, ... 222 n-1 These are connected to the even-numbered gate lines G2, G4 to Gn, respectively. The even-numbered gate driver 22 also synchronizes the shifted data from the primary stage 2221 to the final stage 222 via, for example, a two-phase shift clock (EVN_CKL1, EVN_CLK2) in time with the display timing. n-1 By shifting sequentially, gate lines G2, G4 to Gn can be selected sequentially. The shift clocks supplied to the odd-numbered gate driver 21 and the even-numbered gate driver 22 have a 180-degree phase difference, so the odd-numbered and even-numbered gate lines will not be selected together. Furthermore, the parallel row of display elements with gate lines connected in parallel is called a display row.

[0137] Display control device 1, such as Figure 1As illustrated, it has a system interface circuit (SYSIF) 4, a register circuit (REGC) 5, a control unit (TMGG) 6, a FIFO (First-In First-Out) type buffer memory (BUFMRY) 7, a grayscale voltage generation circuit (GLYSCL) 8, a source drive unit (SRCDRV) 9, a gate line control unit 10, an oscillator circuit (OSC) that generates an internal clock signal 11, and a power supply circuit (PSC) 12.

[0138] The system interface circuit 4 receives display commands and other control data from the host device 2. Furthermore, the control unit 6 outputs response and status information back to the host device 2. Additionally, the system interface circuit 4 inputs image data supplied from the host device 2 according to a specified bus interface specification or high-speed serial interface specification.

[0139] System interface circuit 4 operates by accepting an external input power supply voltage. Power supply circuit 12 receives external logic power supply voltage and analog power supply voltage to generate internal power supply voltages for digital and analog circuits. The internal analog power supply voltage for analog circuits is used as the operating power supply for grayscale voltage generation circuit 8, source drive unit 9, and gate line control unit 10. The internal power supply voltage for logic circuits is supplied to logic circuits such as control unit 6.

[0140] The control unit 6 temporarily stores the image data supplied from the host device 2 in the buffer memory 7. The image data stored in the buffer memory 7, or the image data supplied from the host device 2 as an image data stream, is latched in the line latch circuit 43 of the source drive unit 9 (see reference 1). Figure 5 In the image, although not specifically limited, the row latch circuit 43 latches the input data P1 to Px in a time-division manner for each sub-pixel along one gate line. For each gate line, for example, the red input data P1 to Px is latched initially, followed by the green input data P1 to Px, and finally the blue input data P1 to Px. The input data P1 to Px is image data for x sub-pixels; although not specifically limited, N bits, for example 8 bits, are used for each sub-pixel.

[0141] The grayscale voltage generation circuit 8 generates, for example, grayscale voltages VP0 to VP255 of 256 grayscale as gamma-corrected grayscale voltages.

[0142] The source drive unit 9 selects grayscale voltages VP0 to VP255 corresponding to the values ​​of each sub-pixel of the input data P1 to Px, thereby generating multiple-bit drive signals V1 to Vx for each sub-pixel. The drive signals V1 to Vx are generated as voltage signals. For example... Figure 5As illustrated, the source drive unit 9 shifts the data P1 to Px latched in the row latch 43 from the logic voltage scale to the analog voltage scale level using N-bit sub-pixel unit level shifters 40_1 to 40_x. The grayscale voltage selection circuits 41_1 to 41_x select the grayscale voltage corresponding to the level-shifted data, and output the selected grayscale voltage as drive signals V1 to Vx from the drive terminals S1 to Sx via the source amplifiers 42_1 to 42_x, which act as buffer amplifiers. The operating power supply of the level shifters 40_1 to 40_x, the grayscale voltage selection circuits 41_1 to 41_x, and the source amplifiers 42_1 to 42_x is a high-voltage analog power supply (12V) compared to the power supply for the logic circuits (e.g., 3.3V). The supply / disconnection of the analog power supply to those circuits can be controlled by the analog power supply control signal 44. The analog power supply control signal 44 is generated by the amplifier control logic 6B within the control unit 6.

[0143] Drive signals V1 to Vx are supplied to the display panel 3 from drive terminals S1 to Sx. When the input data P1 to Px is, for example, 8-bit image data with 256 gray levels per sub-pixel, the number of sub-pixels in one display row is 512 × 3 = 1536. Therefore, the input data P1 to Px is 512 bytes of data. In order to drive one display row, each 512 bytes is input in a time-division manner according to each RGB value, totaling 1536 bytes.

[0144] like Figure 4 As illustrated, the drive signals V1 to Vx output from the drive terminals S1 to Sx are supplied to the source line switching circuit 23 of the display panel 3. The source line switching circuit 23 distributes the drive signals V1 to Vx supplied from the drive terminals S1 to Sx in a time-division manner according to each of the R, G, and B of the sub-pixel to the source lines S1_R, S1_G, S1_B to Sx_R, Sx_G, Sx_B of the sub-pixel. The source line switching circuit 23 has three source line switches SW1, SW2, and SW3 for each of the drive signals V1 to Vx, and is capable of distributing the time-division supplied R, G, and B drive signals V1 to Vx to the source lines corresponding to R, G, and B. Source line switch SW1 is controlled by ORing or logically summing the output synchronization signals ODD_SW1 and EVN_SW1. Source line switch SW2 is controlled by ORing or logically summing the output synchronization signals ODD_SW2 and EVN_SW2. Source line switch SW3 is controlled by ORing or logically summing the output synchronization signals ODD_SW3 and EVN_SW3.

[0145] Gate line control unit 10 Figure 1 and Figure 2AAs illustrated, odd-numbered gate line control signals GS1 (ODD_CLK1, ODD_CLK2) are generated as two-phase shift clocks for selecting the odd-numbered gate lines G1, G3, ..., Gn-1 of the display panel 3, and even-numbered gate line control signals GS2 (EVN_CLK1, EVN_CLK2) are generated as two-phase shift clocks for selecting the even-numbered gate lines G2, G4, ..., Gn, and supplied to gate drivers 21 and 22, respectively. The odd-numbered gate line control signals ODD_CLK1 and ODD_CLK2 supplied to the odd-numbered gate driver 21 as shift clocks and the even-numbered gate line control signals EVN_CLK1 and EVN_CLK2 supplied to the even-numbered gate driver 22 as shift clocks have a 180-degree phase difference, and the odd-numbered and even-numbered gate lines will not be selected together. That is, the odd-numbered gate line control signals ODD_CLK1 and ODD_CLK2 and the even-numbered gate line control signals EVN_CLK1 and EVN_CLK2 are activated alternately in sequence. For example... Figure 3 As shown, odd numbers are output from gate buffer (GBUF1) 10A using gate line control signals ODD_CLK1 and ODD_CLK2, while even numbers are output from gate buffer (GBUF2) 10B using gate line control signals EVN_CLK1 and EVN_CLK2.

[0146] Furthermore, the gate line control unit 10 generates the output synchronization signals ODD_SW1~ODD_SW3 (SS1) and EVN_SW1~EVN_SW3 (SS2) and supplies them to the switching circuit 23. The on-time periods of the source line switches SW1, SW2, and SW3 caused by the output synchronization signals ODD_SW1~ODD_SW3 and EVN_SW1~EVN_SW3 do not overlap, and the same drive signal is not supplied to the source lines of different sub-pixels. That is, the output synchronization signals ODD_SW1~ODD_SW3 and EVN_SW1~EVN_SW3, which serve as switch control signals, have the significance of being output synchronization signals. When these output synchronization signals output the drive signals of multiple pixels of one gate line in a time-division manner according to each sub-pixel of R, G, and B in each display period, each sub-pixel output in a time-division manner is output corresponding to its output period. For example... Figure 4 As shown, the output synchronization signals ODD_SW1 to ODD_SW3 are output from gate buffer 10A, and the output synchronization signals EVN_SW1 to EVN_SW3 are output from gate buffer 10B.

[0147] The control unit 6 interprets the commands supplied from the host device 2 and, with reference to the control data set in the register circuit 5, performs internal operation control of the entire display control device 1 for display control of the display panel 3.

[0148] Here, the operating modes performed by the display control device are non-interleaved mode, interleaved mode, and intermittent interleaved mode.

[0149] When a non-interleaved mode is specified, the control unit 6 controls the alternating activation of the odd-number gate line control signal GS1 and the even-number gate line control signal GS2 on a gate line-by-gate-line basis.

[0150] When the interleaving mode is specified, control unit 6, as follows: Figure 6 As illustrated, control is performed by alternately generating ACTodd during the odd-numbered field period when the odd-numbered gate line control signals ODD_CLK1 and ODD_CLK2 are activated and the even-numbered gate line control signals EVN_CLK1 and EVN_CLK2 are deactivated, and ACTevn during the even-numbered field period when the even-numbered gate line control signals EVN_CLK1 and EVN_CLK2 are activated and the odd-numbered gate line control signals ODD_CLK1 and ODD_CLK2 are deactivated.

[0151] When the specified interval interleaving mode is used, the control unit 6, as follows: Figure 7 and Figure 8 As illustrated, control is performed during the gate rest period STP, which sets the gate line control signals of both sides to be inactive between the alternately generated odd field period ACTodd and even field period ACTevn.

[0152] exist Figure 3 The example illustrates control logic 6A for generating odd-number gate line control signals ODD_CLK1, ODD_CLK2, even-number gate line control signals EVN_CLK1, EVN_CLK2, output synchronization signals ODD_SW1 to ODD_SW3 that are sequentially activated in accordance with the selection of odd-number gate lines, and output synchronization signals EVN_SW1 to EVN_SW3 that are sequentially activated in accordance with the selection of even-number gate lines, corresponding to the specified operating mode described above.

[0153] Control logic 6A is included in control unit 6 and includes signal generation logic (GSGNR) 30, shielding control logic (MSKCNT) 31, and multiple AND gates 32. Register circuit 5 has setting areas for interleaved mode data IMD, interval interleaved mode data IVLIMD, rest period data STPP, horizontal synchronization period data, and vertical synchronization period data, etc. These areas are loaded with initial values ​​from non-volatile memory (not shown) during system reset. In addition, they can be made to be rewritten by host device 2 or fixed to desired values ​​by pull-up / pull-down control signals.

[0154] Signal generation logic 30 and shielding control logic 31 receive the setting data from register circuit 5 and synchronously generate shift clocks OCLK1, OCLK2 and shielding signals OMSK1, OMSK2 for odd-number gate line control signals ODD_CLK1 and ODD_CLK2, and generate shift clocks ECLK1, ECLK2 and shielding signals EMSK1, EMSK2 for even-number gate line control signals EVN_CLK1 and EVN_CLK2. Furthermore, they generate non-overlapping three-phase clocks ONCK1 to ONCK3 for output synchronization signals ODD_SW1 to ODD_SW3, and non-overlapping three-phase clocks ENCK1 to ENCK3 for output synchronization signals EVN_SW1 to EVN_SW3.

[0155] When the shielding signal OMSK1 is inactive, clock signal OCLK1 is output from gate buffer 10A as odd-number gate line control signal ODD_CLK1 through the corresponding AND gate 32. Similarly, when the shielding signal OMSK2 is inactive, clock signal OCLK2 is output from gate buffer 10A as odd-number gate line control signal ODD_CLK2 through the corresponding AND gate 32. Likewise, when the shielding signal EMSK1 is inactive, clock signal ECLK1 is output from gate buffer 10B as even-number gate line control signal EVN_CLK1 through the corresponding AND gate 32. When the shielding signal EMSK2 is inactive, clock signal ECLK2 is output from gate buffer 10B as even-number gate line control signal EVN_CLK2 through the corresponding AND gate 32.

[0156] In the case of setting a non-interleaved mode, such as Figure 9As illustrated, when the shift clocks OCLK1, OCLK2 and ECLK1, ECLK2 are activated and staggered by 180 degrees during clock changes, the masking signals OMSK1, OMSK2 and EMSK1, EMSK2 are deactivated. As a result, the odd-numbered gate line control signals ODD_CLK1, ODD_CLK2 and the even-numbered gate line control signals EVN_CLK1, EVN_CLK2 are staggered by 180 degrees during clock changes, thus allowing the ACTflm gate drivers 21, 22 to alternately select gate lines during each frame. That is, during each frame, the ACTflm gate driver 21 (GDRV1) selects gate lines in the order of G1, G3, ..., Gn-1, and the gate driver 22 (GDRV2) selects gate lines in the order of G2, G4, ..., Gn. As a whole, gate drivers 21 and 22 select the gate lines G1, G2, G3, G4...Gn-1, Gn in the order of their spatial arrangement during each frame of ACTflm (i.e., in the order of their spatial arrangement). During one frame of ACTflm, the source driver 9 outputs a drive signal corresponding to one frame of image data to the source lines S1_R to Sx_B in a timing synchronization with the selection of the gate lines.

[0157] When setting the interleaving mode, such as Figure 6As illustrated, when shift clocks OCLK1, OCLK2 and ECLK1, ECLK2 are activated and shifted 180 degrees out of phase during clock changes, the masking signals OMSK1, OMSK2 are inactive during odd-numbered periods (ACTodd) and active during even-numbered periods (ACTevn). Similarly, the masking signals EMSK1, EMSK2 are inactive during even-numbered periods (ACTevn) and active during odd-numbered periods (ACTodd). As a result, during odd-numbered periods (ACTodd), the odd-numbered gate line control signals ODD_CLK1, ODD_CLK2 undergo clock changes, while the even-numbered gate line control signals EVN_CLK1, EVN_CLK2 stop clock changes. Consequently, gate driver 21 (GDRV1) selects gate lines G1, G3, ..., Gn-1 in sequence, while gate driver 22 (GDRV2) does not select gate lines G2, G4, ..., Gn. During the even-numbered field period ACTevn, the even-numbered gate line control signals EVN_CLK1 and EVN_CLK2 undergo clock changes, while the odd-numbered gate line control signals ODD_CLK1 and ODD_CLK2 stop clock changes. Therefore, gate driver 22 (GDRV2) selects gate lines G2, G4, ..., Gn in sequence, while gate driver 21 (GDRV1) does not select gate lines G1, G3, ..., Gn-1. During the odd-numbered field period ACTodd, the source driver 9 outputs drive signals corresponding to the image data of the odd-numbered field quantities within one frame to the source lines S1_R to Sx_B in a timing synchronized with the gate line selection. During the even-numbered field period ACTevn, the source driver 9 outputs drive signals corresponding to the image data of the even-numbered field quantities within one frame to the source lines S1_R to Sx_B in a timing synchronized with the gate line selection.

[0158] When the interval interleaving mode is set, such as Figure 7As illustrated, the gate rest period STP, which stops the clock changes of both the odd-numbered gate line control signals ODD_CLK1, ODD_CLK2 and the even-numbered gate line control signals EVN_CLK1, EVN_CLK2, is inserted between the alternately generated odd-numbered field period ACTodd and even-numbered field period ACTevn, differs from the interleaved mode. Specifically, after the odd-numbered field period ACTodd, a period is inserted where both the mask signals OMSK1, OMSK2 and EMSK1, EMSK2 are active (masked), stopping the clock changes of both the odd-numbered gate line control signals ODD_CLK1, ODD_CLK2 and the even-numbered gate line control signals EVN_CLK1, EVN_CLK2, thereby temporarily halting the display drive operation. The length of the gate rest period STP is controlled by the mask control logic 31 according to the gate rest period data STPP set in register circuit 5. During the gate rest period (STP), the amplifier control logic 6B blocks the power supply to the level shifters 40_1 to 40_n, the grayscale voltage selection circuits 41_1 to 41_n, and the source amplifiers 42_1 to 42_n, which are not required to operate at that time.

[0159] In the interleaved mode, during the gate rest period STP configured between the alternately generated odd-numbered field period ACTodd and even-numbered field period ACTevn, the gate line control signals ODD_CLK1, ODD_CLK2 and EVN_CLK1, EVN_CLK2 are inactive. Therefore, the power consumption per unit time of the display control device 1 can be reduced. Furthermore, during the gate rest period STP, the amplifier control logic 6B blocks the power supply to the source amplifiers 42_1 to 42_n of the source drive section 9, thereby further reducing power consumption.

[0160] In interleaved mode, the gate rest period STP can be programmably set according to the gate rest period data STPP written in register circuit 5. For example... Figure 8 As illustrated, the STP duration (xxms) during the gate rest period is variable. Similarly, the odd-numbered field period (ACTodd) and even-numbered field period (ACTevn) are variable based on the vertical synchronization period data written in register circuit 5. Figure 8 As illustrated, the time yyms of ACTodd during odd-numbered fields and ACTevn during even-numbered fields is variable.

[0161] Signal generation logic 30 controls the non-overlapping three-phase clocks ONCK1 to ONCK3 for odd-numbered fields to a high level during the switch-on period in a predetermined sequence during each horizontal period. Furthermore, corresponding to the interleaved mode or the interval interleaved mode, a waiting period of one horizontal period is inserted into the non-overlapping three-phase clocks ONCK1 to ONCK3 to await clock changes. Similarly, signal generation logic 30 controls the non-overlapping three-phase clocks ENCK1 to ENCK3 for even-numbered fields to a high level during the switch-on period in a predetermined sequence during each horizontal period. Furthermore, corresponding to the interleaved mode or the interval interleaved mode, a waiting period of one horizontal period is inserted into the non-overlapping three-phase clocks ENCK1 to ENCK3 to await clock changes. Here, the non-overlapping three-phase clocks ENCK1 to ENCK3 and ONCK1 to ONCK3 are configured as signals that change in phase. In this way, the non-overlapping three-phase clocks ONCK1 to ONCK3, which are controlled by waveforms, are output as output synchronization signals ODD_SW1 to ODD_SW3 from gate buffer 10A. Similarly, the non-overlapping three-phase clocks ENCK1 to ENCK3, which are controlled by waveforms, are output as output synchronization signals EVN_SW1 to EVN_SW3 from gate buffer 10B.

[0162] When setting the non-interleaved mode, output synchronization signals ODD_SW1~ODD_SW3, EVN_SW1~EVN_SW3. Figure 10 The waveform varies with the clock waveform. Hodd is the horizontal display period for the odd-numbered gate line, and Hevn is the horizontal display period for the even-numbered gate line. Specifically, waveform control is performed such that the output synchronization signal output at the end of each display period (Hodd, Hevn) of a gate line is used as the initial output synchronization signal for the display period of the next gate line. The portion of the waveform that is maintained is shown in Figure EX. Without this consideration, the waveform of the output synchronization signal is made as follows: Figure 13 That way. With Figure 13 In comparison, Figure 10 In this case, the number of switching operations of the source line switches SW1, SW2, and SW3, which are allocated to the source line of the drive signal corresponding to each sub-pixel, can be reduced. That is, by maintaining the output synchronization signal that will be last output during each display period of one gate line as the initial output synchronization signal for the display period of the next gate line, the number of charging and discharging operations of the switching control signals of the source line switches SW1, SW2, and SW3 can be reduced. In this respect, the power consumed by the gate line control unit 10 can be reduced.

[0163] When setting the interleaved mode or the interval interleaved mode, output synchronization signals ODD_SW1~ODD_SW3, EVN_SW1~EVN_SW3 as follows: Figure 11 and Figure 12The clock waveform shown changes accordingly. This corresponds to the display of odd-numbered fields. Figure 11 In this context, Hodd represents the horizontal display period for the odd-numbered gate line, and Hevn_MSK represents the non-display period for the even-numbered gate line, which is also the sustain period of the clock waveform. This corresponds to the display period for even-numbered fields. Figure 12 In this context, Hevn is the horizontal display period for the even-numbered gate line, and Hodd_MSK is the non-display period for the odd-numbered gate line and also the sustain period for the clock waveform. The sustain periods (Hevn_MSK, Hodd_MSK) are, similarly, the periods during which the output synchronization signal output at the end of each display period (Hodd, Hevn) for one gate line is used as the initial output synchronization signal for the display period of the next gate line. Figure 11 , Figure 12 In the diagram, the portion that maintains the waveform is shown as EX in Figure 1. Without this consideration, the waveform of the output synchronization signal is made as follows: Figure 14 That way. With Figure 14 In comparison, Figure 11 , Figure 12 In this case, the number of switching operations of the source line switches SW1, SW2, and SW3 allocated to the source line of the drive signal corresponding to each sub-pixel can be reduced, thus reducing the number of charging and discharging operations of the switching control signals of the source line switches SW1, SW2, and SW3. In this respect, the power consumed by the gate line control unit 10 can be reduced.

[0164] According to the embodiments described above, a gate rest period is inserted between the odd-numbered and even-numbered periods in the interleaved drive. Both the odd-numbered gate line control signal and the even-numbered gate line control signal are inactive during the gate rest period, thus reducing the power consumption per unit time of the display control device 1. During the gate rest period, the power supply to the source amplifier and the like of the source drive unit 9 is also stopped, thus further reducing power consumption. Furthermore, when the drive signal is supplied to the display panel 3 in a time-division manner for each sub-pixel, the switching control signals of the source line switches SW1, SW2, and SW3, which are assigned to the source lines of the drive signal corresponding to each sub-pixel, are changed in a way that reduces the number of switching operations. Therefore, the number of charging and discharging operations of the switching control signals of the source line switches SW1, SW2, and SW3 is reduced, which reduces the power consumed by the gate line control unit 10.

[0165] The invention made by the inventor has been specifically described above based on the implementation method. However, the invention is not limited thereto, and various modifications can be made without departing from its spirit.

[0166] For example, in the above embodiment, the source line switches are driven from both sides by outputting synchronization signals ODD_SW1 to ODD_SW3 and EVN_SW1 to EVN_SW3. Figure 4 Therefore, the output synchronization signals ODD_SW1~ODD_SW3 and EVN_SW1~EVN_SW3 are in-phase signals. However, the present invention is not limited to this and can also be driven on one side. In this case, the output synchronization signals ODD_SW1~ODD_SW3 and EVN_SW1~EVN_SW3 can also be configured to have staggered clock phases in odd field displays and even field displays.

[0167] Furthermore, the gate line control signal is not limited to a two-phase shift clock for the shift register, but can also be three-phase or more. In addition, it is not limited to the shift clock for the shift register, but can also be appropriately modified for control data of the decoder, etc.

[0168] In display control devices, a touch panel controller that not only performs display control functions but also performs touch detection control of a touch panel integrated with the display panel can be mounted on a chip, and other circuit modules such as a local processor can also be mounted on the chip. The display control device is not limited to a single chip; it can also be a multi-chip module packaged by mounting multiple chips on a module substrate.

[0169] The controlled object of the display control device is not limited to liquid crystal display panels; it can also be other display panels such as electroluminescent panels or plasma display panels.

Claims

1. A display control device, comprising: The gate line control unit is configured to control and synchronize the selection of the gate lines of the display panel with the display timing. The source driving section is configured to apply a driving signal to a source line that is arranged to intersect with the gate line of the display panel; as well as The control circuit is configured to control the gate line control unit and the source drive unit. The gate line control section outputs control signals for selecting odd-numbered gate lines of the display panel and control signals for selecting even-numbered gate lines. The control circuit is configured to provide a gate rest period between at least a portion of two adjacent periods during odd-numbered and even-numbered fields, wherein... During the odd-numbered field, the control signals for the odd-numbered gate lines are sequentially activated while the control signals for the even-numbered gate lines are deactivated. During the even-numbered field, the control signals for the even-numbered gate lines are sequentially activated while the control signals for the odd-numbered gate lines are deactivated. During the gate rest period, the control signals for the odd-numbered gate lines and the control signals for the even-numbered gate lines are both deactivated; and The gate line control unit outputs output synchronization signals, each of which specifies the output period during which a drive signal for a corresponding sub-pixel type is output from the drive terminal in a time-division manner. In all of the non-interleaved mode, interleaved mode, and interleaved mode, the control circuit performs control to first enable the output synchronization signal that was last enabled during the display period associated with the next gate line of the specified gate line, such that the output synchronization signal that was last enabled during the display period associated with the specified gate line remains enabled until the start of the display period associated with the next gate line of the specified gate line.

2. The display control device according to claim 1, wherein, The control circuit is configured to perform control that cuts off the supply of operating power supply voltage to the source drive during the gate rest period.

3. The display control device according to claim 1, wherein, When either the interleaving mode or the interval interleaving mode is specified, the control circuit is configured to perform control such that: during each odd field, the supply of the operating power supply voltage to the source driver is cut off during a period when the control signal for the even gate lines is inactive, and during each even field, the supply of the operating power supply voltage to the source driver is cut off during a period when the control signal for the odd gate lines is inactive.

4. The display control device according to claim 1 further comprises a rest period setting register that can be rewritten to set the gate rest period data. in, The control circuit is configured to control the length of the gate rest period in response to the gate rest period data set into the rest period setting register.

5. The display control device according to claim 1, wherein, The control signals for the odd-numbered gate lines include multi-phase odd-numbered shift clock signals. These multi-phase odd-numbered shift clock signals are used to sequentially shift odd-numbered shift data from the primary stage to the final stage of the odd-numbered shift register. The odd-numbered shift data is used to select the odd-numbered gate lines. The control signals for the even-numbered gate lines include multi-phase even-numbered shift clock signals, which are used to shift even-numbered shift data sequentially from the primary stage to the final stage of the even-numbered shift register. Furthermore, the deactivation of the gate line control signals is achieved by stopping the switching of the signal levels of the multi-phase odd-numbered shift clock signals and the multi-phase even-numbered shift clock signals.

6. The display control device according to claim 1, wherein, During each display period associated with each gate line, the source drive unit outputs the drive signal from the drive terminal to the sub-pixel associated with each gate line in a time-division manner, on a sub-pixel type basis.

7. The display control device according to claim 1, wherein, In response to specifying the interleaving mode or the interval interleaving mode, the control circuitry is configured to perform control to first enable, during each of the odd-numbered fields, in the display period associated with the next odd-numbered gate line, the output synchronization signal that was last enabled in the display period associated with each of the odd-numbered gate lines, such that the output synchronization signal that was last enabled in the display period associated with each of the odd-numbered gate lines remains enabled until the display period associated with the next odd-numbered gate line; and to perform control to first enable, during each of the even-numbered fields, in the display period associated with the next even-numbered gate line, the output synchronization signal that was last enabled in the display period associated with each of the even-numbered gate lines, such that the output synchronization signal that was last enabled in the display period associated with each of the even-numbered gate lines remains enabled until the display period associated with the next even-numbered gate line.

8. A display panel module, comprising: Display panel; as well as Display control equipment, including: A gate line control unit is configured to control and synchronize the selection of the gate lines of the display panel with the display timing. A source driving section is configured to apply driving signals in parallel to source lines arranged intersecting the gate lines of the display panel; and The control circuit is configured to control the gate line control unit and the source drive unit. The gate line control section outputs control signals for selecting odd-numbered gate lines of the display panel and control signals for selecting even-numbered gate lines. The control circuit is configured to provide a gate rest period between at least a portion of two adjacent fields during odd-numbered and even-numbered fields. During the odd-numbered field period, the control signals for the odd-numbered gate lines are sequentially activated while the control signals for the even-numbered gate lines are deactivated. During the even-numbered field period, the control signals for the even-numbered gate lines are sequentially activated while the control signals for the odd-numbered gate lines are deactivated. During the gate rest period, the control signals for the odd-numbered gate lines and the control signals for the even-numbered gate lines are both deactivated. The gate line control unit outputs output synchronization signals, each of which specifies the output period during which a drive signal for a corresponding sub-pixel type is output from the drive terminal in a time-division manner. The display panel includes a source line switching circuit, which distributes the driving signals corresponding to the respective sub-pixels, which are output from the driving terminals to the source lines in a time-division manner. The source line switching circuit uses the output synchronization signal as a switching control signal for the corresponding sub-pixel type. In all of the non-interleaved mode, interleaved mode, and interleaved mode, the control circuit performs control to first enable the output synchronization signal that was last enabled during the display period associated with the next gate line of the specified gate line, such that the output synchronization signal that was last enabled during the display period associated with the specified gate line remains enabled until the start of the display period associated with the next gate line of the specified gate line.

9. The display panel module according to claim 8, wherein, The control circuit is configured to perform control that cuts off the supply of operating power supply voltage to the source drive during the gate rest period.

10. The display panel module according to claim 8, wherein, When either the interleaving mode or the interval interleaving mode is specified, the control circuit is configured to perform control such that: in each of the odd-numbered fields, the supply of the operating power supply voltage to the source driver is cut off during the period when the control signal for the even-numbered gate lines is deactivated, and in each of the even-numbered fields, the supply of the operating power supply voltage to the source driver is cut off during the period when the control signal for the odd-numbered gate lines is deactivated.

11. The display panel module according to claim 8, further comprising a rest period setting register capable of rewriting and setting gate rest period data, in, The control circuit is configured to control the length of the gate rest period in response to the gate rest period data set into the rest period setting register.

12. The display panel module according to claim 8, wherein, The display panel includes: An odd-number gate driver configured to select the odd-number gate line in response to odd-number shift data shifted in an odd-number shift register; and An even-number gate driver is configured to select the even-number gate line in response to even-number shift data shifted in an even-number shift register; The control signals for the odd-numbered gate lines include multi-phase odd-numbered shift clock signals. These multi-phase odd-numbered shift clock signals are used to sequentially shift the odd-numbered shift data from the primary stage to the final stage of the odd-numbered shift register. The odd-numbered shift data is used to select the odd-numbered gate lines. The control signals for the even-number gate lines include multi-phase even-number shift clock signals, which are used to shift the even-number shift data sequentially from the primary stage to the final stage of the even-number shift register. Furthermore, the deactivation of the odd-number gate line control signal and the even-number gate line control signal is achieved by stopping the switching of the signal levels of the odd-number shift clock signal and the even-number shift clock signal.

13. The display panel module according to claim 8, wherein, During each display period associated with each gate line, the source drive unit outputs the drive signal from the drive terminal to the sub-pixel associated with each gate line in a time-division manner, on a sub-pixel type basis.

14. The display panel module according to claim 8, wherein, In response to specifying the interleaving mode or the interval interleaving mode, the control circuit performs control to first enable, during each of the odd-numbered fields, in the display period associated with the next odd-numbered gate line, the output synchronization signal that was last enabled in the display period associated with each of the odd-numbered gate lines, such that the output synchronization signal that was last enabled in the display period associated with each of the odd-numbered gate lines remains enabled until the display period associated with the next odd-numbered gate line; and performs control to first enable, during each of the even-numbered fields, in the display period associated with the next even-numbered gate line, the output synchronization signal that was last enabled in the display period associated with each of the even-numbered gate lines, such that the output synchronization signal that was last enabled in the display period associated with each of the even-numbered gate lines remains enabled until the display period associated with the next even-numbered gate line.

Images