Semiconductor device with non-electrical connection

Abstract

The present disclosure relates to a semiconductor device including: a semiconductor chip having a high-frequency circuit and a high-frequency terminal; an external high-frequency terminal; and a non-electrical connection arranged between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal, wherein the non-electrical connection is designed to transmit a high-frequency signal.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor technology. In particular, the present disclosure relates to a semiconductor device having non-electrical connections and a method for manufacturing such a semiconductor device. Background Art

[0002] In semiconductor devices, electrical connections for transmitting high-frequency signals are typically made using metal signal lines. For example, high-frequency signals may be routed from the device's semiconductor chip through the device housing to an application circuit board. Semiconductor device manufacturers are striving to provide improved semiconductor devices and methods for manufacturing them. In particular, it may be desirable to provide high-frequency semiconductor devices and methods for manufacturing them that exhibit minimal performance loss and a reduced likelihood of failure. Summary of the Invention

[0003] Various aspects of the present disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor chip having a high-frequency circuit and a high-frequency terminal. The semiconductor device also includes an external high-frequency terminal. The semiconductor device also includes a non-electrical connection arranged between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal, wherein the non-electrical connection is designed to transmit a high-frequency signal.

[0004] Various aspects of the present disclosure also relate to a method for manufacturing a semiconductor device, comprising forming a non-electrical connection between a high-frequency terminal of a semiconductor chip of the semiconductor device and an external high-frequency terminal of the semiconductor device, wherein the non-electrical connection is designed to transmit a high-frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The semiconductor device with non-electrical connection and the related manufacturing method according to the present invention are described in more detail below with reference to the accompanying drawings. The elements shown in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals may represent the same components.

[0006] Figure 1 schematically illustrates a portion of a cross-sectional side view of a semiconductor device 100 according to the present disclosure, the semiconductor device being mounted on a circuit board;

[0007] Figure 2 schematically illustrates a portion of a top view of a semiconductor device 200 according to the present disclosure;

[0008] Figure 3 schematically illustrates a cross-sectional top view and a cross-sectional side view of a semiconductor device 300 according to the present disclosure;

[0009] Figure 4 schematically illustrates a detail of a top view and a cross-sectional side view of a semiconductor device 400 according to the present disclosure;

[0010] Figure 5schematically illustrates a portion of a top view and a cross-sectional side view of a semiconductor device 500 according to the present disclosure;

[0011] Figure 6 schematically illustrates a cross-sectional top view and a cross-sectional side view of a semiconductor device 600 according to the present disclosure;

[0012] Figure 7 A portion of a top view and a cross-sectional side view of a semiconductor device 700 according to the present disclosure are schematically shown.

[0013] Figure 8 schematically illustrates a cross-sectional top view and a cross-sectional side view of a semiconductor device 800 according to the present disclosure;

[0014] Figure 9 schematically illustrates a portion of a top view of a semiconductor device 900 according to the present disclosure;

[0015] Figure 10 schematically illustrates a portion of a top view of a semiconductor device 1000 according to the present disclosure;

[0016] Figure 11 schematically illustrates a portion of a top view and a cross-sectional side view of a semiconductor device 1100 according to the present disclosure;

[0017] Figure 12 schematically illustrates a cross-sectional top view and a cross-sectional side view of a semiconductor device 1200 according to the present disclosure;

[0018] Figure 13 schematically illustrates a portion of a cross-sectional side view of a semiconductor device 1300 according to the present disclosure;

[0019] Figure 14 schematically illustrates a portion of a perspective view of a semiconductor device 1400 according to the present disclosure;

[0020] Figure 15 shows a circuit having a capacitance formed by a non-electrical connection, Figure 15 The filtering characteristics of the circuit are also shown;

[0021] Figure 16 shows a circuit having a capacitor formed by a non-electrical connection and an inductor, Figure 16 The filtering characteristics of the circuit are also shown;

[0022] Figure 17 shows a circuit having a capacitor and two inductors formed by a non-electrical connection, Figure 17 The filtering characteristics of the circuit are also shown;

[0023] Figure 18shows a circuit having a capacitor and three inductors formed by non-electrical connections, Figure 18 The filtering characteristics of the circuit are also shown;

[0024] Figure 19 A flow chart of a method for manufacturing a semiconductor device according to the present disclosure is shown. DETAILED DESCRIPTION

[0025] In the following detailed description, reference is made to the accompanying drawings, in which specific aspects and embodiments are shown by way of example, in which the present disclosure may be practiced. In this context, directional terms such as "top," "bottom," "front," "back," and the like may be used with reference to the orientation of the accompanying drawings being described. Because the components of the described embodiments may be positioned in different orientations, the directional terms may be used for illustrative purposes and are in no way limiting. Other aspects may be used and structural or logical changes may be made without departing from the concepts of the present disclosure. That is, the following detailed description should not be understood in a limiting sense.

[0026] The following describes schematic diagrams of semiconductor devices according to the present disclosure. The semiconductor devices are shown in a general manner to qualitatively describe various aspects of the present disclosure. Each semiconductor device may have other aspects not shown in the figures for simplicity. For example, any aspect described in conjunction with other devices according to the present disclosure may be utilized to expand upon each semiconductor device.

[0027] Figure 1 A portion of a cross-sectional side view of a semiconductor device 100 according to the present disclosure is schematically shown. The semiconductor device 100 may include a semiconductor chip 2 having a high-frequency circuit (not shown) and a high-frequency terminal 4. In addition, the semiconductor device 100 may have an encapsulation material 6 in which the semiconductor chip 2 may be at least partially embedded. In addition, the semiconductor device 100 may include: an external high-frequency terminal 8 (a high-frequency terminal for transmitting a high-frequency signal to an element outside the semiconductor device) and a redistribution layer 10 that electrically connects the high-frequency terminal 4 of the semiconductor chip 2 to the external high-frequency terminal 8. The semiconductor device 100 can be electrically and mechanically connected to a terminal 12 of a circuit board 14 via the external high-frequency terminal 8. Figure 1 Only a portion of the semiconductor device 100 and the circuit board 14 is shown. The semiconductor device 100 may include other components (such as other terminals), which may be arranged, for example, on Figure 1 To the right of the middle dashed line.

[0028] The semiconductor chip 2 can operate in a high frequency or microwave frequency range, which can generally be in the range of about 10 GHz to about 300 GHz. As an example, the high frequency circuit of the semiconductor chip 2 can operate in a frequency range greater than 10 GHz. Such a microwave circuit can include, for example, a microwave transmitter, a microwave receiver, a microwave transceiver, a microwave sensor or a microwave detector. The device described herein can be used for radar applications in which the frequency of the high frequency signal is modulated. Radar microwave devices can be used for ranging / range finding systems, for example, in automobiles or industrial applications. For example, automatic vehicle speed control systems or vehicle collision avoidance systems can operate in a microwave frequency range, for example, in 24 GHz, 77 GHz or 79 GHz bands. The semiconductor chip 2 can be made of basic semiconductor materials (e.g., Si, etc.) or compound semiconductor materials (e.g., GaN, SiC, SiGe, GaAs, etc.).

[0029] The high-frequency terminals 4 of the semiconductor chip 2 may correspond to output terminals of the semiconductor chip 2 and may provide high-frequency signals (frequencies greater than 10 GHz) processed in the integrated circuit of the semiconductor chip 2 outside the semiconductor chip 2. Such high-frequency signals may be coupled to the circuit board 14 via the redistribution layer 10 and the external high-frequency terminals 8. Alternatively or additionally, the high-frequency terminals 4 may correspond to input terminals of the semiconductor chip 2, through which signals may be fed into the semiconductor chip 2. For example, a signal provided by the circuit board 14 may be transmitted to the high-frequency terminals 4 of the semiconductor chip 2 via the external high-frequency terminals 8 and the redistribution layer 10.

[0030] The semiconductor chip 2 may be at least partially embedded in the encapsulation material 6. Figure 1 In the example shown, one side of the semiconductor chip 2 is covered by the encapsulation material 6. In other examples, the top side of the semiconductor chip 2 may also be covered by the encapsulation material 6. The encapsulation material 6 can protect the semiconductor chip 2 from external influences, such as moisture. The encapsulation material 6 can include, for example, at least one of a molding compound, a laminate, an epoxy resin, a filled epoxy resin, a glass fiber-filled epoxy resin, an imide, a thermoplastic, a thermosetting polymer, or a polymer blend.

[0031] The redistribution layer (or rewiring layer) 10 may include one or more conductor circuits in the form of metal layers or metal circuits and may extend substantially parallel to the activated underside of the semiconductor chip 2 or the top of the circuit board 14. A plurality of dielectric layers may be arranged between the plurality of conductor circuits to electrically isolate the conductor circuits from each other. In addition, the metal layers arranged at different levels may be electrically connected to each other via a plurality of plated through holes (or vias). Figure 1 In the example shown in FIG1 , for simplicity, the conductor circuit and dielectric layer of the redistribution layer 10 are not explicitly shown. Figure 3Shown in.

[0032] The conductor circuit of the redistribution layer 10 can perform a redistribution or rewiring function, for example, to electrically couple the high-frequency terminals 4 of the semiconductor chip 2 to the external high-frequency terminals 8. In other words, the conductor circuit can be designed to make the terminals of the semiconductor chip 2 available at other locations in the semiconductor device 100. Figure 1 In the example, the redistribution layer 10 can be used to redistribute the terminals of the semiconductor chip 2 to external terminals, which can be arranged outside the outline of the semiconductor chip 2. A semiconductor device with such chip connection extension can be called a fan-out device or fan-out package. In the example, Figure 1 The semiconductor device 100 may be a wafer-level package, such as an eWLB (embedded wafer-level ball grid array) package. However, it should be noted that, according to the present disclosure, the semiconductor device described herein does not necessarily need to be configured as a fan-out package. In other examples, the external terminals may also be arranged at least partially within the outline of the semiconductor chip 2.

[0033] Via the external high-frequency terminals 8 and the redistribution layer 10, the internal electronic structure of the semiconductor chip 2 can be contacted from the outside of the semiconductor device 100. In this regard, the external high-frequency terminals 8 can be particularly arranged on the periphery of the semiconductor device 100 and can be electrically and mechanically contacted from the outside of the semiconductor device 100. The external high-frequency terminals 8 can be particularly designed to couple the electrical signals provided by them to the circuit board 14 or the terminals 12 of the circuit board 14. For example, the external high-frequency terminals 8 can include at least one of a solder contact element and an under-bump metallization layer. Figure 1 In the example of FIG. 4 , the external high-frequency terminal 8 is designed in the form of, for example, a solder deposit or a solder ball.

[0034] Figure 2 Schematically shows a portion of a top view of a semiconductor device 200 according to the present disclosure. The semiconductor device 200 may be similar to Figure 1 and have at least some of the same components.

[0035] The semiconductor device 200 may include a semiconductor chip 2 and an encapsulation material 6 which at least partially embeds the semiconductor chip 2 . Figure 2 , the outlines of the semiconductor chip 2 and the packaging material 6 are shown by way of example. The semiconductor chip 2 may have at least one high-frequency terminal 4 and other terminals 18. The other terminals 18 may be signal terminals for analog or digital signals, for example, and the semiconductor chip 2 may provide such signals (for example, to the circuit board 14) or receive such signals.

[0036] The high-frequency terminal 4 and other terminals 18 of the semiconductor chip 2 can be electrically connected to the contact pad through the redistribution layer, and the contact pad can be arranged on the surface of the packaging material 6. The high-frequency terminal 4 of the semiconductor chip 2 can be electrically connected to the high-frequency contact pad 16. The high-frequency contact pad 16 can be, for example, a part of the conductor circuit of the redistribution layer or an under-bump metallization layer. The high-frequency contact pad 16 can be regarded as an external high-frequency terminal of the semiconductor device 200. Alternatively, for example, other solder reservoirs (not shown) arranged on the high-frequency contact pad 16 can be regarded as external high-frequency terminals. The other terminals 18 of the semiconductor chip 2 can be electrically connected to the other contact pads 20 in a similar manner.

[0037] Figure 3 A cross section of a semiconductor device 300 according to the present disclosure is schematically shown. Figure 3 The upper portion shows a top view of the semiconductor device 300, and Figure 3 The lower portion of FIG shows a cross-sectional side view of the semiconductor device 300. The top view and the cross-sectional side view are oriented relative to each other, with the orientation of the various device components being indicated by dashed lines. The portion shown may be, for example, a Figure 2 A more detailed representation of the region of the semiconductor device 200 defined by the dashed rectangle in FIG. Figure 2 The other terminals 18 are shown in FIG.

[0038] The semiconductor device 300 may include a semiconductor chip 2 having at least one high-frequency terminal 4 and an encapsulation material 6, by which the semiconductor chip 2 may be at least partially encapsulated. In addition, the semiconductor device 300 may include a redistribution layer 10, an under-bump metallization layer 26, and an external high-frequency terminal 8. For illustrative purposes, Figure 3 The external high-frequency terminals 8 are not shown in the plan view of FIG. The same applies to the top views of the other figures. The redistribution layer 10 can be designed to electrically couple the high-frequency terminals 4 of the semiconductor chip 2 to the underbump metallization layer 26 or the external high-frequency terminals 8. The redistribution layer 10 can have at least one conductor circuit 22 and be embedded in the dielectric layer 24. Figure 3 An example of a conductor circuit 22 and two dielectric layers 24 is shown. In other examples, the redistribution layer 10 can have any other number of conductive circuits and dielectric layers.

[0039] In particular, the under bump metallization layer 26 may include a substantially vertical via 30 that may be electrically connected to the conductor 22 of the redistribution layer 10. Figure 3In the example of , the external high-frequency terminal 8 can partially cover the under-bump metallization layer 26. In other examples, the under-bump metallization layer 26 can be completely covered by the external high-frequency terminal 8. If the external high-frequency terminal 8 (for example, in the form of a solder warehouse) has not yet been arranged on the under-bump metallization layer 26, the under-bump metallization layer 26 can represent the external high-frequency terminal of the semiconductor device 300. It should be noted that the under-bump metallization layer 26 is optional and may not exist in other examples. In this case, the external high-frequency terminal 8 can directly contact the conductor circuit 22.

[0040] The semiconductor device 300 may have a non-electrical connection 28. The non-electrical connection 28 may be formed by interrupting the electrical connection between the high-frequency terminal 4 of the semiconductor chip 2 and the under-bump metallization layer 26 or the external high-frequency terminal 8. Figure 3 In the example of , such an interruption 28 may be formed in the conductor circuit 22 of the redistribution layer 10. In the following, the terms "interruption" and "non-electrical connection" may be used synonymously.

[0041] exist Figure 3 In the cross-sectional side view of FIG, the interruption 28 can be designed as a horizontal groove in the conductor track 22. The interruption 28 can thus be arranged in a part of the horizontal course of the conductor track 22. In addition, Figure 3 The interruption 28 in the plan view may have the shape of an arc of a circle. Figure 3 In the top view of , the arc may at least partially extend around the outline of the under-bump metallization layer 26 or the outline of the external high-frequency terminal 8. Figure 1 In the example of FIG, the central angle α of the circumference of the arc has a value of about 180 degrees. In other examples, the angle α may have any other value between about 0 degrees and about 360 degrees. In the top view, the possible shape of the interruption 28 is not limited to the arc shape. In other examples, the shape of the interruption 28 in the plan view may have a rectangular, elliptical, or polygonal shape. Figure 3 In the example of a cross-sectional side view of , the interruption 28 can be arranged outside the contour of the under-bump metallization layer 26 or the external high-frequency terminal 8 and perpendicular to the projection of the conductor track 22 .

[0042] exist Figure 3 The portion of conductor track 22 disposed on the left or right side near discontinuity 28 can be considered a first electrical connection portion or a second electrical connection portion. The distance of discontinuity 28 between the first and second connection portions can be substantially constant or variable. The maximum distance between discontinuity 28 and the maximum width of discontinuity 28 can have a value within a range, where the lower limit of the range can be, for example, approximately 1 micron or approximately 5 microns. For example, the upper limit of the range can be approximately 50 microns, approximately 40 microns, approximately 30 microns, approximately 20 microns, or approximately 10 microns.

[0043] The interruptions 28 in the conductor paths 22 can be filled with a dielectric material. Figure 3 In one example, the discontinuities 28 can be filled with the material of the dielectric layer 24 of the redistribution layer 10. In other examples, the material disposed in the discontinuities 28 can be different from the dielectric material of the redistribution layer 10. The dielectric material in the discontinuities 28 can include a polymer, such as polyimide, a low-k material, or air. For example, the dielectric constant of the dielectric material can be in the range of about 2 to about 6. In addition, the dielectric material can have a higher elasticity than the material of the conductor circuit 22. As explained further below, the higher elasticity of the dielectric material can prevent cracks from occurring in the conductor circuit 22. Such cracks can be caused by, for example, material fatigue.

[0044] The non-electrical connection 28 can form a capacitor and have the characteristics of a capacitor. The capacitance value of the non-electrical connection 28 can be influenced or set, for example, by at least one of the following parameters: (1) the area size of the ends of the conductor path 22 between which the interruption 28 is formed; (2) the width of the interruption 28; (3) the dielectric constant of the material arranged in the interruption 28. For example, a larger angle α of the arc can result in a larger area between the ends of the conductor path 22 and thus a larger capacitance value. In addition, the capacitance value can be increased by reducing the maximum width of the interruption 28 and by increasing the dielectric constant of the material arranged in the interruption 28.

[0045] Non-electrical connection 28 can be specifically designed for transmitting high-frequency signals. Signal transmission via non-electrical connection 28 can be performed using capacitive coupling. This means that non-electrical connection 28 can function as a coupling capacitor. Non-electrical connection 28 can be particularly useful in high-frequency signal lines because, due to its relatively high frequency, the high-frequency signal does not need to be interrupted during transmission via non-electrical connection 28. During transmission via non-electrical connection 28, the high-frequency signal may attenuate. As described above, this signal attenuation can be reduced by selecting a high capacitance value for non-electrical connection 28.

[0046] Non-electrical connections 28 may be arranged specifically at points of semiconductor device 300 where thermomechanical stresses may occur during manufacture or operation of semiconductor device 300. For example, due to different coefficients of thermal expansion of components of semiconductor device 300 and circuit board 14, such stresses may occur during temperature-on-board cycling (TCoB). These stresses may particularly cause material fatigue in conductor tracks 22, potentially leading to cracks in conductor tracks 22. Because the material arranged in interruptions 28 may have a higher elasticity than the material of conductor tracks 22, the formation of such cracks in conductor tracks 22 can be prevented. This can improve the reliability and performance of semiconductor device 300.

[0047] The non-electrical connection 28 can be designed to provide a defined phase shift of the high-frequency signal transmitted via the non-electrical connection 28. This phase shift can be controlled and predicted, and ideally can remain constant throughout the life cycle of the semiconductor device 300. In contrast, cracks in the conductor circuit 22 caused by material fatigue can result in an uncontrolled and unpredictable phase shift.

[0048] Figure 4 A cross section of a semiconductor device 400 according to the present disclosure is schematically shown. Figure 4 The upper portion shows a top view of the semiconductor device 400, and Figure 4 The lower portion of FIG. 4 shows a cross-sectional side view of a semiconductor device 400. The semiconductor device 400 may be, for example, at least partially similar to Figure 3 The semiconductor device 300 makes Figure 3 The above statements can also be applied to Figure 4 .

[0049] and Figure 3 In comparison, Figure 4 In the top view of FIG, the interruption 28 may have a completely closed circular shape. In other words, Figure 4 An example of a 360 degree angle α corresponds to Figure 3 Example. Figure 2 In comparison, since the surface area of ​​the capacitor formed by the interruption 28 increases, the capacitance value of the non-electrical connection 28 can be increased. This means that the attenuation of the high-frequency signal transmitted via the non-electrical connection 28 can be reduced. Figure 4 , for illustrative reasons, the external high-frequency terminal 8 is not fully shown. The same applies to the cross-sectional side views of the other drawings.

[0050] Figure 5 A cross section of a semiconductor device 500 according to the present disclosure is schematically shown. Figure 5 The upper portion shows a top view of the semiconductor device 500, and Figure 5 The lower portion of FIG. 5 shows a cross-sectional side view of a semiconductor device 500. The semiconductor device 500 may be, for example, at least partially similar to Figure 4 Semiconductor device 400.

[0051] and Figure 4 compared to, Figure 5 The through hole 30 of the UBM layer 26 may have a smaller diameter d via By reducing the diameter d via , it is possible to reduce mechanical stress that may occur in the connection between the external high-frequency terminal 8 and the redistribution layer 10. This can reduce the risk of cracks in the redistribution layer 10. Figure 4 Middle diameter d viamay have an exemplary value of approximately 240 microns, while Figure 5 The diameter d via An exemplary value of about 50 microns may be used. Figure 5 In the example, the diameter d of the through hole 30 is via The diameter d of the under bump metallization layer 26 UBM The ratio therebetween may be less than about 0.5, or less than about 0.4, or less than about 0.3, or less than about 0.2, or less than about 0.1.

[0052] Figure 6 A cross section of a semiconductor device 600 according to the present disclosure is schematically shown. Figure 6 The upper portion shows a top view of the semiconductor device 600, and Figure 6 The lower portion of FIG. 5 shows a cross-sectional side view of a semiconductor device 600. The semiconductor device 600 may be, for example, at least partially similar to Figure 5 Semiconductor device 500.

[0053] and Figure 5 compared to, Figure 6 The interruption 28 in the embodiment can be arranged within the contour of the under-bump metallization 26 or the external high-frequency terminal 8 and perpendicular to the projection of the conductor track 22 .

[0054] Figure 7 A cross section of a semiconductor device 700 according to the present disclosure is schematically shown. Figure 7 The upper portion shows a top view of the semiconductor device 700, and Figure 7 The lower portion of FIG. 7 shows a cross-sectional side view of a semiconductor device 700. The semiconductor device 700 may be, for example, at least partially similar to Figure 5 Semiconductor device 500.

[0055] and Figure 5 In comparison, Figure 7 In the top view of , the interruption 28 may have an arc shape. Figure 7 In the example of , the central angle of the circumference of the arc can have a value of about 180 degrees. In other examples, the value of the angle can have any other value between about 0 degrees and about 360 degrees.

[0056] Figure 8 A portion of a semiconductor device 800 according to the present disclosure is schematically shown. Figure 8 The upper portion shows a top view of the semiconductor device 800, and Figure 8 The lower portion of FIG. 8 shows a cross-sectional side view of a semiconductor device 800. The semiconductor device 800 may be, for example, at least partially similar to Figure 3 semiconductor device 300.

[0057] and Figure 3 compared to, Figure 8 The semiconductor device 800 may not have an underbump metallization layer. The external high-frequency terminal 8 may directly contact the conductor circuit 22 of the redistribution layer 10. If the external high-frequency terminal 8 (e.g., solder reservoir) is not yet arranged on the conductor circuit 22, the exposed portion of the conductor circuit 22 can be regarded as the external high-frequency terminal of the semiconductor device 800.

[0058] Figure 9 Schematically shows a portion of a top view of a semiconductor device 900 according to the present disclosure. The semiconductor device 900 may, for example, be at least partially similar to Figure 4 Semiconductor device 400.

[0059] and Figure 4 compared to, Figure 9 The conductor circuit 22 in the embodiment may have another portion 22' (straight line form), for example, a second portion 22'. The high-frequency signal transmitted via the conductor circuit 22 can not only be provided to an external high-frequency terminal but also be transmitted to other components of the semiconductor device 900. Figure 9 In the example shown, the direction of the possible signal curves is indicated by an arrow. For example, the high-frequency signal can be transferred to at least one other external high-frequency terminal (not shown) and made available to the latter. The other external high-frequency terminal can be a spare connection with the same function.

[0060] Figure 10 Schematically shows a portion of a top view of a semiconductor device 1000 according to the present disclosure. The semiconductor device 1000 may, for example, be at least partially similar to Figure 3 semiconductor device 300.

[0061] and Figure 3 on the contrary, Figure 10 The angle α in can have a smaller value. Figure 10 As shown, the interruption 28 may have a relatively short arc shape. Figure 3 compared to, Figure 10 The capacitance value of the non-electrical connection 28 in can be correspondingly smaller.

[0062] Figure 11 A cross section of a semiconductor device 1100 according to the present disclosure is schematically shown. Figure 11 The upper portion shows a top view of the semiconductor device 1100, and Figure 11 The lower portion of FIG. 1 shows a cross-sectional side view of a semiconductor device 1100. The semiconductor device 1100 may be, for example, at least partially similar to Figure 3 semiconductor device 300.

[0063] and Figure 3 on the contrary, Figure 11The interruption 28 in the redistribution layer 10 does not necessarily have to be formed in the conductor circuit 22 or in the horizontal direction of the conductor circuit 22. Alternatively, a non-electrical connection 28 can be formed between the conductor circuit 22 of the redistribution layer 10 and the under-bump metallization layer 26 or the external high-frequency terminal 8. Figure 11 In the example of FIG, the interruption 28 is arranged directly between the top of the conductor track 22 and the bottom of the under-bump metallization layer 26, that is, it is limited by these two components. Figure 3 The interruption 28 in the cross-sectional side view is designed as a "horizontal" slot, but in Figure 11 The interruption 28 in the cross-sectional side view can be designed as a "vertical" groove. The interruption 28 can be arranged in a portion of the vertical signal curve of the redistribution layer 10. To this end, for example, a via for connecting the conductor track 22 to the underbump metallization layer 26 can be omitted, and the area between the upper side of the conductor track 22 and the lower side of the underbump metallization layer 26 can be filled with the dielectric material of the redistribution layer 10. Similar to the previous example, the dielectric material arranged in the interruption 28 can absorb any thermal and mechanical loads that may occur due to elasticity.

[0064] Figure 12 A cross section of a semiconductor device 1200 according to the present disclosure is schematically shown. Figure 12 The upper portion shows a top view of the semiconductor device 1200, and Figure 12 The lower portion of FIG. 1 shows a cross-sectional side view of a semiconductor device 1200. The semiconductor device 1200 may be at least partially similar to the previously discussed semiconductor devices according to the present disclosure.

[0065] Semiconductor device 1200 may include a semiconductor chip 2 having at least one high-frequency terminal 4 and an encapsulation material 6, by which semiconductor chip 2 may be at least partially encapsulated. Furthermore, a dielectric layer 32 may be applied to the top surfaces of semiconductor chip 2 and encapsulation material 6. An underbump metallization layer 26 and an external high-frequency terminal 8 may be arranged above dielectric layer 32.

[0066] exist Figure 12 In the plan view, the high-frequency terminals 4 of the semiconductor chip 2 can be arranged within the outline of the bump metallization 26 or within the outline of the external high-frequency terminals 8. In other words, the external high-frequency terminals 8 can be placed directly above the high-frequency terminals 4 of the semiconductor chip 2. In this regard, the semiconductor device 1200 does not need to be at least Figure 12 The illustrated region comprises a redistribution layer, via which an electrical connection is provided between the high-frequency connection 4 of the semiconductor chip 2 and the external high-frequency connection 8 .

[0067] In this case, it should be noted that at least a portion of the encapsulation material 6 adjacent to the side surfaces of the semiconductor chip 2 may be optional. In an example, the semiconductor device 1200 may be a fan-out package having the encapsulation material 6 extending beyond the outline of the semiconductor chip 2. However, in other examples, the external terminals of the semiconductor device 1200 may also be arranged within the outline of the semiconductor chip 2, so that the encapsulation material 6 may be omitted at least on the side surfaces of the semiconductor chip 2.

[0068] exist Figure 12 In the example of FIG, a non-electrical connection or interruption 28 can be formed directly between the high-frequency terminal 4 of the semiconductor chip 2 and the underbump metallization layer 26 or the external high-frequency terminal 8. This means that the interruption 28 can be limited in particular by the upper side of the high-frequency terminal 4 and the lower side of the underbump metallization layer 26.

[0069] Figure 13 Schematically depicts a cross-sectional side view of a semiconductor device 1300 according to the present disclosure.The semiconductor device 1300 may be at least partially similar to the previously described semiconductor devices according to the present disclosure.

[0070] exist Figure 13 In the example of , the non-electrical connection or interruption 28 can have both horizontal and vertical routes. Figure 13 Interrupt 28 in can be considered as Figure 3 and 11 The combination of interrupt 28. Figure 13 In the cross-sectional side view of , the interruption 28 may have a first portion 28A and a second portion 28B, which may be arranged at an angle β to each other. Figure 13 In the example of , the angle β can be about 90 degrees, the first portion 28A can form a "horizontal" slot, and the second portion 28B can form a "vertical" slot. In other examples, the angle β can also be acute or obtuse. Figure 13 In the view of FIG, the interruption 28 may have a non-constant width in the vertical right direction. Figure 13 In the view of FIG, the interrupted first portion 28A may be arranged below the external high-frequency terminal 8.

[0071] As already mentioned above, when transmitting high-frequency signals via non-electrical connections, an attenuation of the high-frequency signal occurs compared to a corresponding transmission via an electrical connection. The attenuation depends, among other things, on the layout and width of the non-electrical connection. In the case of a "horizontal" interruption 28, the attenuation can be in the range of approximately 0.1 dB to approximately 0.5 dB. Figure 4 In the example of , the attenuation may have a value of approximately 0.2 dB. Figure 5 In the example of , the attenuation may have a value of approximately 0.4 dB. Figure 6In the example of , the attenuation may have a value of approximately 0.1 dB. In the case of a "vertical" interruption 28 (see e.g. Figure 11 ) in which case the non-electrical connection can provide performance very similar to that of the corresponding current connection.

[0072] In the described example, only one non-electrical connection is shown between the high-frequency terminal 4 of the semiconductor chip 2 and the external high-frequency terminal 8 of the semiconductor device. In other examples, the semiconductor device according to the present invention may also have more than one non-electrical connection. The possible designs of the non-electrical connections described here can be combined with each other as needed. In one example, two non-electrical connections can be formed in the same conductor circuit. In another example, two non-electrical connections can be formed in different conductor circuits of the redistribution layer. In yet another example, non-electrical connections from a large number of horizontal and vertical slots can be combined with each other as needed.

[0073] In the described examples, non-electrical connections are formed in the semiconductor device according to the present disclosure. Alternatively or additionally, in other examples, one or more non-electrical connections may be formed in the circuit board 14 (see Figure 1 ). This non-electrical connection can be specifically arranged between the terminal 12 of the circuit board 14 and the internal circuit structure of the circuit board 14. The non-electrical connection can be designed to transmit high-frequency signals. The non-electrical connection in the circuit board 14 can be designed based on the example of the non-electrical connection in the semiconductor device described above. For example, as described above, the non-electrical connection in the circuit board 14 can be made in the horizontal and / or vertical direction.

[0074] Figure 14 Schematically shows a portion of a perspective view of a semiconductor device 1400 according to the present disclosure. The portion shown may, for example, be included in any of the above-described semiconductor devices and have similar components.

[0075] The semiconductor device 1400 includes a redistribution layer 10 having at least one conductor track 22. Figure 1 The dielectric layer of the redistribution layer 10 is not shown. The redistribution layer 10 is electrically connected to the under-bump metallization layer 26 or the external high-frequency terminal 8 arranged above it through the non-electrical connection 28. The capacitor 38 formed by the non-electrical connection 28 is Figure 14 , which is represented by a capacitive switch symbol. One end of the inductor 34 can be connected to the conductor circuit 22 at point 36. At the other end, the inductor 34 can be coupled to ground potential (see "GND"). The inductor 34 can be constructed in the redistribution layer 10 to provide a low impedance DC path to ground. Figure 14 In the example of FIG, the inductor 34 is constructed in the form of a meandering inductor and is identified by the inductor circuit symbol. Figure 14 The circuit is shown on the right side of FIG, which corresponds to the cross section of the semiconductor device 1400 shown. Figure 14 In the example shown, the semiconductor device 1400 includes only one inductor. In other examples, the semiconductor device 1400 may have at least one other inductor, as described below.

[0076] The capacitor 38 can provide natural direct current (DC) isolation ("DC blocking") for high frequency signals. In addition, the inductor 36 and the capacitor 38 can provide at least one of ESD protection and high frequency filter functions. Figure 14 In the example of , the inductor 34 may be arranged between the non-electrical connection 28 of the semiconductor chip 2 and the high-frequency terminal 4. Alternatively or additionally, in other examples, the inductor 34 or an additional inductor may be connected between the non-electrical connection 28 of the semiconductor device 1400 and the external high-frequency terminal 8.

[0077] Figure 15 A circuit is shown with a capacitor formed by a non-electrical connection. The capacitor is arranged between a high-frequency terminal of a semiconductor chip (see "chip") and an external high-frequency terminal of a semiconductor device coupled to a circuit board (see "PCB"). The circled circuit points represent connection options for a direct current path to ground potential. As described above, the capacitor can provide direct current (DC) isolation ("DC blocking") for high-frequency signals. In this case, Figure 15 The right side of FIG shows the qualitative filtering characteristics of the circuit shown, with the gain S21 (in dB) plotted against the frequency f. As can be seen from the filter characteristics, the circuit can provide the function of a high-pass filter.

[0078] and Figure 15 compared to, Figure 16 The circuit is shown with an additional inductor. In an example, the inductance L of the inductor can take a value greater than 1 nH. For example, the inductor can be connected to the terminal 36 of the redistribution layer 10, such as Figure 14 shown. Figure 16 The circuit can have the functions of direct current (DC) isolation ("DC blocking"), high-pass filtering and chip-side ESD protection for high-frequency signals. Figure 16 The right side of shows the qualitative filtering characteristics of the circuit shown.

[0079] and Figure 16 compared to, Figure 17 A circuit with a further second inductor is shown. Similar to the already existing first inductor, the further second inductor can provide a low resistance DC path to ground potential. Figure 17 The circuit can have the functions of direct current (DC) isolation ("DC blocking") for high-frequency signals, high-pass filtering, and chip-side and board-side ESD protection. In this case, Figure 17 The right side of shows the qualitative filtering characteristics of the circuit shown.

[0080] and Figure 17 compared to, Figure 18 A circuit with another third inductor is shown. Figure 18 The circuit can have the functions of direct current (DC) isolation ("DC blocking"), bandpass filtering, and chip-side and board-side ESD protection for high-frequency signals. Figure 18 The right side of shows the qualitative filtering characteristics of the circuit shown.

[0081] Figure 19 A flow chart of a method for manufacturing a semiconductor device according to the present disclosure is shown. The method can be used to manufacture any of the above-mentioned semiconductor devices.

[0082] At 40 , a non-electrical connection is formed between a high-frequency terminal of a semiconductor chip of the semiconductor device and an external high-frequency terminal of the semiconductor device. The non-electrical connection is designed to transmit a high-frequency signal.

[0083] In another treatment, Figure 19 The method may include forming a redistribution layer between the high-frequency terminals of the semiconductor chip and the external high-frequency terminals. The conductor circuits of the redistribution layer may be produced, for example, by sputtering, currentless deposition, or vapor deposition. The dielectric layer of the redistribution layer may be deposited or laminated, for example, from the vapor phase or solution. For example, the components of the redistribution layer may be constructed using photolithography, etching, and / or laser drilling. Non-electrical connections may be formed during the production or construction of the redistribution layer.

[0084] Example

[0085] Hereinafter, a semiconductor device having non-electrical connections and a related manufacturing method thereof are described using embodiments.

[0086] Example 1 is a semiconductor device comprising: a semiconductor chip having a high-frequency circuit and a high-frequency terminal; an external high-frequency terminal; and a non-electrical connection arranged between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal, wherein the non-electrical connection is designed to transmit a high-frequency signal.

[0087] Example 2 is the semiconductor device according to Example 1, wherein the high-frequency circuit is designed to operate in a frequency range greater than 10 GHz.

[0088] Example 3 is the semiconductor device according to Example 1 or 2, wherein the non-electrical connection is formed by interruption of the electrical connection between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal.

[0089] Example 4 is the semiconductor device according to Example 3, wherein the interruption is formed in a conductor circuit of the redistribution layer.

[0090] Example 5 is the semiconductor device according to Example 4, wherein the interruption in the conductor circuit has a shape of a circular arc or a shape of a completely closed circle.

[0091] Example 6 is the semiconductor device according to any one of Examples 3 to 5, wherein the interruption is formed between the conductor circuit of the redistribution layer and the external high-frequency terminal.

[0092] Example 7 is the semiconductor device according to any one of Examples 3 to 6, wherein the interruption is formed directly between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal.

[0093] Example 8 is the semiconductor device according to any one of Examples 3 to 7, wherein the interruption is arranged in a projection perpendicular to the conductor circuit below the external high-frequency terminal.

[0094] Example 9 is a semiconductor device according to any one of Examples 3 to 8, wherein the interruption is formed between the first electrical connection portion and the second electrical connection portion, and a maximum distance of the interruption between the first electrical connection portion and the second electrical connection portion is in the range of 1 micrometer to 50 micrometers.

[0095] Example 10 is the semiconductor device of any of Examples 3 to 9, wherein the interruption is filled with a dielectric material having a higher elasticity than a material of the electrical connection, and wherein a dielectric constant of the dielectric material is in a range of 2 to 6.

[0096] Example 11 is the semiconductor device of any one of Examples 3 to 10, wherein the interruption is filled with a dielectric material of a redistribution layer.

[0097] Example 12 is a semiconductor device according to any of the preceding examples, further comprising: at least one inductor, wherein the capacitance formed by the non-electrical connection and the at least one inductor provides at least one function of ESD protection and high frequency filtering.

[0098] Example 13 is the semiconductor device according to Example 12, wherein at least one inductor is connected between the non-electrical connection and the high-frequency terminal of the semiconductor chip and / or is connected between the non-electrical connection and the external high-frequency terminal.

[0099] Example 14 is a semiconductor device according to any of the preceding examples, further comprising: a packaging material, wherein the semiconductor chip is at least partially encapsulated by the packaging material, wherein the external high-frequency terminal comprises a fan-out terminal arranged above the packaging material.

[0100] Example 15 is a semiconductor device according to any of the preceding examples, wherein the external high frequency terminal comprises at least one of a solder contact element and an under bump metallization layer.

[0101] Example 16 is a semiconductor device according to Example 15, further comprising: an electrical via connection between the under bump metallization layer and the conductor circuit of the redistribution layer, wherein a ratio of a diameter of the via connection to a diameter of the under bump metallization layer is less than 0.5.

[0102] Example 17 is a semiconductor device according to any of the preceding examples, wherein the non-electrical connection is designed to provide a defined phase shift of a high frequency signal transmitted via the non-electrical connection.

[0103] Example 18 is a semiconductor device according to any one of the preceding examples, further comprising: a circuit board, wherein the external high-frequency terminal is electrically connected to a terminal of the circuit board; and another non-electrical connection arranged between the terminal of the circuit board and the internal electrical structure of the circuit board, wherein the other non-electrical connection is designed to transmit a high-frequency signal.

[0104] Example 19 is a method for manufacturing a semiconductor device, wherein the method includes: forming a non-electrical connection between a high-frequency terminal of a semiconductor chip of the semiconductor device and an external high-frequency terminal of the semiconductor device, wherein the non-electrical connection is designed to transmit a high-frequency signal.

[0105] Example 20 is the method according to Example 19, further comprising: forming a redistribution layer between the high-frequency terminal of the semiconductor chip and the external high-frequency terminal, wherein the forming of the non-electrical connection is performed during structuring of the redistribution layer.

[0106] In the sense of this specification, the terms "connected," "coupled," "electrically connected," and / or "electrically coupled" do not necessarily mean that components must be directly connected or coupled to each other. Intermediate components may exist between "connected," "coupled," "electrically connected," or "electrically coupled" components.

[0107] In addition, the term "over" may be used in this specification, for example, using the term in relation to a material layer and being constructed or positioned above a surface of an object, such that the material layer is "directly" (e.g., in direct contact with) disposed (e.g., formed, deposited, etc.) on the intended surface. The term "over" may be used in this specification, for example, using the term in relation to a material layer and being formed or positioned above a surface of an object, such that the material layer is "indirectly" disposed (e.g., formed, deposited, etc.) on the intended surface, wherein, for example, one or more additional layers are positioned between the intended surface and the material layer.

[0108] Where the terms "having," "including," "comprising," or variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "comprising." In this specification, this means that the terms "having," "including," "comprising," "including," and the like are open terms that indicate the presence of the elements or features mentioned but do not exclude other elements or features. The articles "a," "an," "the," and "the" should be understood in such a way that they include both plural and singular meanings unless the context clearly indicates a different understanding.

[0109] In addition, the word "exemplary" is used in this article in the sense of serving as an example, case or illustration. An aspect or configuration described in this article as "exemplary" is not necessarily understood in the sense that he or she has advantages over other aspects or configurations. On the contrary, the use of the word "exemplary" should represent the concept in a specific way. For the purposes of this application, the term "or" does not mean an exclusive "or", but an inclusive "or". That is, unless otherwise specified or the context does not allow any other interpretation, "X uses A or B" means any natural inclusive arrangement. That is, if X uses A, X uses B or X uses A and B at the same time, then "X uses A or B" is satisfied in each of the above cases. Otherwise, in this application and the appended claims, the article "one" can generally be interpreted as "one or more", unless explicitly stated or clearly understood from the context to mean only the number "one". In addition, at least one of A and B, etc. generally refers to A or B or both A and B.

[0110] In this specification, devices and methods for making the devices are described. Comments related to the described devices may also apply to the corresponding methods, and vice versa. For example, if a specific component of a device is described, the corresponding method for making the device may include a method for providing the component in a suitable manner, even if the method is not explicitly described or shown in the drawings. In addition, unless otherwise explicitly stated, the features of the various exemplary aspects described herein may be combined with each other.

[0111] Although the present disclosure has been shown and described with reference to one or more embodiments, those skilled in the art will recognize equivalent changes and modifications based, at least in part, on reading and understanding this specification and the accompanying drawings. The present disclosure includes all such changes and modifications and is limited only by the concepts of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components correspond to any components that perform the specified functions of the described components (e.g., functionally equivalent), even if they have a disclosed structure, the functions of the exemplary embodiments of the present disclosure presented herein are not structurally equivalent. In addition, even if a particular feature of the present disclosure is disclosed only with reference to one embodiment in different embodiments, it may be advantageous to combine that feature with one or more other features of other embodiments as required for a given or specific application.

Claims

1. A semiconductor device comprising: A semiconductor chip (2) having a high-frequency circuit and a high-frequency terminal (4); an external high-frequency terminal (8) designed to electrically and mechanically connect the semiconductor device to a circuit board (14); and A non-electrical connection (28) is arranged between the high-frequency terminal (4) of the semiconductor chip (2) and the external high-frequency terminal (8), wherein the non-electrical connection (28) is designed to transmit a high-frequency signal.

2. The semiconductor device according to claim 1, wherein The high-frequency circuit is designed to operate in a frequency range greater than 10 GHz.

3. The semiconductor device according to claim 1, wherein the non-electrical connection (28) is formed by interruption of the electrical connection between the high-frequency terminal (4) of the semiconductor chip (2) and the external high-frequency terminal (8).

4. The semiconductor device according to claim 3, wherein the interruption is formed in a conductor path (22) of the redistribution layer (10).

5. The semiconductor device according to claim 4, wherein the interruption in the conductor path (22) has the shape of a circular arc or a completely closed circle.

6. The semiconductor device according to any one of claims 3 to 5, wherein the interruption is formed between the conductor circuit (22) of the redistribution layer (10) and the external high-frequency terminal (8).

7. The semiconductor device according to any one of claims 3 to 5, wherein the interruption is formed directly between the high-frequency terminal (4) of the semiconductor chip (2) and the external high-frequency terminal (8).

8. The semiconductor device according to claim 3, wherein the interruption is arranged in a projection perpendicular to the conductor path (22) below the external high-frequency terminal (8).

9. The semiconductor device according to claim 3 , wherein the discontinuity is formed between a first electrical connection portion and a second electrical connection portion, and a maximum distance of the discontinuity between the first electrical connection portion and the second electrical connection portion is in a range of 1 μm to 50 μm. 10 . The semiconductor device according to claim 3 , wherein the interruption is filled with a dielectric material, wherein the dielectric material has a higher elasticity than a material of the electrical connection, and wherein a dielectric constant of the dielectric material is in the range of 2 to 6.

11. The semiconductor device according to any one of claims 3 to 5, wherein the interruptions are filled with dielectric material of a redistribution layer (10).

12. The semiconductor device according to any one of claims 1 to 5, further comprising: At least one inductor (34), wherein the capacitance formed by the non-electrical connection (28) and the at least one inductor (34) provides at least one of ESD protection and high frequency filtering.

13. A semiconductor device according to claim 12, wherein the at least one inductor (34) is connected between the non-electrical connection (28) and the high-frequency terminal (4) of the semiconductor chip (2), and / or is connected between the non-electrical connection (28) and the external high-frequency terminal (8).

14. The semiconductor device according to any one of claims 1 to 5, further comprising: Encapsulation material (6), wherein the semiconductor chip (2) is at least partially encapsulated by the encapsulation material (6), wherein the external high-frequency terminal (8) comprises a fan-out terminal arranged above the encapsulation material (6).

15. The semiconductor device according to any one of claims 1 to 5, wherein the external high-frequency terminal (8) comprises at least one of a solder contact element and an under-bump metallization layer (26).

16. The semiconductor device according to claim 15, further comprising: An electrical through-hole connection (30) is provided between the under-bump metallization layer (26) and a conductor track (22) of a redistribution layer (10), wherein the ratio of the diameter of the through-hole connection (30) to the diameter of the under-bump metallization layer (26) is less than 0.

5.

17. The semiconductor device according to any one of claims 1 to 5, wherein the non-electrical connection (28) is designed to provide a defined phase shift of a high-frequency signal transmitted via the non-electrical connection (28).

18. The semiconductor device according to any one of claims 1 to 5, further comprising: a circuit board (14), wherein the external high-frequency terminal (8) is electrically connected to a terminal of the circuit board (14); and Another non-electrical connection is arranged between the terminal of the circuit board (14) and the internal electrical structure of the circuit board (14), wherein the other non-electrical connection is designed to transmit high-frequency signals.

19. A method for manufacturing a semiconductor device, wherein the method comprises: forming a non-electrical connection (28) between a high-frequency terminal (4) of a semiconductor chip (2) of the semiconductor device and an external high-frequency terminal (8) of the semiconductor device; wherein the external high-frequency terminal (8) is designed to electrically and mechanically connect the semiconductor device to a circuit board (14); and The non-electrical connection (28) is designed for transmitting high-frequency signals.

20. The method according to claim 19, further comprising: A redistribution layer (10) is formed between the high-frequency terminal (4) of the semiconductor chip (2) and the external high-frequency terminal (8), wherein the non-electrical connection (28) is formed during the structuring of the redistribution layer (10).

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