Through-Hole Contact Structure, Memory Device, and Method of Forming a Semiconductor Structure

Abstract

The present invention discloses a via contact structure, a memory device, and a method of forming a semiconductor structure. The method of forming the semiconductor structure includes the following steps: forming a first dielectric layer having a first via on a precursor substrate, the first via penetrating through the first dielectric layer; filling a sacrificial material in the first via; forming a second dielectric layer having a second via above the first dielectric layer, the second via exposing the sacrificial material in the first via, wherein the second via has a bottom width that is less than the top width of the first via; replacing the sacrificial material after forming the second dielectric layer having the second via; forming a barrier layer lining the sidewalls of the first via and the sidewalls of the second via; and forming a conductive material in the first and second vias.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method of forming a semiconductor structure. Specifically, the present invention relates to a via contact structure for a semiconductor device, a memory device having the via contact structure, and methods of fabricating the via contact structure and the memory device. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. The manufacturing technology of integrated circuits has produced several generations of integrated circuits, and each generation of integrated circuits has smaller and more complex circuits than the previous generation. The industry has developed a variety of advanced technologies to form smaller feature sizes, and these technologies are utilized in the manufacture of data storage devices such as flash memories. However, some process technologies are not entirely satisfactory. For example, in traditional etching technology, there are challenges in achieving high aspect ratio contact vias. Therefore, one of the technical advantages of the present invention is to provide a solution to form contact vias with high aspect ratios. Summary of the Invention

[0003] One form of the present invention is to provide a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first via on a precursor substrate, the first via penetrating the first dielectric layer; filling a sacrificial material in the first via; forming a second dielectric layer having a second via above the first dielectric layer, the second via exposing the sacrificial material in the first via, wherein the second via has a bottom width that is less than the top width of the first via, and the first via and the second via at least partially overlap in a direction perpendicular to the precursor substrate; after forming the second dielectric layer having the second via, replacing the sacrificial material; forming a barrier layer lining the sidewalls of the first via and the sidewalls of the second via; and forming a conductive material in the first and second vias.

[0004] Another form of the present invention is to provide a via contact structure for a semiconductor device. The via contact structure includes a first conductive structure, a second conductive structure, and a barrier layer. The first conductive structure has a top. The second conductive structure has a bottom that contacts and is disposed on the top of the first conductive structure. The bottom of the second conductive structure has a width that is less than the width of the top of the first conductive structure, such that a portion of the top of the first conductive structure is not occupied by the bottom of the second conductive structure. The barrier layer coats the sidewalls of the first conductive structure and the sidewalls of the second conductive structure, and the barrier layer continuously extends from the sidewalls of the first conductive structure, through the unoccupied portion of the top, to the sidewalls of the second conductive structure.

[0005] Another form of the present invention provides a memory device. The memory device includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive plug. The semiconductor substrate includes a memory array region and a peripheral circuit adjacent to the memory array region. The dielectric layer is disposed above the peripheral circuit and has a first hole and a second hole. The second hole connects to the first hole and is located above the first hole. The bottom width of the second hole is smaller than the top width of the first hole, causing the dielectric layer to form an overhang at the connection of the first hole and the second hole. The barrier layer continuously extends from the sidewall of the first hole through the overhang to the sidewall of the second hole. The conductive plug is filled in the first hole and the second hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. is a flowchart illustrating a method of forming a semiconductor structure according to various embodiments of the present invention.

[0007] Figures 2 - 13 FIGS. are cross-sectional views illustrating a method of forming a semiconductor structure according to various embodiments of the present invention at different process stages.

[0008] Figure 14 FIG. is a schematic cross-sectional view illustrating a via contact structure according to various embodiments of the present invention.

[0009] Figure 15 FIG. is a schematic cross-sectional view illustrating a memory device according to various embodiments of the present invention.

[0010] Figure 16A Illustrates Figure 15 an enlarged view of region R of.

[0011] Figure 16B FIG. is a schematic plan view illustrating a first hole and a second hole along section plane C in region R.

[0012] Figures 17 - 24 FIG. is a schematic cross-sectional view illustrating a method of forming a semiconductor structure according to a comparative example of the present invention at different process stages.

[0013] Figure 25 Illustrates Figure 24 an enlarged view of region M in.

[0014]

DESCRIPTION OF REFERENCE NUMERALS

[0015] 10 Method 12, 14, 16 Steps

[0016] 18, 20, 22 Steps 100 Precursor Substrate

[0017] 100a Memory Array Region 100b Peripheral Circuit Region

[0018] 101 Semiconductor Substrate 102G Gate

[0019] 102 High-voltage p-type metal oxide semiconductor transistor 102 S / D source / drain region

[0020] 104 Metal silicide feature structure 105 Conductive feature structure

[0021] 103 Low-voltage n-type metal oxide semiconductor transistor 103 G gate

[0022] 102 S / D source / drain region / drain region

[0023] 106 Metal silicide feature structure 107 Conductive feature structure

[0024] 108 Isolation structure 109 Dielectric layer

[0025] 110 First dielectric layer 110a Dielectric material layer

[0026] 111 First via 111a Sidewall

[0027] 114 Sacrificial material 120 Second dielectric layer

[0028] 120a Dielectric material layer 122 Second via

[0029] 122a Sidewall 130 Stacked structure

[0030] 132 Conductive layer 134 Insulating layer

[0031] 140 Data storage structure 150 Interlayer dielectric layer

[0032] 151 First contact hole 152 Second contact hole

[0033] 160 Barrier layer 170 Conductive material

[0034] 200 Through-hole contact structure 210 First conductive structure

[0035] 212 Top 214 Bottom

[0036] 210a Sidewall 220 Second conductive structure

[0037] 222 Bottom 220a Sidewall

[0038] 230 Barrier layer 240 Semiconductor substrate

[0039] 242 Conductive feature structure 250, 252 Dielectric layer

[0040] 300 Memory device 310 Semiconductor substrate

[0041] 310a Memory array region 310b Peripheral circuit region

[0042] 312 Peripheral circuit 314 Transistor

[0043] 314G gate, 314S / D source / drain region

[0044] 316 silicide, 317, 320 dielectric layer

[0045] 321 first hole, 322 second hole

[0046] 324 overhang, 330 barrier layer

[0047] 340 conductive plug, 350 stacked structure

[0048] 352 conductive layer, 354 insulating layer

[0049] 360 data storage structure, 380 interlayer dielectric layer

[0050] 381 first contact hole, 382 second contact hole

[0051] 384 contact plug, 400 precursor substrate

[0052] 401 semiconductor substrate, 400a memory array region

[0053] 402 high-voltage p-type metal oxide semiconductor transistor, 400b peripheral circuit region

[0054] 402G gate, 402S / D source / drain region

[0055] 403 low-voltage n-type metal oxide semiconductor transistor, 403G gate

[0056] 403S / D source / drain region, 410 first dielectric layer

[0057] 411 first via, 420 first barrier material

[0058] 430 first conductive material, 420 first barrier layer

[0059] 430 first conductive plug, 430a top

[0060] 440 second dielectric layer, 450 stacked structure

[0061] 452 conductive layer, 454 insulating layer

[0062] 456 wire, 460 data storage structure

[0063] 462 data storage layer, 464 insulating material

[0064] 464 semiconductor layer, 470 interlayer dielectric layer

[0065] 471 first contact hole, 472 second contact hole

[0066] Bottom of the second barrier layer 480

[0067] Contact plug 491, second conductive plug 492

[0068] Direction D1, direction D2

[0069] Height direction D3, main surface S

[0070] Top width W1, bottom width W2 Detailed implementation manners

[0071] In order to make the description of the content of the present invention more detailed and complete, the following provides an illustrative description of the implementation forms and specific embodiments of the present invention; however, this is not the only form for implementing or applying the specific embodiments of the present invention. The various embodiments disclosed below can be combined or replaced with each other in beneficial cases, or other embodiments can be added to one embodiment without further record or explanation.

[0072] The following invention provides many different implementation manners or examples to implement different features of the claimed subject matter. The following describes specific implementation manners of components and arrangements to simplify the present invention. Of course, these implementation manners are only examples and are not intended to be limiting. For example, the following describes that forming a first feature on or above a second feature may include an implementation manner in which the first feature and the second feature are formed in direct contact, and may also include an implementation manner in which additional features are formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may use repeated element symbols and / or letters in various implementation manners. This repetition is for the purpose of simplicity and clarity and does not refer to the relationship between the various implementation manners and / or configurations discussed.

[0073] It should be understood that although the terms "first", "second", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element; similarly, a second element may be referred to as a first element without departing from the scope of the implementation manner. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0074] Furthermore, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", and the like are used herein to describe the relationship of one element or feature shown in the figures to another element (or elements) or feature (or features). In addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted similarly.

[0075] In addition, when terms such as "about", "approximately", etc. are used to describe a numerical value or a range of numerical values, the purpose of such terms is to encompass a range of numerical values within a reasonable range, such as + / - 20% of the stated numerical value or other ranges understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.0 nm to 6.0 nm.

[0076] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0077] Figure 1 The flowchart of a method 10 for forming a semiconductor structure according to various embodiments of the present invention is shown. Method 10 includes steps 12, 14, 16, 18, 20, and 22. Figures 2 - 13 The manufacturing method of various embodiments of the present invention is shown in more detail in a series of cross-sectional views. It should be understood that many steps and / or features are described or shown herein, but not all of these steps and / or features are necessary; and other steps and / or features that are not described or shown may be added. In addition, the order of steps in some embodiments may be different from that shown in the figures. Furthermore, in some specific implementations, the steps shown may be further divided into sub-steps; while in other specific implementations, some of the steps shown may be performed simultaneously with another step.

[0078] Please refer to Figure 1 , method 10 includes step 10 of forming a first dielectric layer having at least one first via on a precursor substrate. As Figure 2As shown, a precursor substrate 100 is provided before forming the first dielectric layer. In some embodiments, the precursor substrate 100 includes a semiconductor substrate 101, which has a memory array region 100a and a peripheral circuit region 100b, and the peripheral circuit region 100b is adjacent to the memory array region 100a. For example, the semiconductor substrate 101 may include silicon. In some embodiments, the semiconductor substrate 101 may include other elemental semiconductors, such as germanium. In some other embodiments, the semiconductor substrate 101 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, etc. In still some other embodiments, the semiconductor substrate 101 may include compound semiconductors, such as gallium arsenide, silicon carbide, indium phosphide, indium arsenide, etc. In still some other embodiments, the semiconductor substrate 101 may include a semiconductor-on-insulator (SOI) structure. In still some other embodiments, the semiconductor substrate 101 may include an epitaxial layer covering the semiconductor material.

[0079] According to certain embodiments, the precursor substrate 100 further includes peripheral circuits located in the peripheral circuit region 100b. The peripheral circuits are, for example, high-voltage p-type metal-oxide semiconductor transistors (hereinafter referred to as "HV pMOS") 102 and low-voltage n-type metal-oxide semiconductor transistors (hereinafter referred to as "LV nMOS") 103. The HV pMOS 102 includes a gate 102G and source / drain regions 102S / D. Optionally, a metal silicide feature 104 is formed on the gate 102G. Optionally, a conductive feature 105 (such as a heavily doped region or a metal silicide) is also formed on the source / drain regions 102S / D. Similarly, the LV nMOS 103 includes a gate 103G and source / drain regions 103S / D. Optionally, a metal silicide feature 106 is formed on the gate 103G. Optionally, a conductive feature 105 (such as a heavily doped region or a metal silicide) is formed on the source / drain regions 103S / D. In subsequent processes, a data storage structure will be formed on the memory array region 100a, which will be described in more detail below. In certain embodiments, the precursor substrate 100 further includes one or more isolation structures 108, such as shallow trench isolation structures formed in the semiconductor substrate 101. The isolation structure 108 is formed between the memory array region 100a and the peripheral circuit region 100b, and separates the memory array region 100a from the peripheral circuit region 100b. In some embodiments, at least one isolation structure 108 is formed between the HV pMOS 102 and the LV nMOS 103, and separates the HV pMOS 102 from the LV nMOS 103. In certain other embodiments, the precursor substrate 100 further includes a dielectric layer 109 that covers the source / drain regions 102S / D and 103S / D on the memory array region 100a and the peripheral circuit region 100b, where the gates 102G and 103G are exposed outside the dielectric layer 109. The present invention is not limited thereto.

[0080] Figure 3 and Figure 4 illustrates a method for forming the first dielectric layer having the first via hole in certain embodiments of the present invention. Refer to Figure 3, a dielectric material layer 110a is formed blanketly on a precursor substrate 100. According to some embodiments, the dielectric material layer 110a covers the memory array region 100a and the peripheral circuit region 100b. The dielectric material layer 110a can be formed by processes such as chemical vapor deposition (CVD) process, high density plasma CVD process, sub-atmospheric pressure CVD process, spin-on dielectric (SOD) process, or other suitable deposition techniques. In various examples, the dielectric material layer 110a may comprise, for example, silicon oxide or a suitable low dielectric constant material. Examples of low dielectric constant materials include fluorinated silicon glass (FSG), benzocyclobutene (BCB), carbon-doped silicon oxide, amorphous fluorocarbon, polyimide, and / or other materials.

[0081] Referring to Figure 4 , according to some embodiments, the dielectric material layer 110a is selectively etched to form a first dielectric layer 110 having at least one first via 111 (i.e., one or more first vias 111); wherein the first via 111 penetrates through the first dielectric layer 110. In some embodiments, the first via 111 is formed in the peripheral circuit region 100b. In some embodiments, the first via 111 is aligned with the gates 102G and 103G, thereby exposing the gates 102G and 103G. For example, the salicided metal features 104, 106 of the gates 102G, 103G are exposed through the first via 111. In some embodiments, the first via 111 further exposes the source / drain regions 102S / D, 103S / D. Although Figure 4 illustrates a plurality of first vias 111, the present invention is not limited to a plurality of first vias. For example, forming a single first via 111 can still implement the present invention. In addition, the present invention is not limited to Figure 3 and 4 the illustrated method. Other suitable techniques can be used to form the first dielectric layer 110 having the first via 111.

[0082] Method 10 proceeds to Figure 1 step 14, filling a sacrificial material into the first via. As Figure 5 shown, a sacrificial material 114 is filled in the first via 111. In some embodiments, the sacrificial material 114 is deposited to fill the first via 111 and cover the first dielectric layer 110, and then an etch-back process or a chemical mechanical polishing (CMP) process is performed to remove the excess material deposited on the first dielectric layer 110, thereby forming Figure 5The sacrificial material 114 shown. In some embodiments, the sacrificial material 114 filled in the first vias 111 contacts at least one of the gates 102G, 103G. For example, the salicide features 104 and / or the salicide features 106 of the gates 102G, 103G contact the sacrificial material 114. In embodiments where a plurality of first vias 111 are formed, the sacrificial material 114 in the first vias 111 can further contact the conductive features 105, 107 of the source / drain regions 102S / D, 103S / D. In some embodiments, the sacrificial material 114 is made of a dielectric material capable of suppressing or inhibiting silicide diffusion. For example, the sacrificial material 114 can be made of silicon nitride or the like. As used herein, the terms "made of" and "formed of" mean "comprising" or "consisting of" in meaning. The sacrificial material 114 formed at this stage or step will provide specific technical effects for subsequent processes, which will be described in detail below.

[0083] Method 10 proceeds to Figure 1 Step 16 of forming a second dielectric layer having at least one second via over the first dielectric layer. There are various ways to implement step 16, which will be described below in conjunction with Figures 6 - 11 The following descriptions are only embodiments or examples, and the present invention is not limited thereto. In addition, other features and / or structures can be formed simultaneously during the process of forming the second dielectric layer having the second via.

[0084] As Figure 6 shown, according to certain embodiments, a dielectric material layer 120a is formed over the first dielectric layer 110 and the sacrificial material 114. In certain embodiments, the dielectric material layer 120a further covers the first dielectric layer 110 in the memory array region 100a. In certain embodiments, the dielectric material layer 120a seals the sacrificial material 114 in the first vias 111. In some other embodiments, the dielectric material layer 120a is made of the same material as the first dielectric layer 110, but the material of the dielectric material layer 120a is different from that of the sacrificial material 114. For example, the first dielectric layer 110 and the dielectric material layer 120a comprise an oxide layer, and the sacrificial material 114 comprises silicon nitride. In some other embodiments, the first dielectric layer 110 and the dielectric material layer 120a can be of different materials. For example, one of them is silicon oxynitride and the other is silicon oxide, and the sacrificial material 114 comprises silicon nitride, but the present invention is not limited thereto. Please refer to Figure 7, in some embodiments, a part of the first dielectric layer 110 and a part of the dielectric material layer 120a are replaced, exposing the memory array region 100a. For example, an etching process can be used to replace part of the first dielectric layer 110 and part of the dielectric material layer 120a. Specifically, after replacing the first dielectric layer 110 and the dielectric material layer 120a above the memory array region 100a, the main surface S of the memory array region 100a on the semiconductor substrate 101 is exposed.

[0085] Please refer to Figure 8 , in some embodiments, a stacked structure 130 including a plurality of conductive layers 132 and a plurality of insulating layers 134 is formed on the memory array region 100a, wherein the conductive layers 132 and the insulating layers 134 are stacked alternately with each other. In some embodiments, the stacked structure 130 may include dozens to hundreds of conductive layers 132 and insulating layers 134. The conductive layer 132 can be formed of any suitable conductive material, such as a semiconductor material, a metal material, or a conductive material. Examples of the semiconductor material include doped polysilicon or undoped polysilicon, and the metal materials include titanium nitride, copper, tungsten, platinum. The present invention is not limited thereto, and those skilled in the art can make selections according to actual needs. The insulating layer 134 can be formed of any suitable dielectric material, such as silicon oxide or a low dielectric constant dielectric material. Examples of the low dielectric constant material include fluorinated silicon glass (FSG), bisbenzocyclobutene (BCB), carbon-doped silicon oxide, amorphous fluorocarbon, polyimide, and / or other materials.

[0086] Please refer to Figure 9 , in some embodiments, a plurality of data storage structures 140 are formed in the stacked structure 130. According to some embodiments, each data storage structure 140 extends along the direction D1. In other words, in these embodiments, the length direction of the data storage structure 140 is substantially perpendicular to the main surface S of the memory array region 100a. In a plurality of embodiments, each data storage structure 140 includes a data storage layer 142, an insulating material 146, and a semiconductor layer 144 located between the data storage layer 142 and the insulating material 146. For example, the data storage layer 142 may include an "ONO" structure (oxide-nitride-oxide), an "ONONO" structure (oxide-nitride-oxide-nitride-oxide), or a "TANOS" structure (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon). The semiconductor layer 144 can be made of, for example, polysilicon or other suitable semiconductor materials. The insulating material 146 can be made of, for example, silicon oxide or a low dielectric constant material. In some embodiments, the insulating material 146 and the insulating layer 134 (labeled in Figure 8) are made of the same material. In addition, any known method can be used to form the data storage structure 140. Briefly, the stacked structure 130 is selectively etched to form a plurality of trenches 138 in the stacked structure 130, and then a data storage layer 142 is formed on the sidewalls of the trenches 138. Thereafter, a semiconductor layer 144 and an insulating material 146 are formed in the remaining space of the trenches 138.

[0087] Please refer to Figure 10 , in some embodiments, an interlayer dielectric layer 150 is formed above the data storage structure 140 in the memory array region 100a and above the dielectric material layer 120a in the peripheral circuit region 100b. Any known techniques and materials can be used to form the interlayer dielectric layer 150. In some embodiments, the thickness of the interlayer dielectric layer 150 is less than the total thickness of the first and second dielectric layers 110, 120.

[0088] Please refer to Figure 11 , in some embodiments, the dielectric material layer 120a is selectively etched to form a second dielectric layer 120 having at least one second via 122 (i.e., one or more second vias 122), wherein the second via 122 exposes the sacrificial material 114 within the first via 111. As described above, in the embodiments where the interlayer dielectric layer 150 is formed, the step of selectively etching the dielectric material layer 120a further includes selectively etching the interlayer dielectric layer 150 to form a plurality of first contact holes 151 and a plurality of second contact holes 152. The first contact holes 151 expose the data storage structure 140 on the memory array region 100a, and the second contacts 152 communicate with the second vias 122 on the peripheral circuit region 100b. In some embodiments, the etching process for forming the second vias 122 can substantially stop on the sacrificial material 114 or slightly etch the sacrificial material 114. Furthermore, the bottom width W2 of the second via 122 is less than the top width W1 of the first via 111. In some embodiments, the first and second vias 111, 122 each have an aspect ratio of about 25 to about 50, such as 30, 35, 40, or 45. Although Figure 11 illustrates a plurality of first vias 111 and a plurality of second vias 122, the present invention is not limited to a plurality of first vias and a plurality of second vias 122. For example, forming only a single first via 111 and a single second via 122 can still implement the present invention.

[0089] Although the foregoing and Figure 11It is illustrated that the second via 122 is formed after the formation of the stacked structure 130, the data storage structure 140, and the interlayer dielectric layer 150. Note, however, that the second via 122 may be formed before the formation of the stacked structure 130, the data storage structure 140, and / or the interlayer dielectric layer 150. In some embodiments, the second via 122 may be formed before the formation of the stacked structure 130. Specifically, in some embodiments, the second via 122 may be formed immediately after the formation of the dielectric material layer 120 shown in Figure 6 Or, according to some other embodiments, the second via 122 may be formed simultaneously in the process shown in Figure 7 i.e., etching a portion of the first dielectric layer 110 and a portion of the dielectric material layer 120a.

[0090] According to some other embodiments, although Figure 8 and Figure 9 the stacked structure 130 and the data storage structure 140 described are formed after steps 12 and 14, the stacked structure 130 and the data storage structure 140 may be formed before step 12. For example, the stacked structure 130 and the data storage structure 140 may be formed on the semiconductor substrate 101 before the formation of the first dielectric layer 110 and / or the peripheral circuits (e.g., HV pMOS 102 and LV nMOS 103) on the precursor substrate 100. In addition, according to other embodiments, although Figures 9 - 11 the HV pMOS 102 and the LV nMOS 103 are shown at a level lower than the top of the stacked structure 130 and the data storage structure 140, the HV pMOS 102 and the LV nMOS 103 may be formed at a position higher than the top of the stacked structure 130 and the data storage structure 140.

[0091] Please return to Figure 1 , method 10 proceeds to step 18, where the sacrificial material is replaced after the formation of the second dielectric layer with the second via. As Figure 12 shown, the sacrificial material 114 in the first via 111 is replaced. For example, the sacrificial material 114 may be replaced by a wet etching process using a hot phosphoric acid solution as the etchant. After replacing the sacrificial material 114, the sidewalls 111a, 122a of the first and second vias 111, 122 are exposed, and the second via 122 communicates with the first via 111. In some embodiments, after replacing the sacrificial material 114, the salicided metal features 104, 106 of the gates 102G, 103G and the conductive features 105, 107 of the source / drain regions 102S / D, 103S / D are exposed through the first and second vias 111, 122.

[0092] Method 10 proceeds to Figure 1In step 20, a barrier layer is formed lining the sidewalls of the first via and the second via. As Figure 13 shown, a barrier layer 160 is formed lining the sidewalls 111a, 122a of the first and second vias 111, 122. In various embodiments, the barrier layer 160 is continuous from the sidewall 111a of the first via 111 to the sidewall 122a of the second via 122. Specifically, the barrier layer 160 has a sawtooth profile in a cross-section along the height direction of the first and second vias 111, 122. In some other embodiments, the barrier layer 160 is further formed at the bottom of the first via 111, so that the barrier layer 160 contacts the salicide features 104, 106 of the gates 102G, 103G and / or the conductive features 105, 107 of the source / drain regions 102S / D, 103S / D. In embodiments where the first and second contact holes 151, 152 are formed in the interlayer dielectric layer 150, the barrier layer 160 also lines the first and second contact holes 151, 152. In multiple embodiments, the barrier layer 160 can be formed using a suitable chemical vapor deposition process, such as a high density plasma chemical vapor deposition process, a sub-atmospheric chemical vapor deposition process, a flow-type chemical vapor deposition process, or other suitable deposition techniques. In addition, the barrier layer 160 can also be referred to as an "adhesion layer". In some embodiments, the barrier layer 160 can include titanium, titanium nitride, tantalum nitride, or a combination of the above or similar materials. In some other embodiments, the barrier layer 160 can include silicon nitride, silicon oxynitride (SiON), or a combination of the above or similar materials.

[0093] Method 10 proceeds to Figure 1 step 22, forming a conductive material within the first and second vias. Please continue to refer to Figure 13 , a conductive material 170 is formed filling the first and second vias 111, 122. Specifically, when the barrier layer 160 lines the first and second vias 111, 122, there is still remaining space within the first and second vias 111, 122. The conductive material 170 fills the remaining space within the first and second vias 111, 122. In embodiments where the interlayer dielectric layer 150 having the first and second contact holes 151, 152 is formed, the conductive material 170 also fills the first and second contact holes 151, 152. In multiple embodiments, the conductive material 170 can be formed of tungsten, aluminum, aluminum silicide, tungsten silicide, copper, or an alloy including tungsten, or similar materials.

[0094] According to certain embodiments, the barrier layer 160 and the conductive material 170 may be formed by the following method. First, a conformal blanket layer of barrier material is deposited such that the barrier material is deposited on the inner surfaces of the first and second vias 111, 122 and on the inner surfaces of the first and second contact holes 151, 152, and the deposited barrier material also covers the interlayer dielectric layer 150. Then, a layer of conductive material is deposited to fill the first and second vias 111, 122 and the first and second contact holes 151, 152, and the conductive material is also deposited over the interlayer dielectric layer 150. Thereafter, a chemical mechanical polishing or etch-back process is performed to remove the excess barrier material and conductive material deposited over the interlayer dielectric layer 150, thereby forming Figure 13 the illustrated barrier layer 160 and conductive material 170.

[0095] The methods disclosed herein provide various advantages in manufacturing processes and semiconductor devices. Specifically, this method is suitable for forming contact holes with a high aspect ratio, such as an aspect ratio greater than 30 or more, especially where the barrier layer 160 continuously extends from the sidewall 111a of the first via 111 to the sidewall 122a of the second via 122. Furthermore, no barrier layer is interposed in the conductive material 170. In addition, the methods disclosed herein can prevent the formation of oxides in the conductive material 170 within the first and second vias 111, 122 because the conductive material 170 is formed using a single deposition process. Therefore, the electrical performance of the manufactured via contact structure is reliable, and the manufacturing process is robust. Furthermore, referring to Figure 5 , a sacrificial material 114 is formed in the first via 111 on the silicided metal feature structure, and during the subsequent process of forming the data storage structure 140 (refer to Figures 8 - 9 ), the sacrificial material 114 can inhibit or mitigate the diffusion of the silicided metal into the dielectric layer. The above or other various advantages can be more fully understood after referring to Figures 17 - 24 the illustrated comparative examples, which will be described in more detail below.

[0096] Another form of the present invention is to provide a via contact structure. Figure 14 A cross-sectional schematic view of a via contact structure 200 according to various embodiments of the present invention is shown. The via contact structure 200 may be formed in a semiconductor device such as a memory device or other functional device. For example, the via contact structure 200 may be formed in the peripheral circuit region of a 3D NAND flash memory. As Figure 14 shown, the via contact structure 200 at least includes a first conductive structure 210, a second conductive structure 220, and a barrier layer 230.

[0097] According to certain embodiments, the first conductive structure 210 is disposed over and aligned with the conductive feature 242 of the semiconductor substrate 240. The first conductive structure 210 includes a top 212 and a bottom 214, where the width and / or cross-sectional area of the top 212 is greater than the width and / or cross-sectional area of the bottom 214. The first conductive structure 210 has a major axis direction D2 that is substantially perpendicular to the surface of the semiconductor substrate 240.

[0098] The second conductive structure 220 is disposed on the top 212 of the first conductive structure 210. In certain embodiments, the second conductive structure 220 extends upward from the top 212 of the first conductive structure 210 along the major axis direction D2. The second conductive structure 220 has a bottom 222 that contacts the top 212 of the first conductive structure 210. The width and / or cross-sectional area of the bottom 222 of the second conductive structure 220 is less than the width and / or cross-sectional area of the top 212 of the first conductive structure 210. Here, the term "cross-sectional area" for the top 212 and the bottom 222 is defined in a cross-section perpendicular to the direction D2. Accordingly, a partial portion 212a of the top 212 is not occupied by the bottom 222 of the second conductive structure 220. In certain embodiments, the first and second conductive structures 210, 220 each have an aspect ratio of from about 25 to about 50, such as 30, 35, 40, or 45.

[0099] The barrier layer 230 coats the sidewalls 210a, 220a of the first and second conductive structures 210, 220. The barrier layer 230 further covers the unoccupied partial portion 212a of the top 212 of the first conductive structure 210. Note that the barrier layer 230 is continuous from the sidewall 210a of the first conductive structure 210, through the unoccupied partial portion 212a of the top 212, and extends to the sidewall 220a of the second conductive structure 220. In various embodiments, the barrier layer 230 has a sawtooth profile in a cross-section along the direction D2 (also referred to as the "height direction"). In certain embodiments, the barrier layer 230 also coats the bottom 214 of the first conductive structure 210.

[0100] According to certain embodiments, the via contact structure 200 can be embedded in the dielectric layers 250, 252 over the semiconductor substrate 240. In multiple embodiments, the dielectric layers 250, 252 surround the outer sidewalls of the barrier layer 230, where the barrier layer 230 surrounds the sidewalls of the first and second conductive structures 210, 220.

[0101] Another form of the present invention is to provide a memory device. Figure 15A cross-sectional schematic diagram of a memory device 300 showing various embodiments of the present invention. The memory device 300 at least includes a semiconductor substrate 310, dielectric layers 317, 320, a barrier layer 330, and conductive plugs 340.

[0102] The semiconductor substrate 310 includes a memory array region 310a and a peripheral circuit region 310b connected to the memory array region 310a. According to some embodiments, although Figure 15 only a part of the memory device 300 is shown, the peripheral circuit region 310b can actually surround the memory array region 310a. The semiconductor substrate 310 also includes a peripheral circuit 312 located on the peripheral circuit region 310b. In some embodiments, the peripheral circuit 312 includes transistors 314 (such as HV pMOS or LV nMOS), and the transistors 314 have gates 314G and source / drain regions 314S / D. In multiple embodiments, a metal silicide 316 can be formed on the gate 314G and / or the source / drain region 314S / D of the transistor 314. On the memory array region 310a, a plurality of data storage structures are provided, which will be described in detail below.

[0103] The dielectric layers 317, 320 are disposed above the peripheral circuit 312. The dielectric layers 317, 320 respectively have a first hole 321 and a second hole 322. The second hole 322 is located above the first hole 321 and is connected to the first hole 321. Figure 16A Shown Figure 15 is an enlarged view of the region R. Figure 16B A plan view showing the first hole 321 and the second hole 322 along the section plane C in the region R. As Figure 16A and Figure 16B shown, the second hole 322 has a bottom width W2 and a bottom area 322B. The bottom width W2 and the bottom area 322B are respectively smaller than the top width W1 and the top area 321T of the first hole 321, so that the dielectric layer 320 forms an overhang 324 at the connection between the first hole 321 and the second hole 322. In multiple embodiments, the overhang 324 has a bottom surface 324b, and the bottom surface 324b extends from the sidewall 321a of the first hole 321 to the sidewall 322a of the second hole 322. According to some embodiments, each of the dielectric layers 317, 320 has a plurality of first holes 321 and a plurality of second holes 322, as Figure 15 shown. Each second hole 322 is located above a corresponding first hole 321 and is connected to this corresponding first hole; each first hole 321 and each second hole 322 have structures similar to or the same as those Figure 16A and Figure 16B shown.

[0104] The barrier layer 330 continuously lines the sidewalls 321a, 322a and the overhang 324 of the first and second holes 321, 322. Specifically, the barrier layer 330 continuously extends from the sidewall 321a of the first hole 321, through the bottom surface 324b of the overhang 324, to the sidewall 322a of the second hole 322. The barrier layer 330 only partially fills the first and second holes 321, 322, so there is still remaining space in the first and second holes 321, 322. For example, the thickness of the barrier layer 330 is from several tens of angstroms to several tens of nanometers. In some embodiments, as Figure 15 shown, the barrier layer 330 has a sawtooth profile in the cross-section along the height direction D3 of the first and second holes 321, 322. In some other embodiments, the barrier layer 330 is also formed at the bottom of the first hole 321, so the barrier layer 330 contacts the metal silicide 316 on the transistor 314. According to some embodiments, although Figure 15 and FIG. 16 show the barrier layer 330 as a single layer, note that the barrier layer 330 may include multiple sub-layers or sub-layers (composite layers), so that the barrier layer 330 has the dual functions of an adhesion layer and a barrier layer. Therefore, the barrier layer 330 can also be referred to as an "adhesion layer".

[0105] The conductive plugs 340 are filled in the first hole 321 and the second hole 322. In some embodiments, the conductive plugs 340 fill the remaining space in the first hole 321 and the second hole 322. Although Figure 15 、 Figure 16A and Figure 16B show only the barrier layer 330 and the conductive plugs 340 formed in the first hole 321 and the second hole 322, other layer structures can be formed between the barrier layer 330 and the conductive plugs 340. In some embodiments, the barrier layer 330 covers the conductive plugs 340 except for the top of the conductive plugs 340. According to some other embodiments, the conductive plugs 340 are aligned with the metal silicide 316 on the peripheral circuit 312. In embodiments where the dielectric layers 317, 320 each have a plurality of first holes 321 and a plurality of second holes 322, the memory device 300 includes a plurality of conductive plugs 340. Each conductive plug 340 is filled in the corresponding first hole 321 and second hole 322. Therefore, some conductive plugs 340 connect to the gate 314G of the transistor 314, and some conductive plugs 340 connect to the source / drain regions 314S / D of the transistor 314. Exemplary materials for the conductive plugs 340 include tungsten, aluminum, aluminum silicide (AlSi), tungsten silicide (WSi), copper, or similar materials.

[0106] In some embodiments, the memory device 300 further includes a stacked structure 350 located on the memory array region 310a. The stacked structure 350 includes a plurality of conductive layers 352 and a plurality of insulating layers 354 that are alternately stacked with each other. The embodiments of the stacked structure 350 may be the same as or similar to the stacked structure 130 described above with respect to Figure 8 and thus will not be repeated.

[0107] In some embodiments, the memory device 300 further includes a plurality of data storage structures 360 located on the memory array region 310a. According to some embodiments, each data storage structure 360 penetrates the stacked structure 350. The embodiments of the data storage structures 360 may be the same as or similar to the data storage structures 140 described above with respect to Figure 9 and thus will not be repeated.

[0108] In other embodiments, the memory device 300 further includes an interlayer dielectric layer 380 located on the dielectric layer 320. According to some embodiments, the interlayer dielectric layer 380 has a plurality of first contact holes 381 and a plurality of second contact holes 382. In some embodiments, the barrier layer 330 lines the inner surfaces of the first contact holes 381 and the second contact holes 382. In some other embodiments, each first contact hole 381 is aligned with a corresponding one of the data storage structures 360. According to some other embodiments, the memory device 300 further includes contact plugs 384 filling the remaining space in the first contact holes 381. In an embodiment, each second contact hole 382 is connected to a corresponding second hole 322 in the dielectric layer 320, and thus the conductive plugs 340 also fill the second contact holes 382.

[0109] Figures 17 - 24 A cross-sectional schematic diagram showing a method of forming a semiconductor structure according to a comparative example of the present invention. Those of ordinary skill in the art to which the present invention pertains can more clearly understand the various advantages of the content of the present invention after comparing Figures 17 - 24 the method shown with the embodiments of the present invention.

[0110] In Figure 17In, a first dielectric layer 410 is formed on a precursor substrate 400. The precursor substrate 400 includes a semiconductor substrate 401 which has a memory array region 400a and a peripheral circuit region 400b adjacent to the memory array region 400a. The precursor substrate 400 further includes an HV pMOS 402 and an LV nMOS 403 on the peripheral circuit region 400b. The HV pMOS 402 includes a gate 402G and source / drain regions 402S / D. Similarly, the LV nMOS 403 includes a gate 403G and source / drain regions 403S / D. The formed first dielectric layer 410 has a plurality of first vias 411. Some of the first vias 411 expose the gates 402G, 403G, while some other first vias 411 expose the source / drain regions 402S / D, 403S / D. Thereafter, a first barrier material 420 is deposited to line the first vias 411 and cover the first dielectric layer 410, and then a first conductive material 430 is deposited on the first barrier material 420 and fills the first vias 411.

[0111] In Figure 18 a, an etch process or a chemical mechanical polishing process is performed to remove the excess material deposited above the first dielectric layer 410. Thus, a first barrier layer 420 lining the first vias 411 and a plurality of first conductive plugs 430 filling the first vias 411 are formed.

[0112] In Figure 19 a, a second dielectric layer 440 is formed to cover the first dielectric layer 410, the first barrier layer 420, and the first conductive plugs 430.

[0113] In Figure 20 a, a portion of the first and second dielectric layers 410, 440 is removed to expose the memory array region 400a. The remaining portions of the first and second dielectric layers 410, 440 still cover the peripheral circuit region 400b.

[0114] In Figure 21 a, a stacked structure 450 including a plurality of conductive layers 452 and a plurality of insulating layers 454 is formed on the memory array region 400a, wherein the conductive layers 452 and the insulating layers 454 are stacked alternately with each other. During the formation of the stacked structure 450, a plurality of conductive lines 456 are formed simultaneously. Each conductive line 456 is connected to a corresponding one of the conductive layers 452.

[0115] In Figure 22 a, a plurality of data storage structures 460 are formed in the stacked structure 450. Each data storage structure 460 includes a data storage layer 462, an insulating material 464, and a semiconductor layer 464 located between the data storage layer 462 and the insulating material 464.

[0116] In Figure 23In [description], a blanket-type interlayer dielectric layer 470 is formed to cover the second dielectric layer 440, the stacked structure 450, and the data storage structure 460. Subsequently, the interlayer dielectric layer 470 and the second dielectric layer 440 are etched to form a first contact hole 471 and a second contact hole 472 in the interlayer dielectric layer 470 and a second via hole 442 in the second dielectric layer 440. The first contact hole 471 exposes the data storage structure 460. The second contact hole 472 is located in the peripheral circuit region 400b. The second via hole 442 penetrates through the second dielectric layer 440. The second contact hole 472 is aligned with and communicates with the second via hole 442, thereby exposing the first conductive plug 430.

[0117] In Figure 24 [description], a second barrier layer 480 is formed to line the inner surfaces of the first and second contact holes 471, 472 and the second via hole 442. Then, a second conductive material is deposited to fill the remaining spaces of the first and second contact holes 471, 472 and the second via hole 442, thereby forming a contact plug 491 in the first contact hole 471 and a second conductive plug 492 in the second via hole 442 and the second contact hole 472.

[0118] Figure 25 Shows Figure 24 An enlarged view of region M in [description]. As shown, note that the first barrier layer 420 does not physically contact the second barrier layer 480. Specifically, a portion of the top 430a of the first conductive plug 430 is not covered by any of the first barrier layer 420 or the second barrier layer 480, which will lead to a reduction in the reliability of the contact structure. In addition, the bottom 480a of the second barrier layer 480 is inserted between the first conductive plug 430 and the second conductive plug 492. The bottom 480a constructs an additional interface between the first and second conductive plugs 430, 492, which also reduces the performance and reliability of the overall contact structure. Furthermore, please go back to Figure 18 [description], when performing an etch-back process or a chemical mechanical polishing process to remove the excess material deposited above the first dielectric layer 410, the top 430a of the first conductive plug 430 is exposed to air (including oxygen), so an undesired oxide will form on the top 430a. To ensure the conductivity of the first conductive plug 430 and avoid various problems in subsequent processes, before forming Figure 19 the second dielectric layer 440 shown, an additional etching process must be performed to remove the oxide on the top 430a.

[0119] According to various embodiments of the present invention, the various disadvantages of the above comparative examples can be solved. Please go back to Figure 14, the barrier layer 230 covers the sidewalls 210a, 220a of the first and second conductive structures 210, 220, and further covers the unoccupied partial portion 212a of the top 212 of the first conductive structure 210. Note that the barrier layer 230 is continuous from the sidewall 210a of the first conductive structure 210, through the unoccupied partial portion 212a of the top 212, to the sidewall 220a of the second conductive structure 220. In addition, no barrier layer is interposed between the first and second conductive structures 210, 220. Furthermore, the first and second conductive structures 210, 220 are formed using a single deposition step. Therefore, the embodiments of the present invention solve all the disadvantages of the comparative examples.

[0120] Although the present invention has been disclosed above in embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising: forming a first dielectric layer having a first via on a precursor substrate, the first via penetrating through the first dielectric layer; filling a sacrificial material into the first via; forming a second dielectric layer having a second via above the first dielectric layer, the second via exposing the sacrificial material in the first via, wherein the second via has a bottom width that is less than a top width of the first via, and the first via and the second via at least partially overlap in a direction perpendicular to the precursor substrate; forming an interlayer dielectric layer having a second contact hole above the second dielectric layer, the second contact hole communicating with the second via; replacing the sacrificial material after forming the second dielectric layer having the second via; forming a barrier layer lining a sidewall of the first via, a sidewall of the second via, and a sidewall of the second contact hole; and forming a conductive material in the first and second vias.

2. The method according to claim 1, wherein the barrier layer continuously extends from the sidewall of the first via to the sidewall of the second via.

3. The method according to claim 1, wherein the barrier layer has a sawtooth profile in a cross-section along a height direction of the first and second vias.

4. The method according to claim 1, wherein the precursor substrate includes a memory array region and a peripheral circuit region adjacent to the memory array region, and the first and second vias and the sacrificial material are formed in the peripheral circuit region.

5. The method according to claim 1, wherein forming the second dielectric layer having the second via above the first dielectric layer includes: depositing a dielectric material layer blanketly on the first dielectric layer and the sacrificial material; and selectively etching the dielectric material layer to form the second via.

6. The method according to claim 5, after depositing the dielectric material layer but before selectively etching the dielectric material layer to form the second via, further including replacing a part of the first dielectric layer and a part of the dielectric material layer to expose the memory array region.

7. The method according to claim 4, wherein forming the interlayer dielectric layer having a second contact hole above the second dielectric layer further includes: forming a first contact hole that exposes a data storage structure on the memory array region.

8. The method according to claim 7, wherein forming a barrier layer lining a sidewall of the first via, a sidewall of the second via, and a sidewall of the second contact hole further includes: forming a barrier layer lining a sidewall of the first contact hole.

9. A memory device, comprising: a semiconductor substrate, including a memory array region and a peripheral circuit adjacent to the memory array region; a dielectric layer disposed above the peripheral circuit, the dielectric layer having a first hole and a second hole, the second hole being connected and located above the first hole, wherein a bottom width of the second hole is less than a top width of the first hole, such that the dielectric layer forms an overhang at a connection of the first hole and the second hole; An interlayer dielectric layer is disposed above the dielectric layer. The interlayer dielectric layer has a second contact hole that connects to the second hole. A barrier layer continuously extends from a sidewall of the first hole through the overhang portion to a sidewall of the second hole and a sidewall of the second contact hole. And A conductive plug is filled in the first hole, the second hole, and the second contact hole.

10. The memory device according to claim 9, further comprising: A stacked structure is located in the memory array region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked with each other: and A plurality of data storage structures are located in the memory array region. Each of the data storage structures penetrates the stacked structure.

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