Superjunction semiconductor device and method for manufacturing superjunction semiconductor device

Abstract

The present invention provides a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device that can suppress the reduction in withstand voltage caused by manufacturing deviation. The semiconductor device has a terminal structure (40) and an active area (30) for current flow. A first semiconductor layer (2) of the first conductivity type is provided on the front surface of a semiconductor substrate (1) of the first conductivity type. A first parallel pn structure is provided on the surface of the active area (30) of the first semiconductor layer (2) in which first columns (3a) of the first conductivity type and second columns (4a) of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second parallel pn structure is provided in which third columns (3b) of the first conductivity type and fourth columns (4b) of the second conductivity type are repeatedly and alternately arranged in the terminal structure (40), and a first semiconductor area (17) of the second conductivity type including a plurality of areas separated from each other is provided on the surface of the second parallel pn structure.

Description

Technical Field

[0001] The present invention relates to a super junction semiconductor device and a method for manufacturing the super junction semiconductor device. Background Art

[0002] In a conventional n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor), among the multiple semiconductor layers formed in the semiconductor substrate, the n-type conduction layer (drift layer) is the semiconductor layer with the highest resistance. The resistance of the n-type drift layer has a great influence on the on-resistance of the entire vertical MOSFET. The reduction of the on-resistance of the entire vertical MOSFET can be achieved by reducing the thickness of the n-type drift layer and shortening the current path.

[0003] However, in the off state, the depletion layer of the vertical MOSFET expands to the high-resistance n-type drift layer, thereby also having the function of maintaining the withstand voltage. Therefore, in the case of thinning the n-type drift layer in order to reduce the on-resistance, the expansion distance of the depletion layer in the off state will be shortened, so it is easy to reach the breakdown electric field strength under a low applied voltage, thereby reducing the withstand voltage. On the other hand, in order to improve the withstand voltage of the vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer to increase the on-resistance. Such a relationship between the on-resistance and the withstand voltage is called a trade-off relationship, and it is usually difficult to improve both of them in the trade-off relationship. It is known that the trade-off relationship between the on-resistance and the withstand voltage is also established in semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor), bipolar transistors, and diodes.

[0004] As a structure of a semiconductor device that solves the above-mentioned problems, a super junction (SJ) structure is known. For example, a MOSFET having a super junction structure (hereinafter referred to as SJ-MOSFET) is known. Fig.19 is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

[0005] like Fig.19 As shown, the SJ-MOSFET 150 is formed at a high impurity concentration n + A wafer in which an n-type drift layer 102 is grown on an n-type semiconductor substrate 101 is used as a material. A plurality of n-type drift layers 102 are provided from the surface of the wafer through the n-type drift layer 102 and to the n-type semiconductor substrate 101. + The p-type column region 104 of the p-type semiconductor substrate 101 is formed.

[0006] In addition, in the n-type drift layer 102, a p-type region (p-type column region 104) extending in a direction perpendicular to the substrate main surface and having a narrow width in a plane parallel to the substrate main surface and an n-type region (a portion of the n-type drift layer 102 sandwiched between adjacent p-type column regions 104, hereinafter referred to as n-type column region 103) are alternately arranged in a plane parallel to the substrate main surface (hereinafter referred to as a parallel pn region) in a parallel structure. The p-type column region 104 and the n-type column region 103 constituting the parallel pn region are regions with increased impurity concentrations corresponding to the n-type drift layer 102. By making the impurity concentrations contained in the p-type column region 104 and the n-type column region 103 in the parallel pn region substantially equal, it is possible to generate a similar undoped layer in the off state and achieve a high withstand voltage.

[0007] A p-type base region 105 is provided in the parallel pn region on the active region 130 side where the element is formed and current flows in the on state of the SJ-MOSFET 150. An n-type base region 105 is provided inside the p-type base region 105. + A gate insulating film 107 is provided over the surface of the p-type base region 105 and the n-type column region 103. A gate electrode 108 is provided on the surface of the gate insulating film 107, and an insulating film 113 is provided to cover the gate electrode 108. + A source electrode 110 is disposed on the n-type source region 106, and + A drain electrode 114 is provided on the back surface of the semiconductor substrate 101 .

[0008] In the edge termination region 140 surrounding the active region 130 of the SJ-MOSFET 150, a parallel pn region and an insulating film 113 are provided in the n-type drift layer 102, similarly to the active region 130. + A drain electrode 114 is provided on the back surface of the semiconductor substrate 101 .

[0009] In the power semiconductor element, the edge termination region 140 must also maintain a withstand voltage similarly to the active region 130. In order to obtain a high withstand voltage in the edge termination region 140, a field plate, a resurf, a guard ring, and the like are known as well-known techniques. Fig.19An SJ-MOSFET 150 having a reduced surface electric field structure is shown. In the SJ-MOSFET 150, the electric field concentration in the edge termination region 140 can be alleviated by partially or completely depleting the reduced surface electric field region 117 while maintaining the withstand voltage. In addition, the reduced surface electric field region 117 can also be connected to the parallel pn region. In this case, the depletion layer expands from the junction of the parallel pn region connected to the reduced surface electric field region 117, so that the drift layer is completely depleted at a low voltage. As the voltage rises, the parallel pn region acts as a guard ring, the depletion layer further expands from the adjacent parallel pn region, and the depletion layers are combined with each other to form a depletion layer when fully depleted, thereby ensuring a high withstand voltage.

[0010] For example, the following semiconductor device is known (for example, refer to the following patent document 1): in an SJ-MOSFET including an n-type column layer 2 and a p-type column layer 3 in an element portion and an n-type column layer 10 and a p-type column layer 11 in an element terminal portion, a high resistance n-type column layer 10 is provided on the upper surface of the n-type column layer 10 and the p-type column layer 11 in the element terminal portion. - The p-type layer 12 includes an outermost p-type column layer 14 between the n-type column layer 2 of the element part and the high resistance n-type layer 12. In addition, a p-type base layer 4 is provided at the boundary between the element part and the element terminal part, and a RESURF layer 13 is provided adjacent to the p-type base layer 4.

[0011] In addition, the following semiconductor device is known (for example, refer to the following patent document 2): in an SJ-MOSFET in which the repetition pitch P2 of the second parallel pn layer 15 in the element peripheral portion 3 is smaller than the repetition pitch P1 of the first parallel pn layer 12 in the central portion of the element active portion 1, a p base region 5 is provided at the boundary between the first parallel pn layer 12 and the second parallel pn layer 15 so as to extend over a plurality of first p-type regions 14 and second p-type regions 17, and an n base region 5 surrounding the first parallel pn layer 12 is provided between the second parallel pn layer 15 and the first main surface. - Surface area 19, in addition, in n - Two or more p-type guard ring regions 20 are provided on the first main surface side of the surface region 19 so as to be separated from each other.

[0012] In addition, the following semiconductor device is known (for example, refer to the following patent document 3): the p-type column region 6 of the peripheral region 120 is in contact with the p-type connection region 17, the p-type connection region 17 is in ohmic contact with the source electrode 10 via the body region 5', and there is an n-type depleted semiconductor region 18 between the p-type connection region 17 and the first main surface 101, and the doping concentration of the n-type depleted semiconductor region 18 is higher than the doping concentration of the low-doped semiconductor region 2 between the terminal of the pn column and the field stop region 8 arranged at the outermost periphery.

[0013] Prior art literature

[0014] Patent Literature

[0015] Patent Document 1: Japanese Patent Application Publication No. 2006-5275

[0016] Patent Document 2: Japanese Patent Application Publication No. 2013-149761

[0017] Patent Document 3: U.S. Patent No. 9281392 Summary of the invention

[0018] Technical issues

[0019] In the parallel pn region, when the impurity amount of the n-type column region 103 is approximately equal to the impurity amount of the p-type column region 104 (the state where the charge balance is "1"), the withstand voltage of the SJ-MOSFET 150 is at its maximum value. However, due to the manufacturing deviation of the semiconductor device, the impurity amount of the parallel pn region is prone to deviation. As a result, the charge balance is unbalanced, and the withstand voltage is prone to decrease. Furthermore, due to the deviation of the impurity amount of the surface electric field reduction region 117 and the diffusion depth of the impurities, the withstand voltage is more likely to decrease. As a result, there is a problem that a single unit with low withstand voltage of the element is prone to occur.

[0020] The present invention aims to solve the above-mentioned problems of the prior art and to provide a superjunction semiconductor device and a method for manufacturing the superjunction semiconductor device that can suppress a decrease in withstand voltage caused by manufacturing variations.

[0021] Technical Solution

[0022] In order to solve the above problems and achieve the purpose of the present invention, the superjunction semiconductor device of the present invention has the following characteristics. It is a superjunction semiconductor device having a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region. A first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of a semiconductor substrate of a first conductivity type. On the upper surface of the first semiconductor layer, a first parallel pn structure in which a first column of a first conductivity type and a second column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface is provided in the active region. On the upper surface of the first semiconductor layer, a second parallel pn structure in which a third column of a first conductivity type and a fourth column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface is provided in the terminal structure. On the surface of the second parallel pn structure of the terminal structure, a first semiconductor region of a second conductivity type including a plurality of regions separated from each other is provided. On the surface of the second column of the second conductivity type of the first parallel pn structure of the active region, a second semiconductor region of a second conductivity type is provided. A third semiconductor region of the first conductivity type is selectively provided on a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate side. A gate insulating film is provided in contact with the second semiconductor region. A gate electrode is provided on a surface of the gate insulating film on the opposite side to the surface in contact with the second semiconductor region.

[0023] Furthermore, in the superjunction semiconductor device of the present invention, in the above invention, the first semiconductor region includes a first region on the active region side and a second region separated from the first region.

[0024] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the first region and the second region of the first semiconductor region, the ratio of the width of the first region to the width of the second region is 3:7 to 5:5.

[0025] Furthermore, in the superjunction semiconductor device of the present invention, in the above invention, the first region and the second region of the first semiconductor region have a ring shape in plan view.

[0026] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the width of the first column of the first parallel pn structure of the active region is greater than the width of the third column of the second parallel pn structure of the terminal structure portion, and the width of the second column of the first parallel pn structure of the active region is greater than the width of the fourth column of the second parallel pn structure of the terminal structure portion.

[0027] Furthermore, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, a third semiconductor region of the first conductivity type is provided on a surface of the first semiconductor region on the opposite side to the semiconductor substrate.

[0028] In order to solve the above problems and achieve the purpose of the present invention, the manufacturing method of the superjunction semiconductor device of the present invention is a manufacturing method of a superjunction semiconductor device having a terminal structure part and an active area where current flows, wherein the terminal structure part is arranged outside the active area and forms a voltage-resistant structure surrounding the active area. First, a first process is performed: on the front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having an impurity concentration lower than the impurity concentration of the semiconductor substrate is formed. Next, a second process is performed: a first parallel pn structure is formed in the active area of ​​the first semiconductor layer, and a second parallel pn structure is formed in the terminal structure part of the first semiconductor layer. The first parallel pn structure is a structure in which a first column of a first conductivity type and a second column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, and the second parallel pn structure is a structure in which a third column of a first conductivity type and a fourth column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. Next, a third step is performed: in the active region, the first parallel pn structure is formed on the surface of the first parallel pn structure, and in the terminal structure portion, a first semiconductor region of the second conductivity type including a plurality of regions separated from each other is formed on the surface of the second parallel pn structure. Next, a fourth step is performed: a second semiconductor region of the second conductivity type is formed on the surface of the second column of the first parallel pn structure in the active region. Next, a fifth step is performed: a third semiconductor region of the first conductivity type is selectively formed in the surface layer of the second semiconductor region on the opposite side relative to the semiconductor substrate side. Next, a sixth step is performed: a gate insulating film is formed in contact with the second semiconductor region. Next, a seventh step is performed to form a gate electrode on the surface of the gate insulating film on the opposite side of the surface in contact with the second semiconductor region.

[0029] Furthermore, the method for manufacturing a superjunction semiconductor device of the present invention is characterized in that, in the above invention, in the third step, the first parallel pn structure and the first semiconductor region are simultaneously formed by epitaxial growth and ion implantation.

[0030] In addition, the manufacturing method of the superjunction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the opening width of the ion-implanted photoresist when forming the above-mentioned second parallel pn structure is larger than the opening width of the ion-implanted photoresist when forming the above-mentioned first semiconductor region.

[0031] In addition, the method for manufacturing a superjunction semiconductor device of the present invention is characterized in that, in the above invention, in the above third step, impurities are implanted into multiple locations by ion implantation, and the implanted impurities are thermally diffused, thereby forming the above first semiconductor region.

[0032] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the above-mentioned first semiconductor region has: a first region on the above-mentioned active region side, a second region separated from the above-mentioned first region, a third region separated from the above-mentioned second region, and a fourth region separated from the above-mentioned third region.

[0033] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the width w1 of the first region, the width w2 of the second region, the width w3 of the third region and the width w4 of the fourth region satisfy w1≤w2≤w3≤w4.

[0034] Furthermore, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the first region, the second region, the third region, and the fourth region are connected to an electrode provided in the terminal structure portion via the second semiconductor region.

[0035] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the above-mentioned second parallel pn structure has an inner structure on the side of the above-mentioned active region, and an outer structure farther away from the above-mentioned active region than the above-mentioned inner structure, and the length of the above-mentioned fourth column of the above-mentioned outer structure from the upper surface of the above-mentioned first semiconductor layer is less than the length of the above-mentioned fourth column of the above-mentioned inner structure from the upper surface of the above-mentioned first semiconductor layer.

[0036] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the impurity concentration of one of the first region, the second region, the third region and the fourth region is higher as it is closer to the active region.

[0037] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above-mentioned invention, one of the above-mentioned first region, the above-mentioned second region, the above-mentioned third region and the above-mentioned fourth region has: a first part close to the above-mentioned active region, a second part farther away from the above-mentioned active region than the above-mentioned first part, and a third part farther away from the above-mentioned active region than the above-mentioned second part, and the impurity concentration D1 of the above-mentioned first part, the impurity concentration D2 of the above-mentioned second part and the impurity concentration D3 of the above-mentioned third part satisfy D1:D2=1.5:1~1.2:1 and D2:D3=1:0.75~1:0.5.

[0038] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, taking the depth from the upper surface of the above-mentioned first semiconductor layer to the center of the above-mentioned first semiconductor region as the starting point, the distance d1 from the above-mentioned depth to the surface of the above-mentioned first part, the distance d2 from the above-mentioned depth to the surface of the above-mentioned second part, and the distance d3 from the above-mentioned depth to the surface of the above-mentioned third part satisfy d1>d2>d3.

[0039] According to the above invention, the surface electric field reduction region (the first semiconductor region of the second conductivity type) is divided into two or more. As a result, the surface electric field reduction region close to the cutoff electrode can be used as a buffer to alleviate the sharp drop in withstand voltage. Therefore, the reduction in withstand voltage caused by manufacturing deviation can be suppressed. In addition, in the case where charge accumulates on the protective film, the movement of the equipotential line stops at the position where the surface electric field reduction region is divided, so that the influence of the charge is localized. Therefore, the withstand voltage fluctuation in the case where charge accumulates on the protective film of the semiconductor device can be suppressed.

[0040] In addition, since the movement of the equipotential line stops at the position where the RESURF region is divided, by dividing the RESURF region into four, the influence of the charge can be more localized than by dividing the RESURF region into two, and the withstand voltage fluctuation when the charge is accumulated on the protective film of the semiconductor device can be further suppressed. In addition, by setting the RESURF region to a shape in which its width decreases toward the outside of the element and its impurity concentration decreases, the withstand voltage fluctuation when the charge is accumulated on the protective film of the semiconductor device can be further suppressed.

[0041] Technical Effects

[0042] According to the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention, it is possible to suppress a decrease in withstand voltage due to manufacturing variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a cross-sectional view showing the structure of the SJ-MOSFET according to the first embodiment.

[0044] Figure 2 FIG. 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1 Top view of the A-A' portion.

[0045] Figure 3 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1 Top view of the B-B' portion.

[0046] Figure 4 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1Another top view of the BB' portion.

[0047] Figure 5 This is a cross-sectional view showing the structure of the SJ-MOSFET according to the second embodiment.

[0048] Figure 6 : is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET of the comparative example.

[0049] Fig. 7A 1 is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET according to the first embodiment.

[0050] Figure 7B It is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET according to the second embodiment.

[0051] Figure 8 This is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the first and second embodiments (part 1).

[0052] Fig. 9 This is a cross-sectional view showing the state of the SJ-MOSFET of the first and second embodiments during the manufacturing process (part 2).

[0053] Fig.10 This is a cross-sectional view showing the state of the SJ-MOSFET of the first and second embodiments during the manufacturing process (part 3).

[0054] Fig.11 1 is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET of the first and second embodiments (the fourth one).

[0055] Fig.12 This is a cross-sectional view showing the state of the SJ-MOSFET of the first and second embodiments during the manufacturing process (Part 5).

[0056] Fig.13 1 is a cross-sectional view showing the state of the SJ-MOSFET of the first embodiment and the second embodiment during the manufacturing process (the sixth).

[0057] Fig.14 This is a cross-sectional view showing the structure of an SJ-MOSFET according to a third embodiment.

[0058] Fig.15 It is a cross-sectional view showing the structure of the SJ-MOSFET according to the fourth embodiment.

[0059] Fig.16 1 is a cross-sectional view showing a detailed structure of a resurf layer of the SJ-MOSFET according to the fourth embodiment.

[0060] Fig.17 Graphs showing the relationship between charge balance and breakdown voltage in the SJ-MOSFETs of the first, third, and fourth embodiments and the SJ-MOSFET of the comparative example.

[0061] Fig.18 Graphs showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs of the first embodiment, the third embodiment, and the fourth embodiment and the SJ-MOSFET of the comparative example.

[0062] Fig.19 is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

[0063] Explanation of symbols

[0064] 1.101n + Semiconductor Substrate

[0065] 2. 102 n-type drift layer

[0066] 2a~2f n-type layer

[0067] 3a, 3b, 103 n-type column area

[0068] 4a, 4b, 4c, 4d, 104 p-type column area

[0069] 5. 105 p-type base region

[0070] 6.106 n + Type source region

[0071] 7.107 Gate insulation film

[0072] 8.108 Gate electrode

[0073] 10, 110 source electrode

[0074] 13, 113 Insulation film

[0075] 14, 114 Drain electrode

[0076] 15 Field plate electrode

[0077] 15a Field plate electrode

[0078] 15b Field plate electrode

[0079] 15c Field plate electrode

[0080] 15d Field plate electrode

[0081] 16 Cut-off electrode

[0082] 17, 117 Reduced surface electric field area

[0083] 17a First RESURF region

[0084] 17b Second RESURF region

[0085] 17c Third RESURF region

[0086] 17d Fourth RESURF region

[0087] 18 n-type region

[0088] 19 p-type region

[0089] 20a, 20b Mask for ion implantation

[0090] 21 Ion implantation

[0091] 25 End of the first RESURF region

[0092] 30, 130 Active area

[0093] 40, 140 Edge terminal area

[0094] 50, 150 SJ-MOSFET

[0095] 60 Equipotential lines

[0096] 70 Surface protection film

[0097] w1 Width of the first RESURF region

[0098] w2 Width of the second RESURF region

[0099] w3 Width of the third RESURF region

[0100] w4 width of the fourth RESURF region

[0101] w11 opening width of active area

[0102] w12 Opening width of edge termination area

[0103] w13 Opening width of edge termination area

[0104] w14 Photoresist width in edge termination area

[0105] w15: width of the photoresist at the portion divided into the first RESURF region 17a and the second RESURF region 17b

[0106] P1 Pitch of opening (active area)

[0107] P2 Pitch of opening (edge ​​termination area)

[0108] P3 Pitch of opening (edge ​​termination area) DETAILED DESCRIPTION

[0109] Hereinafter, preferred embodiments of the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layers or regions prefixed with n or p, it is indicated that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n or p respectively indicate that the doping concentration is higher and lower than the doping concentration of the layers or regions not marked with + and -. When the marks of n or p containing + and - are the same, it means that the concentration is close, and is not limited to the same concentration. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations, and repeated descriptions are omitted.

[0110] (Implementation Method 1)

[0111] The superjunction semiconductor device of the present invention is described by taking SJ-MOSFET as an example. Figure 1 This is a cross-sectional view showing the structure of the SJ-MOSFET according to the first embodiment. Figure 2 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1 A top view of the A-A' portion. In addition, Figure 3 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1 A top view of the B-B' portion. In addition, Figure 4 1 is a diagram showing the structure of the SJ-MOSFET according to the first embodiment. Figure 1 Another top view of the BB' portion. Figure 1 yes Figure 2 to Figure 4 Cross-sectional view of the a-a' portion.

[0112] Figure 1 The SJ-MOSFET 50 shown is an SJ-MOSFET 50 having a MOS (Metal Oxide Semiconductor) gate on the front side (the side of the p-type base region 5 described later) of a semiconductor substrate (silicon substrate: semiconductor chip) including silicon (Si). The SJ-MOSFET 50 includes an active region 30 and an edge termination region 40 surrounding the active region 30. The active region 30 is a region where current flows when in the on state. The edge termination region 40 is a region that relaxes the electric field on the front side of the substrate of the drift region and maintains a withstand voltage. Figure 1 In the active region 30 of FIG. 1 , only one unit cell (functional unit of the element) is shown, and other unit cells adjacent thereto are omitted from the illustration. It should be noted that the boundary between the active region 30 and the edge termination region 40 is the end of the p-type base region 5 .

[0113] n + The n-type semiconductor substrate (first conductivity type semiconductor substrate) 1 is a silicon single crystal substrate doped with phosphorus (P), for example. The n-type drift layer (first conductivity type first semiconductor layer) 2 is a silicon single crystal substrate doped with phosphorus (P), for example. + The impurity concentration of the n-type semiconductor substrate is low, and the n-type drift layer is doped with a low concentration of impurities such as phosphorus. + The n-type semiconductor substrate 1 and the n-type drift layer 2 together serve as a semiconductor base. A MOS gate structure (element structure) is formed on the front side of the semiconductor base. In addition, a drain electrode 14 is provided on the back side of the semiconductor base.

[0114] A first parallel pn region is provided on the active region 30 side of the SJ-MOSFET 50. The first parallel pn region is formed by alternately and repeatedly configuring n-type column regions 3a and p-type column regions 4a. The p-type column regions 4a are arranged so as not to reach the n-type drift layer 2 from the surface. + The surface of the semiconductor substrate 1 is arranged in a manner as shown in FIG. Figure 2 to Figure 4 As shown, the planar shapes of the n-type column region 3 a and the p-type column region 4 a in the active region 30 are stripe shapes.

[0115] In addition, a p-type base region (second semiconductor region of the second conductivity type) 5 is selectively provided in the surface layer of the n-type drift layer 2 in contact with the p-type column region 4a. + The p-type source region (third semiconductor region of the first conductivity type) 6. The p-type base region 5 is sandwiched between the n + A gate electrode 8 is provided on the surface of a portion between the n-type source region 6 and the n-type column region 3a via a gate insulating film 7. The gate electrode 8 may be provided on the surface of the n-type column region 3a via a gate insulating film 7.

[0116] The insulating film 13 is provided on the front side of the semiconductor substrate so as to cover the gate electrode 8. The source electrode 10 is connected to the n electrode 8 via a contact hole opened in the interlayer insulating film (not shown). + The p-type source region 6 is in contact with the p-type base region 5 and is connected to the n-type + The p-type source region 6 and the p-type base region 5 are electrically connected.

[0117] The source electrode 10 is electrically insulated from the gate electrode 8 by the insulating film 13. On the source electrode 10, a protective film (not shown) such as a passivation film made of, for example, polyimide is selectively provided.

[0118] A field plate electrode 15 is disposed outside the source electrode 10 (on the edge termination region 40 side) and apart from the source electrode 10. The field plate electrode 15 is provided in a substantially annular shape along the boundary between the active region 30 and the edge termination region 40. The field plate electrode 15 may also function as a gate wiring electrically connected to the gate electrode 8.

[0119] A second parallel pn region is also provided on the edge termination region 40 side of the SJ-MOSFET 50. Figure 3 As shown, the planar shape of the n-type column region 3b and the p-type column region 4b in the edge termination region 40 may be a stripe shape, such as Figure 4 As shown, the planar shapes of the n-type column region 3 b and the p-type column region 4 b in the edge termination region 40 may also be rectangular shapes.

[0120] In addition, if Figure 1 to Figure 4 As shown, the width of the n-type column region 3a in the active region 30 is greater than the width of the n-type column region 3b in the edge termination region 40, and the width of the p-type column region 4a in the active region 30 is greater than the width of the p-type column region 4b in the edge termination region 40. Thus, the impurity concentration of the second parallel pn structure in the edge termination region 40 can be lower than the impurity concentration of the first parallel pn region in the active region 30. Therefore, the withstand voltage of the edge termination region 40 can be higher than the withstand voltage of the active region 30.

[0121] An n-type drift layer 2 may be provided outside the second parallel pn region so as to surround the second parallel pn region, and an n-type drift layer 2 may be provided on the surface of the n-type drift layer 2 to function as a channel stopper region. + A resurf region (second conductivity type first semiconductor region) 17 is provided on the surface of the second parallel pn region. An insulating film 13 is provided on the surface of the resurf region 17 and the n-type drift layer 2. + A cut-off electrode 16 is provided on the surface of the die area.

[0122] like Figure 1 and Figure 2 As shown, in Embodiment 1, the RESURF region 17 extends toward the blocking electrode 16 so as to overlap with the outer end of the field plate electrode 15 in a plan view and is divided into two or more parts. Figure 1 In the example of FIG. 1 , the resurf region 17 is divided into two resurf regions: a first resurf region 17 a close to the active region 30 and a second resurf region 17 b far from the active region 30 .

[0123] like Figure 2 As shown, the planar shapes of the first resurf region 17a and the second resurf region 17b are set to be ring-shaped. In addition, the first resurf region 17a and the second resurf region 17b are electrically connected to the p-type column region 4b of the second parallel pn region. Further, as Figure 1 As shown, a p-type column region 4b which is not connected to the first and second resurf regions 17a and 17b may be disposed between the first resurf region 17a and the second resurf region 17b.

[0124] In addition, an n-type region 18 is provided between the first resurf region 17a and the second resurf region 17b and the insulating film 13 thereon. It should be noted that an end portion 25 of the first resurf region 17a on the active region 30 side may be in contact with the insulating film 13. In addition, the end portion 25 of the first resurf region 17a may be electrically connected to the field plate electrode 15. The end portion 25 of the first resurf region 17a may be provided in a ring shape.

[0125] As described above, while maintaining the withstand voltage, the electric field concentration in the edge termination region 40 can be alleviated by partially or completely depleting the resurf region 17. By dividing the resurf region 17, the potential in the resurf region 17 can be shared with each other, and the electric field strength can be partially increased. Therefore, in the case where the charge balance of the second parallel pn region with more p-type impurities is caused due to manufacturing deviation, or in the case where the p-type impurity concentration of the resurf region 17 increases, the resurf region 17b on the side close to the blocking electrode 16 can also serve as a buffer to alleviate the rapid decrease in the withstand voltage. Therefore, the decrease in the withstand voltage caused by the manufacturing deviation can be suppressed.

[0126] (Implementation Method 2)

[0127] Figure 5 This is a cross-sectional view showing the structure of the SJ-MOSFET according to the second embodiment. Figure 5 The A-A' portion of FIG. 1 is the same as that of FIG. 1 which shows the structure of the SJ-MOSFET of the first embodiment. Figure 2 The same part as the top view of the embodiment 2. Figure 5 The BB' portion of FIG. 1 is the same as that of FIG. 1 which shows the structure of the SJ-MOSFET of the first embodiment. Figure 3 The same part as the top view of the embodiment 2. Figure 5 Other top views of the B-B' section and Figure 4 The top view is the same.

[0128] The difference of the second embodiment is that the p-type column region 4 b which is not connected to the first and second resurf regions 17 a and 17 b is not arranged between the first and second resurf regions 17 a and 17 b .

[0129] In Embodiment 2, the same effects as those of Embodiment 1 can be obtained even if the p-type column region 4 b which is not connected to the first and second resurf regions 17 a and 17 b is not disposed between the first and second resurf regions 17 a and 17 b .

[0130] In addition, in one SJ-MOSFET 50, a mixture of Figure 1 The portion of the p-type column region 4b which is not connected to the first and second resurf regions 17a and 17b is arranged between the first and second resurf regions 17a and 17b, and Figure 5 As shown, a portion of the p-type column region 4 b which is not connected to the first and second resurf regions 17 a and 17 b is not arranged between the first and second resurf regions 17 a and 17 b .

[0131] However, in the case of mixed existence, the first resurf region 17a and the second resurf region 17b are separated from each other. In addition, the width w1 of the first resurf region 17a and the width w2 of the second resurf region 17b away from the active region 30 satisfy the relationship described below.

[0132] in addition, Figure 1 The SJ-MOSFET 50 shown is used in a state sealed by a sealing resin such as a mold resin. If the sealing resin and the SJ-MOSFET 50 are not in close contact, ionic substances such as moisture may enter between the sealing resin and the SJ-MOSFET 50. In this case, electric charges may accumulate on the protective film of the SJ-MOSFET 50.

[0133] Figure 6 1 is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example is different from the SJ-MOSFET of Embodiment 1 in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b. Figure 6 As shown, if the surface electric field reduction region 117 is not divided, the equipotential lines 60 are arranged roughly uniformly on the surface electric field reduction region 117. In such a state, if charges are accumulated on the surface protection film 70, the equipotential lines 60 move inward (active region 30 side) or outward (cutoff electrode 16 side). For example, if positive charges are accumulated, they move inward, and if negative charges are accumulated, they move outward. In this case, a dense portion of the equipotential lines 60 is generated at the end of the surface electric field reduction region 117, causing the withstand voltage to change.

[0134] Fig. 7A 1 is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET of Embodiment 1. Fig. 7AAs shown, if the surface electric field reduction region 17 is divided, the interval between the equipotential lines 60 becomes wider at the divided position. If charge is accumulated on the surface protective film 70 in such a state, even if the equipotential lines 60 move inward or outward, the movement of the equipotential lines 60 stops at the divided position. Thus, the influence caused by the charge can be localized. Therefore, the withstand voltage fluctuation when the charge is accumulated on the protective film of the semiconductor device can be suppressed. In addition, since the movement of the equipotential lines 60 stops at the divided position, the more the surface electric field reduction region 17 is divided, the more the withstand voltage fluctuation when the charge is accumulated can be suppressed.

[0135] Figure 7B 1 is a diagram showing the internal state of the potential distribution of the SJ-MOSFET according to the second embodiment. Figure 7B Able to obtain Fig. 7A Same effect.

[0136] In addition, in Figure 1 and Figure 5 In the case where the resurf region 17 is divided into two as shown, the ratio of the width w1 of the first resurf region 17a close to the active region 30 to the width w2 of the second resurf region 17b far from the active region 30 is preferably in the range of 3:7 to 5:5. Here, the width w1 of the first resurf region 17a refers to the length from the inside to the outside of the first resurf region 17a. The same is true for the width w2 of the second resurf region 17b. That is, it is preferably in the range from the case where the width w1 of the first resurf region 17a is 3 and the width w2 of the second resurf region 17b is 7 to the case where the width w1 of the first resurf region 17a is 5 and the width w2 of the second resurf region 17b is 5.

[0137] In order to maintain the withstand voltage, it is preferred that the RESURF region be completely depleted, but the withstand voltage can also be maintained by partially depleting the RESURF region. Figure 6 Compared with the case where the surface electric field reduction region 117 is completely depleted, Fig. 7A and Figure 7B In the case where the first surface electric field reduction region 17a on the side of the active region 30 is partially depleted, there is a tendency that the intervals between the equipotential lines 60 become wider as a whole. In addition, in the region sandwiched between the first surface electric field reduction region 17a and the second surface electric field reduction region 17b, the intervals between the equipotential lines 60 become narrower (become denser). As a result, the intervals between the equipotential lines 60 of the second surface electric field reduction region 17b become wider, so that the electric field is relaxed. By relaxing the electric field on the side close to the cutoff electrode 16, the reduction in withstand voltage caused by surface charge can be suppressed.

[0138] Furthermore, when the resurf region 17 is divided into two, in order to reduce the reduction in withstand voltage due to surface charges, the width w1 of the first resurf region 17a close to the active region 30 is preferably shorter than the width w2 of the second resurf region 17b far from the active region 30. In addition, when the resurf region 17 is divided into three or more, in order to reduce the reduction in withstand voltage due to surface charges, the width of the resurf region close to the cutoff electrode 16 is preferably the longest.

[0139] Furthermore, by providing the n-type region 18 between the RESURF region 17 and the insulating film 13 , the fluctuation of the withstand voltage of the edge termination region 40 due to surface charges can be further stabilized. In addition, the n-type region 18 can reduce the penetration of holes into the insulating film 13 .

[0140] (Method for Manufacturing Superjunction Semiconductor Device According to Embodiment 1 and Embodiment 2)

[0141] Next, a method for manufacturing the superjunction semiconductor device according to Embodiment 1 and Embodiment 2 will be described. Figure 8 to Figure 13 The SJ-MOSFET 50 of the first embodiment and the second embodiment is a cross-sectional view showing a state during the manufacturing process. First, a silicon-containing n-type semiconductor device is prepared. + n-type drain layer + Next, on n + On the front surface of the semiconductor substrate 1, the impurity concentration is made higher than n + The n-type layer 2a with low impurity concentration is epitaxially grown on the semiconductor substrate 1. The state up to this point is described in Figure 8 .

[0142] The impurity concentration of the n-type layer 2a can be set to, for example, 1.0×10 14 / cm 3 Above and 1.0×10 17 / cm 3 The epitaxial growth is performed by doping with n-type impurities in the following manner.

[0143] Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2a by photolithography technology using, for example, a photoresist. At this time, the opening width w11 of the active region is set to be larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening portion of the active region is set to be larger than the pitch P2 of the opening portion of the edge termination region. Using the ion implantation mask 20a as a mask, ion implantation 21 of a p-type impurity such as boron (B) is performed to form a p-type region 19 in the surface layer of the n-type layer 2a. The state so far is recorded in Fig. 9 Next, the ion implantation mask 20a is removed.

[0144] Next, on the front side of the n-type layer 2a, an n-type layer 2b having the same impurity concentration as that of the n-type layer 2a is epitaxially grown. Next, on the surface of the n-type layer 2b, an ion implantation mask 20a having a predetermined opening width is formed by photolithography technology using, for example, a photoresist. At this time, the opening width w11 of the active region is set to be larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening portion of the active region is set to be larger than the pitch P2 of the opening portion of the edge termination region. Using the ion implantation mask 20a as a mask, ion implantation 21 of a p-type impurity, such as boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2b. Next, the ion implantation mask 20a is removed.

[0145] Next, on the front side of the n-type layer 2b, an n-type layer 2c having the same impurity concentration as that of the n-type layer 2b is epitaxially grown. Next, on the surface of the n-type layer 2c, an ion implantation mask 20a having a predetermined opening width is formed by photolithography technology using, for example, a photoresist. At this time, the opening width w11 of the active region is set to be larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening portion of the active region is set to be larger than the pitch P2 of the opening portion of the edge termination region. Using the ion implantation mask 20a as a mask, ion implantation 21 of a p-type impurity, such as boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2c. Next, the ion implantation mask 20a is removed.

[0146] Next, on the front side of the n-type layer 2c, an n-type layer 2d having the same impurity concentration as that of the n-type layer 2c is epitaxially grown. Next, on the surface of the n-type layer 2d, an ion implantation mask 20a having a predetermined opening width is formed by photolithography technology using, for example, a photoresist. At this time, the opening width w11 of the active region is set to be larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening portion of the active region is set to be larger than the pitch P2 of the opening portion of the edge termination region. Using the ion implantation mask 20a as a mask, ion implantation 21 of a p-type impurity, such as boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2d. Thus, a first parallel pn region and a second parallel pn region including the n-type layer 2a to the n-type layer 2d and the lower portion of the p-type region 19 are formed. The state so far is recorded in Fig.10 .

[0147] exist Fig.10 In the example of , an example of repeating ion implantation and epitaxial growth four times is shown, but the present invention is not limited to this, and the number of ion implantation and epitaxial growth can be appropriately changed according to target characteristics such as withstand voltage.

[0148] Next, the ion implantation mask 20a is removed. Next, on the front side of the n-type layer 2d, an n-type layer 2e having an impurity concentration equal to that of the n-type layer 2d is epitaxially grown. Next, on the surface of the n-type layer 2e, an ion implantation mask 20b having a predetermined opening width is formed by photolithography using, for example, a photoresist. At this time, the opening width w13 of the edge termination region is set smaller than the opening width w12 of the edge termination region of the mask formed on the n-type layer 2a to the n-type layer 2d, and the pitch P3 of the openings of the edge termination region is set smaller than the pitch P2 of the openings of the edge termination region of the mask formed on the n-type layer 2a to the n-type layer 2d. In addition, the photoresist width w15 of the portion where the resurf region 17 is divided into the first resurf region 17a and the second resurf region 17b is larger than the photoresist width w14 (= P3-w13) of the edge termination region. Using the ion implantation mask 20b as a mask, ion implantation 21 of p-type impurities such as boron (B) is performed to form a p-type region 19 in the surface layer of the n-type layer 2e. Thus, a first parallel pn region including the n-type layer 2e and the upper part of the p-type region 19 is formed in the active region 30, and a resurf region 17 is formed in the edge termination region 40. The state so far is described in Fig.11 Next, the ion implantation mask 20b is removed.

[0149] Next, on the front side of the n-type layer 2e, an n-type layer 2f having an impurity concentration substantially equal to that of the n-type layer 2e is epitaxially grown. The state thus far is described in Fig.12 .

[0150] Next, a heat treatment (annealing) is performed to activate the p-type region 19. The injected impurities are diffused by the heat treatment, and the diffused impurities are connected in the vertical direction, thereby forming the p-type column regions 4a and 4b. In addition, since the intervals between the p-type regions 19 formed in the n-type layer 2e are narrow, the diffused impurities are connected in the horizontal direction, forming the resurf region 17.

[0151] Here, in the edge termination region 40, the opening width of the mask is smaller than the opening width of the mask of the active region 30, so the amount of impurities injected into one part is small and the diffusion amount is small. Therefore, the impurities do not reach the surface of the n-type region 2f during heat treatment. Therefore, the n-type region 18 is formed on the upper part of the reduced surface electric field region 17. On the other hand, in the active region 30, the amount of impurities is large and the diffusion amount is large, so the impurities reach the surface of the n-type region 2f, and the p-type column region 4a is exposed on the surface. Although sometimes the impurities do not reach the surface of the n-type region 2f in the active region 30 due to the amount of impurities, since ion implantation is performed when the p-type base region 5 is formed, in the active region 30, the p-type column region 4a is connected to the p-type base region 5, and the p-type region is exposed on the surface. The state up to this point is recorded in Fig.13 .

[0152] Next, a mask having a desired opening is formed on the surface of the n-type column region 3a and the p-type column region 4a on the active region 30 side by photolithography technology using, for example, a resist. Then, the p-type impurity is ion-implanted by ion implantation using the resist mask as a mask. Thus, the p-type base region 5 is formed on the entire surface region of the p-type column region 4a and a portion of the surface region of the n-type column region 3a. Next, the mask used for ion implantation to form the p-type base region 5 is removed.

[0153] Next, a mask having a desired opening is formed on the surface of the p-type base region 5 by photolithography using, for example, a resist. Then, the n-type impurity is ion-implanted by ion implantation using the resist mask as a mask. Thus, an n-type impurity is formed on a portion of the surface of the p-type base region 5. + Next, the n type source region 6 is removed. + A mask used when ion implantation of type source region 6 occurs.

[0154] Next, the p-type base region 5 and the n-type base region 5 are connected. + In addition, a p-type base region 5 and an n-type source region 6 are formed. + The order of the type source regions 6 can be changed in various ways.

[0155] Next, the front side of the semiconductor substrate is thermally oxidized to form a gate insulating film 7. Next, a polysilicon layer doped with, for example, phosphorus is formed on the gate insulating film 7 as a gate electrode 8. Next, the polysilicon layer is patterned and selectively removed, leaving the polysilicon layer on the p-type base region 5 sandwiched between the n-type base region 5. + At this time, the polysilicon layer may be left on the n-type column region 3a.

[0156] Next, a film of, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as an insulating film 13 so as to cover the gate electrode 8. Next, the insulating film 13 and the gate insulating film 7 are patterned and selectively removed. For example, by removing the n + The insulating film 13 and the gate insulating film 7 on the type source region 6 form a contact hole so that the n + The source region 6 is exposed. Next, in order to planarize the interlayer insulating film 9, a heat treatment (reflow) is performed.

[0157] Next, the source electrode 10, the field plate electrode 15, and the cutoff electrode 16 are formed by sputtering, and the source electrode 10, the field plate electrode 15, and the cutoff electrode 16 are patterned by photolithography and etching. At this time, the source electrode 10 is buried in the contact hole, so that n +The source region 6 is electrically connected to the source electrode 10. It should be noted that a tungsten plug or the like may be buried in the contact hole via a barrier metal.

[0158] Then, in n + A nickel film is formed on the surface of the semiconductor substrate 1 (the back side of the semiconductor substrate) as a drain electrode 14. Then, a heat treatment is performed to form an n + The ohmic junction between the semiconductor substrate 1 and the drain electrode 14 is completed. Figure 1 The SJ-MOSFET 50 is shown.

[0159] As described above, according to Embodiment 1 and Embodiment 2, the surface electric field reduction region is divided into two or more. As a result, the surface electric field reduction region close to the cutoff electrode can be used as a buffer to alleviate the sharp drop in withstand voltage. Therefore, the reduction in withstand voltage caused by manufacturing deviation can be suppressed. In addition, when charges are accumulated on the protective film, the movement of the equipotential line stops at the position where the surface electric field reduction region is divided, so that the influence of the charge is localized. Therefore, the withstand voltage variation when charges are accumulated on the protective film of the semiconductor device can be suppressed.

[0160] (Implementation method 3)

[0161] Fig.14 1 is a cross-sectional view showing the structure of an SJ-MOSFET according to Embodiment 3. Embodiment 3 is different from Embodiments 1 and 2 in that the resurf region 17 is divided into four parts: a first resurf region 17a, a second resurf region 17b, a third resurf region 17c, and a fourth resurf region 17d.

[0162] In Embodiment 3, the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d preferably have a relationship of w1≤w2≤w3≤w4. Fig.14 In the embodiment, the end portion 25 of the first resurf region 17a is a part of the p-type base region 5, and the first resurf region 17a can be connected to the field plate electrode 15a via the p-type base region 5. Similarly, the second resurf region 17b, the third resurf region 17c, and the fourth resurf region 17d can also be connected to the field plate electrode 15b, the field plate electrode 15c, and the field plate electrode 15d, respectively, via the p-type base region 5.

[0163] The field plate electrode 15a can also play the role of a gate electrode electrically connected to the gate electrode 8. However, if the field plate electrodes 15b, 15c, and 15d are electrically connected to the gate electrode 8, they will be at the same potential as the gate electrode 8 and will not be able to maintain a withstand voltage. Therefore, the field plate electrodes 15b, 15c, and 15d are not electrically connected to the gate electrode 8.

[0164] The p-type column regions 4c and 4d arranged at both ends of the third resurf region 17c may or may not be in contact with the third resurf region 17c.

[0165] As described above, in Embodiment 3, the surface electric field reduction region is divided into four. Thus, as in Embodiments 1 and 2, the rapid decrease in withstand voltage can be alleviated, and the decrease in withstand voltage caused by manufacturing deviation can be suppressed. Furthermore, since the movement of the equipotential line stops at the position where the surface electric field reduction region is divided, Embodiment 3 can further localize the influence of the charge compared to Embodiments 1 and 2 in which the surface electric field reduction region is divided into two. Therefore, compared to Embodiments 1 and 2, Embodiment 3 can further suppress the withstand voltage variation when the charge is accumulated on the protective film of the semiconductor device.

[0166] (Implementation 4)

[0167] Fig.15 1 is a cross-sectional view showing the structure of the SJ-MOSFET of Embodiment 4. The impurity concentration of the fourth resurf region 17d and the length of the outer p-type column region 4b of Embodiment 4 are different from those of Embodiment 3. As in Embodiment 3, in Embodiment 4, it is also preferred that the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d have a relationship of w1≤w2≤w3≤w4.

[0168] like Fig.15 In the fourth embodiment, the second parallel pn structure in the edge termination region 40 is composed of an inner structure S1 on the inner side of the element (on the active region 30 side) and an outer structure S2 on the outer side of the element (on the cutoff electrode 16 side) farther from the active region 30 than the inner structure S1. The length t2 of the p-type column region 4b of the outer structure S2 from the surface of the n-type drift layer may be shorter than the length t1 of the p-type column region 4b of the inner structure S1 from the surface of the n-type drift layer, or may be the same length (the length t2 may be less than the length t1 (t2≤t1)). It should be noted that the p-type column region 4c and the p-type column region 4d arranged at both ends of the third resurf region 17c may be in contact with the third resurf region 17c or may not be in contact with it.

[0169] Fig.16 1 is a cross-sectional view showing a detailed structure of a resurf layer of the SJ-MOSFET according to the fourth embodiment. Fig.16 FIG. 1 is an enlarged view of the fourth resurf region 17d. Fig.16 As shown, the width of the fourth resurf region 17d becomes narrower as it goes outward from the element. In addition, the impurity concentration of the fourth resurf region 17d becomes lower as it goes outward from the element. The fourth resurf region 17d has a first portion 17d1 on the inner side of the element (the side close to the active region 30), a second portion 17d2 farther from the active region 30 than the first portion 17d1, and a third portion 17d3 on the outer side of the element farther from the active region 30 than the second portion 17d2. The (diffusion) distance from the center depth t3 of the resurf region to the surface of the first portion 17d1 is set to d1 and its impurity concentration is set to D1, the (diffusion) distance from the center depth t3 of the resurf region to the surface of the second portion 17d2 is set to d2 and its impurity concentration is set to D2, and the (diffusion) distance from the center depth t3 of the resurf region to the surface of the third portion 17d3 is set to d3 and its impurity concentration is set to D3. In this case, preferably, d1>d2>d3, D1:D2=1.5:1 to 1.2:1, D2:D3=1:0.75 to 1:0.5.

[0170] In embodiment 4, only the fourth resurf region 17d is configured such that its width becomes narrower and its impurity concentration becomes lower toward the outside of the element, but the inner first resurf region 17a, second resurf region 17b, and third resurf region 17c may also be configured to have the same shape.

[0171] As described above, in Embodiment 4, the fourth resurf region is configured to have a shape in which its width becomes narrower and its impurity concentration becomes lower as it moves toward the outside of the element. Thus, Embodiment 4 can further suppress the variation in withstand voltage when charges are accumulated on the protective film of the semiconductor device compared to Embodiments 1 to 3.

[0172] Fig.17 : is a graph showing the relationship between charge balance and withstand voltage in the SJ-MOSFET of the first embodiment, the third embodiment, the fourth embodiment and the SJ-MOSFET of the comparative example. Figure 6 As shown, the SJ-MOSFET of the comparative example is different from the SJ-MOSFET of the first embodiment in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b. Fig.17In the figure, the vertical axis represents the withstand voltage of the SJ-MOSFET, and the unit is V. The horizontal axis represents the charge balance, and the charge balance of "1" indicates a state in which the impurity amount of the n-type column regions 3a and 3b is approximately equal to the impurity amount of the p-type column regions 4a and 4b in the first parallel pn region and the second parallel pn region, and the side closer to the origin ((n-rich) side) than the charge balance of "1" indicates a state in which the n-type impurity amount is greater, and the side farther from the origin ((p-rich) side) than the charge balance of "1" indicates a state in which the p-type impurity amount is greater.

[0173] like Fig.17 As shown, when the charge balance is "1", the withstand voltage of the SJ-MOSFET of Embodiment 1, Embodiment 3, and Embodiment 4 is equal to the withstand voltage of the SJ-MOSFET of the comparative example. In addition, even in the state where the charge balance is biased to one side (the state where the amount of impurities of either n-type or p-type is greater), the decrease in the withstand voltage of the SJ-MOSFET of Embodiment 1, Embodiment 3, and Embodiment 4 is less than the decrease in the withstand voltage of the SJ-MOSFET of the comparative example. In addition, in the state where the charge balance is biased to one side, the decrease in the withstand voltage of the SJ-MOSFET of Embodiment 3 and Embodiment 4 is less than the decrease in the withstand voltage of the SJ-MOSFET of Embodiment 1.

[0174] It should be noted that the same effect can be obtained in the SJ-MOSFET of the second embodiment. Figure 1 The cross-sectional shape shown and the embodiment 2 Figure 5 The same effect can be achieved by using the cross-sectional shape shown.

[0175] Fig.18 Graph showing the relationship between the surface charge and the withstand voltage in the SJ-MOSFETs of Embodiment 1, Embodiment 3, and Embodiment 4 and the SJ-MOSFET of the comparative example. Fig.18 In the figure, the vertical axis represents the withstand voltage of the SJ-MOSFET in V. The horizontal axis represents the surface charge. On the horizontal axis, the position 0 represents the state where the surface charge is zero, the side closer to the origin than the position 0 (the negative (-) side) represents the state where the negative charge is greater, and the side farther from the origin than the position 0 (the positive (+) side) represents the state where the positive charge is greater. In addition, Fig.18 The relationship between the surface charge and the withstand voltage when the charge balance is "1" is shown. The surface charge is accumulated in the surface protection film (for example, Figure 6 , Fig. 7A and Figure 7B The charge of the surface protection film 70 shown).

[0176] like Fig.18As shown in the figure, in the state where the surface charge is zero, the withstand voltage of the SJ-MOSFETs of Embodiments 1, 3, and 4 is equal to that of the SJ-MOSFET of the comparative example. Even in the state where the negative charge is greater, the withstand voltage of the SJ-MOSFET of Embodiment 1 is equal to that of the SJ-MOSFET of the comparative example. On the other hand, in the state where the positive charge is greater, the decrease in the withstand voltage of the SJ-MOSFET of Embodiment 1 is less than that of the SJ-MOSFET of the comparative example.

[0177] The SJ-MOSFETs of Embodiments 3 and 4 have a smaller decrease in breakdown voltage than the SJ-MOSFET of the comparative example in both the state where the negative charge is greater and the state where the positive charge is greater. In addition, the SJ-MOSFET of Embodiment 3 has the smallest decrease in breakdown voltage in the state where the positive charge is greater. The SJ-MOSFET of Embodiment 4 has the smallest decrease in breakdown voltage in the state where the negative charge is greater.

[0178] It should be noted that the same effect can be obtained in the SJ-MOSFET of the second embodiment. Figure 1 The cross-sectional shape shown and the embodiment 2 Figure 5 The same effect can be achieved by using the cross-sectional shape shown.

[0179] In the above, in the present invention, the case where a MOS gate structure is formed on the first main surface of a silicon substrate is used as an example for explanation, but it is not limited to this, and various changes can be made to the type of semiconductor (such as silicon carbide (SiC)), the surface orientation of the main surface of the substrate, etc. In addition, in the present invention, the first conductivity type is set to n-type and the second conductivity type is set to p-type in each embodiment, but the present invention also holds true when the first conductivity type is set to p-type and the second conductivity type is set to n-type.

[0180] Industrial Applicability

[0181] As described above, the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention are useful for high withstand voltage semiconductor devices used in power conversion devices, power supply devices of various industrial equipment, and the like.

Claims

1. A superjunction semiconductor device, characterized in that: The superjunction semiconductor device has a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region, and comprises: a semiconductor substrate of a first conductivity type; A first semiconductor layer of a first conductivity type, which is disposed on the front surface of the semiconductor substrate and has an impurity concentration lower than that of the semiconductor substrate; A first parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has first columns of the first conductivity type and second columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the active region; A second parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has third columns of the first conductivity type and fourth columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the terminal structure portion; A first semiconductor region of a second conductivity type, which is disposed on a surface of the second parallel pn structure of the terminal structure portion and includes a plurality of regions separated from each other; A second semiconductor region of a second conductivity type is disposed on a surface of a second column of the second conductivity type of the first parallel pn structure of the active region; A third semiconductor region of the first conductivity type, which is selectively provided in a surface layer of the second semiconductor region on the side opposite to the semiconductor substrate side; a gate insulating film in contact with the second semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region; as well as an insulating film provided on surfaces of the first semiconductor region and the first semiconductor layer, A fourth semiconductor region of the first conductivity type is provided between the first semiconductor region and the insulating film.

2. The superjunction semiconductor device according to claim 1, characterized in that: The first semiconductor region has a first region on the active region side and a second region separated from the first region.

3. The superjunction semiconductor device according to claim 2, characterized in that: In the first region and the second region of the first semiconductor region, a ratio of a width of the first region to a width of the second region is 3:7 to 5:

5.

4. The superjunction semiconductor device according to claim 2, characterized in that: The first region and the second region of the first semiconductor region have a ring shape in plan view.

5. A superjunction semiconductor device, characterized in that: The superjunction semiconductor device has a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region, and comprises: a semiconductor substrate of a first conductivity type; A first semiconductor layer of a first conductivity type, which is disposed on the front surface of the semiconductor substrate and has an impurity concentration lower than that of the semiconductor substrate; A first parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has first columns of the first conductivity type and second columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the active region; A second parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has third columns of the first conductivity type and fourth columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the terminal structure portion; A first semiconductor region of a second conductivity type, which is disposed on a surface of the second parallel pn structure of the terminal structure portion and includes a plurality of regions separated from each other; A second semiconductor region of a second conductivity type is disposed on a surface of a second column of the second conductivity type of the first parallel pn structure of the active region; A third semiconductor region of the first conductivity type, which is selectively provided in a surface layer of the second semiconductor region on the side opposite to the semiconductor substrate side; a gate insulating film in contact with the second semiconductor region; and a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region, The first semiconductor region includes a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region. The width w1 of the first region, the width w2 of the second region, the width w3 of the third region, and the width w4 of the fourth region satisfy w1≤w2≤w3≤w4.

6. The superjunction semiconductor device according to claim 5, characterized in that: The second parallel pn structure has an inner structure on the active region side and an outer structure farther from the active region than the inner structure. A length of the fourth pillar of the outer structure from the upper surface of the first semiconductor layer is less than or equal to a length of the fourth pillar of the inner structure from the upper surface of the first semiconductor layer.

7. A superjunction semiconductor device, characterized in that: The superjunction semiconductor device has a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region, and comprises: a semiconductor substrate of a first conductivity type; A first semiconductor layer of a first conductivity type, which is disposed on the front surface of the semiconductor substrate and has an impurity concentration lower than that of the semiconductor substrate; A first parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has first pillars of the first conductivity type and second pillars of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the active region; A second parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has third columns of the first conductivity type and fourth columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the terminal structure portion; A first semiconductor region of a second conductivity type, which is disposed on a surface of the second parallel pn structure of the terminal structure portion and includes a plurality of regions separated from each other; A second semiconductor region of a second conductivity type is disposed on a surface of a second column of the second conductivity type of the first parallel pn structure of the active region; A third semiconductor region of the first conductivity type, which is selectively provided in a surface layer of the second semiconductor region on the side opposite to the semiconductor substrate side; a gate insulating film in contact with the second semiconductor region; and a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region, The first semiconductor region includes a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region. The closer one of the first region, the second region, the third region, and the fourth region is to the active region, the higher the impurity concentration thereof.

8. A superjunction semiconductor device, characterized in that: The superjunction semiconductor device has a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region, and comprises: a semiconductor substrate of a first conductivity type; A first semiconductor layer of a first conductivity type, which is disposed on the front surface of the semiconductor substrate and has an impurity concentration lower than that of the semiconductor substrate; A first parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has first columns of the first conductivity type and second columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the active region; A second parallel pn structure, which is disposed on the upper surface of the first semiconductor layer and has third columns of the first conductivity type and fourth columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface, and is disposed in the terminal structure portion; A first semiconductor region of a second conductivity type, which is disposed on a surface of the second parallel pn structure of the terminal structure portion and includes a plurality of regions separated from each other; A second semiconductor region of a second conductivity type is disposed on a surface of a second column of the second conductivity type of the first parallel pn structure of the active region; A third semiconductor region of the first conductivity type, which is selectively provided in a surface layer of the second semiconductor region on the side opposite to the semiconductor substrate side; a gate insulating film in contact with the second semiconductor region; and a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region, The first semiconductor region includes a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region. One of the first region, the second region, the third region, and the fourth region has a first portion close to the active region, a second portion farther from the active region than the first portion, and a third portion farther from the active region than the second portion, The impurity concentration D1 of the first portion, the impurity concentration D2 of the second portion, and the impurity concentration D3 of the third portion satisfy D1:D2=1.5:1-1.2:1 and D2:D3=1:0.75-1:0.

5.

9. The superjunction semiconductor device according to claim 8, characterized in that: Taking the depth from the upper surface of the first semiconductor layer to the center of the first semiconductor region as the starting point, the distance d1 from the depth to the surface of the first part, the distance d2 from the depth to the surface of the second part, and the distance d3 from the depth to the surface of the third part satisfy d1>d2>d3.

10. The superjunction semiconductor device according to any one of claims 5 to 9, characterized in that: The first region and the second region of the first semiconductor region have a ring shape in plan view.

11. The superjunction semiconductor device according to any one of claims 1 to 9, characterized in that: The width of the first column of the first parallel pn structure in the active area is greater than the width of the third column of the second parallel pn structure in the terminal structure part, and the width of the second column of the first parallel pn structure in the active area is greater than the width of the fourth column of the second parallel pn structure in the terminal structure part.

12. The superjunction semiconductor device according to claim 10, characterized in that: The width of the first column of the first parallel pn structure in the active area is greater than the width of the third column of the second parallel pn structure in the terminal structure part, and the width of the second column of the first parallel pn structure in the active area is greater than the width of the fourth column of the second parallel pn structure in the terminal structure part.

13. The superjunction semiconductor device according to any one of claims 5, 7 and 8, characterized in that: The first region, the second region, the third region, and the fourth region are connected to an electrode provided in the terminal structure portion via the second semiconductor region.

14. A method for manufacturing a superjunction semiconductor device, characterized in that: The method for manufacturing a superjunction semiconductor device according to any one of claims 1 to 13, wherein the superjunction semiconductor device has a terminal structure and an active region for current flow, wherein the terminal structure is arranged outside the active region and forms a voltage-resistant structure surrounding the active region. The manufacturing method of the superjunction semiconductor device comprises: In a first step, a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on a front surface of a semiconductor substrate of a first conductivity type; In a second step, a first parallel pn structure is formed in the active region of the first semiconductor layer, and a second parallel pn structure is formed in the terminal structure portion of the first semiconductor layer, wherein the first parallel pn structure is a structure in which first pillars of a first conductivity type and second pillars of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, and the second parallel pn structure is a structure in which third pillars of a first conductivity type and fourth pillars of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface; In a third step, in the active region, the first parallel pn structure is formed on the surface of the first parallel pn structure, and in the terminal structure portion, a first semiconductor region of the second conductivity type including a plurality of regions separated from each other is formed on the surface of the second parallel pn structure; The fourth step is to form a second semiconductor region of a second conductivity type on the surface of the second pillar of the first parallel pn structure in the active region; A fifth step of selectively forming a third semiconductor region of the first conductivity type in a surface layer of the second semiconductor region on the side opposite to the semiconductor substrate side; A sixth step is to form a gate insulating film in contact with the second semiconductor region; and In the seventh step, a gate electrode is formed on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region.

15. The method for manufacturing a superjunction semiconductor device according to claim 14, characterized in that: In the third process, the first parallel pn structure and the first semiconductor region are formed simultaneously by epitaxial growth and ion implantation.

16. The method for manufacturing a superjunction semiconductor device according to claim 15, characterized in that: The opening width of the ion-implanted photoresist when forming the second parallel pn structure is greater than the opening width of the ion-implanted photoresist when forming the first semiconductor region.

17. The method for manufacturing a superjunction semiconductor device according to claim 15 or 16, characterized in that: In the third step, impurities are implanted into a plurality of locations by ion implantation, and the implanted impurities are thermally diffused, thereby forming the first semiconductor region.

Images