Reverse blocking power semiconductor device and method for processing reverse blocking power semiconductor device

Abstract

A reverse blocking power semiconductor device and a method for processing a reverse blocking power semiconductor device. A reverse blocking power semiconductor device (1) comprises: a first load terminal structure (11) and a second load terminal structure (12); a semiconductor body (10) configured to conduct a load current between the first load terminal structure (11) and the second load terminal structure (12); a plurality of control units (14) electrically connected to the first load terminal structure (11) and comprising: a forward blocking junction (103) configured to block a forward voltage between the first load terminal structure (11) and the second load terminal structure (12) in a forward blocking state of the reverse blocking power semiconductor device (1); and a control electrode (150) separated from the forward blocking junction (103) by means of a control electrode insulating layer (151) and configured to switch the reverse blocking power semiconductor device (1) between a forward blocking state and a forward conducting state.

Description

Technical Field

[0001] The present description relates to embodiments of reverse blocking power semiconductor devices and to embodiments of methods of producing such reverse blocking power semiconductor devices. Background Art

[0002] Modern devices rely on power semiconductor devices for many functions in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or electric machines. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters, such as in traction applications.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. Furthermore, in the case where the power semiconductor device has a transistor configuration, the load current path may be controlled by means of an insulating electrode, often referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode may set the power semiconductor device in one of a conducting state and a forward blocking state, wherein the power semiconductor device is configured to block a forward voltage in the forward blocking state.

[0004] Sometimes, such power semiconductor devices are also configured to block reverse voltage in the reverse blocking state. In this case, the device can be referred to as a reverse blocking power semiconductor device. Reverse blocking IGBT (RB-IGBT) or reverse blocking emitter switch thyristor (RB-EST) are common examples of bipolar reverse blocking power semiconductor switches. For example, other types of reverse blocking power semiconductor devices can be configured as unipolar reverse blocking power semiconductor transistors.

[0005] It is generally desirable to improve the electrical performance of reverse blocking power semiconductor devices, for example with respect to their on-state losses and / or switching losses. For example, it may therefore be desirable to reduce the device thickness at a given forward and reverse blocking voltage that the device should support. Summary of the invention

[0006] According to an embodiment, a reverse blocking power semiconductor device comprises: a first load terminal structure and a second load terminal structure; a semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure; a plurality of control units (cells) electrically connected to the first load terminal structure. The control unit comprises: a forward blocking junction configured to block a forward voltage between the first load terminal structure and the second load terminal structure in a forward blocking state of the reverse blocking power semiconductor device; and a control electrode separated from the forward blocking junction by a control electrode insulating layer and configured to switch the reverse blocking power semiconductor device between a forward blocking state and a forward conducting state. The reverse blocking power semiconductor device further comprises: a reverse blocking junction configured to block a reverse voltage between the first load terminal structure and the second load terminal structure in a reverse blocking state of the reverse blocking power semiconductor device; and a plurality of trench field plates arranged in a plurality of field plate trenches, each field plate trench comprising a field plate insulating layer, which separates one of the trench field plates from the reverse blocking junction, and the trench field plate is electrically connected to the second load terminal structure.

[0007] According to another embodiment, a method for forming a power semiconductor device is proposed. The method includes: providing a semiconductor body; coupling each of a first load terminal structure and a second load terminal structure to the semiconductor body; forming a plurality of control units electrically connected to the first load terminal structure, wherein the control unit includes: a forward blocking junction configured to block a forward voltage between the first load terminal structure and the second load terminal structure in a forward blocking state of a reverse blocking power semiconductor device; and a control electrode separated from the forward blocking junction by a control electrode insulating layer and configured to switch the reverse blocking power semiconductor device between a forward blocking state and a forward conducting state. The method also includes: forming a reverse blocking junction configured to block a reverse voltage between the first load terminal structure and the second load terminal structure in a reverse blocking state of the reverse blocking power semiconductor device; and forming a plurality of trench field plates, the plurality of trench field plates being arranged in a plurality of field plate trenches, each field plate trench including a field plate insulating layer, the field plate insulating layer separating one of the trench field plates from the reverse blocking junction, and the trench field plate being electrically connected to the second load terminal structure.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The parts in the drawings are not necessarily to scale, instead emphasis is placed upon illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts. In the drawings:

[0010] Figure 1A-D each schematically and exemplarily illustrate a portion of a vertical cross-section of a bipolar reverse blocking power semiconductor device according to one or more embodiments;

[0011] Figure 2A Figure 1C Simulated blocking characteristics of reverse blocking power semiconductor devices;

[0012] Figure 2B In the forward blocking state and the reverse blocking state, respectively, the Figure 1C The simulated electric field strength of a vertical cut of a reverse blocking power semiconductor device;

[0013] Figure 3A -E each schematically and exemplarily shows a portion of a vertical cross-section of a unipolar reverse blocking power semiconductor device according to one or more embodiments;

[0014] Figure 4-15 Each of schematically and exemplarily shows a portion of a vertical cross section of a reverse blocking power semiconductor device according to one or more embodiments, wherein the portion includes an edge termination region; and

[0015] Fig.16 A portion of a horizontal cross section of a lateral inverted power semiconductor device according to one or more embodiments is schematically and exemplarily shown. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0017] In this regard, directional terms such as "top," "bottom," "below," "before," "after," "rear," "leading," "trailing," "above," and the like may be used with reference to the orientation of the accompanying drawings being described. Because components of the embodiments may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present invention. The detailed description thereof that follows should not be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0018] Reference will now be made in detail to various embodiments, one or more examples of which are shown in the accompanying drawings. Each example is provided by way of explanation and is not meant as a limitation of the invention. For example, a feature shown or described as part of one embodiment may be used on or in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals in different drawings unless otherwise specified.

[0019] The term "horizontal" as used in this specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or a semiconductor structure. This may be, for example, a surface of a semiconductor wafer or a die or a chip. For example, the first lateral direction X and the second lateral direction Y mentioned below may both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0020] The term "vertical" as used in this specification is intended to describe an orientation that is substantially arranged perpendicular to a horizontal surface, i.e., arranged parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0021] In this specification, n-doped is referred to as the “first conductivity type” and p-doped is referred to as the “second conductivity type.” Alternatively, a relative doping relationship may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0022] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, segments, zones, parts or components of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a part or component of a semiconductor device. Furthermore, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, the transition between two elements contacting each other may not include additional intermediate elements or the like.

[0023] Furthermore, in the context of this specification, if not otherwise specified, the term "electrically insulated" is used in the context of its general valid understanding, and is therefore intended to describe that two or more components are located separately from each other and there is no ohmic connection connecting those components. However, components that are electrically insulated from each other may still be coupled to each other, such as mechanically coupled and / or capacitively coupled and / or inductively coupled. To give an example, two electrodes of a capacitor may be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, such as by means of an insulation such as a dielectric.

[0024] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that exhibit a stripe cell or honeycomb cell configuration, for example, a power semiconductor device that can be used in a power converter or power supply. Therefore, in an embodiment, such a device can be configured to carry a load current to be fed to a load and / or provided separately by a power supply. For example, a power semiconductor device may include one or more active power semiconductor units, such as a monolithic integrated diode unit such as a monolithic integrated unit of two anti-serially connected diodes, a monolithic integrated transistor unit such as a monolithic integrated IGBT unit, and / or its derivatives. Such diode / transistor units can be integrated in a power semiconductor module. A plurality of such units can constitute a cell field in which an active region of a power semiconductor device is arranged.

[0025] The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device on a single chip having high voltage blocking and / or high current carrying capabilities. In other words, such power semiconductor devices are intended for high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and above, such as up to at least 500 V or even more, such as even up to at least 6 kV or more.

[0026] For example, the power semiconductor device described below may be a semiconductor device exhibiting a stripe cell configuration or a honeycomb (columnar / needle) cell configuration, and may be configured to be used as a power component in low, medium, and / or high voltage applications.

[0027] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0028] Figure 1A-D each schematically and exemplarily shows a portion of a vertical cross-section of a reverse blocking power semiconductor device 1 according to one or more embodiments. The reverse blocking power semiconductor device 1 includes a semiconductor body 10 and a first load terminal structure 11 and a second load terminal structure 12 coupled to a front side 10-1 and a back side 10-2 of the semiconductor body 10, respectively. The semiconductor body 10 is configured to conduct a load current between the first load terminal structure 11 and the second load terminal structure 12. For example, the first load terminal structure 11 includes a front side metallization, which can be coupled to, for example, an emitter terminal or a source terminal of the reverse blocking power semiconductor device 1. Accordingly, the second load terminal structure 12 can include a back side metallization, which is coupled to, for example, a collector terminal or a drain terminal of the reverse blocking power semiconductor device 1.

[0029] exist Figure 1A In the exemplary embodiment depicted in FIG. 1-D, the reverse blocking power semiconductor device 1 has an IGBT configuration, so that the first load terminal structure 11 can be well referred to as an emitter load terminal structure, and the second load terminal structure 12 can be referred to as a collector terminal structure. In other words, in Figure 1A In an exemplary embodiment of the reverse blocking power semiconductor device 1, the reverse blocking power semiconductor device 1 is or includes a reverse blocking IGBT (RB-IGBT). In other embodiments, the reverse blocking power semiconductor device 1 may be or include a different kind of bipolar reverse blocking power semiconductor device 1, such as, for example, a reverse blocking emitter switch thyristor (RB-EST). In other embodiments, the reverse blocking power semiconductor device 1 may alternatively be configured as a unipolar reverse blocking power semiconductor device 1, such as, for example, a unipolar reverse blocking transistor, such as a reverse blocking MOSFET (RB-MOSFET). This will be described below with reference to, for example, Figures 3A-3E Further explained in more detail.

[0030] In addition, Figure 1A In the embodiment shown in -D, the reverse blocking power semiconductor device 1 has a vertical configuration. That is, the load current flows between the front side 10-1 and the back side 10-2 of the semiconductor body 10. However, it should be noted that the present invention is not limited to a vertical reverse blocking power semiconductor device 1. For example, the following will refer to Fig.16 The lateral reverse blocking power semiconductor device 1 is further explained, wherein the load current flows substantially along a first lateral direction X.

[0031] As is known in principle in the field of vertical IGBTs, Figure 1AThe power semiconductor device 1 comprises a plurality of control units 14, which are arranged at the front side 10-1 and are electrically connected to the first load terminal structure 11, and the control unit 14 comprises a forward blocking junction 103 in the form of a pn junction, which is formed at the transition between the drift region 100 of the semiconductor body 10 and the body region 101 of the semiconductor body 10. The drift region 100 has a dopant of a first conductivity type (e.g., n-type), while the body region 101 has a dopant of a second conductivity type (e.g., p-type) complementary to the first conductivity type. The forward blocking junction 103 is configured to block a forward voltage between the first load terminal structure 11 and the second load terminal structure 12 in a forward blocking state of the reverse blocking power semiconductor device 1.

[0032] Each control unit 14 comprises a control electrode 150 extending in a vertical control trench 15. The control trench 15 comprises a control electrode insulating layer 151 which insulates the control electrode 150 from a portion of the semiconductor body 10 surrounding the trench 15. The control electrode 150 is separated from the forward blocking junction 103 by means of the control electrode insulating layer 151. In other words, the control electrode insulating layer 151 is arranged between the control electrode 150 and the pn junction forming the forward blocking junction 103. For example, the control electrode insulating layer 151 may be adjacent to each of the control electrode 150 and the pn junction 103. For example, the control electrode insulating layer 151 may comprise silicon dioxide, such as thermally grown silicon dioxide. The control trench 15 adjoins a source region 102 of the first conductivity type, the body region 101 and a portion of the drift region 100. Each control electrode 150 may be insulated from the first load terminal structure 11 by means of an insulating block 154 (e.g., in the form of an oxide block). The control electrode 150 may be electrically connected to a control terminal, such as a gate terminal (not shown) of the reverse blocking power semiconductor device 1. For example, the control electrode 150 may be configured to receive an external control signal, such as a gate voltage signal, via an external control terminal. The control electrode 150 is configured to switch the reverse blocking power semiconductor device 1 between a forward blocking state and a forward conducting state. For example, the switching may occur according to a control signal provided to the control electrode 150. The control electrode 150 may be configured to induce a conduction channel in the body region 101 adjacent to the trench 15. For example, an electrical path may thus be opened between the source region 102 electrically connected to the first load terminal structure 11 and the drift region 100 in the forward conducting state of the reverse blocking power semiconductor device 1.

[0033] At the back side 10-2, the semiconductor body 10 comprises a back side emitter region 107 of a second conductivity type, which is known in principle in the field of IGBTs. The back side emitter region 107 is electrically connected to the second load terminal structure 12 on one side and to the drift region 100 on the other side. At the transition between the back side emitter region 107 and the drift region 100, a pn junction is formed. The pn junction forms a reverse blocking junction 104, which is configured to block a reverse voltage between the first load terminal structure 11 and the second load terminal structure 12 in a reverse blocking state of the reverse blocking power semiconductor device 1.

[0034] In addition, a plurality of field plate trenches 16 are provided at the back side 10-2. The field plate trenches 16 extend from the back side 10-2 into the semiconductor body 10 in parallel with the vertical direction Z. Each field plate trench 16 includes a trench field plate 160 and a field plate insulating layer 161, which insulates the trench field plate 160 from surrounding parts of the semiconductor body 10, such as from the back side emitter region 107 and the drift region 100. The corresponding trench field plate 160 is separated from the reverse blocking junction 104 by means of the field plate insulating layer 161. In other words, the field plate insulating layer 161 is arranged between the trench field plate 160 and the pn junction forming the reverse blocking junction 104. For example, the field plate insulating layer 161 may be adjacent to each of the trench field plate 160 and the pn junction 104. For example, the field plate insulating layer 161 may include one of silicon dioxide and silicon nitride. In an embodiment, the field plate insulating layer 161 includes, for example, a stacked layer of silicon oxide and silicon nitride. The trench field plate 160 comprises a conductive material, such as polysilicon or a metal. Furthermore, the trench field plate 160 is electrically connected to the second load terminal structure 12. In other words, there is a low-ohmic electrical connection between the second load terminal structure 12 provided within the reverse blocking power semiconductor device 1 itself and the trench field plate 160 (as opposed to, for example, an electrical connection established outside the reverse blocking power semiconductor device 1, such as by means of an external lead or circuit that can be coupled to a terminal of the reverse blocking power semiconductor device 1).

[0035] The trench field plate 160 may be configured to prevent punch-through of the electric field to the backside emitter region 107 in the forward blocking state. For example, a plurality of semiconductor mesas 17 are formed between the field plate trenches 16, wherein the width W of each semiconductor mesa 17 is sufficiently small to prevent such punch-through (in the case of Figure 1A The width W is not indicated in the reference Figure 1D ). For example, in an embodiment, the field plate trench 16 may have a field plate trench depth D, wherein the width of each semiconductor terrace 17 is less than half of the field plate trench depth D, see Figure 1D For example, the width W may be smaller than 2 μm, such as equal to or smaller than 1 μm.

[0036] The functionality of the trench field plate 160 may be supported by a first field stop region 108 extending at least partially between the field plate trenches 16 . Figure 1A Such a first field stop area 108 is not shown in FIG. Figure 1C The first field stop zone 108 comprises a dopant of the first conductivity type at a higher dopant concentration than the drift zone 100. The first field stop zone 108 may be arranged between the drift zone 100 and the backside emitter zone 108. As is known in principle in the art, such a first field stop zone 108 may fulfil the function of a buffer for the electric field in the forward blocking state. Figure 1C According to an exemplary embodiment, punch-through of an electric felt field in a forward conduction state may be prevented by a combined effect of the shielding of the trench field plate 160 and the buffering effect of the first field stop zone 108 .

[0037] For example, the dopant concentration of the first field stop zone 108 may be chosen to be relatively low due to the presence of the trench plate 160 compared to a conventional setup, where the first field stop zone 108 would have to prevent punch-through alone. For example, in an embodiment, a maximum concentration of the concentration of dopants of the first conductivity type within the first field stop zone 108 exceeds the concentration of dopants of the first conductivity type of the drift zone 100 by a factor of at least 10, such as by a factor of at least 100. In other words, the dopant concentration in the first field stop zone 108 may be at least one or even at least two orders of magnitude higher than the dopant concentration of the drift zone 100. For example, the doping of the drift zone 100 may be substantially that of the semiconductor substrate, i.e. the base doping of the semiconductor body 10.

[0038] Furthermore, in an embodiment, the maximum concentration of the concentration of the first conductivity type dopant within the first field stop zone 108 may be less than , such as, for example, less than .

[0039] It is also possible to arrange the first field stop zone 108 and / or the maximum concentration of the dopant concentration of the first conductivity type within the first field stop zone 108 at a certain distance from the reverse blocking junction 104. Figure 1D It is shown exemplarily in Figure 1DAn enlarged view of a portion of a vertical cross-sectional portion of a reverse blocking semiconductor device 1 according to some embodiments is shown, wherein the depicted portion is located near the back side 10-2. For example, in an embodiment, a maximum concentration of the concentration of the dopant of the first conductivity type within the first field stop zone 108 may be located at a distance of at least 0.2 μm, such as at least 0.5 μm, from the reverse blocking junction 104.

[0040] Further references Figure 1D In an embodiment, the concentration of the dopant of the first conductivity type in the first field stop zone 108 in the distal portion of the terrace 17 may be less than or equal to five times the dopant concentration of the drift region 100, wherein the distal portion of the terrace 17 extends from a first depth D1 corresponding to the distal end of the trench field plate 160 to a second depth D2, and the second depth D2 is less than the first depth D1 by half of the terrace width W, i.e., by W / 2. In other words, the second depth D2 is positioned closer to the proximal end of the trench field plate 160, by W / 2 than the distal end of the trench field plate 160. In another variation, the field stop zone may be in the terrace 17 only outside the distal portion of the terrace 17, i.e., at Figure 1D Below the distal portion of the tube (not shown).

[0041] according to Figure 1B and 1C In each of the exemplary embodiments shown in , a second field stop zone 109 may also be provided at the front side 10-1. Similar to what has been explained above with respect to the first field stop zone 108, the second field stop zone 109 may also include dopants of the first conductivity type at a higher doping concentration than the drift zone 100. Furthermore, the second field stop zone 109 is located between the drift zone 100 and the body region 101. In fact, in these embodiments, the forward blocking junction 103 is formed at the transition between the body region 101 and the second field stop zone 109. The second field stop zone 109 extends at least partially inside the control unit 15, such as between the control trenches 15. For example, in the reverse blocking state of the reverse blocking power semiconductor device 1, the second field stop zone 109 may prevent the electric field from punching through to the body region 101. For example, similar to what has been explained above with respect to the terraces 17 at the back side 10-2, the semiconductor terrace regions between adjacent control trenches 15 may also be designed to be narrow enough to prevent punching through in the reverse blocking state.

[0042] For example, using the above reference Figures 1A to 1D The design of the exemplary embodiment explained can realize a RB-IGBT with substantially symmetrical blocking capability. In other words, the maximum forward blocking voltage of such a RB-IGBT can be equal to or similar to the maximum reverse blocking voltage of such a RB-IGBT.

[0043] To further illustrate this point, Figure 2A The example shows Figure 1C Simulated blocking characteristics of the RB-IGBT 1. For this simulation, a device thickness of 100 μm was assumed. The forward blocking characteristics (solid curve) and reverse blocking characteristics (dashed curve) show that the device is able to block more than 1400 V in each direction. Figure 2B The electric field distribution at breakdown for both directions is shown in , where, again, the solid curve corresponds to the forward blocking state and the dashed curve corresponds to the reverse blocking state. Figure 2B , the dependence of the electric field on the depth (in micrometers) measured from the front side of the device 1 is shown. Due to the shielding of the trench field plate 160, in the reverse blocking state, the electric field is not significantly reduced within the first field stop zone 108, as it would be the case without the trench field plate 160, or in the case where the first field stop zone 108 extends deeper into the semiconductor body than the field trenches 16. As a result, relatively high blocking voltages can also be achieved in the reverse direction.

[0044] So far, reference has been made to bipolar reverse blocking power semiconductor devices 1 such as Figures 1A to 1D The RB-IGBT shown in FIG. 1 is used to exemplarily explain the present invention. As an alternative, Figures 3A to 3E An embodiment of a unipolar reverse blocking power semiconductor device 1 is shown, such as a RB-MOSFET, in which the reverse blocking junction 104 is formed by a Schottky junction instead of a pn junction. For example, the reverse blocking junction 104 may be formed by a semiconductor-to-metal transition between the drift region 102 and a backside metallization forming part of the second load terminal structure 12. In this case, due to the Schottky barrier at the semiconductor-to-metal transition 104, the reverse blocking capability of the device 1 may be accompanied by a threshold in the forward characteristic.

[0045] In addition to the unipolar operation of device 1 and the different reverse blocking junction 104, Figures 3A to 3E The embodiment shown in FIG. Figures 1A to 1D Therefore, what has been explained above, for example, with respect to the control unit 14 at the front side 10-1 and the trench field plate 160 at the back side 10-2, can also be applied to Figures 3A to 3D Reference is also made to the above explanations regarding the first and second field stop areas 108, 109 (see Figure 3B , 3D and 3E). For example, it should be noted that the first field stop zone 108 and / or the maximum concentration of the dopant concentration within the first field stop zone 108 may be arranged at a certain distance from the reverse blocking junction formed by the Schottky contact, such as Figure 3EAlternatively, the first field stop layer 108 may directly adjoin the Schottky contact 104, as shown in FIG. Figure 3D as shown in .

[0046] In addition, according to Figure 3C and 3E In each of the embodiments, the unipolar reverse blocking transistor 1 may have a super-junction configuration, which is well known in the art. That is, the drift region 100 may include a plurality of first columns 1001 of a first conductivity type and a plurality of second columns 1002 of a second conductivity type, wherein the first columns 1001 and the second columns 1002 are arranged adjacent to each other in an alternating manner. Figure 3C and 3E As shown in each of the above, the pillars 1001, 1002 extend along the vertical direction Z between the control unit 14 at the front side 10-1 and the field plate trench 16 at the back side 10-2. For example, it may be provided that the second pillar 1002 is not connected to the body region 101. Figure 3C As shown in , a second field stop zone 109 may separate the body region 101 from a second pillar 1002 of such a super junction structure.

[0047] Figures 4 to 15 Each of them schematically and exemplarily shows a portion of a vertical cross-section of a reverse blocking power semiconductor device 1 according to one or more embodiments, wherein each of the depicted portions includes a portion of an active region 18 and an edge termination region 19 of the reverse blocking power semiconductor device 1 .

[0048] For example, the edge termination structure arranged in the edge termination region 19 of the reverse blocking power semiconductor device 1 needs to be compatible with the reverse blocking capability. Figures 4 to 15 Several examples of how this can be achieved are shown in .

[0049] According to an embodiment, the potential of the second load terminal structure 12 (e.g., collector potential) may be transferred to the front side 10-1, e.g., by means of a connection region 106 of the second conductivity type, which extends along a lateral chip edge 10-4, as shown. This is known in principle in the field of reverse blocking power semiconductor devices.

[0050] Furthermore, it may be provided that the narrow terrace 17 at the back side 10-2 and the field plate trench 16 are also present in at least a portion of the edge termination region 19, such as at least in an inner portion of the edge termination region 19. In an embodiment, the field plate trench 160 may be present in a substantial portion of the edge termination region 19, which may be, for example, along a length equal to or greater than Figure 4 The distance extends by the thickness of the device in the vertical cross section shown in .

[0051] On the other hand, a corresponding structure may also be provided at the front side 10 - 1 inside at least a portion of the edge termination region 19 . Figure 4 . As shown, a plurality of trenches 13 with electrodes 130 and trench insulating layers 131 are provided at the front side 10-1, as well as semiconductor regions 134 of the second conductivity type arranged therebetween. These structures may be similar to or structurally identical to the control trenches 15, the control electrodes 150, the control electrode insulating layers 151 and the body region 101, respectively. For example, the trenches 13 in the edge termination region 19 may have been formed together with the control trenches 15 in the active region 18 in one or more common processing steps.

[0052] For example, Figure 5 As schematically shown in FIG. 1 , the outermost electrode 131 may be electrically connected to the second load terminal structure 12 via the connection region 106. Figure 5 As shown in , the other electrodes 131 may be connected to respective adjacent regions 134 of the second conductivity type. These regions 134 are separated from each other by trenches 13 and may assume different potentials during forward blocking and during reverse blocking.

[0053] Furthermore, in case the first and / or second field stop zones 108, 109 are provided inside the active cell field 18, they may also be provided at least in a part of the edge termination 19, such as Figure 5 As shown exemplarily in FIG.

[0054] Figure 6 Another exemplary embodiment of edge termination of RB-IGBT1 is shown, where an exemplary course of the space charge region during forward blocking is indicated as a dashed line. As shown, the semiconductor region 100-5 of the first conductivity type, which may be an extension of the drift region 100 into the edge termination region 19, may touch the front surface 10-1 at one or more locations in the edge termination region 19. Furthermore, it should be noted that the second field stop region 109 need not extend continuously to the connection region 106 at the chip edge 10-4.

[0055] In accordance with Figures 7 to 9 In each of the embodiments of the present invention, the chip edge 10-4 may exhibit a slope corresponding to, for example, the (111) equivalent crystal plane, as it may be produced using anisotropic wet etching with KOH or TMAH. In addition, a field stop region 1060 may be provided adjacent to the connection region 106 at the chip edge, see Figure 8 .exist Figure 7 and8 In FIG. , the dotted line indicates an exemplary process of the space charge region in the forward blocking state.

[0056] Fig.10 The extension of the boundary of the space charge zone during reverse blocking is shown by way of example.

[0057] exist Figure 5-10 In FIG. 1 , only the electrical connection between the second conductivity type separation region 134 and the trench electrode 130 is schematically shown. Fig.11 , a specific implementation is exemplarily shown, in which the connection can be achieved by means of a plurality of metal field plates 191. Of course, there are many possibilities of how to perform these connections in detail. In addition to establishing the connection, the field plate structure 191 can even further reduce the electric field strength in the forward blocking state and / or in the reverse blocking state.

[0058] In accordance with Fig.12 In the embodiment of the present invention, not all trenches 13 in the edge termination region 19 are filled with a conductive material. Instead, it is also possible to use an insulating filling 192 such as an oxide in some trenches 13, such as Fig.12 Schematically shown in FIG.

[0059] In addition, if Fig.13 As exemplarily shown in FIG. 1 , the thickness of the trench insulation layer 131 separating the conductive fillers 130 of all or some trenches in the edge termination region 19 may be greater than the thickness of the control electrode insulation layer 151 and / or greater than the thickness of the field plate insulation layer 161 .

[0060] Fig.14 Schematically and exemplarily, an embodiment of an edge termination 19 of a RB-MOSFET 1 is shown. In the case of a unipolar device with a Schottky contact 104 at the drain terminal structure 12, the Schottky contact 104 may, for example, extend to the edge 10-4 of the chip (not shown). Alternatively, the drain terminal structure 12 may, for example, contact a region 107 of the second conductivity type (such as a p-region 107) at least in a portion of the edge termination region 19, such as Fig.14 as shown in .

[0061] The edge termination structure explained above can also be used for a bidirectional switch 1, such as Fig.15exemplarily shown in . In this case, the source region 1020 may be provided in the cell field at the back side 10-2. The gate electrode 1600 arranged in the gate trench 16-1 and insulated from the body region 1070 by the gate insulation structure 1610 may be connected to a second gate terminal (not shown) instead of the second load terminal structure 12. In addition, the gate electrode 1600 is insulated from the second load terminal structure 12 by means of an insulating block 1640 (e.g., in the form of an oxide block). However, the trench field plate 160 in the edge termination region 19 may be connected to the second load terminal structure 12, as described previously. In addition, there may also be a provided trench field plate 160 connected to the second load terminal structure (instead of the second gate terminal) in the cell field, i.e. in the active region 18.

[0062] Fig.16 The lateral design of the reverse blocking RB-IGBT 1 is shown exemplarily and schematically. It should be noted that in contrast to the other figures, a horizontal cross section of the semiconductor device 1 is shown. In this embodiment, the load current flows mainly in the second lateral direction Y. Apart from this difference, the structure is similar to that described above with reference to e.g. Figure 1A The structure explained.

[0063] A method for processing a reverse blocking power semiconductor device 1, comprising:

[0064] - providing a semiconductor body 10;

[0065] - coupling each of the first load terminal structure 11 and the second load terminal structure 12 to the semiconductor body 10;

[0066] - forming a plurality of control units 14 electrically connected to the first load terminal structure 11 and comprising:

[0067] - a forward blocking junction 103 configured for blocking a forward voltage between the first load terminal structure 11 and the second load terminal structure 12 in a forward blocking state of the reverse blocking power semiconductor device 1 ; and

[0068] - a control electrode 150 which is separated from the forward blocking junction 103 by means of a control electrode insulating layer 151 and is configured for switching the reverse blocking power semiconductor device 1 between a forward blocking state and a forward conducting state;

[0069] - forming a reverse blocking junction 104 configured to block a reverse voltage between the first load terminal structure 11 and the second load terminal structure 12 in a reverse blocking state of the reverse blocking power semiconductor device 1; and

[0070] - forming a plurality of trench field plates 160 arranged in the plurality of field plate trenches 16 , each field plate trench 16 comprising a field plate insulating layer 161 separating one of the trench field plates 160 from the reverse blocking junction 104 , the trench field plates 160 being electrically connected to the second load terminal structure 12 .

[0071] The method steps do not need to be performed in the order in which they are mentioned above. For example, it is clear to a person skilled in the art that after formation of the field plate trench 16 including the trench field plate 160 and / or of the reverse blocking junction 104, such as the control unit 14, the load terminal structures 11, 12 can be arranged on the semiconductor body 10.

[0072] The above-described embodiments of the method of forming a reverse blocking power semiconductor device correspond to the above-described embodiments of the reverse blocking power semiconductor, and vice versa. Thus, for example, the features of the above-described embodiments of the reverse blocking power semiconductor device can be implemented by performing corresponding processing method steps.

[0073] In the above, embodiments of reverse blocking power semiconductor devices and corresponding processing methods are explained. For example, these semiconductor devices are based on silicon (Si). Therefore, single-crystalline semiconductor regions or layers such as semiconductor body 10 and its regions / region zones such as regions 100, 101, 102, 107, 108, 109, etc. can be single-crystalline Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0074] However, it should be understood that the semiconductor body 10 and its regions / zones may be made of any semiconductor material suitable for use in manufacturing semiconductor devices. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium galliumarsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The above semiconductor materials are also called "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0075] For ease of description, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the corresponding device other than those depicted in the figures. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. The same terms refer to the same elements throughout the specification.

[0076] As used herein, the terms “having,” “containing,” “including,” “comprising,” “exhibiting,” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

[0077] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A reverse blocking power semiconductor device (1), comprising: - a first load terminal structure (11) and a second load terminal structure (12); - a semiconductor body (10) configured to conduct a load current between a first load terminal structure (11) and a second load terminal structure (12); - a plurality of control units (14), electrically connected to the first load terminal structure (11) and comprising: a forward blocking junction (103) configured to block a forward voltage between the first load terminal structure (11) and the second load terminal structure (12) in a forward blocking state of the reverse blocking power semiconductor device (1); and A control electrode (150) separated from the forward blocking junction (103) by means of a control electrode insulating layer (151) and configured to switch the reverse blocking power semiconductor device (1) between a forward blocking state and a forward conducting state; - a reverse blocking junction (104) configured to block a reverse voltage between the first load terminal structure (11) and the second load terminal structure (12) in a reverse blocking state of the reverse blocking power semiconductor device (1); as well as - a plurality of trench field plates (160) arranged in a plurality of field plate trenches (16), each field plate trench (16) comprising a field plate insulating layer (161) separating one of the trench field plates (160) from the reverse blocking junction (104), the trench field plates (160) being electrically connected to the second load terminal structure (12), wherein the field plate trenches (16) have a field plate trench depth (D), wherein a plurality of semiconductor terraces (17) are formed between the field plate trenches (16), wherein a width (W) of each of the semiconductor terraces (17) is less than half of the field plate trench depth (D), wherein the semiconductor body (10) comprises - a drift region (100) comprising dopants of a first conductivity type, and A first field stop zone (108) comprising dopants of the first conductivity type at a higher dopant concentration than the drift zone (100), the first field stop zone (108) extending at least partially between the field plate trenches (16).

2. A reverse blocking power semiconductor device (1) according to claim 1, wherein the semiconductor body (10) has a front side (10-1) and a rear side (10-2), the first load terminal structure (11) being arranged at the front side (10-1) and the second load terminal structure (10-2) being arranged at the rear side (10-2).

3. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, wherein a plurality of semiconductor terraces (17) are formed between the field plate trenches (16), wherein a width (W) of each of the semiconductor terraces (17) is less than 2 μm.

4. The reverse blocking power semiconductor device (1) according to claim 1, wherein the first field stop zone (108) and / or the maximum concentration of the concentration of the first conductivity type dopant of the first field stop zone (108) is arranged at a certain distance from the reverse blocking junction (104).

5. A reverse blocking power semiconductor device (1) according to claim 1 or 2, wherein the maximum concentration of the concentration of the first conductivity type dopant within the first field stop zone (108) exceeds the concentration of the first conductivity type dopant in the drift zone (100) by at least 100 times.

6. The reverse blocking power semiconductor device (1) according to one of claims 1 to 2, wherein the maximum concentration of the concentration of the dopant of the first conductivity type in the first field stop zone (108) is less than 5E17 cm -3 .

7. The reverse blocking power semiconductor device (1) according to one of claims 1 to 2, wherein a maximum concentration of the concentration of the dopant of the first conductivity type within the first field stop zone (108) is located at a distance of at least 0.2 μm from the reverse blocking junction (104).

8. A reverse blocking power semiconductor device (1) according to one of claims 1 to 2, wherein a plurality of semiconductor terraces (17) having a terrace width (W) are formed between the field plate trenches (16), wherein a concentration of a dopant of a first conductivity type in a first field stop zone (108) in a distal portion of the terrace (17) is less than or equal to 5 times a dopant concentration in the drift region (100), wherein the distal portion of the terrace (17) extends from a first depth (D1) corresponding to a distal end of the trench field plate (160) to a second depth (D2), the second depth (D2) being less than the first depth (D1) by half the terrace width (W).

9. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, wherein the semiconductor body (10) comprises - a drift region (100) comprising dopants of a first conductivity type, and - a second field stop zone (109) comprising dopants of the first conductivity type at a higher dopant concentration than the drift zone (100), the second field stop zone (108) extending at least partially inside the control unit (14).

10. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, wherein the reverse blocking junction (104) is formed by a pn junction.

11. The reverse blocking power semiconductor device (1) according to one of claims 1 to 2, wherein the reverse blocking junction (104) is formed by a Schottky junction.

12. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1 - 2, wherein the reverse blocking power semiconductor device (1) is a bipolar reverse blocking power semiconductor device (1).

13. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1 -2, wherein the reverse blocking power semiconductor device (1) is a unipolar reverse blocking power semiconductor device (1).

14. A reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, wherein the semiconductor body (10) includes a drift region (100), the drift region including a plurality of first columns (1001) of a first conductivity type and a plurality of second columns (1002) of a second conductivity type complementary to the first conductivity type, the first columns (1001) and the second columns (1002) being arranged adjacent to each other in an alternating manner.

15. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, exhibiting an active region (18) and an edge termination region (19), wherein a portion of the plurality of field plate trenches (16) is arranged in the edge termination region (19).

16. The reverse blocking power semiconductor device (1) according to one of the preceding claims 1-2, wherein the reverse blocking power semiconductor device (1) is a bidirectional switching device.

17. A method for processing a reverse blocking power semiconductor device (1), comprising: - providing a semiconductor body (10); - coupling each of the first load terminal structure (11) and the second load terminal structure (12) to the semiconductor body (10); - a plurality of control units (14) electrically connected to the first load terminal structure (11) and comprising: a forward blocking junction (103) configured to block a forward voltage between the first load terminal structure (11) and the second load terminal structure (12) in a forward blocking state of the reverse blocking power semiconductor device (1); and A control electrode (150) separated from the forward blocking junction (103) by means of a control electrode insulating layer (151) and configured to switch the reverse blocking power semiconductor device (1) between a forward blocking state and a forward conducting state; - forming a reverse blocking junction (104), the reverse blocking junction (104) being configured to block a reverse voltage between the first load terminal structure (11) and the second load terminal structure (12) in a reverse blocking state of the reverse blocking power semiconductor device (1); as well as - forming a plurality of trench field plates (160) arranged in a plurality of field plate trenches (16), each field plate trench (16) comprising a field plate insulating layer (161) separating one of the trench field plates (160) from the reverse blocking junction (104), the trench field plates (160) being electrically connected to the second load terminal structure (12), wherein the field plate trenches (16) have a field plate trench depth (D), wherein a plurality of semiconductor terraces (17) are formed between the field plate trenches (16), wherein a width (W) of each of the semiconductor terraces (17) is less than half of the field plate trench depth (D), wherein the semiconductor body (10) comprises - a drift region (100) comprising dopants of a first conductivity type, and A first field stop zone (108) comprising dopants of the first conductivity type at a higher dopant concentration than the drift zone (100), the first field stop zone (108) extending at least partially between the field plate trenches (16).

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