Power semiconductor device

Abstract

The invention discloses a power semiconductor device, and the device comprises a first semiconductor body which is used for forming a depletion mode transistor; the second semiconductor body is located on the first surface of the first semiconductor body; the second semiconductor body is used for forming an enhancement mode transistor and is connected in series with the depletion mode transistor; the forbidden bandwidth of the third semiconductor body is lower than that of the second semiconductor body, and the third semiconductor body is located on one side, away from the first semiconductor body, of the second semiconductor body; the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer which is different from the first semiconductor layer and the third semiconductor layer in conduction type and is located between the first semiconductor layer and the third semiconductor layer; a first electrode electrically connected to the second semiconductor body, the first semiconductor body, and the third semiconductor layer; the second electrode is located on the second surface. According to the technical scheme provided by the invention, by integrating the polycrystalline silicon NPN structure, the passive over-temperature turn-off capability of the device is realized, and the robustness of the device is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] Field-Effect Transistor (FET) is a semiconductor device that uses electric field effects to control current. Its core is to modulate channel conductivity by changing the gate voltage.

[0003] In related technologies, SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has lower switching losses than bipolar transistors such as IGBT (Insulate-Gate Bipolar Transistor), which makes it more competitive in high-frequency application scenarios, such as being used as a switching device in a bridge circuit.

[0004] However, due to the high interface state density of the silicon carbide MOSFET channel, the effective channel mobility is very low, which will lead to an increase in the device's specific on-resistance and concentrate the heat of the chip on the surface. Taking the high-frequency SiC MOSFET bridge circuit as an example, the high-frequency switching speed will lead to an increase in dv / dt. The rapid change of the switch node voltage will cause the Miller capacitance in the power MOSFET to charge and discharge rapidly. This charging and discharging current will form a potential difference between the gate and source of the power MOSFET through the peripheral drive circuit. When this potential difference reaches a certain magnitude, it will cause the device to be mistakenly turned on, resulting in a short circuit between the upper and lower transistors, and eventually the device will burn out.

[0005] This overcurrent damage is essentially caused by surface heating of the device. Typically, a sensor collects temperature signals, converts them into electrical signals, and transmits them to the driver circuit for processing and judgment, which then shuts down the device for protection. However, this feedback process takes considerable time, and often the device is not shut down in time, resulting in damage.

[0006] Therefore, how to achieve rapid over-temperature protection for power semiconductor devices to improve the robustness of power semiconductor devices has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0007] An embodiment of the present invention provides a power semiconductor device to achieve rapid over-temperature protection for the power semiconductor device and improve the robustness of the power semiconductor device.

[0008] An embodiment of the present invention provides a power semiconductor device, including at least one cellular structure, wherein the cellular structure includes:

[0009] A first semiconductor body comprising a first surface and a second surface opposite to each other; the first semiconductor body is used to form a depletion-mode transistor;

[0010] a second semiconductor body located on a first surface of the first semiconductor body; the second semiconductor body is configured to form an enhancement-mode transistor; wherein the material of the first semiconductor body is different from the material of the second semiconductor body, and the depletion-mode transistor formed by the first semiconductor body and the enhancement-mode transistor formed by the second semiconductor body are connected in series;

[0011] a third semiconductor body, located on a side of the second semiconductor body away from the first semiconductor body and electrically isolated from the second semiconductor body; a band gap width of a material of the third semiconductor body is lower than a band gap width of a material of the second semiconductor body; wherein the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer having a different conductivity type from the first semiconductor layer and the third semiconductor layer, and the first semiconductor layer being used as a gate of the enhancement-mode transistor;

[0012] a first electrode electrically connected to the second semiconductor body, the first semiconductor body and the third semiconductor layer;

[0013] The second electrode is located on the second surface.

[0014] Optionally, the material of the first semiconductor body includes SiC, the material of the second semiconductor body includes GaN; and the material of the third semiconductor body includes polysilicon.

[0015] Optionally, the first semiconductor body includes a first ohmic contact region and a second ohmic contact region of different conductivity types, both of which are located on the first surface, and the first ohmic contact region and the second ohmic contact region are spaced apart;

[0016] The first semiconductor body further includes a buried layer located on a side of the first ohmic contact region and the second ohmic contact region close to the second surface;

[0017] The buried layer and the second ohmic contact region have the same conductivity type as the second semiconductor layer; and the depletion-type transistor formed by the first semiconductor body is a depletion-type junction field-effect transistor.

[0018] Optionally, the orthographic projection of the first ohmic contact region on the second surface is located in the orthographic projection of the buried layer on the second surface, and the first ohmic contact region extends from a boundary of the first surface to the second ohmic contact region;

[0019] A portion of the orthographic projection of the second ohmic contact region on the second surface overlaps with the orthographic projection of the buried layer on the second surface.

[0020] Optionally, the second semiconductor body includes a third ohmic contact region and a fourth ohmic contact region, which are spaced apart on a surface of the second semiconductor body away from the first semiconductor body; the conductivity type of the third ohmic contact region and the fourth ohmic contact region are different from the conductivity type of the second semiconductor body;

[0021] The enhancement transistor formed by the second semiconductor body is a metal oxide semiconductor field effect transistor, the channel region of the enhancement transistor is located between the third ohmic contact region and the fourth ohmic contact region, and the orthographic projection of the first semiconductor layer on the second semiconductor body covers the channel region of the enhancement transistor.

[0022] Optionally, in the third semiconductor body, a direction in which the first semiconductor layer points to the third semiconductor layer is parallel to the first surface, and the third semiconductor layer is closer to the first electrode than the first semiconductor layer;

[0023] The cell structure further includes a conductive structure; the conductive structure and the first electrode are located on opposite sides of the second semiconductor body; a first ohmic contact region and a second ohmic contact region of the exposed portion of the second semiconductor body;

[0024] One end of the conductive structure is electrically connected to the exposed first ohmic contact area, and the other end of the conductive structure is electrically connected to the third ohmic contact area; the first electrode is electrically connected to the exposed second contact area, the fourth contact area and the third semiconductor layer.

[0025] Optionally, the cellular structure further includes:

[0026] a first insulating layer, the first insulating layer being located between the conductive structure and a sidewall of the second semiconductor body;

[0027] a second insulating layer, the second insulating layer being located between the first electrode and a sidewall of the second semiconductor body;

[0028] A third insulating layer is located between the first semiconductor body and the second semiconductor body.

[0029] Optionally, the cellular structure further includes:

[0030] a first ohmic contact layer, located on a surface of the first ohmic contact region away from the second surface, the conductive structure being electrically connected to the first ohmic contact region through the first ohmic contact layer;

[0031] and / or, a second ohmic contact layer located on a surface of the second ohmic contact region away from the second surface, the first electrode being electrically connected to the second ohmic contact region through the second ohmic contact layer;

[0032] and / or a third ohmic contact layer located on a surface of a portion of the third ohmic contact region, wherein the conductive structure is electrically connected to the third ohmic contact region through the third ohmic contact layer;

[0033] And / or, a fourth ohmic contact layer is located on a surface of a portion of the fourth ohmic contact region, and the first electrode is electrically connected to the fourth ohmic contact region through the fourth ohmic contact layer.

[0034] Optionally, the cellular structure further includes:

[0035] a fourth insulating layer, located on a side of the third semiconductor body away from the first semiconductor body, a side of the conductive structure away from the first semiconductor body, and between the third semiconductor body and the conductive structure;

[0036] The first electrode is also located on a surface of the fourth insulating layer away from the first semiconductor body, and extends toward the second ohmic contact region along sidewalls of the fourth insulating layer, the third semiconductor body, and the second semiconductor body.

[0037] Optionally, the power semiconductor device includes at least two of the cellular structures, and two adjacent cellular structures are mirror-symmetric in a first direction; the first direction is parallel to the first surface.

[0038] The technical solution provided by the embodiment of the present invention is to provide an enhancement-mode transistor formed by a second semiconductor body in cascade connection with a depletion-mode transistor formed by a first semiconductor body, so that the depletion-mode transistor formed by the first semiconductor body can be used to improve the voltage resistance of the entire power semiconductor device. On this basis, a third semiconductor body is provided on a side of the second semiconductor body away from the first semiconductor body, and the third semiconductor body includes a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer. The second semiconductor layer has a different conductivity type from the first semiconductor layer and the third semiconductor layer, so that a PN junction is formed between the first semiconductor layer and the second semiconductor layer, and a PN junction is formed between the third semiconductor layer and the second semiconductor layer; wherein the first semiconductor layer is used as a gate of the enhancement-mode transistor, and is connected to a gate voltage that can control the conduction state of the enhancement-mode transistor, and the third semiconductor layer is electrically connected to the first electrode; when the power semiconductor device is operating normally During operation, the gate of the device is electrically isolated from the first electrode by a PN junction. When the device encounters overcurrent, short circuit, overtemperature, etc., the surface of the second semiconductor body becomes severely heated, and the PN junction in the third semiconductor body will fail intrinsically, clamping the gate voltage to the voltage of the first electrode to force the device to shut down. At this time, since the band gap width of the material of the second semiconductor body is higher than the band gap width of the material of the third semiconductor body, the PN junction in the second semiconductor body will retain its normal function and maintain its blocking capability to avoid damage to the device due to overtemperature, thereby achieving rapid overtemperature protection for the power semiconductor device and improving the robustness of the power semiconductor device; in addition, the first semiconductor layer and the third semiconductor layer also provide additional capacitance for the device, which enables the device to form a lower voltage drop across the gate and the first electrode when crosstalk current arrives, thereby preventing the device from being mistakenly turned on due to crosstalk, achieving short-circuit protection for the power semiconductor device in high-frequency applications, and thus improving the reliability of the power semiconductor device.

[0039] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a schematic structural diagram of a power semiconductor device provided by an embodiment of the present invention;

[0042] Figure 2 yes Figure 1 Equivalent circuit diagram of the structure shown;

[0043] Figure 3 yes Figure 1 The working principle diagram of the structure shown in the on state;

[0044] Figure 4 yes Figure 1 The working principle diagram of the structure shown in the reverse blocking state;

[0045] Figure 5 yes Figure 1 A diagram showing the working principle of the third semiconductor body in the structure shown;

[0046] Figure 6 yes Figure 1 Another equivalent circuit diagram of the structure shown;

[0047] Figure 7 This is a partial circuit diagram of a half-bridge circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] An embodiment of the present invention provides a power semiconductor device, Figure 1 is a schematic structural diagram of a power semiconductor device provided by an embodiment of the present invention. Figure 2 yes Figure 1 The equivalent circuit diagram of the structure shown is shown in Figure 2. Figure 1 and Figure 2 The power semiconductor device includes at least one cellular structure 01, and the cellular structure 01 includes:

[0051] The first semiconductor body 10 includes a first surface and a second surface opposite to each other; the first semiconductor body 10 is used to form a depletion-mode transistor;

[0052] A second semiconductor body 20 is located on a first surface of the first semiconductor body 10. The second semiconductor body 20 is used to form an enhancement-mode transistor. The depletion-mode transistor formed by the first semiconductor body 10 and the enhancement-mode transistor formed by the second semiconductor body 20 are connected in series. The material of the first semiconductor body 10 is different from that of the second semiconductor body 20.

[0053] a third semiconductor body 30 located on a side of the second semiconductor body 20 away from the first semiconductor body 10 and electrically isolated from the second semiconductor body 20; the bandgap width of the material of the third semiconductor body 30 is lower than the bandgap width of the material of the second semiconductor body 20; wherein the third semiconductor body 30 includes a first semiconductor layer 31, a third semiconductor layer 33, and a second semiconductor layer 32 located between the first semiconductor layer 31 and the third semiconductor layer 33; the second semiconductor layer 32 has a different conductivity type from the first semiconductor layer 31 and the third semiconductor layer 33; and the first semiconductor layer 31 is used to serve as a gate G of the enhancement-mode transistor;

[0054] A first electrode 1 electrically connected to the second semiconductor body 20 , the first semiconductor body 10 and the third semiconductor layer 33 ;

[0055] The second electrode 2 is located on the second surface.

[0056] Specifically, the first semiconductor body 10 is used to form a first transistor 101. The first transistor 101 is a depletion-mode transistor in a normally-on state. The second semiconductor body 20 is used to form a second transistor 201. The second transistor 201 is an enhancement-mode transistor in a normally-off state. The gate voltage can control the conduction of the second transistor 201. The first transistor 101 and the second transistor 201 are connected in series. Therefore, the conduction and disconnection of the entire power semiconductor device are controlled by the second transistor 201 formed by the second semiconductor body 20.

[0057] A third semiconductor body 30 is arranged on a side of the second semiconductor body 20 away from the first semiconductor body 10. The third semiconductor body 30 includes a first semiconductor layer 31, a third semiconductor layer 33, and a second semiconductor layer 32 located between the first semiconductor layer 31 and the third semiconductor layer 33. The second semiconductor layer 32 has a different conductivity type from the first semiconductor layer 31 and the third semiconductor layer 33, so that a PN junction is formed between the first semiconductor layer 31 and the second semiconductor layer 32, and a PN junction is formed between the third semiconductor layer 33 and the second semiconductor layer 32. The first semiconductor layer 31 is used as the gate G of the enhancement-mode transistor (the second transistor 201), and is connected to a gate voltage that can control the conduction state of the enhancement-mode transistor. The third semiconductor layer 33 is electrically connected to the first electrode 1.

[0058] When the power semiconductor device is operating normally, the device's gate G (first semiconductor layer 31) is electrically isolated from the first electrode 1 by a PN junction. After the enhancement-mode transistor formed by the second semiconductor body 20 is controlled to conduct, the depletion-mode transistor formed by the first semiconductor body 10 and the enhancement-mode transistor formed by the second semiconductor body 20 conduct electricity between the first electrode 1 and the second electrode 2. The depletion-mode transistor formed by the first semiconductor body 10 and the enhancement-mode transistor formed by the second semiconductor body 20 jointly divide the voltage applied between the first electrode 1 and the second electrode 2, thereby improving the withstand voltage of the power semiconductor device. In other words, by cascading the enhancement-mode transistor formed by the second semiconductor body 20 and the depletion-mode transistor formed by the first semiconductor body 10, the depletion-mode transistor formed by the first semiconductor body 10 can be utilized to improve the withstand voltage of the entire power semiconductor device. Compared to forming the first semiconductor body 10 as an enhancement-mode transistor, the embodiment of the present invention forms the first semiconductor body 10 as a depletion-mode transistor, thereby reducing the resistance of the entire power semiconductor device. The first electrode 1 can be a source electrode S, and the second electrode 2 can be a drain electrode D; alternatively, the first electrode 1 can be a drain electrode D, and the second electrode 2 can be a source electrode S. Figure 1 In the structure shown, the first electrode 1 is the source S, and the second electrode 2 is the drain D.

[0059] When the power semiconductor device experiences overcurrent, short circuit, or overtemperature, the surface of the second semiconductor body 20 becomes severely heated, and the PN junction in the third semiconductor body 30 intrinsically fails, clamping the gate voltage on the first semiconductor layer 31 to the voltage of the first electrode 1, thereby forcing the device to shut down. At this time, because the bandgap width of the material of the second semiconductor body 20 is higher than the bandgap width of the material of the third semiconductor body 30, the PN junction in the second semiconductor body 20 retains normal function and maintains its blocking capability, preventing device damage due to overtemperature, achieving rapid overtemperature protection for the power semiconductor device and improving the robustness of the power semiconductor device. In addition, the first semiconductor layer 31 and the third semiconductor layer 33 simultaneously provide additional gate-source capacitance for the device, which results in a lower voltage drop across the gate G and the first electrode 1 when crosstalk current arrives, thereby preventing the device from being accidentally turned on due to crosstalk, achieving short-circuit protection for the power semiconductor device in high-frequency applications, and thus improving the reliability of the power semiconductor device.

[0060] The above is the core invention of the present invention. The structure of the power semiconductor device will be described in detail below with reference to the accompanying drawings.

[0061] refer to Figure 1 The first semiconductor body 10 can be formed by a single epitaxial growth or multiple epitaxial growths. That is, the first semiconductor body 10 can be a single first semiconductor epitaxial layer 12 or a stacked structure formed by multiple first semiconductor epitaxial layers 12. The first semiconductor body 10 can also include a substrate 11, that is, the first semiconductor body 10 includes the substrate 11 and at least one first semiconductor epitaxial layer 12 formed on one side of the substrate 11. The material of the substrate 11 is the same as that of the first semiconductor epitaxial layer 12.

[0062] When the first semiconductor body 10 includes a substrate 11 and a first semiconductor epitaxial layer 12 , the second surface is a surface of the substrate 11 away from the first semiconductor epitaxial layer 12 , and the first surface is a surface of the first semiconductor epitaxial layer 12 farthest from the substrate 11 away from the substrate 11 . Figure 1 The first semiconductor body 10 shown includes a substrate 11 and a first semiconductor epitaxial layer 12 located on one side of the substrate 11. The first surface is the surface of the first semiconductor epitaxial layer 12 facing away from the substrate 11, and the second surface is the surface of the substrate 11 facing away from the first semiconductor epitaxial layer 12. The second semiconductor body 20 is disposed on the first surface of the first semiconductor body 10. The second semiconductor body 20 can be formed by a single epitaxial growth process or multiple epitaxial growth processes. That is, the second semiconductor body 20 can include a single second semiconductor epitaxial layer or a stacked structure formed by multiple second semiconductor epitaxial layers.

[0063] Based on the above embodiments, Figure 1Optionally, the first semiconductor body 10 includes a first ohmic contact region 121 and a second ohmic contact region 122 of different conductivity types, both of which are located on the first surface, and the first ohmic contact region 121 and the second ohmic contact region 122 are spaced apart; the first semiconductor body 10 also includes a buried layer 123, located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 close to the second surface; wherein the buried layer 123 and the second ohmic contact region 122 have the same conductivity type as the second semiconductor layer 32; the second ohmic contact region 122 has the same conductivity type as the first semiconductor layer 31 and the third semiconductor layer 32; the first transistor 101 formed by the first semiconductor body 10 is a depletion-type junction field-effect transistor (JFET).

[0064] Specifically, the first semiconductor epitaxial layer 12 includes a first ohmic contact region 121 and a second ohmic contact region 122 of different conductivity types, and a buried layer 123 of the same conductivity type as the second ohmic contact region 122. The buried layer 123 is located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 that is closer to the substrate 11. The conductivity type of the first ohmic contact region 121 is the same as that of the first semiconductor epitaxial layer 12, both being the first conductivity type. The doping concentration of the first conductivity type ions in the first ohmic contact region 121 is greater than the doping concentration of the first conductivity type ions in the first semiconductor epitaxial layer 12. The conductivity type of the second ohmic contact region 122 is the second conductivity type. Both the first ohmic contact region 121 and the second ohmic contact region 122 are heavily doped regions. The second ohmic contact region 122 and the buried layer 123 can be formed by implanting second conductive type ions into the first semiconductor epitaxial layer 12 , and the doping concentration of the second conductive type ions in the second ohmic contact region 122 can be equal to or different from the doping concentration of the second conductive type ions in the buried layer 123 .

[0065] The orthographic projection of the first ohmic contact region 121 on the second surface is located within the orthographic projection of the buried layer 123 on the second surface, and the first ohmic contact region 121 extends from the boundary of the first surface toward the second ohmic contact region 122. A portion of the orthographic projection of the second ohmic contact region 122 on the second surface overlaps with the orthographic projection of the buried layer 123 on the second surface, while a portion of the orthographic projection of the second ohmic contact region 122 on the second surface does not overlap with the orthographic projection of the buried layer 123 on the second surface. The region outside the buried layer 123, the first ohmic contact region 121, and the second ohmic contact region 122 in the first semiconductor epitaxial layer 12 constitutes a drift region. The width between the buried layer 123 and the second ohmic contact region 122 is sufficient to ensure that the channel is not pinched off by the depletion region after a depletion region is formed between the buried layer 123 and the drift region, and between the second ohmic contact region 122 and the drift region, thereby allowing current to flow between the second electrode 2 and the first ohmic contact region 121. The first ohmic contact region 121 is configured to be electrically connected to the second semiconductor body 20 , so as to achieve a series connection of an enhancement mode transistor formed with the second semiconductor body 20 .

[0066] The first conductivity type may be N-type, and the second conductivity type may be P-type, that is, the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type. Alternatively, the first conductivity type may be P-type, and the second conductivity type may be N-type, that is, the conductivity type of the first ohmic contact region 121 is P-type, and the conductivity type of the second ohmic contact region 122 is N-type. Figure 1 In the structure shown, the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type. The first electrode 1 is a source electrode S, and the second electrode 2 is a drain electrode D.

[0067] Based on the above embodiments, Figure 1 Optionally, the second semiconductor body 20 includes a third ohmic contact region 21 and a fourth ohmic contact region 22, which are spaced apart on the surface of the second semiconductor body 20 away from the first semiconductor body 10; the conductivity type of the third ohmic contact region 21 and the fourth ohmic contact region 22 are different from the conductivity type of the second semiconductor body 20; wherein the second transistor 201 formed by the second semiconductor body 20 is an enhancement-type metal oxide semiconductor field effect transistor (MOSFET).

[0068] Specifically, the third ohmic contact region 21 and the fourth ohmic contact region 22 can be formed by ion implantation on the surface of the second semiconductor body 20 on a side away from the first semiconductor body 10. The third ohmic contact region 21 and the fourth ohmic contact region 22 have the same conductivity type. The channel region of the enhancement-mode transistor formed by the second semiconductor body 20 is located between the third ohmic contact region 21 and the fourth ohmic contact region 22. The orthographic projection of the first semiconductor layer 31 on the second semiconductor body 20 covers the channel region of the enhancement-mode transistor. The first semiconductor layer 31 serves as the gate G of the enhancement-mode transistor.

[0069] In the embodiment of the present invention, the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode MOSFET. The conductivity type of the third ohmic contact region 21 is the same as the conductivity type of the first ohmic contact region 121. The third ohmic contact region 21 is electrically connected to the first ohmic contact region 121 via the conductive structure 40, thereby achieving a series connection between the depletion-mode JFET formed by the first semiconductor body 10 and the enhancement-mode MOSFET formed by the second semiconductor body 20.

[0070] Furthermore, if the conductivity type of the first ohmic contact region 121 is N-type, the conductivity type of the third ohmic contact region 21 and the fourth ohmic contact region 22 are both N-type, the conductivity type of the second semiconductor body 20 is set to P-type, and the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode N-type MOSFET; the third ohmic contact region 21 is used to serve as the source contact region of the second transistor 201, and the fourth ohmic contact region 22 is used to serve as the drain contact region of the second transistor 201. The conductive structure 40 is made of a metal material. Using a metal conductive structure 40 to electrically connect the first semiconductor body 10 and the second semiconductor body 20 avoids the problem of increased conduction loss caused by the heterojunction barrier, as well as the problem of increased leakage or reduced breakdown voltage caused by lattice mismatch.

[0071] Based on the above embodiment, optionally, the material of the first semiconductor body 10 includes SiC, and the material of the second semiconductor body 20 includes GaN.

[0072] Specifically, the first transistor 101 formed by the first semiconductor body 10 is a depletion-mode SiC JFET; the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode GaN MOSFET. The power semiconductor device then comprises a cascaded high-voltage SiC JFET and a low-voltage GaN MOSFET. When the power semiconductor device is in the on state, current flows from the drain D through the SiC JFET channel and the GaN MOSFET channel to the source S. When the device is in the blocking state, the SiC JFET carries the majority of the voltage, while the GaN MOSFET carries a small portion of the voltage.

[0073] The technical solution provided by the embodiment of the present invention replaces the SiC MOSFET structure in the related art with a GaN MOSFET, thereby avoiding the problem of excessively high interface state density of the SiC MOSFET, improving the channel mobility, and reducing the specific on-resistance of the device; moreover, replacing the SiC MOSFET structure in the related art with a GaN MOSFET can also avoid reliability issues caused by excessive tunneling current between the SiC and the gate oxide layer (SiO2 layer).

[0074] When the power semiconductor device is turned on, the reference Figure 1 , and combined with Figure 3 , current The current flows from the drain D (second electrode 2) of the power semiconductor device through the drift region in the first semiconductor body 10 to the first ohmic contact region 121, and then flows through the interconnect metal to the third ohmic contact region 21, and then through the GaN MOSFET channel to the fourth ohmic contact region 22, and finally flows out from the source S (first electrode 1) of the power semiconductor device. DS The current does not need to pass through the heterojunction in its path, so the influence of the heterojunction barrier on the conduction characteristics can be completely avoided.

[0075] When the power semiconductor device is reverse blocked, the reference Figure 1 , and combined with Figure 4 The PN junctions formed by the P-type buried layer 123 and the P-type second ohmic contact region 122, respectively, and the N-type drift region 124 are in a reverse biased state, widening the depletion region. The potential of the device drain D will primarily fall within the depletion region, and the SiC JFET portion will therefore bear the majority of the voltage. Furthermore, because the second ohmic contact region 122 is electrically connected to the first electrode 1, the breakdown current flows through the second ohmic contact region 122 and the first electrode 1, and does not pass through the second semiconductor body 20. Consequently, the lattice mismatch between the second semiconductor body 20 and the first semiconductor body 10 does not affect the blocking characteristics of the device.

[0076] Based on the above embodiments, optionally, in the third semiconductor body 30 , the direction (first direction X) from the first semiconductor layer 31 to the third semiconductor layer 33 is parallel to the first surface, and the third semiconductor layer 33 is closer to the first electrode 1 than the first semiconductor layer 31 .

[0077] Specifically, the conductivity type of the first semiconductor layer 31 and the conductivity type of the third semiconductor are the same as the conductivity type of the first ohmic contact region 121 , and the conductivity type of the second semiconductor layer 32 is the same as the conductivity type of the second ohmic contact region 122 . Figure 1In the structure shown, the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type; the conductivity type of the first semiconductor layer 31 and the third semiconductor are both N-type, and the conductivity type of the second semiconductor is P-type.

[0078] refer to Figure 1 , and combined with Figure 5 The third semiconductor body 30 forms a lateral NPN structure, i.e., two reverse-directed PN diodes. When the power semiconductor device is operating normally, the PN diode formed between the first semiconductor layer 31 and the second semiconductor layer 32 is reverse-biased, and the gate G of the power semiconductor device is electrically isolated from the first electrode 1 by the PN junction formed between the first semiconductor layer 31 and the second semiconductor layer 32. When the device experiences overcurrent, short circuit, or overtemperature, the surface of the second semiconductor body 20 becomes severely heated, and the PN junction in the third semiconductor body 30 intrinsically fails, clamping the gate voltage on the first semiconductor layer 31 to the voltage of the first electrode 1, thereby forcing the device to shut down. At this time, because the band gap width of the material of the second semiconductor body 20 is higher than the band gap width of the material of the third semiconductor body 30, the PN junction in the second semiconductor body 20 retains normal function and maintains its blocking capability, preventing device damage due to overheating and achieving rapid overtemperature protection for the power semiconductor device. The material of the second semiconductor body 20 includes, but is not limited to, GaN, and the material of the third semiconductor body 30 includes, but is not limited to, polycrystalline silicon.

[0079] In addition, in the related art, when power MOSFET is used in high-frequency scenarios, such as in bridge circuits, since the upper bridge transistor is turned on in a very short time, the voltage drop at the switch point (the point where the upper bridge transistor is electrically connected to the lower bridge transistor) changes rapidly during the turn-on process. This voltage change will be reflected in the Miller capacitance of the lower bridge transistor. The charge and discharge current will form a potential difference in the peripheral drive circuit, causing the lower bridge transistor that was originally turned off to be turned on by mistake. At this time, the upper bridge transistor has been turned on, and eventually the voltage terminal VDD to the ground terminal GND is short-circuited, and the device is burned.

[0080] refer to Figure 1 , and combined with Figure 6 In the embodiment of the present invention, the NPN structure formed by the first semiconductor layer 31, the second semiconductor layer 32 and the third semiconductor layer 33 can be equivalent to a capacitor , and the NPN structure is equivalent to a capacitor and gate-source capacitance Parallel connection, that is, the NPN structure is equivalent to a capacitor Provides additional gate-source capacitance to the device. Figure 7 ,Will Figure 1 The power semiconductor device shown is applied to the lower bridge transistor in the half-bridge circuit. Since the NPN structure is equivalent to a capacitor and gate-source capacitance The parallel connection makes the power semiconductor device form a lower voltage drop across the gate G and source S when the crosstalk current arrives, thereby preventing the power semiconductor device from being turned on by mistake due to crosstalk, achieving short-circuit protection for the power semiconductor device in high-frequency applications, and thus improving the reliability of the power semiconductor device. is the capacitance formed between the gate G and the source S, is the capacitance formed between the first semiconductor layer 31 and the third semiconductor layer 33, and the capacitance is the capacitance formed between the drain D and the source S; the resistance is the equivalent resistance of the first semiconductor layer 31, the resistor R is the external gate-source resistance, and the inductor is the equivalent inductance and resistance of the circuit in the peripheral drive circuit is the external gate resistor, the current Miller capacitance The crosstalk current formed by charging and discharging, is the driving gate voltage.

[0081] Based on the above embodiments, Figure 1 Optionally, the conductive structure 40 and the first electrode 1 are located on opposite sides of the second semiconductor body 20, and the first ohmic contact region 121 and the second ohmic contact region 122 of the second semiconductor body 20 are exposed; wherein, one end of the conductive structure 40 is electrically connected to the exposed first ohmic contact region 121, and the other end of the conductive structure 40 is electrically connected to the third ohmic contact region 21; the first electrode 1 is electrically connected to the exposed second ohmic contact region 122, the fourth ohmic contact region 22 and the third semiconductor layer 33.

[0082] Based on the above embodiment, optionally, the cellular structure 01 further includes:

[0083] a first insulating layer 51 , the first insulating layer 51 being located between the conductive structure 40 and a sidewall of the second semiconductor body 20 ;

[0084] The second insulating layer 52 is located between the first electrode 1 and the sidewall of the second semiconductor body 20 .

[0085] Specifically, the second semiconductor body 20 covers a portion of the first surface of the first semiconductor body 10, exposing a portion of the first ohmic contact region 121 and a portion of the second ohmic contact region 122. This facilitates electrical connection between the conductive structure 40 and the first ohmic contact region 121, and facilitates electrical connection between the first gate G and the second contact region. The exposed first ohmic contact region 121 and the exposed second ohmic contact region 122 are located on opposite sides of the second semiconductor body 20, and the conductive structure 40 and the first electrode 1 are located on opposite sides of the second semiconductor body 20. A first insulating layer 51 is disposed between the sidewalls of the conductive structure 40 and the second semiconductor body 20 to prevent electrical connection between the conductive structure 40 and the sidewalls of the second semiconductor body 20. A second insulating layer 52 is disposed between the first electrode 1 and the other sidewall of the second semiconductor body 20 to prevent electrical connection between the first electrode 1 and the sidewalls of the second semiconductor body 20. The material of the first insulating layer 51 includes, but is not limited to, silicon oxide, and the material of the second insulating layer 52 includes, but is not limited to, silicon oxide. The first insulating layer 51 and the second insulating layer 52 can be formed simultaneously. The materials of the first insulating layer 51 and the second insulating layer 52 can also be high-K dielectric materials, such as 、 or .

[0086] Furthermore, the cell structure 01 further includes a third insulating layer 53, which is located between the first semiconductor body 10 and the second semiconductor body 20 to electrically isolate the third semiconductor body 30 from the second semiconductor body 20; the third insulating layer 53 can be understood as the gate insulating layer of the second transistor 201. The material of the third insulating layer 53 includes but is not limited to silicon oxide. The material of the third insulating layer 53 can also be a high-K dielectric material, such as 、 or .

[0087] Based on the above embodiment, optionally, the cellular structure 01 further includes:

[0088] a first ohmic contact layer 61 located on a surface of the first ohmic contact region 121 away from the second surface, wherein the conductive structure 40 is electrically connected to the first ohmic contact region 121 via the first ohmic contact layer 61, thereby reducing contact resistance between the conductive structure 40 and the first ohmic contact region 121;

[0089] and / or, the second ohmic contact layer 62 is located on a surface of the second ohmic contact region 122 away from the second surface, and the first electrode 1 is electrically connected to the second ohmic contact region 122 through the second ohmic contact layer 62, thereby reducing the contact resistance between the first electrode 1 and the second ohmic contact region 122;

[0090] and / or, a third ohmic contact layer 63 is located on a portion of the surface of the third ohmic contact region 21 , and the conductive structure 40 is electrically connected to the third ohmic contact region 21 through the third ohmic contact layer 63 , thereby reducing the contact resistance between the conductive structure 40 and the third ohmic contact region 21 ;

[0091] And / or, the fourth ohmic contact layer 64 is located on a portion of the surface of the fourth ohmic contact area 22 , and the first electrode 1 is electrically connected to the fourth ohmic contact area 22 through the fourth ohmic contact layer 64 , thereby reducing the contact resistance between the first electrode 1 and the fourth ohmic contact area 22 .

[0092] Based on the above embodiment, the cell structure 01 optionally further includes: a fourth insulating layer 54 located on a side of the third semiconductor body 30 away from the first semiconductor body 10, a side of the conductive structure 40 away from the first semiconductor body 10, and between the third semiconductor body 30 and the conductive structure 40; the first electrode 1 is also located on a surface of the fourth insulating layer 54 away from the first semiconductor body 10, and extends along the sidewalls of the fourth insulating layer 54, the sidewalls of the third semiconductor body 30, and the sidewalls of the second semiconductor body 20 toward the second ohmic contact region 122. The fourth insulating layer 54 serves as an interlayer dielectric layer to electrically isolate the first electrode 1 from the third semiconductor body 30, and from the conductive structure 40. The material of the fourth insulating layer 54 includes, but is not limited to, silicon oxide.

[0093] Based on the above embodiments, Figure 1 Optionally, the power semiconductor device includes at least two cellular structures 01, and the two adjacent cellular structures 01 are mirror-symmetrical in a first direction X. The first direction X and the second direction Y are perpendicular to each other, wherein the second direction Y is a direction from the first surface to the second surface.

[0094] Two adjacent cellular structures 01 share the same first electrode 1 ; two adjacent cellular structures 01 share the same second electrode 2 .

[0095] Furthermore, the two adjacent cellular structures 01 are prepared and formed synchronously, that is, the same membrane layers in the two adjacent cellular structures 01 are prepared and formed synchronously.

[0096] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A power semiconductor device, characterized in that: comprising at least one cellular structure, the cellular structure comprising: A first semiconductor body comprising a first surface and a second surface opposite to each other; the first semiconductor body is used to form a depletion-mode transistor; a second semiconductor body located on a first surface of the first semiconductor body; the second semiconductor body is used to form an enhancement-mode transistor, the depletion-mode transistor formed by the first semiconductor body and the enhancement-mode transistor formed by the second semiconductor body being connected in series; wherein the material of the first semiconductor body is different from the material of the second semiconductor body; a third semiconductor body, located on a side of the second semiconductor body away from the first semiconductor body and electrically isolated from the second semiconductor body; a band gap width of a material of the third semiconductor body is lower than a band gap width of a material of the second semiconductor body; wherein the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer having a different conductivity type from the first semiconductor layer and the third semiconductor layer, and the first semiconductor layer being used as a gate of the enhancement-mode transistor; a first electrode electrically connected to the second semiconductor body, the first semiconductor body and the third semiconductor layer; The second electrode is located on the second surface.

2. The power semiconductor device according to claim 1, wherein: The material of the first semiconductor body includes SiC, the material of the second semiconductor body includes GaN; and the material of the third semiconductor body includes polysilicon.

3. The power semiconductor device according to claim 1, wherein: The first semiconductor body includes a first ohmic contact region and a second ohmic contact region of different conductivity types, both of which are located on the first surface, and the first ohmic contact region and the second ohmic contact region are spaced apart; The first semiconductor body further includes a buried layer located on a side of the first ohmic contact region and the second ohmic contact region close to the second surface; The buried layer and the second ohmic contact region have the same conductivity type as the second semiconductor layer; and the depletion-type transistor formed by the first semiconductor body is a depletion-type junction field-effect transistor.

4. The power semiconductor device according to claim 3, characterized in that The orthographic projection of the first ohmic contact region on the second surface is located in the orthographic projection of the buried layer on the second surface, and the first ohmic contact region extends from a boundary of the first surface to the second ohmic contact region; A portion of the orthographic projection of the second ohmic contact region on the second surface overlaps with the orthographic projection of the buried layer on the second surface.

5. The power semiconductor device according to claim 3, wherein: The second semiconductor body includes a third ohmic contact region and a fourth ohmic contact region, which are spaced apart on a surface of the second semiconductor body away from the first semiconductor body; the conductivity type of the third ohmic contact region and the fourth ohmic contact region are different from the conductivity type of the second semiconductor body; The enhancement transistor formed by the second semiconductor body is a metal oxide semiconductor field effect transistor, the channel region of the enhancement transistor is located between the third ohmic contact region and the fourth ohmic contact region, and the orthographic projection of the first semiconductor layer on the second semiconductor body covers the channel region of the enhancement transistor.

6. The power semiconductor device according to claim 5, characterized in that In the third semiconductor body, the direction from the first semiconductor layer to the third semiconductor layer is parallel to the first surface, and the third semiconductor layer is closer to the first electrode than the first semiconductor layer; The cell structure further includes a conductive structure; the conductive structure and the first electrode are located on opposite sides of the second semiconductor body; a first ohmic contact region and a second ohmic contact region of the exposed portion of the second semiconductor body; One end of the conductive structure is electrically connected to the exposed first ohmic contact area, and the other end of the conductive structure is electrically connected to the third ohmic contact area; the first electrode is electrically connected to the exposed second ohmic contact area, the fourth ohmic contact area and the third semiconductor layer.

7. The power semiconductor device according to claim 6, characterized in that The cellular structure further includes: a first insulating layer, the first insulating layer being located between the conductive structure and a sidewall of the second semiconductor body; a second insulating layer, the second insulating layer being located between the first electrode and a sidewall of the second semiconductor body; A third insulating layer is located between the first semiconductor body and the second semiconductor body.

8. The power semiconductor device according to claim 6, wherein: The cellular structure further includes: a first ohmic contact layer, located on a surface of the first ohmic contact region away from the second surface, the conductive structure being electrically connected to the first ohmic contact region through the first ohmic contact layer; and / or, a second ohmic contact layer located on a surface of the second ohmic contact region away from the second surface, the first electrode being electrically connected to the second ohmic contact region through the second ohmic contact layer; and / or a third ohmic contact layer located on a surface of a portion of the third ohmic contact region, wherein the conductive structure is electrically connected to the third ohmic contact region through the third ohmic contact layer; And / or, a fourth ohmic contact layer is located on a surface of a portion of the fourth ohmic contact region, and the first electrode is electrically connected to the fourth ohmic contact region through the fourth ohmic contact layer.

9. The power semiconductor device according to claim 6, wherein: The cellular structure further includes: a fourth insulating layer, located on a side of the third semiconductor body away from the first semiconductor body, a side of the conductive structure away from the first semiconductor body, and between the third semiconductor body and the conductive structure; The first electrode is also located on a surface of the fourth insulating layer away from the first semiconductor body, and extends toward the second ohmic contact region along sidewalls of the fourth insulating layer, the third semiconductor body, and the second semiconductor body.

10. The power semiconductor device according to claim 1, wherein: It comprises at least two of the cellular structures, and the two adjacent cellular structures are mirror-symmetrical in a first direction; the first direction is parallel to the first surface.

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