Integrated circuit comprising a power gating cell

Abstract

An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a supply voltage from a first supply line and output a first drive voltage to a first virtual supply line, and a logic circuit electrically connected to the first virtual supply line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first supply line and the first virtual supply line.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0043308, filed with the Korean Intellectual Property Office on April 12, 2019, and Korean Patent Application No. 10-2020-0023012, filed with the Korean Intellectual Property Office on February 25, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to an integrated circuit, and more specifically, to an integrated circuit including a power gating unit. Background Technology

[0004] In integrated circuit design, power gating circuits are used to reduce power consumption. Power gating circuits reduce power consumption by cutting off current flowing to unused logic blocks in the circuit. Power gating circuits can also reduce leakage current by blocking power supply to logic blocks in sleep mode. Power gating circuits can also provide a hold mode, in which a hold voltage lower than the operating voltage in power-on mode is provided to maintain the internal state or register value of the logic block. Summary of the Invention

[0005] At least one embodiment of the present invention relates to an integrated circuit including a power gating circuit, a method for designing the integrated circuit, and a computing system for designing the integrated circuit.

[0006] According to an exemplary embodiment of the present invention, an integrated circuit is provided, comprising: a power gating circuit configured to receive a power supply voltage from a first power line and output a first drive voltage to a first dummy power line; and logic circuitry electrically connected to the first dummy power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first dummy power line.

[0007] According to an exemplary embodiment of the present invention, an integrated circuit is provided, the integrated circuit including a first power gating unit configured to receive a power supply voltage from a first power line and provide a first drive voltage to a logic unit via a first dummy power line. The first power gating unit includes a first P-type metal-oxide-semiconductor (PMOS) region having a first p-type transistor connected between the first power line and the first dummy power line, a first N-type metal-oxide-semiconductor (NMOS) region having a first n-type transistor connected between the first power line and the first dummy power line, and a second NMOS region having a second n-type transistor connected between the first power line and the first dummy power line. The first PMOS region includes an n-well doped with n-type impurities and extending along a first direction.

[0008] According to an exemplary embodiment of the present invention, an integrated circuit is provided, the integrated circuit including a first power gating unit, the first power gating unit being configured to receive a ground voltage from a ground line and provide a drive voltage to logic cells via a virtual ground line. The first power gating unit includes a first NMOS region having an n-type transistor connected between the ground line and the virtual ground line, a first PMOS region having a first p-type transistor connected between the ground line and the virtual ground line, and a second PMOS region having a second p-type transistor connected between the ground line and the virtual ground line. The first PMOS region is formed in an n-well doped with n-type impurities and extends in a first direction. Attached Figure Description

[0009] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present invention.

[0011] Figure 2 This is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the concept of the present invention;

[0012] Figures 3A to 3D It shows the basis Figure 2 The operation of the power gating circuit provides a view of the voltage to the logic circuit.

[0013] Figure 4A This is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the concept of the present invention;

[0014] Figure 4B This is a view illustrating the voltage supplied to the logic circuit according to the operation of the power gating circuit, based on an exemplary embodiment of the present invention.

[0015] Figure 5 This is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the concept of the present invention;

[0016] Figure 6 This is a block diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present invention.

[0017] Figure 7 This is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the concept of the present invention;

[0018] Figure 8 This is a block diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present invention.

[0019] Figure 9 This is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the concept of the present invention;

[0020] Figure 10 This is a layout diagram illustrating an exemplary embodiment of the invention, including a head unit in a power gating circuit arranged in an integrated circuit.

[0021] Figure 11 This is a layout diagram illustrating an exemplary embodiment of the invention, including a tail unit in a power gating unit arranged in an integrated circuit;

[0022] Figure 12 This is a layout diagram illustrating an exemplary embodiment of the invention, including a head unit in a power gating circuit arranged in an integrated circuit.

[0023] Figure 13 This is a layout diagram illustrating an exemplary embodiment of the present invention, including a head unit and a tail unit in a power gating unit arranged in an integrated circuit;

[0024] Figure 14 This is a flowchart illustrating an exemplary embodiment of a method for manufacturing an integrated circuit according to the concept of the present invention; and

[0025] Figure 15 This is a block diagram illustrating an exemplary embodiment of a computing system including a memory for storing programs, according to a concept conceived in accordance with the present invention. Detailed Implementation

[0026] Figure 1 This is a block diagram illustrating an integrated circuit 10 including a power gating circuit 100, according to an exemplary embodiment of the present invention.

[0027] Reference Figure 1The integrated circuit 10 includes a logic circuit 200 and a power gating circuit 100 for providing power to the logic circuit 200. The logic circuit 200 is electrically connected to a first virtual power line VVDD and a second power line RGND, and receives power through the first virtual power line VVDD and the second power line RGND. According to an exemplary embodiment, the second power line RGND is a ground line, and the ground voltage GND is applied to the logic circuit 200 through the second power line RGND.

[0028] According to an exemplary embodiment of the present invention, integrated circuit 10 is a system-on-a-chip (SOC). For example, integrated circuit 10 may be an application processor, media processor, microprocessor, central processing unit (CPU), or similar device.

[0029] The power gating circuit 100 is electrically connected to a first virtual power line VVDD that provides the power supply voltage VDD. The power gating circuit 100 can control the first drive voltage supplied to the logic circuit 200 and the power mode of the logic circuit 200 by selectively connecting the first power line RVDD to the first virtual power line VVDD in response to the control signal IN.

[0030] For example, the power gating circuit 100 can supply the power supply voltage VDD to the logic circuit 200 by connecting the first power line RVDD to the first virtual power line VVDD in the power-on mode, and can provide the logic circuit 200 with a high holding voltage VR having a level lower than the power supply voltage VDD by connecting the first power line RVDD to the first virtual power line VVDD in the holding mode. On the other hand, the power gating circuit 100 can make the first virtual power line VVDD float by blocking the first power line RVDD from the first virtual power line VVDD in the power-off mode. For example, the power gating circuit 100 can disconnect the first power line RVDD from the first virtual power line VVDD to make the first virtual power line VVDD float.

[0031] Integrated circuit 10 may also include power management circuitry, and a control signal IN may be provided from the power management circuitry external to power gate circuitry 100. The power management circuitry may apply the control signal IN to power gate circuitry 100, causing the voltage level supplied to logic circuitry 200 to vary according to the power mode.

[0032] Logic circuit 200 can selectively receive power via a first virtual power line VVDD. A first drive voltage having a level that varies according to the power supply mode can be provided to logic circuit 200. For example, logic circuit 200 can receive the power supply voltage VDD in a power-on mode and a high holding voltage VR in a holding mode, and power can be blocked in a power-off mode. Figure 1In the diagram, only one high holding voltage VR is shown. However, the integrated circuit 10 conceived according to the present invention may include multiple holding modes and may provide high holding voltages with different voltage levels to the logic circuit 200.

[0033] The logic circuit 200 may include any circuit electrically connected to the first virtual power line VVDD. For example, the logic circuit 200 may be implemented by at least one of an inverter, NAND gate, AND gate, NOR gate, OR gate, XOR gate, XOR gate, multiplexer, adder, latch, or flip-flop.

[0034] Figure 2 This is a circuit diagram illustrating an integrated circuit 10 including a power gating circuit 10, according to an exemplary embodiment of the present invention.

[0035] Reference Figure 2 The power gating circuit 100 includes a head transistor unit 110 connected between a first power line RVDD and a first virtual power line VVDD, and a control circuit 120 for providing first to third switching signals CS_P, CS_N1, and CS_N2 to the head transistor unit 110. The control circuit 120 can generate the first to third switching signals CS_P, CS_N1, and CS_N2 in response to a control signal IN. Figure 2 Unlike the example shown, the power gating circuit 100 according to the alternative embodiment does not include the control circuit 120 and the head transistor unit 110, but instead receives the first to third switching signals CS_P, CS_N1 and CS_N2 directly from a source located outside the power gating circuit 100.

[0036] In an exemplary embodiment, the head transistor unit 110 includes a p-type transistor PT, a first n-type transistor NT1, and a second n-type transistor NT2 connected in parallel between the first power line RVDD and the first virtual power line VVDD. Figure 2 The p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2 can be shown as equivalent transistors, and each of the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2 may include multiple transistors.

[0037] The first n-type transistor NT1 has a first threshold voltage VTH_N1, and the second n-type transistor NT2 has a second threshold voltage VTH_N2. According to an exemplary embodiment, the first threshold voltage VTH_N1 is less than the second threshold voltage VTH_N2.

[0038] Control circuit 120 can selectively turn on the transistors included in head transistor unit 110 in response to control signal IN. According to an exemplary embodiment, control signal IN is a 2-bit signal. Control circuit 120 can generate a first switching signal CS_P for switching p-type transistor PT, a second switching signal CS_N1 for switching first n-type transistor NT1, and a third switching signal CS_N2 for switching second n-type transistor NT2 in response to control signal IN. For example, control circuit can apply the first switching signal CS_P to the gate terminal of p-type transistor PT, apply the second switching signal CS_N1 to the gate terminal of first n-type transistor NT1, and apply the third switching signal CS_N2 to the gate terminal of second n-type transistor NT2.

[0039] Based on the operation of the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2 included in the head transistor unit 110, the voltage of the first virtual power line VVDD electrically connected to the logic circuit 200 and the power supply mode of the logic circuit 200 can be changed. According to an exemplary embodiment, the logic circuit 200 includes an inverter. Figure 2 The logic circuit shown is different; logic circuit 200 may include logic circuits other than inverters.

[0040] According to an exemplary embodiment of the present invention, the power gating circuit 100 can control the amplitude of the first drive voltage supplied to the logic circuit 200 by turning on a transistor selected from a p-type transistor PT, a first n-type transistor NT1, and a second n-type transistor NT2. Reference will be made below to... Figures 3A to 3D Provide a description of the power supply mode of logic circuit 200 and the magnitude of the voltage supplied to logic circuit 200.

[0041] Figures 3A to 3D It shows the basis Figure 2 The operation of the power supply gating circuit provides a view of the voltage for the logic circuit 200. Figures 3A to 3D These are views showing the operation of logic circuit 200 in power-on mode, first hold mode, second hold mode, and power-off mode, respectively.

[0042] Reference Figure 3AIn the power-on mode, the control circuit 120 generates first to third switching signals CS_P, CS_N1, and CS_N2 to turn on the p-type transistor PT, turn off the first n-type transistor NT1, and turn off the second n-type transistor NT2. For example, the control circuit 120 can generate a first switching signal CS_P at a logic low level, a second switching signal CS_N1 at a logic low level, and a third switching signal CS_N2 at a logic low level. Among the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2, only the p-type transistor PT is turned on, allowing current to flow through it, and the voltage level of the first virtual power line VVDD can be the same as the power supply voltage VDD of the first power line RVDD.

[0043] Reference Figure 3B In the first holding mode, the control circuit 120 generates first to third switching signals CS_P, CS_N1, and CS_N2 to turn on the first n-type transistor NT1, turn off the p-type transistor PT, and turn off the second n-type transistor NT2. For example, the control circuit 120 can generate a first switching signal CS_P at a logic high level, a second switching signal CS_N1 at a logic high level, and a third switching signal CS_N2 at a logic low level.

[0044] In the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2, only the first n-type transistor NT1 is turned on, allowing current to flow through it, and the voltage level of the first virtual power line VVDD can be the same as the level of the first high holding voltage VR1. When the first n-type transistor NT1 is turned on, due to the first threshold voltage VTH_N1 of the first n-type transistor NT1, the first virtual power line VVDD can have a first high holding voltage VR1 that is lower than the power supply voltage VDD of the first power line RVDD by the first threshold voltage VTH_N1.

[0045] Reference Figure 3C In the second holding mode, the control circuit 120 generates first to third switching signals CS_P, CS_N1, and CS_N2 to turn on the second n-type transistor NT2, turn off the p-type transistor PT, and turn off the first n-type transistor NT1. For example, the control circuit 120 can generate a first switching signal CS_P at a logic high level, a second switching signal CS_N1 at a logic low level, and a third switching signal CS_N2 at a logic high level.

[0046] In the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2, only the second n-type transistor NT2 is turned on, allowing current to flow through it and ensuring that the voltage level of the first dummy power line VVDD is the same as the level of the second high holding voltage VR2. When the second n-type transistor NT2 is turned on, due to the second threshold voltage VTH_N2 of the second n-type transistor NT2, the first dummy power line VVDD can have a second high holding voltage VR2 that is lower than the power supply voltage VDD of the first power line RVDD.

[0047] According to an exemplary embodiment, the second threshold voltage VTH_N2 is greater than the first threshold voltage VTH_N1. Therefore, the second high holding voltage VR2 can be at a level lower than the first high holding voltage VR1.

[0048] Reference Figure 3D In power-down mode, control circuit 120 generates first to third switching signals CS_P, CS_N1, and CS_N2 to turn off all p-type transistors PT, the first n-type transistor NT1, and the second n-type transistor NT2. For example, control circuit 120 can generate a first switching signal CS_P at a logic high level, a second switching signal CS_N1 at a logic low level, and a third switching signal CS_N2 at a logic low level. Since all p-type transistors PT, the first n-type transistor NT1, and the second n-type transistor NT2 are turned off, the first virtual power line VVDD can be blocked from the first power line RVDD and can be floated.

[0049] Reference Figures 3A to 3D According to an exemplary embodiment of the present invention, the power gating circuit 100 can control the amplitude of the voltage of the first virtual power line VVDD electrically connected to the logic circuit 200 according to the power mode. Therefore, the integrated circuit 10 can operate in various holding modes (e.g., a first holding mode and a second holding mode) other than the power-on mode and the power-off mode.

[0050] Figure 4A This is a circuit diagram illustrating an integrated circuit 10a including a power gating circuit 100a, according to an exemplary embodiment of the present invention. Figure 4B This is a view showing the voltage supplied to the logic circuit 200 according to the operation of the power gating circuit 100a in accordance with an exemplary embodiment of the present invention.

[0051] Reference Figure 4AThe integrated circuit 10a includes a logic circuit 200 and a power gating circuit 100a for supplying power to the logic circuit 200. The power gating circuit 100a can control the power mode of the logic circuit 200 in response to a control signal Ina, and can supply the logic circuit 200 with a voltage of one of various amplitudes.

[0052] The logic circuit 200 can be electrically connected to a first virtual power line VVDD and a second power line RGND, and can receive power through the first virtual power line VVDD and the second power line RGND. According to an exemplary embodiment, the second power line RGND is a ground line.

[0053] The power gating circuit 100a includes a head transistor unit 110a connected between a first power line RVDD and a first virtual power line VVDD, and a control circuit 120a for providing first to fourth switching signals CS_P, CS_N1, CS_N2, and CS_N3 to the head transistor unit 110a. The control circuit 120a can generate the first to fourth switching signals CS_P, CS_N1, CS_N2, and CS_N3 in response to a control signal INa.

[0054] The head transistor unit 110a includes a p-type transistor PT, a first n-type transistor NT1, a second n-type transistor NT2, and a third n-type transistor NT3 connected in parallel between the first power line RVDD and the first virtual power line VVDD. According to an exemplary embodiment, the third n-type transistor NT3 may include multiple transistors. Figure 4A In the diagram, the third n-type transistor NT3 can be shown as an equivalent transistor.

[0055] The third n-type transistor NT3 has a third threshold voltage VTH_N3. According to an exemplary embodiment, the first threshold voltage VTH_N1 is less than the second threshold voltage VTH_N2, and the second threshold voltage VTH_N2 is less than the third threshold voltage VTH_N3.

[0056] Control circuit 120a can selectively turn on the transistors included in head transistor unit 110a in response to control signal INa. According to an exemplary embodiment, control signal INa is a 2-bit signal. Control circuit 120a can generate a first switching signal CS_P for switching p-type transistor PT, a second switching signal CS_N1 for switching first n-type transistor NT1, a third switching signal CS_N2 for switching second n-type transistor NT2, and a fourth switching signal CS_N3 for switching third n-type transistor NT3 in response to control signal INa. The example of control signal INa being a 2-bit signal is merely an embodiment. The integrated circuit 10a conceived in this invention is not limited thereto, and control signal INa can vary.

[0057] Reference Figure 4A and Figure 4B Based on the operation of the p-type transistor PT, the first n-type transistor NT1, the second n-type transistor NT2 and the third n-type transistor NT3 included in the head transistor unit 110a, the voltage of the first virtual power line VVDD electrically connected to the logic circuit 200 and the power mode of the logic circuit 200 can be changed.

[0058] For example, in power-on mode, only the p-type transistor PT is turned on, while the first n-type transistor NT1, the second n-type transistor NT2, and the third n-type transistor NT3 are turned off. Therefore, the power supply voltage VDD can be applied to the first virtual power line VVDD.

[0059] In the first holding mode, only the first n-type transistor NT1 is turned on, while the p-type transistor PT, the second n-type transistor NT2, and the third n-type transistor NT3 are turned off. Therefore, a first high holding voltage VR1 can be applied to the first dummy power line VVDD. In an exemplary embodiment, the first high holding voltage VR1 is a first threshold voltage VTH_N1 lower than the power supply voltage VDD.

[0060] In the second holding mode, only the second n-type transistor NT2 is turned on, while the p-type transistor PT, the first n-type transistor NT1, and the third n-type transistor NT3 are turned off. Therefore, the second high holding voltage VR2 can be applied to the first dummy power line VVDD. In an exemplary embodiment, the second high holding voltage VR2 is lower than the power supply voltage VDD by a second threshold voltage VTH_N2.

[0061] In the third holding mode, only the third n-type transistor NT3 is turned on, while the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2 are turned off. Therefore, the third high holding voltage VR3 can be applied to the first virtual power line VVDD. In an exemplary embodiment, the third high holding voltage VR3 is a third threshold voltage VTH_N3 lower than the power supply voltage VDD. According to an exemplary embodiment, the first high holding voltage VR1 is greater than the second high holding voltage VR2, and the second high holding voltage VR2 is greater than the third high holding voltage VR3.

[0062] According to an exemplary embodiment, the logic circuit 200 does not operate in power-down mode. For example, when the logic circuit 200 is the main processor, it does not operate in power-down mode. When the control signal INa is a 2-bit signal, the power gating circuit 100A can electrically connect the first power line RVDD to the first virtual power line VVDD without floating the first virtual power line VVDD. That is, the power gating circuit 100A can turn on at least one of the p-type transistor PT and the first to third n-type transistors NT1 to NT3.

[0063] Figure 5 This is a circuit diagram illustrating an integrated circuit 10b including a power gating circuit 100b, according to an exemplary embodiment of the present invention.

[0064] Reference Figure 5 The integrated circuit 10b includes logic circuit 200 and a power gating circuit 100b for providing power to the logic circuit 200. The power gating circuit 100b can control the power mode of the logic circuit 200 in response to a control signal INb, and can provide the logic circuit 200 with a first drive voltage of one of various amplitudes.

[0065] The power gating circuit 100b includes a head transistor unit 110b connected between a first power line RVDD and a first virtual power line VVDD, and a control circuit 120b for providing the head transistor unit 110b with first to (n+1)th switching signals CS_P and CS_N1 to CS_Nn. The control circuit 120b can generate the first to (n+1)th switching signals CS_P and CS_N1 to CS_Nn in response to the control signal INb.

[0066] The head transistor unit 110b includes a p-type transistor PT and first to nth n-type transistors NT1 to NTn connected in parallel between the first power line RVDD and the first virtual power line VVDD. According to an exemplary embodiment, each of the p-type transistor PT and the first to nth n-type transistors NT1 to NTn may include multiple transistors. Figure 5 In the diagram, the p-type transistor PT and the first to nth n-type transistors NT1 to NTn can be shown as equivalent transistors. For example... Figure 5 As shown, n can be a natural number not less than 3.

[0067] In an exemplary embodiment, the first to the nth n-type transistors NT1 to NTn have different threshold voltage values. The nth n-type transistor NTn has an nth threshold voltage VTH_Nn. According to the exemplary embodiment, the first threshold voltage VTH_N1 is less than the second threshold voltage VTH_N2, and the second threshold voltage VTH_N2 is less than the nth threshold voltage VTH_Nn.

[0068] Control circuit 120b can selectively turn on the transistors included in head transistor unit 110b in response to control signal INb. According to an exemplary embodiment, control signal INb is a signal of not less than 3 bits. Control circuit 120b generates a first switching signal CS_P for switching p-type transistor PT, a second switching signal CS_N1 for switching first n-type transistor NT1, a third switching signal CS_N2 for switching second n-type transistor NT2, and a (n+1)th switching signal CS_Nn for switching nth n-type transistor NTn in response to control signal INb.

[0069] Based on the operation of the p-type transistor PT and the first to nth n-type transistors NT1 to NTn included in the head transistor unit 110b, the voltage of the first virtual power line VVDD electrically connected to the logic circuit 200 and the power supply mode of the logic circuit 200 can be changed. For example, in the power-on mode, only the p-type transistor PT is turned on, and the first to nth n-type transistors NT1 to NTn are turned off. Therefore, the power supply voltage VDD can be applied to the first virtual power line VVDD.

[0070] In the nth hold mode, only the nth n-type transistor NTn is turned on, and the p-type transistor PT and the first to (n-1)-type transistors NT1 to NTn-1 are turned off. Therefore, the nth highest hold voltage can be applied to the first dummy power line VVDD. In an exemplary embodiment, the nth highest hold voltage is smaller than the power supply voltage VDD than the nth threshold voltage VTH_Nn. According to an exemplary embodiment, the first high hold voltage VR1 ( Figure 3B ) and the second highest holding voltage VR2 ( Figure 3B It is greater than the nth highest holding voltage VRn.

[0071] The power supply gating circuit 100b of the integrated circuit 10b according to the present invention can be implemented as including n-type transistors having various numbers of different threshold voltages, and the logic circuit 200 can operate in various numbers of holding modes. That is, the amplitude of the voltage of the first virtual power line VVDD electrically connected to the logic circuit 200 can vary.

[0072] Figure 6 This is a block diagram illustrating an integrated circuit 10c including a power gating circuit 100c, according to an exemplary embodiment of the present invention.

[0073] Reference Figure 6The integrated circuit 10c includes a logic circuit 200 and a power gating circuit 100c for supplying power to the logic circuit 200. The logic circuit 200 can be electrically connected to a first power line RVDD and a second virtual power line VGND, and can receive power through the first power line RVDD and the second virtual power line VGND. For example, the power supply voltage VDD can be applied to the logic circuit 200 through the first power line RVDD.

[0074] The power gating circuit 100c can be electrically connected to the second power line RGND to provide ground voltage GND. The power gating circuit 100c can control the power mode of the logic circuit 200 by selectively connecting the second virtual power line VGND to the second power line RGND in response to the control signal INc. For example, the power gating circuit 100c can provide a second drive voltage of ground voltage GND to the logic circuit 200 by connecting the second power line RGND to the second virtual power line VGND in power-on mode, and can provide a low holding voltage VGR, having a higher level than ground voltage GND, as a second drive voltage to the logic circuit 200 by connecting the second power line RGND to the second virtual power line VGND in holding mode. On the other hand, the power gating circuit 100c can make the second virtual power line VGND float by blocking the second power line RGND from the second virtual power line VGND in power-off mode. For example, the power gating circuit 100c can make the second virtual power line VGND float by disconnecting the second virtual power line VGND from the second virtual power line VGND.

[0075] Logic circuit 200 can selectively receive power via the second virtual power line VGND. In this case, drive power with a level that varies according to the power mode can be supplied to logic circuit 200. For example, logic circuit 200 can receive ground voltage GND in power-on mode, and a low holding voltage VGR in holding mode, and power can be blocked in power-off mode. Figure 6 In the diagram, only one low holding voltage VGR is shown. However, the integrated circuit 10c conceived according to the present invention can include multiple holding modes and can provide low holding voltages at different levels to the logic circuit 200.

[0076] Figure 7 This is a circuit diagram illustrating an integrated circuit 10c including a power gating circuit 100c, according to an exemplary embodiment of the present invention.

[0077] Reference Figure 7The power gating circuit 100c includes a tail transistor unit 110c connected between the second power line RGND and the second virtual power line VGND, and a control circuit 120c for providing first to third switching signals CS_N, CS_P1, and CS_P2 to the tail transistor unit 110c. The control circuit 120c can generate the first to third switching signals CS_N, CS_P1, and CS_P2 in response to the control signal INc. Figure 7 Unlike the example shown, in an alternative embodiment, the power gating circuit 100c does not include the control circuit 120c and the tail transistor unit 110c, but instead receives the first to third switching signals CS_N, CS_P1 and CS_P2 from a source located outside the power gating circuit 100c.

[0078] The tail transistor unit 110c includes an n-type transistor NT, a first p-type transistor PT1, and a second p-type transistor PT2 connected in parallel between the second power line RGND and the second virtual power line VGND. Figure 7 In the diagram, the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2 can be shown as equivalent transistors.

[0079] A first p-type transistor PT1 has a first threshold voltage VTH_P1, and a second p-type transistor PT2 has a second threshold voltage VTH_P2. According to an exemplary embodiment, the first threshold voltage VTH_P1 and the second threshold voltage VTH_P2 are different from each other.

[0080] The control circuit 120c can selectively turn on the transistors included in the tail transistor unit 110c in response to the control signal INc. The control circuit 120c can generate a first switching signal CS_N for switching the n-type transistor NT, a second switching signal CS_P1 for switching the first p-type transistor PT1, and a third switching signal CS_P2 for switching the second p-type transistor PT2. For example, the control circuit 120c can apply the first switching signal CS_N to the gate terminal of the n-type transistor NT, apply the second switching signal CS_P1 to the gate terminal of the first p-type transistor PT1, and apply the third switching signal CS_P2 to the gate terminal of the second p-type transistor PT2.

[0081] Based on the operation of the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2 included in the tail transistor unit 110c, the second drive voltage and the power supply mode of the logic circuit 200, which are electrically connected to the second virtual power line VGND of the logic circuit 200, can be changed. For example, the logic circuit 200 can operate in one of the following modes: power-on mode, first holding mode, second holding mode, and power-off mode.

[0082] In the power-on mode, the control circuit 120c generates first to third switching signals CS_N, CS_P1, and CS_P2 to turn on the n-type transistor NT, turn off the first p-type transistor PT1, and turn off the second p-type transistor PT2. For example, the control circuit 120c can generate a first switching signal CS_N at a logic high level, a second switching signal CS_P1 at a logic high level, and a third switching signal CS_P2 at a logic high level. Among the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2, only the n-type transistor NT is turned on, allowing current to flow through it, and the second driving voltage of the second virtual power line VGND can be the same as the ground voltage GND of the second power line RGND.

[0083] In the first holding mode, the control circuit 120c can generate first to third switching signals CS_N, CS_P1, and CS_P2 to turn on the first p-type transistor PT1. For example, the control circuit 120c can generate a first switching signal CS_N at a logic low level, a second switching signal CS_P1 at a logic low level, and a third switching signal CS_P2 at a logic high level. Among the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2, only the first p-type transistor PT1 is turned on, allowing current to flow through it. Due to the first threshold voltage VTH_P1 of the first p-type transistor PT1, the second virtual power line VGND can have a first low holding voltage with an amplitude greater than the first threshold voltage VTH_P1 than the ground voltage GND.

[0084] In the second holding mode, the control circuit 120c generates first to third switching signals CS_N, CS_P1, and CS_P2 to turn on the second p-type transistor PT2, turn off the n-type transistor NT, and turn off the first p-type transistor PT1. For example, the control circuit 120c can generate a first switching signal CS_N at a logic low level, a second switching signal CS_P1 at a logic high level, and a third switching signal CS_P2 at a logic low level. Among the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2, only the second p-type transistor PT2 is turned on, allowing current to flow through it. Due to the second threshold voltage VTH_P2 of the second p-type transistor PT2, the second virtual power line VGND can have a second low holding voltage that is larger than the ground voltage GND by the magnitude of the second threshold voltage VTH_P2. According to an exemplary embodiment, the second threshold voltage VTH_P2 has a different value than the first threshold voltage VTH_P1.

[0085] In power-down mode, control circuit 120c generates first to third switching signals CS_N, CS_P1, and CS_P2 to turn off n-type transistor NT, first p-type transistor PT1, and second p-type transistor PT2. For example, control circuit 120c can generate a first switching signal CS_N at a logic low level, a second switching signal CS_P1 at a logic high level, and a third switching signal CS_P2 at a logic high level. By turning off all n-type transistor NT, first p-type transistor PT1, and second p-type transistor PT2, the second virtual power line VGND can be blocked from the second power line RGND and can be floated.

[0086] exist Figure 7 The diagram shows a tail transistor unit 110c comprising only a first p-type transistor PT1 and a second p-type transistor PT2, which are two transistors with different threshold voltages. However, the power gating circuit 100c conceived according to the present invention can include various numbers of p-type transistors with different threshold voltages. Therefore, various holding modes can be provided to the logic circuit 200. According to an exemplary embodiment, the power gating circuit 100c does not operate in a power-off mode. For example, the control circuit 120c can be designed not to turn off all n-type transistors NT, the first p-type transistor PT1, and the second p-type transistor PT2.

[0087] In an exemplary embodiment, power gate circuit 100, power gate circuit 100a, or power gate circuit 100b is added. Figure 7 This is to connect the added power gating circuit to the first virtual power line VVDD.

[0088] Figure 8 This is a block diagram illustrating an integrated circuit 10d including a power gating circuit 100d according to an exemplary embodiment of the present invention.

[0089] Reference Figure 8 The integrated circuit 10d includes a logic circuit 200 and a power gating circuit 100d for providing power to the logic circuit 200. The logic circuit 200 can be electrically connected to a first virtual power line VVDD and a second virtual power line VGND, and can receive power through the first virtual power line VVDD and the second virtual power line VGND.

[0090] The power gating circuit 100d can be electrically connected to a first power line RVDD for providing the power supply voltage VDD and a second power line RGND for providing the ground voltage GND. The power gating circuit 100d can control the power mode of the logic circuit 200 by selectively connecting the first virtual power line VVDD to the first power line RVDD and selectively connecting the second virtual power line VGND to the second power line RGND in response to the control signal INd.

[0091] For example, the power gating circuit 100d can provide the power supply voltage VDD and the ground voltage GND to the logic circuit 200 by connecting the first power line RVDD to the first virtual power line VVDD and the second power line RGND to the second virtual power line VGND in power-on mode. In an exemplary embodiment, the power gating circuit 100d does not provide a high holding voltage VR to the first virtual power line VVDD in holding mode, but provides a low holding voltage VGR to the second virtual power line VGND. In an exemplary embodiment, the power gating circuit 100d floats the first virtual power line VVDD and the second virtual power line VGND by blocking the first power line RVDD from the first virtual power line VVDD and the second power line RGND from the second virtual power line GND in power-off mode. Figure 8 The diagram shows a high holding voltage VR and a low holding voltage VGR. However, the integrated circuit 10d according to the present invention can provide the logic circuit 200 with high and low holding voltages at different levels.

[0092] Figure 9 This is a circuit diagram illustrating an integrated circuit 10d including a power gating circuit 100d according to an exemplary embodiment of the present invention.

[0093] Reference Figure 9 The power gating circuit 100d includes: a head transistor unit 110_1d connected between a first power line RVDD and a first virtual power line VVDD; a tail transistor unit 110_2d connected between a second power line RGND and a second virtual power line VGND; and a control circuit 120d for providing switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 to the head transistor unit 110_1d and the tail transistor unit 110_2d. The control circuit 120d can generate first to third head switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 in response to a control signal INd. Unlike... Figure 9 As shown, in an alternative embodiment, the power gating circuit 100d does not include the control circuit 120d.

[0094] The head transistor unit 110_1d includes a p-type transistor PT, a first n-type transistor NT1, and a second n-type transistor NT2 connected in parallel between the first power line RVDD and the first virtual power line VVDD. According to an exemplary embodiment, the p-type transistor PT, the first n-type transistor NT1, and the second n-type transistor NT2 can be shown as equivalent transistors connected in parallel. Figure 2 The description of the head transistor unit 110 can be applied to the head transistor unit 110_1d.

[0095] The tail transistor unit 110_2d includes an n-type transistor NT, a first p-type transistor PT1, and a second p-type transistor PT2 connected in parallel between the second power line RGND and the second virtual power line VGND. According to an exemplary embodiment, the n-type transistor NT, the first p-type transistor PT1, and the second p-type transistor PT2 can be shown as equivalent transistors connected in parallel. Figure 7 The description of transistor cell 110c can be applied to tail transistor cell 110_2d.

[0096] The control circuit 120d can selectively turn on the transistors included in the head transistor unit 110_1d and the tail transistor unit 110_2d in response to the control signal INd. The control circuit 120d can generate a first head switching signal CS_P for switching the p-type transistor PT, a second head switching signal CS_N1 for switching the first n-type transistor NT1, and a third head switching signal CS_N2 for switching the second n-type transistor NT2. For example, the control circuit 120d applies the first head switching signal CS_P to the gate of the p-type transistor PT, applies the second head switching signal CS_N1 to the gate of the first n-type transistor NT1, and applies the third head switching signal CS_N2 to the gate of the second n-type transistor NT2. Additionally, the control circuit 120d can generate a first tail switching signal CS_N for switching the n-type transistor NT, a second tail switching signal CS_P1 for switching the first p-type transistor PT1, and a third tail switching signal CS_P2 for switching the second p-type transistor PT2 in response to the control signal INd. For example, the control circuit 120d applies a first tail switching signal CS_N to the gate terminal of the n-type transistor NT, applies a second tail switching signal CS_P1 to the gate terminal of the first p-type transistor PT1, and applies a third tail switching signal CS_P2 to the gate terminal of the second p-type transistor PT2.

[0097] Based on the operation of the head transistor unit 110_1d and the tail transistor unit 110_2d, the first drive voltage of the first virtual power line VVDD electrically connected to the logic circuit 200, the second drive voltage of the second virtual power line VGND electrically connected to the logic circuit 200, and the power mode of the logic circuit 200 can be changed. For example, the logic circuit 200 can operate in one of the following modes: a power-on mode, multiple holding modes, and a power-off mode.

[0098] In the power-on mode, the control circuit 120d generates switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 to turn on the p-type transistor PT of the head transistor unit 110_1d and the n-type transistor NT of the tail transistor unit 110_2d. Current flows through the p-type transistor PT of the head transistor unit 110_1d and the n-type transistor NT of the tail transistor unit 110_2d, such that the voltage level of the first virtual power line VVDD can be the same as the power supply voltage VDD of the first power line RVDD, and the second voltage of the second virtual power line VGND can be the same as the ground voltage GND of the second power line RGND.

[0099] In multiple holding modes, control circuit 120d can generate switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 to turn on one of the first n-type transistor NT1 and the second n-type transistor NT2 of head transistor unit 110_1d or one of the first p-type transistor PT1 and the second p-type transistor PT2 of tail transistor unit 110_2d. In multiple holding modes, a first high holding voltage (e.g., Figure 3D VR1) or a second high holding voltage (e.g., Figure 3C VR2) can be applied to the first virtual power line VVDD, or the first low holding voltage or the second low holding voltage can be applied to the second virtual power line VGND.

[0100] According to an exemplary embodiment, the amplitudes of the first threshold voltage VTH_N1 of the first n-type transistor NT1, the second threshold voltage VTH_N2 of the second n-type transistor NT2, the first threshold voltage VTH_P1 of the first p-type transistor PT1, and the second threshold voltage VTH_P2 of the second p-type transistor PT2 are different from each other. In this case, the power supply gating circuit 100d can drive the logic circuit 200 in one of eight different holding modes.

[0101] In power-down mode, control circuit 120d generates switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 to turn off at least one of the head transistor unit 110_1d and the tail transistor unit 110_2d. By turning off at least one of the head transistor unit 110_1d and the tail transistor unit 110_2d, the first virtual power line VVDD or the second virtual power line VGND can be floated. Therefore, power can be blocked from logic circuit 200.

[0102] exist Figure 9 The diagram shows that the head transistor unit 110_1d includes only a first n-type transistor NT1 and a second n-type transistor NT2, and the tail transistor unit 110_2d includes only a first p-type transistor PT1 and a second p-type transistor PT2. However, the power supply gating circuit 100d according to the present invention can include various numbers of n-type and p-type transistors with different threshold voltages. Therefore, the power supply gating circuit 100d can provide various holding modes to the logic circuit 200.

[0103] Figure 10 This is a layout diagram illustrating an exemplary embodiment of the invention, comprising a head unit in a power gating circuit arranged in an integrated circuit. The layout diagram shows a plane having a first direction X and a second direction Y. Components arranged in greater quantity than other components in the third direction Z can be referred to as being above the other components, while components arranged in greater quantity than other components in the direction opposite to the third direction Z can be referred to as being below the other components.

[0104] Reference Figure 10 The first to fifth head units C110_1 and C110_1a to C110_1d can extend along the first direction X on the substrate and can include an n-well doped with n-type impurities, and the substrate can be doped with p-type impurities. Therefore, first to fourth NMOS regions NA1 to NA4 in which n-type transistors are formed can be formed on the substrate, and a PMOS region PA in which p-type transistors are formed can be formed in the n-well. The head transistor unit of the power supply gate circuit can be formed in each of the first to fifth head units C110_1 and C110_1a to C110_1d.

[0105] In an exemplary embodiment, each of the first to fourth NMOS regions NA1 to NA4 and the PMOS region PA includes a fin extending in a first direction X. Alternatively, according to an exemplary embodiment, each of the first to fourth NMOS regions NA1 to NA4 and the PMOS region PA includes a nanosheet extending in the first direction X.

[0106] Each of the first to fifth head units C110_1 and C110_1a to C110_1d can be electrically connected to a logic unit and can provide power to the logic unit. The logic unit can be implemented by at least one of various circuits (e.g., an inverter, NAND gate, AND gate, NOR gate, OR gate, XOR gate, XOR gate, multiplexer, adder, latch, and flip-flop).

[0107] Each of the first to fifth head units C110_1 and C110_1a to C110_1d can be electrically connected to the first power supply line (e.g., Figure 1 RVDD) and the first virtual power line (e.g., Figure 1 Each of the first to fifth head units C110_1 and C110_1a to C110_1d may have an input pin and an output pin. According to an exemplary embodiment, the input pin of each of the first to fifth head units C110_1 and C110_1a to C110_1d may be electrically connected to the gate of a transistor formed in each of the first to fifth head units C110_1 and C110_1a to C110_1d, and a switching signal provided by a control circuit may be input to the input pin of each of the first to fifth head units C110_1 and C110_1a to C110_1d. The output pin of each of the first to fifth head units C110_1 and C110_1a to C110_1d may be electrically connected to the first virtual power line VVDD.

[0108] The first head unit C110_1 includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, and a PMOS region PA in which a p-type transistor is formed. The first head unit C110_1 may have a first height H1 defined in the second direction Y.

[0109] The second head unit C110_1a includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, a second NMOS region NA2 in which an n-type transistor with a second threshold voltage VTH_N2 is formed, and a PMOS region PA in which a p-type transistor is formed. The second head unit C110_1a may have a second height H2 defined in the second direction Y.

[0110] The PMOS region PA of the second head unit C110_1a is arranged between the first NMOS region NA1 and the second NMOS region NA2. For example, in the second head unit C110_1a, the second NMOS region NA2, the PMOS region PA, and the first NMOS region NA1 can be arranged in parallel in the second direction Y.

[0111] According to an exemplary embodiment, the first threshold voltage VTH_N1 and the second threshold voltage VTH_N2 are different from each other. Therefore, the second head unit C110_1a can provide more high holding voltages to the logic units electrically connected to the second head unit C110_1a than the first head unit C110_1 provides. In an exemplary embodiment, the second height H2 is greater than the first height H1. In an exemplary embodiment, the number of p-type transistors formed in the PMOS region PA of the first head unit C110_1 is greater than the number of p-type transistors formed in the PMOS region PA of the second head unit C110_1a, and the power supply voltage (e.g., ...) can be... Figure 1 The VDD is stably provided to the logic circuit.

[0112] The third head unit C110_1b includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, a second NMOS region NA2 in which an n-type transistor with a second threshold voltage VTH_N2 is formed, and a PMOS transistor PA in which a p-type transistor is formed. In an exemplary embodiment, the PMOS region PA of the third head unit C110_1b is arranged between the first NMOS region NA1 and the second NMOS region NA2. For example, in the third head unit C110_1b, the second NMOS region NA2, the PMOS region PA, and the first NMOS region NA1 may be arranged in parallel in the second direction Y.

[0113] The third head unit C110_1b may have a third height H3 defined in the second direction Y. In an exemplary embodiment, the PMOS region PA of the third head unit C110_1b is wider than the PMOS region PA of the second head unit C110_1a, and the third height H3 is greater than the second height H2. Therefore, the number of p-type transistors formed in the PMOS region PA of the third head unit C110_1b can be greater than the number of p-type transistors formed in the PMOS region PA of the second head unit C110_1a, and the power supply voltage (e.g., ...) can be applied in the power-on mode. Figure 1 The VDD is stably provided to the logic circuit.

[0114] The fourth header unit C110_1c includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, a second NMOS region NA2 in which an n-type transistor with a second threshold voltage VTH_N2 is formed, a third NMOS region NA3 in which an n-type transistor with a third threshold voltage VTH_N3 is formed, and a PMOS region PA in which a p-type transistor is formed. According to an exemplary embodiment, the first threshold voltage VTH_N1, the second threshold voltage VTH_N2, and the third threshold voltage VTH_N3 are different from each other. Therefore, the fourth header unit C110_1c can provide the logic cell with a wider variety of high holding voltages than the first to third header units C110_1, C110_1a, and C110_1b.

[0115] The first NMOS region NA1 and the second NMOS region NA2 can be arranged adjacent to the PMOS region PA of the fourth head cell C110_1c in the second direction Y, and the third NMOS region NA3 can be arranged adjacent to the PMOS region PA of the fourth head cell C110_1c in the opposite direction to the second direction Y. According to an exemplary embodiment, the third NMOS region NA3 is wider than the first NMOS region NA1 and the second NMOS region NA2, and the number of n-type transistors formed in the third NMOS region NA3 can be greater than the number of n-type transistors formed in the first NMOS region NA1 and the second NMOS region NA2. For example, in the third NMOS region NA3, n-type transistors for providing a specific holding mode with a high operating frequency can be formed, and in the specific holding mode, a voltage obtained by subtracting a third threshold voltage VTH_N3 from the power supply voltage can be provided to the logic cell electrically connected to the fourth head cell C110_1c.

[0116] The fifth header cell C110_1d includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, a second NMOS region NA2 in which an n-type transistor with a second threshold voltage VTH_N2 is formed, a third NMOS region NA3 in which an n-type transistor with a third threshold voltage VTH_N3 is formed, a fourth NMOS region NA4 in which an n-type transistor with a fourth threshold voltage VTH_N4 is formed, and a PMOS region PA in which a p-type transistor is formed. According to an exemplary embodiment, the first to fourth threshold voltages VTH_N1 to VTH_N4 are different from each other. Therefore, the fifth header cell C110_1d can provide the logic cell with a wider variety of high holding voltages than the first to fourth header cells C110_1 and C110_1a to C110_1c.

[0117] The first NMOS region NA1 and the second NMOS region NA2 can be arranged to be adjacent to the PMOS region PA of the fifth head unit C110_1d in the second direction Y, and the third NMOS region NA3 and the fourth NMOS region NA4 can be arranged to be adjacent to the PMOS region PA of the fifth head unit C110_1d in the opposite direction to the second direction Y.

[0118] The second head unit C110_1a and the third head unit C110_1b can correspond to Figure 2 The head transistor unit 110, and the fourth head unit C110_1c can correspond to Figure 4A The header transistor unit 110a. Alternatively, the fourth header unit C110_1c and the fifth header unit C110_1d can correspond to Figure 5 The head transistor unit 120b. The power supply gating circuit including the head transistor unit is... Figure 10 The first to fifth head units C110_1 and C110_1a to C110_1d shown are used to implement this. The power gating circuit conceived according to the present invention is not limited to this, and can be implemented by head units having various structures.

[0119] Figure 11 This is a layout diagram illustrating an exemplary embodiment of the invention, comprising a tail unit in a power gating unit arranged in an integrated circuit.

[0120] Reference Figure 11 Each of the first to fifth tail units C110_2 and C110_2a to C110_2d may include an n-well extending along a first direction X on the substrate and doped with n-type impurities, and the substrate may be doped with p-type impurities. Therefore, an NMOS region NA in which an n-type transistor is formed can be formed on the substrate, and PMOS regions PA1 to PA4 in which a p-type transistor is formed can be formed in the n-well. The tail transistor unit of the power supply gate circuit may be formed in each of the first to fifth tail units C110_2 and C110_2a to C110_2d.

[0121] Each of the first to fifth tail units C110_2 and C110_2a to C110_2d can be electrically connected to the second power line (e.g., Figure 6The first to fifth tail units C110_2 and C110_2a to C110_2d may have input pins and output pins. According to an exemplary embodiment, the input pins of each of the first to fifth tail units C110_2 and C110_2a to C110_2d are electrically connected to the gates of the transistors formed in each of the first to fifth tail units C110_2 and C110_2a to C110_2d, and a switching signal provided by the control circuit can be input to the input pins of each of the first to fifth tail units C110_2 and C110_2a to C110_2d. The output pins of each of the first to fifth tail units C110_2 and C110_2a to C110_2d may be electrically connected to the second virtual power line VGND.

[0122] The first tail unit C110_2 includes a first PMOS region PA1 in which a p-type transistor with a first threshold voltage VTH_P1 is formed and an NMOS region NA in which an n-type transistor is formed. The first tail unit C110_2 may have a first height H1′ defined in the second direction Y.

[0123] The second tail unit C110_2a includes a first PMOS region PA1 in which a p-type transistor with a first threshold voltage VTH_P1 is formed, a second PMOS region PA2 in which a p-type transistor with a second threshold voltage VTH_P2 is formed, and an NMOS region NA in which an n-type transistor is formed. The second tail unit C110_2a may have a second height H2′ defined in the second direction Y.

[0124] The NMOS region NA of the second tail unit C110_2a is arranged between the first PMOS region PA1 and the second PMOS region PA2. For example, in the second tail unit C110_2a, the second PMOS region PA2, the NMOS region NA, and the first PMOS region PA1 can be arranged in parallel in the second direction Y.

[0125] According to an exemplary embodiment, the first threshold voltage VTH_P1 and the second threshold voltage VTH_P2 are different from each other. Therefore, the second tail unit C110_2a can provide more low holding voltages to the logic units electrically connected to the second tail unit C110_2a than the first tail unit C110_2 provides. In an exemplary embodiment, the second height H2′ is greater than the first height H1′, and the number of n transistors formed in the NMOS region NA of the second tail unit C110_2a can be greater than the number of n transistors formed in the NMOS region NA of the first tail unit C110_2. Therefore, the ground voltage (e.g., ...) can be... Figure 7 The GND is stably provided to the logic unit.

[0126] The third tail unit C110_2b includes a first PMOS region PA1 in which a p-type transistor with a first threshold voltage VTH_P1 is formed, a second PMOS region PA2 in which a p-type transistor with a second threshold voltage VTH_P2 is formed, and an NMOS region NA in which an n-type transistor is formed. The NMOS region NA of the third tail unit C110_2b is arranged between the first PMOS region PA1 and the second PMOS region PA2. For example, in the third tail unit C110_2b, the second PMOS region PA2, the NMOS region NA, and the first PMOS region PA1 can be arranged parallel to each other in the second direction Y.

[0127] The third tail unit C110_2b may have a third height H3′ defined in the second direction Y. In an exemplary embodiment, the NMOS region NA of the third tail unit C110_2b is wider than the NMOS region NA of the second tail unit C110_2a, and the third height H3′ is greater than the second height H2′. Therefore, the number of n-type transistors formed in the NMOS region NA of the third tail unit C110_2b can be greater than the number of n-type transistors formed in the NMOS region NA of the second tail unit C110_2a, and the ground voltage (e.g., ...) can be ... in the power-on mode. Figure 7 The GND is stably provided to the logic unit.

[0128] The fourth tail unit C110_2c includes a first PMOS region PA1 in which a p-type transistor with a first threshold voltage VTH_P1 is formed, a second PMOS region PA2 in which a p-type transistor with a second threshold voltage VTH_P2 is formed, a third PMOS region PA3 in which a p-type transistor with a third threshold voltage VTH_P3 is formed, and an NMOS region NA in which an n-type transistor is formed. According to an exemplary embodiment, the first threshold voltage VTH_P1, the second threshold voltage VTH_P2, and the third threshold voltage VTH_P3 are different from each other. Therefore, the fourth tail unit C110_2c can provide the logic cell with a wider range of low holding voltages than the first to third tail units C110_2, C110_2a, and C110_2b.

[0129] The first PMOS region PA1 and the second PMOS region PA2 can be arranged adjacent to the NMOS region NA of the fourth tail unit C110_2c in the second direction Y, and the third PMOS region PA3 can be arranged adjacent to the NMOS region NA of the fourth tail unit C110_2c in the direction opposite to the second direction Y. According to an exemplary embodiment, the third PMOS region PA3 is wider than the first PMOS region PA1 and the second PMOS region PA2, and the number of p-type transistors formed in the third PMOS region PA3 can be greater than the number of p-type transistors formed in the first PMOS region PA1, and also greater than the number of p-type transistors formed in the second PMOS region PA2. For example, in the third PMOS region PA3, p-type transistors for providing a specific holding mode with a high operating frequency can be formed, and in the specific holding mode, a voltage obtained by subtracting the third threshold voltage VTH_P3 from the power supply voltage can be provided to the logic unit electrically connected to the fourth tail unit C110_2c.

[0130] The fifth tail unit C110_2d includes a first PMOS region PA1 in which a p-type transistor with a first threshold voltage VTH_P1 is formed, a second PMOS region PA2 in which a p-type transistor with a second threshold voltage VTH_P2 is formed, a third PMOS region PA3 in which a p-type transistor with a third threshold voltage VTH_P3 is formed, a fourth PMOS region PA4 in which a p-type transistor with a fourth threshold voltage VTH_P4 is formed, and an NMOS region NA in which an n-type transistor is formed. According to an exemplary embodiment, the first to fourth threshold voltages VTH_P1 to VTH_P4 are different from each other. Therefore, the fifth tail unit C110_2d can provide the logic circuit with a wider range of low holding voltages than the first to fourth tail units C110_2 and C110_2a to C110_2c.

[0131] The first PMOS region PA1 and the second PMOS region PA2 can be arranged to be adjacent to the NMOS region NA of the fifth tail unit C110_2d in the second direction Y, and the third PMOS region PA3 and the fourth PMOS region PA4 can be arranged to be adjacent to the NMOS region NA of the fifth tail unit C110_2d in the opposite direction to the second direction Y.

[0132] The second tail unit C110_2a and the third tail unit C110_2b can correspond to Figure 7 The tail transistor 110c. The power supply gating circuit including the tail transistor unit can be... Figure 11The first to fifth tail units C110_2 and C110_2a to C110_2d shown are used to implement this. The power gating circuit conceived according to the present invention is not limited to this, and can be implemented by tail units having various structures.

[0133] Figure 12 This is a layout diagram illustrating an exemplary embodiment of the invention, comprising a head unit arranged in a power gating circuit within an integrated circuit.

[0134] Reference Figure 12 The head unit group C100e includes a first type head unit C110_1b and a second type head unit C110_1b′. The first type head unit C110_1b and the second type head unit C110_1b′ can be electrically connected to a first power supply line (e.g., Figure 1 RVDD) and the first virtual power line (e.g., Figure 1 VVDD).

[0135] The first type of head unit C110_1b and the second type of head unit C110_1b′ included in the head unit group C100e may include transistors with different threshold voltages. For example, the first type of head unit C110_1b includes a first NMOS region NA1 in which an n-type transistor with a first threshold voltage VTH_N1 is formed, a second NMOS region NA2 in which an n-type transistor with a second threshold voltage VTH_N2 is formed, and a PMOS region PA in which a p-type transistor is formed. Additionally, for example, the second type of head unit C110_1b′ includes a third NMOS region NA3 in which an n-type transistor with a third threshold voltage VTH_N3 is formed, a fourth NMOS region NA4 in which an n-type transistor with a fourth threshold voltage VTH_N4 is formed, and a PMOS region PA in which a p-type transistor is formed. According to an exemplary embodiment, the first to fourth threshold voltages VTH_N1 to VTH_N4 are different from each other. However, the inventive concept is not limited thereto, and some of the first to fourth threshold voltages VTH_N1 to VTH_N4 may be the same.

[0136] exist Figure 12 The diagram shows that each of the first type head unit C110_1b and the second type head unit C110_1b′ has the same shape as the third head unit C110_1b. However, the head unit group C100e conceived according to the present invention is not limited thereto. The head unit group C100e may include... Figure 10 At least one of the first to fifth head units C110_1 and C110_1a to C110_1d.

[0137] According to an exemplary embodiment, the first type head unit C110_1b and the second type head unit C110_1b′ included in the head unit group C100e can be arranged parallel to each other in the first direction X. However, the inventive concept is not limited thereto. According to an exemplary embodiment, the first type head unit C110_1b and the second type head unit C110_1b′ included in the head unit group C100e have the same height. However, the inventive concept is not limited thereto.

[0138] The first output pin P1 of the first type head unit C110_1b and the second output pin P2 of the second type head unit C110_1b′ included in the head unit group C100e are electrically connected to each other, and the first output pin P1 and the second output pin P2 can be electrically connected to a first virtual power line (e.g., Figure 1 (VVDD). The header unit group C100e can operate as a header unit. For example, the header unit group C100e can be like... Figure 10 It operates in the same way as the fifth head unit C110_1d.

[0139] As the number of n-type transistors in a header cell increases, the size of the header cell can gradually increase. Furthermore, as the ratio of p-type to n-type transistors in a standard header cell gradually decreases, the resistance may increase in the power-on mode. Therefore, when the header transistor cell of the power-gated circuit is implemented by header cell group C100e, compared to the case where the header transistor cell is implemented by the fifth header cell C110_1d, the decrease in the ratio of p-type to n-type transistors can be prevented, and the operating characteristics of header cell group C100e can be predicted.

[0140] To arrange the header unit group C100e in the integrated circuit, a first type header unit C110_1b and a second type header unit C110_1b′ are arranged, and the output pin of the first type header unit C110_1b can be electrically connected to the output pin of the second type header unit C110_1b′. When via Figure 10 When the power supply gate circuit of the fifth head unit C110_1d is used to implement the head transistor unit, the wiring can be made easier compared to the case where the head transistor unit is implemented through the head unit group C100e, and the area in which the head transistor unit is formed can be reduced in the integrated circuit.

[0141] exist Figure 12The diagram illustrates an embodiment where different types of head units form a head unit group. However, different types of tail units can form a tail unit group. The output pins of the tail units included in the tail unit group can be electrically connected to each other. For example, the integrated circuit may include a first type of tail unit and a second type of tail unit electrically connected to a second power line RGND and a second virtual power line VGND. The first type of tail unit may include a first p-type transistor having a first threshold voltage therein. Figure 11 The first PMOS region of VTH_P1 ( Figure 11 PA1) and therein formed a second threshold voltage ( Figure 11 The second PMOS region of the second p-type transistor (VTH_P2) Figure 11 PA2). The second type of tail unit may include having a third threshold voltage formed therein. Figure 11 The third PMOS region of the third p-type transistor (VTH_P3) and the fourth PMOS region therein, wherein a fourth p-type transistor having a fourth threshold voltage (VTH_P4) is formed. According to an exemplary embodiment, the first type of tail unit and the second type of tail unit may be arranged parallel to each other in the first direction X, and the output pin of the first type of tail unit may be electrically connected to the output pin of the second type of tail unit.

[0142] Figure 13 This is a layout diagram illustrating an exemplary embodiment of the invention, comprising a head unit and a tail unit in a power gating unit arranged in an integrated circuit.

[0143] Reference Figure 13 The power gating unit group C100f can correspond to Figure 9 The head transistor unit 110_1d and the tail transistor unit 110_2d are included. The power gating unit group C100f includes a third head unit C110_1b and a third tail unit C110_2b. The third head unit C110_1b can be electrically connected to the first power line (e.g., Figure 1 RVDD) and the first virtual power line (e.g., Figure 1 The third tail unit C110_2b can be electrically connected to the second power line (e.g., VVDD). Figure 1 RVDD) and the second virtual power line (e.g., Figure 1 For example, the output pin of the third head unit C110_1b can be electrically connected to the first virtual power line VVDD, and the output pin of the third tail unit C110_2b can be electrically connected to the second virtual power line VGND.

[0144] According to an exemplary embodiment, the third head unit C110_1b and the third tail unit C110_2b included in the power gating unit group C100f are arranged to overlap in the first direction X.

[0145] For convenience, the following are shown: Figure 10 The third head unit C110_1b and Figure 11 The power gating group C100f is the third tail unit C110_2b. However, various power gating unit groups, including head units and tail units with various shapes, can form the power gating circuit 100f. For example, Figure 10 The first to fifth head units C110_1 and C110_1a and C110_1d and one of them Figure 11 One of the first to fifth tail units C110_2 and C110_2a to C110_2d can form a power gating unit group.

[0146] Figure 14 This is a flowchart illustrating an exemplary embodiment of a method for manufacturing an integrated circuit according to a concept based on the present invention.

[0147] Reference Figure 14 The standard cell library D10 may include information items about the standard cells, such as functional information, feature information, and layout information. The standard cell library D10 may also include data defining the layout of the standard cells.

[0148] The standard cell library D10 can define header cells (e.g., Figure 10 The layout of the first to fifth head elements (C110_1 and C110_1a to C110_1d). The standard element library D10 can define the tail elements (e.g., Figure 11 The layout of the first to fifth tail elements (C110_2 and C110_2a to C110_2d). Additionally, the standard element library D10 can define the head element group (e.g., Figure 12 The layout of the head unit group C100e, the layout of the tail unit group, and the power gating unit group (e.g., Figure 13 The layout of the power gating unit group C100f.

[0149] In operation S10, logic synthesis can be performed to generate netlist data based on register transfer level (RTL) data. The netlist data may include a description of the connectivity of electronic circuits. The netlist data may include a list of electronic components of the circuit and a list of nodes to which they are connected. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis using a reference standard cell library D10 to generate netlist data, including bitstreams or netlists, based on RTL data created in a hardware description language (HDL) (e.g., VHSIC Hardware Description Language (VHDL) or Verilog).

[0150] In operation S20, referencing the standard cell library D10, a placement and routing (P&R) operation is performed to generate placement data D20 based on the netlist data. In P&R operation S20, operations such as placing standard cells, generating interconnects, and generating placement data D20 can be performed.

[0151] For example, a semiconductor design tool (e.g., a P&R tool) can reference a standard cell library D10 to arrange multiple standard cells based on netlist data. For instance, a semiconductor design tool can select one of multiple standard cell layouts defined by netlist data and can refer to the standard cell library D10 to arrange the selected standard cell layout.

[0152] For example, semiconductor design tools can be selected Figure 10 The first to fifth header units C110_1 and C110_1a to C110_1d can be selected, and the selected header unit can be arranged as a power-gated circuit. For example, semiconductor design tools can select... Figure 12 The first to fifth tail units C110_2 and C110_2a to C110_2d can be selected, and the selected tail unit can be arranged as a power-gated circuit. Additionally, for example, semiconductor design tools can... Figure 12 The head unit group C100e is arranged as a power gating circuit, and can... Figure 13 The power gating unit group C100f is arranged as a power gating circuit. Semiconductor design tools can arrange standard cells by taking into account the feasibility of predicting the operating characteristics of the arranged standard cells, the magnitude of the resistance in the power-on mode, and the feasibility of routing.

[0153] Interconnections can electrically connect the output pins of a standard cell to the input pins of that standard cell. For example, at least one via and at least one routing line can be provided. The layout data D20 can be in a format such as GDSII and can include geometric information about the standard cells and their interconnections.

[0154] In operation S30, optical proximity correction (OPC) is performed. OPC can refer to an operation used to form a pattern of a desired shape by correcting distortions such as refraction caused by the properties of light, as included in photolithography in semiconductor processes used to manufacture integrated circuits. The pattern on the mask can be determined by applying OPC to the layout data D20.

[0155] In operation S40, the operation of manufacturing a mask is performed. For example, when OPC is applied to layout data D20, a pattern on the mask can be defined to form a pattern formed in multiple layers, and at least one mask (or photomask) for forming the pattern of multiple layers can be manufactured.

[0156] In operation S50, operations for manufacturing an integrated circuit are performed. For example, an integrated circuit can be manufactured by patterning multiple layers using at least one mask manufactured in operation S40. According to an exemplary embodiment, operation S50 includes operations S51 and S52.

[0157] In operation S51, front-end (FEOL) processing is performed. During the FEOL process in the manufacturing of integrated circuits, various components, such as transistors, capacitors, and resistors, can be formed on the substrate.

[0158] In operation S52, back-end processing (BEOL) is performed. During the manufacturing of integrated circuits, in the BEOL process, various components, such as transistors, capacitors, and resistors, are interconnected.

[0159] Figure 15 This is a block diagram illustrating a computing system 1000 including a memory for storing programs, according to an exemplary embodiment of the present invention. A method for manufacturing an integrated circuit (e.g., manufacturing...) according to an exemplary embodiment of the present invention. Figure 14 At least some of the operations included in the method for integrating integrated circuits can be performed by the computing system 1000.

[0160] Reference Figure 15 The computing system 1000 can be a fixed computing system such as a desktop computer, workstation, or server, or a portable computing system such as a laptop computer. The computing system 1000 includes a processor 1100, input and output devices 1200, a network interface 1300, random access memory (RAM) 1400, read-only memory (ROM) 1500, and storage devices 1600. The processor 1100, input and output devices 1200, network interface 1300, RAM 1400, ROM 1500, and storage devices 1600 can communicate with each other via a bus 1700.

[0161] Processor 1100 may be referred to as a processing unit and may include at least one core capable of executing any set of instructions, such as a microprocessor, application processor (AP), digital signal processor (DSP), or graphics processing unit (GPU). For example, processor 1100 may access memory, namely RAM 1400 or ROM 1500, via bus 1700 and may execute instructions stored in RAM 1400 or ROM 1500.

[0162] RAM 1400 may store program 1400_1, or at least a portion thereof, for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. For example, program 1400_1 may include semiconductor design tools, such as logic synthesis tools and P&R tools.

[0163] Program 1400_1 can be executed including during manufacturing. Figure 14 The method of integrating an integrated circuit includes at least some operations. That is, program 1400_1 may include multiple instructions executable by processor 1100, and multiple instructions included in program 1400_1 may cause processor 1100 to perform... Figure 14 The manufacturing process of integrated circuits includes some operations.

[0164] Even if the power supply to the computing system 1000 is interrupted, the data stored in the memory 1600 will not be lost. For example, the memory 1600 may include a non-volatile storage device and may include a storage medium such as magnetic tape, optical disc, or magnetic disk. The storage device 1600 may store a program 1400_1 according to an exemplary embodiment of the present invention, and the program 1400_1 or at least a portion thereof may be loaded from the memory 1600 before the processor 110 executes the program 1400_1. Alternatively, the storage device 1600 may store a file created by a programming language, and the program 1400_1 or at least a portion thereof generated by a compiler from the file may be loaded into the RAM 1400.

[0165] Storage device 1600 can store database 1600_1, and database 1600_1 can include information required for designing integrated circuits. For example, database 1600_1 can include... Figure 14 The standard cell library D10. In addition, storage device 1600 can store data to be processed by processor 110 or data processed by processor 1100.

[0166] Input and output devices 1200 may include input devices such as a keyboard or pointing device and output devices such as a display device or printer. Network interface 1300 can handle access to networks located outside the computing system 1000.

[0167] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: A power gating circuit is configured to receive a power supply voltage from a first power supply line and output a first drive voltage to a first virtual power supply line, wherein the power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power supply line and the first virtual power supply line, and a second n-type transistor connected between the first power supply line and the first virtual power supply line. as well as A logic circuit, electrically connected to the first virtual power line and configured to receive power from the power gating circuit. In this configuration, the P-type metal-oxide-semiconductor (PMOS) region of the first p-type transistor is positioned between the N-type metal-oxide-semiconductor (NMOS) region of the first n-type transistor and the NMOS region of the second n-type transistor.

2. The integrated circuit of claim 1, wherein the power gating circuit operates in one of a power-on mode, a first holding mode, a second holding mode, and a power-off mode, and In the power-on mode, the p-type transistor is turned on and the n-type transistor is turned off; in the first hold mode, the p-type transistor and the second n-type transistor are turned off and the first n-type transistor is turned on; in the second hold mode, the p-type transistor and the first n-type transistor are turned off and the second n-type transistor is turned on; and in the power-off mode, the p-type transistor and the n-type transistor are turned off.

3. The integrated circuit according to claim 1, wherein the power gating circuit operates in one of a power-on mode, a first holding mode, and a second holding mode. The power gating circuit outputs a first driving voltage of the power supply voltage in the power-on mode, a first driving voltage of a first holding voltage in the first holding mode, and a first driving voltage of a second holding voltage in the second holding mode. The first holding voltage is lower than the power supply voltage by a first threshold voltage of the first n-type transistor, and the second holding voltage is lower than the power supply voltage by a second threshold voltage of the second n-type transistor.

4. The integrated circuit of claim 1, wherein the logic circuit is electrically connected to a second power supply line, the second power supply line being subjected to a ground voltage.

5. The integrated circuit of claim 1, wherein the power gating circuit receives a ground voltage from a second power line and outputs a second drive voltage to a second virtual power line, and The power gating circuit includes an n-type transistor and a p-type transistor connected in parallel between the second power line and the second virtual power line.

6. The integrated circuit of claim 1, wherein the power gating circuit further comprises a control circuit configured to generate a switching signal for switching the first p-type transistor, the first n-type transistor, and the second n-type transistor in response to a control signal received from a source located outside the power gating circuit.

7. An integrated circuit, comprising a first power gating unit configured to receive a power supply voltage from a first power supply line and provide a first drive voltage to a logic unit via a first dummy power supply line. The first power gating unit includes: The first P-type metal-oxide-semiconductor PMOS region includes a first p-type transistor connected between the first power line and the first dummy power line; The first N-type metal-oxide-semiconductor (NMOS) region includes a first n-type transistor connected between the first power line and the first dummy power line; as well as The second NMOS region includes a second n-type transistor connected between the first power line and the first dummy power line, and The first PMOS region includes an n-well doped with n-type impurities and extending along a first direction. The first PMOS region is arranged between the first NMOS region and the second NMOS region.

8. The integrated circuit of claim 7, wherein the first threshold voltage of the first n-type transistor is different from the second threshold voltage of the second n-type transistor.

9. The integrated circuit of claim 7, wherein the first power supply gating unit further comprises a third NMOS region, the third NMOS region comprising a third n-type transistor connected between the first power line and the first dummy power line, and The first NMOS region and the third NMOS region are arranged to be adjacent to the first PMOS region in a second direction perpendicular to the first direction, and the second NMOS region is arranged to be adjacent to the PMOS region in a direction opposite to the second direction.

10. The integrated circuit of claim 9, wherein the second NMOS region is wider than the first NMOS region.

11. The integrated circuit of claim 9, wherein the first power supply gating unit further comprises a fourth NMOS region, the fourth NMOS region comprising a fourth n-type transistor connected between the first power line and the first dummy power line, and The fourth NMOS region is arranged to be adjacent to the first PMOS region in a direction opposite to the second direction.

12. The integrated circuit of claim 7, wherein the integrated circuit further comprises a second power gating unit configured to provide the first drive voltage to the logic unit, and The second power gating unit includes: The second PMOS region includes a second p-type transistor connected between the first power line and the first dummy power line; The third NMOS region includes a third n-type transistor connected between the first power line and the first virtual power line; as well as The fourth NMOS region includes a fourth n-type transistor connected between the first power line and the first dummy power line.

13. The integrated circuit of claim 12, wherein the first power gating unit and the second power gating unit are arranged in parallel in the first direction.

14. The integrated circuit of claim 12, wherein the first output pin of the first power gating unit is electrically connected to the second output pin of the second power gating unit.

15. The integrated circuit of claim 7, further comprising a second power gating unit configured to receive a ground voltage from a second power line and provide a second drive voltage to the logic unit via a second virtual power line. The second power gating unit includes: The third NMOS region includes a third n-type transistor connected between the second power line and the second virtual power line; The first PMOS region includes a second p-type transistor connected between the second power line and the second dummy power line; as well as The second PMOS region includes a third p-type transistor connected between the second power line and the second dummy power line.

16. The integrated circuit of claim 15, wherein the first power gating unit and the second power gating unit are arranged to overlap in the first direction.

17. An integrated circuit, comprising a first power gating unit, the first power gating unit being configured to receive a ground voltage from a ground line and provide a drive voltage to logic cells via a virtual ground line. The first power gating unit includes: A first N-type metal-oxide-semiconductor (NMOS) region includes a first n-type transistor connected between the ground line and the virtual ground line; A first P-type metal-oxide-semiconductor (PMOS) region includes a first p-type transistor connected between the ground line and the virtual ground line; as well as The second PMOS region includes a second p-type transistor connected between the ground line and the virtual ground line, and The first PMOS region is located in an n-well doped with n-type impurities and extending along a first direction. The first NMOS region is arranged between the first PMOS region and the second PMOS region.

18. The integrated circuit of claim 17, wherein the first threshold voltage of the first p-type transistor is different from the second threshold voltage of the second p-type transistor.

19. The integrated circuit of claim 17, wherein the first power supply gating unit further comprises a third PMOS region, the third PMOS region comprising a third p-type transistor connected between the ground line and the virtual ground line, and The first PMOS region and the third PMOS region are arranged to be adjacent to the first NMOS region in a second direction perpendicular to the first direction, and the second PMOS region is arranged to be adjacent to the first NMOS region in a direction opposite to the second direction.

20. The integrated circuit of claim 19, wherein the second PMOS region is wider than the first PMOS region.

21. The integrated circuit of claim 19, wherein the first power supply gating unit further comprises a fourth PMOS region, the fourth PMOS region including a fourth p-type transistor connected between the ground line and the virtual ground line, and The fourth PMOS region is arranged to be adjacent to the first NMOS region in a direction opposite to the second direction.

22. The integrated circuit of claim 17, further comprising a second power supply gating unit configured to provide a drive voltage to the logic unit. The second power gating unit includes: The second NMOS region includes a second n-type transistor connected between the ground line and the virtual ground line; The third PMOS region includes a third p-type transistor connected between the ground line and the virtual ground line; as well as The fourth PMOS region includes a fourth p-type transistor connected between the ground line and the virtual ground line.

Images