Electronic circuits and methods for initializing electronic circuits

Abstract

A method is provided for initializing an electronic circuit based on an externally applied voltage. The electronic circuit includes a first input circuit and other circuit components. In a first step, when the voltage does not exceed the first threshold, a first enable signal for operating the first input circuit and another enable signal for operating the other circuit components are disabled. In a second step, when the voltage exceeds the first threshold, the first enable signal for operating the first input circuit is activated and the other enable signal for operating the other circuit components is disabled. Then, a selection signal for activating the electronic circuit and a code word at a terminal of a command bus are received via the first input circuit. If the received selection signal and the received code word have predetermined values, then the other enable signal for operating the other circuit components is activated.

Description

Technical Field

[0001] In electronic circuits, especially those containing digital circuitry, it is essential to ensure that the electronic circuitry remains in a safe state even during the startup of the corresponding system containing it. During startup, the voltage supplied to the electronic circuitry increases, for example, from 0V, so that the electronic circuitry has sufficient voltage and energy to operate from a specific voltage threshold. Background Technology

[0002] During a voltage rise, short-duration voltage spikes (glitches) or prolonged temporary voltage drops may occur. This can cause one part of the electronic circuit to be operational while others are not yet responding because the voltage is not high enough for those other parts. It is also possible that one part of the electronic circuit is initially operational, then briefly inactive during a voltage drop, and then immediately operational again. Different parts of the electronic circuit may react differently. Accordingly, the internal memory of the electronic circuit is loaded with values ​​at startup that cause the electronic circuit to enter a state not set for normal operation.

[0003] It is known, for example, that in US7,272,709, the master chip uses a chip select signal to select the chip it controls, ensuring that the chip can only send signals after at least the master chip has been initialized. However, this introduces the problem that the initialization time for the master chip and other chips in the system can differ. It also presents the risk that the host may unintentionally send the chip select signal during startup. Summary of the Invention

[0004] The object of this invention is to provide an apparatus and a method that solve the aforementioned problems. This is achieved through the subject matter of the invention. Advantageous designs will emerge from the following description.

[0005] In one embodiment, a method is provided for initializing electronic circuitry based on an externally applied voltage, said electronic circuitry including a first input circuit and other circuitry, the first input circuit being configured to receive at least one select signal (CS1) and a signal from a command bus (SPI). In a first step, when the voltage does not exceed a first threshold, a first enable signal for operating the input circuitry and another enable signal for operating the other circuitry are disabled.

[0006] In the second step, when the voltage exceeds the first threshold, a first enable signal for running the input circuit is activated while another enable signal for running other circuit sections is disabled.

[0007] Next, the first input circuit receives a selection signal for activating the electronic circuitry and a code word at a terminal on the command bus. If the received selection signal and the received code word have predetermined values, then another enable signal for operating other circuit sections is activated.

[0008] In one implementation, the other enable signal is activated only when the voltage exceeds a second threshold (V3), the second threshold being greater than the first threshold (V2).

[0009] Furthermore, a corresponding electronic circuit is proposed, which is capable of performing the described method. Attached Figure Description

[0010] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings...

[0011] Figure 1 A system is shown in which the described initialization method can be used;

[0012] Figure 2 A switching threshold is shown, which is used to initialize electronic circuitry;

[0013] Figure 3 The different stages used to initialize electronic circuits are shown;

[0014] Figure 4 The first embodiment is shown. Figure 1 The circuit details of the electronic circuits in the document;

[0015] Figure 5 The second embodiment is shown. Figure 1 The circuit details of the electronic circuits in the text. Detailed Implementation

[0016] Figure 1 The diagram illustrates a system 10, such as an entertainment electronic product, comprising a host 11 and multiple slave devices 12, 13, and 14. The host 11 and slave devices 12, 13, and 14 are electronic circuits. In this case, they are configured as integrated circuits, also known as chips. System 10 is connected at two terminals 25 and 26 to a voltage supply unit, which is operated, for example, by a switching power supply. This switching power supply outputs a voltage of 0V between potentials VDD and VSS when not in operation, and outputs, for example, a voltage of 3V when in operation. During system startup, the voltage rises from 0V to 3V, but this causes, and typically also causes, the aforementioned voltage peaks in both the positive and negative directions, and a prolonged temporary voltage drop. Electronic circuits 11, 12, 13, and 14 are connected to terminals 25 and 26, from which they are supplied with electrical power.

[0017] Furthermore, the master 11 and slaves 12, 13, and 14 are interconnected via an SPI bus 16, through which the master and slaves exchange data. The SPI bus 16 here has a width of 4, that is, it has four parallel lines.

[0018] The master unit 11 is also connected to the slave unit 12 via a chip select line CS1, by which the master unit 11 selects or deselects the slave unit 12. Similarly, the master unit 11 is connected to the slave unit 13 via a chip select line CS2, and correspondingly to the slave unit 14 via a chip select line CS3, such that these slave units are selected or deselected by the master unit 11. Selection here indicates that the slave unit is ready to receive and transmit data. Even in the unselected state, the slave unit performs basic functions by maintaining, for example, the internally generated voltage at a desired level and in a predetermined operating state. Furthermore, in the unselected state, the slave unit must at least activate a portion of its input circuitry to identify when it will be selected again. Additionally, the master unit 11 drives a clock signal CLK, which is received by all slave units 12, 13, and 14 at their respective clock inputs.

[0019] Figure 2 The following voltage range is shown, in which, Figure 1 The slave device in this case, namely slave device 12, operates. Within the range of 0V to 1V, the corresponding slave device does not operate. Voltage V1 is also referred to as the "minimum voltage for interface operation." From voltage V1 onwards, the following circuitry can operate, by means of which the slave device is at least able to receive and evaluate the selected input signal.

[0020] However, a slightly higher voltage is required to ensure safe operation under all conditions, such as at all different temperatures. For this purpose, a threshold V2 is established, referred to as the "voltage at which the interface is activated," and the slave is activated to receive the selected signal at this threshold. However, when the voltage is greater than or equal to the threshold V2, not all parts of the slave are activated because specific areas of the slave, such as the area with analog circuitry for operating the internal memory, are not yet safely operational.

[0021] In the first embodiment, there is another threshold V3, referred to as the "minimum voltage level". From this threshold V3, the entire slave device can operate safely, and the operation of the entire slave device 12 can begin. Figure 2 The term "slave" is merely illustrative. The corresponding method can be used in any electronic circuit with an external voltage supply and input interface, especially semiconductor devices.

[0022] In the alternative election Figure 2 In the second implementation, system operation begins from the threshold V2.

[0023] Figure 3 The different stages of implementing the first embodiment are shown in tabular form. In the first stage, the external supply voltage is below the threshold V2. In this stage, not only the input terminals for the interface are disabled, but the rest of the slave device is also disabled. This ensures that the slave device is not in a state that is not specifically set for the slave device. In this unset state, it is possible that the chip outputs signals that cause interference in other chips, and / or the chip no longer leaves the unset state, while the voltage does not completely drop to 0V.

[0024] The chip may be ready to operate from a voltage threshold V1 that is less than V2, but operation may not be safe in all cases. For this reason, wait until the voltage exceeds the threshold V2.

[0025] In one implementation, when the input circuit is disabled, only the forwarding of the received signal is blocked; however, the received signal is evaluated internally in the first input circuit. In an alternative implementation, the input circuit is completely turned off.

[0026] When the threshold V2 is exceeded, phase 2 begins, in which at least the first input circuit is activated to receive at least the selected interface signal. Activation here means enabling the circuit to operate, that is, applying voltage or enabling it by means of an exemplary digital enable signal (Reset). Thus, the first input circuit is ready to receive signals and forward them to the output of the input circuit.

[0027] The rest of the chip, especially the analog section used to run the internal memory, remains disabled during this stage. This is to prevent, in particular, writing erroneous data to non-volatile memory, as this would permanently corrupt the functionality of System 10.

[0028] In this embodiment, two circuit sections are described, each activated by a different enable signal. Alternatively, an additional circuit section may be present, activated by an additional enable signal.

[0029] In the next stage 3, the interface receives logic 0 from line CS1, which in this case indicates that slave 12 is selected. Furthermore, the input interface receives a signal from the SPI bus 16 indicating that a specific codeword has been received on line [0] of the SPI bus 16. The codeword consists of an 8-bit sequence, such as "0101 0110". The remaining lines of the SPI bus 16 are not considered. This means that if the voltage in slave 12 is sufficiently high, slave 12 should be fully activated. Thus, in the first embodiment, in stage 4, when a voltage greater than level V3 has been detected in slave 12, the rest of slave 12 is also activated.

[0030] The current method ensures that slave device 12 is fully activated, and the master device also requests it accordingly. Otherwise, the risk arises that the slave device is activated, but the master device lacks sufficient voltage and therefore sends meaningless commands. With the current method, it is feasible to ensure the overall orderly startup of the chip. Additional image reception and evaluation from the SPI interface enhances security. In other implementations, it is feasible to evaluate more bits of the SPI bus to further improve security.

[0031] Figure 4 The proposed method is illustrated in slave device 12. Selection of input terminals for slave device 12 is shown, specifically terminals for the voltage supply VDD and GND, a terminal for the clock CLK, a terminal for the chip select line CS, and one of the four terminals for the command bus SPI. Slave device 12 includes a first comparator 110 and a second comparator 111, wherein when the supply voltage VDD is greater than V2, the first comparator 110 outputs a logic 1 with level VDD on line RESET1, thereby activating the first enable signal RESET1. Similarly, when the voltage VDD is greater than V3, comparator 111 outputs a logic 1 with voltage level VDD.

[0032] The comparison voltages used for comparators 110 and 111 can be generated, for example, by means of a bandgap voltage generator in slave device 12.

[0033] Line RESET1 is connected to first input circuits 112 and 113 for terminals CS and SPI[0]. When RESET1 represents logic 1, these first input circuits 112 and 113 are enabled, that is, they forward the signal received at their input terminal SPI[0] to their respective output terminals. The output terminals of these circuits 112 and 113 are connected in particular to a switching mechanism 114. The switching mechanism 114 receives the clock signal CLK from the corresponding input terminal of the slave 12 and receives signals from the first input circuits 112 and 113. When signal CS1 is 0 and SPI[0] is a specific codeword of four consecutive bits, the switching mechanism 114 switches the signal RELEASE to 1.

[0034] The first comparator 110 can be referred to as the first enable circuit, and the second comparator 111 can be referred to as the second enable circuit. The activation circuit includes a switching mechanism 114 and an AND gate 115. Circuits 116, 117, and 118 enabled by other enable signals 3 can be referred to as other circuit sections, but they can also include other circuits not described herein. Furthermore, besides in Figure 4 The circuit block shown can contain multiple other circuit blocks.

[0035] By using bus signals, no additional lines are needed besides the existing ones, which would increase system overhead. Furthermore, the master can determine the order in which it controls the slaves. For example, if the master wants to prevent a temporary voltage drop caused by all masters initializing simultaneously and all requiring large currents at the same time, it can activate the slave it needs first.

[0036] If the supply voltage VDD is greater than V2 and an instruction to activate the circuit has been detected from the first input circuit, then the level on line RELEASE is close to logic 1, corresponding to the voltage level of VDD. With logic 1 present on lines RESET2 and RELEASE respectively, signal RESET3 is also set to logic 1 by means of AND gate 115. Other enable signal RESET3 is thus activated and turns on the internal voltage generator 116, which generates internal voltages VCC, VPP, and VBB for the internal memory 117. Furthermore, signal RESET3 also enables output driver 118, allowing it to drive signals to output terminals OUT[0:8]. If line RESET3 is at logic 0, then output terminals OUT[0:8] are high ohms and the internal voltage generator 116 is turned off.

[0037] In one implementation, when slave device 12 has finally initialized all circuitry, it does not signal master device 11. Master device 11 must then be programmed to wait a predetermined time after activating via the CS1 signal and sending an SPI codeword to activate the circuitry until it accesses slave device 12.

[0038] In an alternative implementation, after slave 12 has internally measured that the required voltage has reached its target value, slave 11, for example, also signals to the master via the SPI interface that the initialization process is complete.

[0039] Figure 5 An embodiment of the electronic circuit according to the second embodiment is shown. Here, the AND gate receives the signal RELEASE and the level VDD. Thus, the output signal of the AND gate 115 corresponds to the signal RELEASE. When logic 1 exists on the line RELEASE, the signal RESET3 is also set to logic 1 by means of the AND gate 115. Thus, without waiting to reach the threshold V3, a voltage greater than or equal to V2 is supplied to enable and thus operate other circuits.

Claims

1. A method for initializing an electronic circuit (12) based on an externally applied voltage (VDD, VSS), wherein the electronic circuit includes a first input circuit (112, 113) and other circuit portions (116, 117, 118), the first input circuit being configured to receive at least one selection signal (CS1) and a signal from a command bus (SPI), the other circuit portions being circuit portions within the electronic circuit other than the first input circuit, wherein the method includes the following steps: a) When the voltage does not exceed the first threshold (V2), disable the first enable signal (RESET1) for operating the first input circuit and disable another enable signal (RESET3) for operating the other circuit sections; b) When the voltage exceeds the first threshold (V2), activate the first enable signal (RESET1) for operating the first input circuit and disable the other enable signal (RESET3) for operating the other circuit sections; c) Receive a selection signal (CS1) for activating the electronic circuit (12) and a code word at a terminal of the command bus (SPI) using the first input circuit (112, 113); d) If the received selection signal (CS1) and the received codeword have predetermined values, then activate the other enable signal (RESET 3) for running the other circuit sections.

2. The method according to claim 1, characterized in that, In step d), activation is performed only if the following additional condition is met: the voltage exceeds a second threshold (V3), and the second threshold is greater than the first threshold (V2).

3. The method according to claim 2, characterized in that, The command bus (SPI) signals are transmitted via a bus line configured to connect to other electronic circuits (13, 14).

4. The method of claim 3, wherein the bus lines are controlled by a bus according to a serial interface protocol.

5. The method according to any one of claims 1 to 4, characterized in that, The other circuit portions (116, 117, 118) include a memory or a voltage generator for the memory.

6. The method according to any one of claims 1 to 4, characterized in that, The other circuit sections (116, 117, 118) include drivers for the output terminals of the electronic circuit (12).

7. The method according to any one of claims 1 to 4, characterized in that, Another step is provided: a signal is output to an output terminal, which emits a signal indicating the end of the initialization of the other circuit sections.

8. The method according to any one of claims 1 to 4, wherein the codeword is a sequence of at least 8 bits.

9. An electronic circuit (12) supplied with voltages (VDD, VSS) applied from an external source, wherein the electronic circuit has the following characteristics: First input circuit (112, 113), the first input circuit is configured to receive at least one select signal (CS1) and a signal from the command bus (SPI); Other circuit sections (116, 117, 118), which are the circuit sections in the electronic circuit other than the first input circuit; The first enable circuit (110) is used for: When the voltage does not exceed the first threshold (V2), disable the first enable signal (RESET1) for operating the first input circuit and disable another enable signal (RESET3) for operating the other circuit sections. When the voltage exceeds the first threshold (V2), a first enable signal (RESET1) for operating the first input circuit is activated and another enable signal (RESET3) for operating the other circuit sections is disabled. An activation circuit is configured to: activate another enable signal (RESET 3) for running the other circuit sections (116, 117, 118) if the selection signal (CS1) received by the first input circuit corresponds to a predetermined value and the signal of the command bus received by the first input circuit corresponds to a predetermined code word.

10. The electronic circuit (12) according to claim 9, characterized in that, Activation is performed only if the following additional condition is met: the voltage exceeds a second threshold (V3), and the second threshold is greater than the first threshold (V2).

11. The electronic circuit (12) according to claim 10, characterized in that, The signals of the command bus (SPI) are transmitted via bus lines configured for connecting other electronic circuits (13, 14).

12. The electronic circuit (12) according to claim 11, characterized in that, The bus lines are controlled by a bus according to a serial interface protocol.

13. The electronic circuit (12) according to any one of claims 9 to 12, characterized in that, The other circuit portions (116, 117, 118) include a memory or a voltage generator for the memory.

14. The electronic circuit (12) according to any one of claims 9 to 12, characterized in that, The other circuit sections (116, 117, 118) include drivers for the output terminals of the electronic circuit (12).

15. The electronic circuit (12) according to any one of claims 9 to 12, characterized in that, An output device is provided, which is configured to output a signal to an output terminal, wherein the output terminal emits a signal indicating the end of initialization of the other circuit parts.

16. The electronic circuit (12) according to any one of claims 9 to 12, wherein the code word is a sequence of at least 8 bits.

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