Component carrier with high passive intermodulation performance and method of manufacturing and using the same

Abstract

The invention relates to a component carrier (100) comprising a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), wherein a conductive wiring structure (108) is part of the at least one electrically conductive layer structure (104), wherein a passive intermodulation (PIM) value of a signal propagating along the conductive wiring structure (108) is less than ‑153 dBc. The invention also relates to a method for manufacturing the component carrier (100) and a method for using the component carrier (100) for high frequency applications.

Description

Technical Field

[0001] The present invention relates to a component carrier, a method for manufacturing the component carrier and a method for using the component carrier. Background Art

[0002] Against the background of the growing product functionality of component carriers equipped with one or more electronic components, the miniaturization of such electronic components and the increasing number of electronic components mounted on component carriers such as printed circuit boards, increasingly powerful array-like components or packages with several electronic components are used, which have a plurality of contacts or connections and the spacing between these contacts is getting smaller and smaller. During operation, the dissipation of heat generated by such electronic components and the component carrier itself is becoming an increasingly serious problem. At the same time, the component carrier should be mechanically robust and electrically reliable in order to be able to operate even under harsh conditions.

[0003] Furthermore, artifacts may occur when high-frequency signals propagating along the wiring structure of the component carrier mix or multiply with each other to generate distorted signals. This undesirable phenomenon can be expressed as passive intermodulation (PIM) and may degrade the signal transmission on the component carrier. Passive intermodulation can significantly degrade the overall performance of the mobile communication system, among other things. Summary of the invention

[0004] SUMMARY OF THE INVENTION It is an object of the present invention to provide a component carrier which has a high performance with regard to signal transmission.

[0005] In order to achieve the above objects, a component carrier, a method for producing a component carrier and a method for using the component carrier are provided according to the independent claims.

[0006] According to an exemplary embodiment of the present invention, a component carrier is provided, wherein the component carrier includes a stack including at least one conductive layer structure and at least one electrically insulating layer structure; the conductive wiring structure is a part of at least one conductive layer structure; wherein the passive intermodulation (PIM) value of a signal propagating along the conductive wiring structure is less than -153dBc.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes forming a stacked part, the stacked part including at least one conductive layer structure and at least one electrically insulating layer structure; forming a conductive wiring structure, the conductive wiring structure being a part of at least one conductive layer structure; wherein the conductive wiring structure is formed so that a passive intermodulation (PIM) value of a signal propagating along the conductive wiring structure is less than -153dBc.

[0008] According to a further exemplary embodiment of the present invention, an electrically conductive wiring structure of a component carrier having the above-described features is used for high-frequency applications, in particular for conducting radio frequency (RF) signals, in particular radio frequency signals with a frequency above 1 GHz.

[0009] In the context of the present application, the term "component carrier" may particularly denote any support structure capable of accommodating one or more components on and / or in which to provide mechanical support and / or electrical connectivity. In other words, the component carrier may be configured as a mechanical and / or electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board, which combines different types of the above-mentioned types of component carriers.

[0010] In the context of the present application, the term "layer structure" may particularly denote a continuous layer, a patterned layer or a plurality of non-continuous islands in the same plane.

[0011] In the context of the present application, the term "passive intermodulation (PIM)" may particularly denote a phenomenon according to which high-frequency signals propagating along the wiring structure of a component carrier may mix or multiply with each other to generate other signals related to the first signal, thus involving intermodulation distortion. Passive intermodulation may produce unwanted interference and may even hide the desired signal. Passive intermodulation may be measured in dBc. The parameter "dBc" (decibels relative to carrier) may represent the power ratio of a signal to a carrier (or reference) signal, expressed in decibels (i.e., expressed in a logarithmic scale). If the dBc value is negative, the relative signal strength is less than the carrier signal strength. In other words, a larger negative dBc value may indicate better performance of the component carrier than a smaller negative dBc value. Passive intermodulation may be measured according to standard IEC62037 (in particular in the latest version effective on the priority date of this patent application). For example, passive intermodulation measurements can be performed as published in Kathrein’s July 2018 white paper “Calculating Passive Intermodulation for Wideband Antenna Arrays”. https: / / www.kathrein.com / en / solutions / mobile-communication / support / technical-documents / passive-intermodulation / download.

[0012] In the context of the present application, the term "high frequency application" may particularly denote a task performed by a component carrier or a task to which a component carrier contributes, wherein the task may be related to the processing of radio frequency signals. Such radio signals or high frequency signals may be electrical or electromagnetic signals or other signals propagating along a wiring structure in a frequency range used for communication. In particular, a radio frequency (RF) signal may, for example, have a frequency in a range between 3 kHz and 300 GHz.

[0013] According to an exemplary embodiment of the present invention, there is provided a component carrier having a conductive wiring structure or a conductive trace, the passive intermodulation value of which is less than -153dBc. It has been proven that by taking one or more appropriate measures, such as providing a conductive wiring structure with a sufficiently smooth surface, using an appropriate surface treatment agent, an appropriate patterning treatment and / or using an adhesion promoter instead of surface roughening, etc., the component carrier can transmit or conduct a low-loss high-frequency signal caused by frequency mixing and / or multiplication. Such a conductive wiring structure can also meet the PIM design rule of -153dBc, that is, the PIM-related signal loss is less than -153dB per centimeter of signal transmission length or wiring structure length. Therefore, according to an exemplary embodiment, distortion caused by interference between different radio frequency signals during signal transmission can be strongly suppressed. Therefore, the risk of signal distortion in high-frequency applications (such as 5G) in particular may become extremely unlikely, and high signal strength and signal quality can be obtained.

[0014] In the following, further exemplary embodiments of a component carrier and a method will be explained.

[0015] In one embodiment, the conductive wiring structure forms an antenna structure. In the context of the present application, the term "antenna structure" may particularly denote a conductive structure whose shape, size and configuration enable it to receive and / or transmit an electromagnetic radiation signal corresponding to an electrical or electromagnetic signal conducted along the conductive wiring structure of the component carrier. However, alternatively, the component carrier may also only transmit signals along the wiring structure without necessarily having an antenna structure.

[0016] In one embodiment, the value of passive intermodulation (PIM) is less than -155dBc, particularly less than -160dBc, more particularly less than -165dBc, and preferably less than -168dBc. By taking the various measures described herein, it is even possible to meet more stringent design rules for PIM values, see the above values.

[0017] The roughness of a surface can be defined as and can be measured as the centerline average height Ra. Ra is the arithmetic mean of all distances from the profile to the centerline. However, the roughness of a surface can also be defined as and can be measured as the average roughness depth Rz. When a reference length is sampled from the roughness curve in the direction of the average line, Rz can be determined and is expressed as the distance measured in the longitudinal direction of the roughness curve between the top profile peak line and the bottom profile valley line on the sampled portion (for example, Rz can be determined by averaging five separate measurement paths). For example, the measurement or determination of roughness Ra and Rz can be implemented according to DIN EN ISO 4287:2010.

[0018] In one embodiment, the roughness Rz of at least a portion of the outer surface of the conductive wiring structure is less than 300nm, in particular less than 200nm. It turns out that providing at least a portion of the surface of the conductive wiring structure with the mentioned high smoothness or low roughness properties allows very advantageous properties to be obtained in terms of PIM performance.

[0019] In one embodiment, the roughness Rz of the horizontal (i.e., upper and / or lower) surface of the conductive wiring structure is less than 300 nm, in particular less than 200 nm. The upper surface or the lower surface may be the surface of the wiring structure parallel to the main surface of the component carrier or stack. It has been shown that the upper surface in particular has a great influence on the PIM performance.

[0020] In one embodiment, the roughness Rz of the entire surface of the plated portion of the conductive wiring structure (which can be combined into a foil portion and a plated portion) is less than 300nm, in particular less than 200nm. In particular, the upper surface and / or lower surface of the plated portion and at least a portion of the side surface can be formed to have the mentioned highly smooth surface characteristics to improve PIM performance.

[0021] In one embodiment, the surface roughness Rz of the conductive base structure (e.g. foil portion) of the conductive wiring structure below the plated portion of the conductive wiring structure is less than 1.6 μm, in particular less than 1 μm. Therefore, a relatively smooth base structure such as a copper foil can also be used to form the conductive wiring structure. Such a smooth base structure also has a positive effect on the PIM performance. As an alternative to providing a laminated copper foil as a base structure, such a base structure can also be formed by, for example, sputtering a conductive material such as copper on an electrically insulating layer structure.

[0022] The mentioned roughness values ​​are compatible with low-loss transmission of radio frequency signals through one or more wiring structures, since, taking into account the skin effect, there is no excessive surface roughness that deteriorates the signal propagation. According to the skin effect, electrical signals with high frequencies, for example in the gigahertz range, do not propagate over the entire cross-section of the conductor, but essentially only within its skin-like surface portion. Traditionally, this can lead to large signal losses due to the surface roughness. Without wishing to be bound by a particular theory, it is currently believed that such signal losses may be caused by the additional resistance or impedance to which the traveling radio frequency signal is subjected due to the micro-roughness of the surface. Advantageously, such signal losses can be prevented or at least strongly suppressed when the roughness of the conductive wiring structure of the component carrier is reduced.

[0023] In one embodiment, the component carrier includes a surface finishing layer covering at least a portion of the conductive wiring structure. Forming one or more surface finishing layers on a component carrier such as a printed circuit board (PCB) is an effective measure to protect the conductive structure of the component carrier. The conductive structure typically includes conductive materials such as copper, which may be oxidized when not protected, resulting in degradation of the component carrier. Therefore, a surface finishing layer is formed on the conductive wiring structure, which has two main functions: protecting the conductive wiring structure from oxidation and providing an electrically connectable surface for assembling electronic components to the component carrier.

[0024] In one embodiment, the surface finishing layer comprises tin or consists of tin, in particular chemical tin or immersion tin. However, electroplated tin or hot air leveling (which may also include tin) can also be used as the material of the surface finishing layer. In different embodiments, hot air leveling can be achieved with lead or lead-free. It turns out that, surprisingly, the surface finishing layer based on tin, in particular chemical tin, significantly promotes the PIM performance of the conductive wiring structure of the component carrier. Surprisingly, chemical tin also adheres appropriately even on the highly smooth surface of the conductive wiring structure.

[0025] However, other surface finishes such as electroless nickel immersion gold (ENIG) may also be used.

[0026] In one embodiment, at least a portion of the surface of the conductive wiring structure is covered with an adhesion promoter. By chemically promoting adhesion of the component carrier material on the surface of the conductive wiring structure rather than mechanically roughening the surface of the wiring structure, proper adhesion can be promoted and delamination suppression can thereby be achieved, while signal attenuation can be significantly reduced by suppressing passive intermodulation.

[0027] In one embodiment, the stack includes a central electrically insulating layer structure, which is covered with a corresponding one of at least one conductive layer structure on two opposing main surfaces. For example, the stack may be a core. Such a core may have a central dielectric layer, which may include resin and optionally include reinforcing particles such as glass fiber. For example, the central dielectric layer may be a prepreg layer. The central dielectric layer may be covered with corresponding copper foils or the like on two opposing main surfaces.

[0028] In one embodiment, the stack includes at least one through hole, which is at least partially filled with a conductive filling medium (such as copper plating) for electrically connecting the relative main surfaces of the stack. For example, the through hole can be formed by laser processing or by mechanical drilling. The filling medium can be copper, which can be inserted into the through hole, for example, by chemical deposition and / or plating. By means of such a plated hole, a short vertical connection path can be obtained between the two relative main surfaces of the component carrier, which also suppresses signal losses.

[0029] In one embodiment, the conductive wiring structure comprises a base structure (in particular on at least one electrically insulating layer structure) and comprises a plated structure (i.e., a conductive structure formed by plating) on ​​the base structure. Thus, the wiring structure can be configured as a metal composite material, in particular a metal layer stack. It has been shown that by forming the wiring structure as a foil-type base structure and a plated structure thereon, a high smoothness of the wiring structure can be obtained with low effort. This, in turn, can result in low losses during radio frequency transmission along the corresponding wiring structure.

[0030] In one embodiment, the base structure is a patterned metal foil, in particular a patterned copper foil. For example, the thickness of the base structure is in the range between 5 μm and 30 μm. With such a small thickness, a compact component carrier can be obtained.

[0031] In one embodiment, the plated structure is a copper plated structure, ie is formed by copper plating. For example, the thickness of the plated structure is in the range between 20 μm and 70 μm. With such a small thickness, a compact component carrier can be obtained.

[0032] In one embodiment, the plating structure comprises at least two stacked plating layers, in particular configured as a double plating layer. The plating can be performed partially before and after forming the patterned resist. The mentioned patterning process has also been shown to have a positive influence on the PIM performance of the component carrier.

[0033] In one embodiment, the method comprises attaching, in particular laminating, a metal foil as a base structure (or as a preform of a base structure) to at least one electrically insulating layer structure. The metal foil may be transformed from the preform into the final base structure by patterning.

[0034] In one embodiment, the method includes plating a conductive material on a base structure or a preform of a base structure as a plated structure (or as a preform of a plated structure). The plated material can be transformed from the preform to the final plated structure by patterning at least a portion of the plated material.

[0035] In one embodiment, the method includes forming a plated structure as a first plating layer on a base structure and a second plating layer on the first plating layer, wherein the first plating layer and the second plating layer are formed in a separate plating process. In particular, the method may include forming a first plating layer on the base structure before applying a resist, and forming a second plating layer on the first plating layer after applying the resist. Advantageously, the method may include etching only the first plating layer and the base structure and the resist thereon after the resist has been applied. More specifically, the second plating layer may be selectively arranged and deposited in an opening between portions of the patterned resist rather than on portions of the resist. The method may also include selectively applying etching protection to the second plating layer rather than portions of the resist before etching. Therefore, etching protection may be selectively applied to the exposed surface portion of the second plating layer rather than to the resist therebetween. By subsequent etching processes, the resist and the first plating layer below the resist and portions of the base structure (or its preform) may be removed. In contrast, during the etching process, surface portions corresponding to the etch protector (along with portions of the base structure, first plating layer and second plating layer beneath corresponding portions of the etch protector) may still exist, thereby defining portions of the conductive wiring structure.

[0036] In one embodiment, the method includes forming a first coating by rapid plating. Initially (i.e., before forming a second coating), a plating deposit in the form of a first coating, denoted as a rapid coating, can be used to form a very thin (e.g., less than 0.1 μm thick) coating of high quality and good adhesion to the base structure (or its preform). This lays the foundation for a subsequent plating process to form the second coating. A high current density is used for striking, while a plating solution with a low ion concentration can be used for rapid plating. It turns out that the described two-stage plating process also has a positive impact on the PIM performance of the component carrier, as this can promote the formation of a wiring structure with high smoothness.

[0037] In one embodiment, the component carrier is used for 5G. Mobile wireless communications according to the 5G standard involve high-frequency transmissions with a high amount of data per transmission, and therefore require excellent properties in terms of PIM performance. A component carrier according to an exemplary embodiment of the present invention having a PIM performance of less than -153dBc or even less than -160dBc meets these demanding requirements. The fifth generation (5G) networks have higher mobile data rates, in particular significantly above 100Mb / s. Higher transmission rates may expose PIM vulnerabilities in the communication network. When implementing a component carrier according to an exemplary embodiment of the present invention, the fifth generation communication network can experience excellent network transmission fidelity.

[0038] In one embodiment, the component carrier is used for high-frequency applications above 1 GHz, in particular above about 100 GHz. On account of the skin effect, signal transmission is particularly sensitive to artifacts caused by surface roughness, in particular for such high frequencies. The high PIM performance of the component carrier according to an exemplary embodiment of the present invention allows low-loss signal transmission even at such high-frequency values.

[0039] In one embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier can be a stack of the mentioned one or more electrically insulating layer structures and one or more electrically conductive layer structures, in particular formed by applying mechanical pressure and / or thermal energy. The mentioned stack can provide a plate-like component carrier, which can provide a large mounting surface for other components and still be very thin and compact.

[0040] In one embodiment, the component carrier is formed as a plate. This contributes to a compact design, wherein the component carrier still provides a large basis for mounting components thereon. Furthermore, in particular, for example, bare chips as examples of embedded electronic components can be conveniently embedded in thin boards such as printed circuit boards due to their small thickness. The plate-shaped component carrier also ensures short electrical connection paths, thus suppressing signal distortions during transmission.

[0041] In one embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (particularly an IC substrate) and an interposer.

[0042] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier, which is formed by laminating a plurality of conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or by providing thermal energy. As a preferred material for PCB technology, the conductive layer structure is made of copper, and the electrically insulating layer structure may include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. By forming through holes through the lamination, for example by laser drilling or mechanical drilling, and by filling them with conductive material (particularly copper), thereby forming holes as through-hole connections, various conductive layer structures can be connected to each other in a desired manner. In addition to being able to embed one or more components in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one or two opposing surfaces of the plate-like printed circuit board. They can be connected to the corresponding main surface by welding. The dielectric part of the PCB can be composed of a resin with reinforcing fibers (such as glass fibers).

[0043] In the context of the present application, the term "substrate" can specifically refer to a small component carrier having substantially the same size as the components (particularly electronic components) to be mounted thereon. More specifically, a substrate can be understood as a carrier for electrical connection or electrical networking and a component carrier comparable to a printed circuit board (PCB), but it has a relatively high density in the connections arranged horizontally and / or vertically. The horizontal connection is, for example, a conductive path, and the vertical connection can be, for example, a drill hole. These horizontal and / or vertical connections are arranged in the substrate and can be used to provide shelled components or unshelled components (such as bare chips), particularly IC chips, with electrical and / or mechanical connections to a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" also includes "IC substrate". The dielectric portion of the substrate can be composed of a resin with reinforcing particles (such as reinforcing balls, particularly glass balls).

[0044] The substrate or interposer may include or consist of at least one layer of glass, silicon (Si) or a photoimageable or dry-etchable organic material (e.g., an epoxy-based buildup material (such as an epoxy-based buildup film) or a polymer (such as polyimide, polybenzoxazole or benzocyclobutene).

[0045] In one embodiment, at least one electrically insulating layer structure comprises at least one of the group consisting of resin (such as reinforced or non-reinforced resin, for example epoxy resin or bismaleimide triazine resin), cyanate ester, polyphenylene derivative, glass (especially glass fiber, multilayer glass, glass-like material), prepreg (such as FR-4 or FR-5), polyimide, polyamide, liquid crystal polymer (LCP), epoxy-based stacking film, polytetrafluoroethylene (Teflon), ceramic and metal oxide. Reinforcement materials such as mesh, fibers or balls made of glass (multilayer glass) may also be used. Although prepregs, especially FR4, are usually preferred for rigid PCBs, other materials may also be used, especially epoxy-based stacking films for substrates. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers and / or cyanate ester resins, low-temperature co-fired ceramics (LTCC) or other low, very low or ultra-low DK materials may be implemented in component carriers as electrically insulating layer structures.

[0046] In one embodiment, at least one conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium and tungsten. Although copper is generally preferred, other materials or coated versions thereof are also possible, in particular coated with superconducting materials such as graphene.

[0047] In one embodiment, the component carrier further comprises an electronic component mounted on the component carrier material and / or embedded in the component carrier material, in particular in the stack. For example, the electronic component may be a radio frequency semiconductor chip configured to transmit and / or receive radio frequency signals via the wiring structure and electrically coupled to the conductive wiring structure. Thus, the electronic component may be configured to perform radio frequency applications, in particular radio frequency applications involving frequencies above 1 GHz.

[0048] At least one component may be surface mounted on the component carrier and / or embedded in the component carrier and may in particular be selected from a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (such as a heat pipe), a light-conducting element (such as an optical waveguide or optical conductor connection), an electronic component, or a combination thereof. For example, the component may be an active electronic component, a passive electronic component, an electronic chip, a storage device (such as a DRAM or other data storage), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a light-emitting diode, an optocoupler, a voltage converter (such as a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may also be embedded in the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element can be a permanent magnet (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for example a ferrite core) or can be a paramagnetic element. However, the component can also be a substrate, an intermediate layer or other component carrier, for example in a board-to-board configuration. The component can be surface-mounted on the component carrier and / or can be embedded in it. In addition, as the component, other components can also be used, in particular those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagated from the environment.

[0049] In one embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a compound of a multilayer structure that is stacked and connected together by applying pressure and / or heat.

[0050] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figures 1 to 7 A cross-sectional view showing a structure obtained during the execution of a method for manufacturing a component carrier according to an exemplary embodiment of the present invention, as shown in FIG. Figure 7 shown.

[0052] Figure 8 A conductive wiring structure of a component carrier obtained by a PIM structure according to an exemplary embodiment of the present invention is shown.

[0053] Fig. 9 The PIM structure is shown in Figure 2. Figure 8 Detail of the conductive wiring structure, and shows that the roughness Rz of the surface of the wiring structure can take a very small value of less than 200nm.

[0054] Fig.10 A diagram is shown which illustrates the values ​​of the roughness Ra of an electrically conductive wiring structure of a component carrier according to an exemplary embodiment of the present invention in comparison with a conventional component carrier.

[0055] Fig.11 A component carrier configured for performing radio frequency applications according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0056] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.

[0057] Before describing the exemplary embodiments in more detail with reference to the drawings, some basic considerations based on which the exemplary embodiments of the invention have been developed will be summarized.

[0058] According to an exemplary embodiment of the present invention, a component carrier (in particular a printed circuit board, PCB) having a PIM value of less than -153 dBc, preferably less than -160 dBc, for antenna applications is provided. This unique PIM performance can be obtained, for example, by ensuring a low roughness of an underlying structure (such as a copper foil) and a very low roughness of a plated structure formed by pattern plating on such an underlying structure. By appropriately controlling the roughness of the conductive wiring structure on its (in particular rising and / or falling) edges and / or on its top and / or bottom surfaces, preferably in combination with a chemical tin-type surface finishing layer on the top and / or bottom surfaces of the conductive wiring structure, it has been proven to be an effective method to reduce PIM losses in the manner described. This can in particular allow preventing communication interruptions caused by interruptions in data transmission caused by the component carrier. In addition, fluctuations in the transmission quality during wireless communications involving the component carrier can be reduced.

[0059] For example, such an architecture allows the manufacture of component carriers with antennas suitable for demanding high-frequency applications, such as those required by 4G or 5G. More specifically, the component carriers can be used for mobile applications, automotive applications (especially car-to-car applications), cloud applications, fog applications, Internet of Things (IOT) applications, etc.

[0060] Figures 1 to 7A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown, as shown in FIG. Figure 7 shown.

[0061] Reference Figure 1 , a stack 102 is provided, which includes two conductive layer structures 104 on opposite main surfaces of a central electrically insulating layer structure 106. The electrically insulating layer structure 106 may, for example, include a resin (such as an epoxy resin), optionally containing reinforcing particles such as glass fibers. For example, the electrically insulating layer structure 106 may be made of prepreg. The two conductive layer structures 104 may be copper layers laminated on opposite main surfaces of the electrically insulating layer structure 106. For example, the stack 102 may be a fully cured core with laminated copper foil.

[0062] The conductive layer structure 104 is used as a preform for a base structure 112, which in turn subsequently forms part of a conductive wiring structure 108 having a highly suitable passive intermodulation (PIM) performance. The preform of the base structure 112 on each of the top main surface and the bottom main surface of the electrically insulating layer structure 106 can have a very small thickness in the range between 5 μm and 30 μm. Preferably, the surface of the preform of the conductive base structure 112 facing the electrically insulating layer structure 106 (i.e., the lower main surface of the upper preform of the conductive base structure 112 and the upper main surface of the lower preform of the conductive base structure 112) is selected to have a low roughness Rz of less than 1 μm. The roughness between the electrically insulating layer structure 106 and the conductive base structure 112 can also be expressed as a processing roughness. This will have a positive impact on the PIM properties of the component carrier 100, which is easy to manufacture.

[0063] Figure 1 Also shown are one or more through holes 118 that may be formed in the stack 102 to extend vertically through the entire stack 102. The through holes 118 may be formed by mechanical drilling, laser drilling, etc., and may later be used to electrically connect the conductive wiring structures 108 on the opposite major surfaces of the stack 102 with a short path length. Such a short connection path for propagating electrical signals can suppress signal distortion.

[0064] Reference Figure 2 , a rapid plating process may be performed to deposit more copper material on the exposed surface of the preform of the base structure 112. As a result, another component of the conductive wiring structure 108 may be formed in the form of a preform of the plated structure 110 deposited on the preform of the base structure 112. More precisely, according to Figure 2The rapid plating process forms only a portion of the entire plated structure 110, that is, a preform of the first plating layer 122 of the plated structure 110 is formed on the previously formed preform of the base structure 112. Figure 6 As described, the second plating layer 124 of the plating structure 110 will be formed later.

[0065] Additionally, the described rapid electroplating process will also deposit conductive material (more specifically copper) on the vertical walls of the stack 102 defining the via 118. Thus, the via 118 is partially (or fully) filled with the conductive fill medium 120 to electrically connect the opposing major surfaces of the stack 102.

[0066] To promote adhesion, a chemical adhesion promoter (not shown) may also be applied to the preform of the base structure 112 prior to plating of the preform of the first plating layer 122 .

[0067] Reference Figure 3 , a resist 126 (e.g., a photoresist) is applied (particularly by lamination) to Figure 2 1. Thus, the preform of the first plating layer 122 on the preform of the first base structure 112 is covered by the resist 126.

[0068] Reference Figure 4 , Figure 3 Specific portions of the resist 126 on two opposing major surfaces of the structure shown are exposed to electromagnetic radiation 130 generated by an electromagnetic radiation source 132. The electromagnetic radiation source 132 may be, for example, a laser source configured to generate a laser such as an ultraviolet laser or a visible laser. A mask 134 (such as a film mask) having alternating transparent and opaque portions may be disposed between the electromagnetic radiation source 132 and the Figure 3 Between the structures shown for exposure.

[0069] Reference Figure 5 , showing the result of the development process. Since only selected portions of the resist 126 are irradiated with electromagnetic radiation 130, only the irradiated portions of the resist 126 remain on the stack 102, while the unirradiated portions of the resist 126 can be removed by stripping, etching, etc. As a result, patterned resist 126 remains on the two opposing major surfaces of the stack 102.

[0070] Optionally, the material of the resist 126 can also be selected so that since only selected portions of the resist 126 are irradiated with electromagnetic radiation 130, only the unirradiated portions of the resist 126 remain on the stack 102, while the irradiated portions of the resist 126 can be removed by stripping, etching, etc.

[0071] Reference Figure 6 , first make Figure 5 The structure shown is subjected to a further plating process and then to a surface finishing layer deposition process.

[0072] Therefore, the method includes continuing to form the plated structure 110 by selectively plating the second plating layer 124 on the exposed surface portions of the preform of the first plating layer 122, that is, plating the second plating layer 124 on the surface portions of the first plating layer 122 that are not covered by the rest of the patterned resist 126. For example, the formation of the second plating layer 124 can be achieved by electroplating. Therefore, the second plating layer 124 is only formed on specific surface portions of the preform of the first plating layer 122 between the rest of the resist 126. Therefore, the preform of the plated structure 110 shown includes two superimposed plating layers 122, 124, and is therefore embodied as a double layer. The exposed portions of the dielectric resist 126 will not be covered by the copper material of the second plating layer 124. From Figure 6 and Figure 2 As can be seen in FIG. 1 , the preform of the first plating layer 122 on the one hand and the second plating layer 124 on the other hand are formed in separate plating processes. The preform of the plated structure 110 may have an overall very small thickness in the range between 20 μm and 70 μm.

[0073] After forming the patterned second plating layer 124, the etch protection 113 is selectively deposited on the exposed surface portion of the second plating layer 124. The material of the etch protection 113 will not be deposited on the exposed surface portion of the dielectric resist 126.

[0074] To promote adhesion, a chemical adhesion promoter (not shown) may also be applied to the exposed surface of the preform of the first plating layer 122 before plating the second plating layer 124. To further promote adhesion, a chemical adhesion promoter (not shown) may also be applied to the exposed surface of the second plating layer 124 before depositing the etch protection 113.

[0075] Reference Figure 7 , etching and stripping can be performed. More specifically, the method includes etching away the resist 126, a portion of the preform of the first plating layer 122 below the resist 126, and a portion of the preform of the base structure 112 below the portion of the preform of the first plating layer 122. The etching protection 113 and the corresponding portions of the layer structures 112, 122 and 124 below the etching protection 113 are not etched. As a result, according to Figure 7The layer structures on the two opposite main surfaces of the electrically insulating layer structure 106 are patterned. As a result, a conductive trace is formed consisting of the base structure 112, the plating structure 110 (consisting of the first plating layer 122 and the second plating layer 124) and a part of the etching protection 113. The described patterning process can be adjusted in such a way that an antenna structure is formed from the conductive wiring structure 108.

[0076] The etching protection 113 can then be removed. A surface finishing layer 114 can then be formed on top of the conductive wiring structure 108. Preferably, the surface finishing layer 114 is made of chemical tin. Surprisingly, chemical tin has been shown to be able to adhere appropriately to very smooth copper surfaces, and therefore also to the exposed main surface of the second plating layer 124, preferably with a very small roughness Rz of less than 200 nm. However, electroplated tin or hot air leveling can also be used as the material of the surface finishing layer 114.

[0077] The described plating process can be performed in such a way that the roughness Rz of at least a portion of the surface of the conductive wiring structure 108 is preferably less than 200nm. In particular, the surface portion of the conductive wiring structure 108 associated with the (e.g. inclined) sidewall and / or the surface portion of the conductive wiring structure 108 opposite to the electrically insulating layer structure 106 can have a roughness Rz preferably less than 200nm. The surface portion of the conductive wiring structure 108 facing the electrically insulating layer structure 106 can have a low roughness Rz of less than μm. It has been proven that this smoothness of the conductive wiring structure 108 has a highly positive effect on the PIM performance of the component carrier 100 obtained. In particular, in view of the low surface roughness of the conductive wiring structure 108 and the specific selection of the surface finishing layer 114, the conductive wiring structure 108 is obtained to ensure that the value of the passive intermodulation PIM of the high-frequency electrical signal propagating along the conductive wiring structure 108 can be less than -160dBc. Therefore, it is possible to obtain the component carrier 100 according to the exemplary embodiment of the present invention, which has excellent PIM performance and thus has a suitable ability to transmit radio frequency signals with low signal loss.

[0078] The obtained component carrier 100 is embodied as a plate-like laminated printed circuit board (PCB) with excellent PIM performance. The component carrier 100 consists of a stack 102 of conductive layer structures 104 on two opposite main surfaces of a central electrically insulating layer structure 106. A conductive wiring structure 108 forming a part of the conductive layer structure 104 forms an antenna structure and is configured for high-frequency signal transmission on two opposite main surfaces of the electrically insulating layer structure 106. A chemical tin-type surface finishing layer 114 covers the exposed upper and lower surfaces of the conductive wiring structure 108. Through the plated through-holes 118, high-frequency signals can propagate along a very short and therefore low-loss path between the two opposite main surfaces of the electrically insulating layer structure 106.

[0079] Figure 8 A conductive routing structure 108 of a component carrier 100 formed by a PIM structure according to an exemplary embodiment of the present invention is shown. Fig. 9 The PIM structure is shown in Figure 2. Figure 8 Detail of the conductive wiring structure 108 is shown, and it is shown that the roughness Rz of the surface of the wiring structure 108 can take a very small value of less than 200 nm.

[0080] Fig.10 A diagram 150 is shown which illustrates the values ​​of the roughness Ra of the electrically conductive wiring structure 108 of the component carrier 100 according to an exemplary embodiment of the present invention in comparison with a conventional component carrier.

[0081] Reference numeral 151 relates to an exemplary embodiment of the present invention using tin as the surface finishing layer 114. Reference numeral 152 relates to another exemplary embodiment of the present invention using NaP as the surface finishing layer 114. Reference numeral 153 relates to another exemplary embodiment of the present invention using SiT as the surface finishing layer 114. Reference numeral 154 relates to another exemplary embodiment of the present invention using electroless nickel immersion gold (ENIG) as the surface finishing layer 114. Reference numeral 155 relates to another exemplary embodiment of the present invention using copper.

[0082] Reference numeral 156 relates to a conventional method without the above-mentioned plating and patterning process and using ENIG as a surface finishing layer. Reference numeral 157 relates to another conventional method without the above-mentioned patterning process and using standard copper.

[0083] As can be seen from the diagram 150, only five exemplary embodiments of the present invention allow obtaining a roughness Ra around a favorable value of 200 nm. In contrast, conventional methods cannot obtain sufficiently low roughness and do not exhibit sufficient PIM performance.

[0084] Fig.11 A component carrier 100 configured for performing radio frequency applications according to an exemplary embodiment of the present invention is shown.

[0085] exist Fig.11 In the component carrier 100 shown in cross section in FIG. 1 , the electronic component 116 is embedded in the stack 102 and connected to the copper wiring structure 108 between the prepreg layer structure 106 through the pad 186 and the copper filled via as a vertical through connection or conductive filling medium 120. The wiring structure 108 is embedded in the dielectric material of the electrically insulating layer structure 106. By referring to Figures 1 to 7The wiring structure 108 is formed by a method corresponding to the method described. Detail 188 shows a portion of the wiring structure 108 from above, wherein the wiring structure 108 can be configured, for example, to have a structure similar to Figure 7 In the illustrated embodiment, the electronic component 116 may be a semiconductor chip configured to perform radio frequency applications by sending electrical signals having a frequency of, for example, 10 GHz or higher via the wiring structure 108.

[0086] Due to the skin effect, electrical signals with very high frequencies will basically only propagate within the thin skin surface 197 of the conductive wiring structure 108. The thickness of the skin surface 197 depends in particular on the frequency, but may be on the order of 2 μm. The rough surfaces conventionally used to promote the adhesion of the wiring structure to the surrounding dielectric material include microstructures on the order of several microns, which can interfere with the propagation of radio frequency signals. In contrast, the wiring structure 108 of the component carrier 100 according to an exemplary embodiment of the present invention achieves an improvement in surface adhesion through the above-mentioned adhesion promoter, so that the roughening process can be made dispensable. Therefore, the surface of the wiring structure 108 can have a very small roughness. This reduces the loss of radio frequency signals.

[0087] It should be noted that the term "comprising" does not exclude other elements or steps and "a" or "an" does not exclude a plurality. Furthermore, elements described in connection with different embodiments may be combined.

[0088] It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

[0089] The implementation of the invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, several modifications using the solutions shown and according to the principle of the invention are possible, even in the case of fundamentally different embodiments.

Claims

1. A component carrier (100), wherein: The component carrier (100) is one of the following: a printed circuit board, an organic interposer, an integrated circuit substrate, and a hybrid board combining different types of component carriers of the above types of component carriers (100), and the component carrier (100) includes: A stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); A conductive wiring structure (108), the conductive wiring structure being part of the at least one conductive layer structure (104), wherein a surface portion of the conductive wiring structure (108) related to the sidewall and / or a surface portion of the conductive wiring structure (108) opposite to the electrically insulating layer structure (106) has a roughness of less than 200 nm, and a surface portion of the conductive wiring structure (108) facing the electrically insulating layer structure (106) has a low roughness of less than 1 μm; The passive intermodulation value of the signal propagating along the conductive wiring structure (108) is less than -153dBc.

2. The component carrier (100) according to claim 1, wherein: The value of the passive intermodulation is less than -155dBc.

3. The component carrier (100) according to claim 1, wherein: The value of the passive intermodulation is less than -160dBc.

4. The component carrier (100) according to claim 1, wherein: The value of the passive intermodulation is less than -165dBc.

5. The component carrier (100) according to claim 1, wherein: The value of the passive intermodulation is less than -168dBc.

6. The component carrier (100) according to claim 1, comprising the following features: in, The roughness of the entire surface of the plated structure (110) of the conductive wiring structure (108) is less than 300 nm.

7. The component carrier (100) according to claim 1, wherein: The roughness of the horizontal surface of the conductive wiring structure (108) is less than 200 nm.

8. The component carrier (100) according to claim 1, wherein: The roughness of the entire surface of the plated structure (110) of the conductive wiring structure (108) is less than 200 nm.

9. The component carrier (100) according to any one of claims 1 to 8, comprising at least one of the following features: in, The component carrier includes a surface finishing layer (114) covering at least a portion of the conductive wiring structure (108); wherein at least a portion of the surface of the conductive wiring structure (108) is covered with an adhesion promoter; wherein the component carrier comprises at least one electronic component (116); wherein the stack (102) comprises a central electrically insulating layer structure (106) covered with corresponding conductive layer structures (104) on two opposite main surfaces thereof; The stack (102) includes at least one through hole (118), which vertically extends through the at least one electrically insulating layer structure (106) and is at least partially filled with a conductive filling medium (120) for electrically connecting the conductive wiring structure (108) on two opposite main surfaces of the at least one electrically insulating layer structure (106).

10. The component carrier (100) according to claim 9, wherein: The surface finishing layer (114) includes or consists of tin.

11. The component carrier (100) according to claim 9, wherein: The surface finishing layer (114) includes or consists of chemical tin.

12. The component carrier (100) according to claim 9, wherein: The at least one electronic component (116) is at least one radio frequency semiconductor chip, which is configured to transmit and / or receive radio frequency signals via the conductive wiring structure (108), is mounted and / or embedded in the stack (102), and is electrically coupled to the conductive wiring structure (108).

13. The component carrier (100) according to any one of claims 1 to 5, wherein: The conductive wiring structure (108) includes a base structure (112), and the conductive wiring structure includes a plated structure (110) located on the base structure (112).

14. The component carrier (100) according to claim 13, wherein: The base structure (112) is located on the at least one electrically insulating layer structure (106).

15. The component carrier (100) according to claim 13, comprising at least one of the following features: in, The base structure (112) is a patterned metal foil; wherein the thickness of the base structure (112) is in the range between 5 μm and 30 μm; Wherein, the plated structure (110) is a plated copper structure; Wherein, the plating structure (110) comprises at least two superimposed plating layers (122, 124); The thickness of the plated structure (110) is within a range between 20 μm and 70 μm.

16. The component carrier (100) according to claim 15, wherein: The patterned metal foil is a patterned copper foil.

17. The component carrier (100) according to claim 13, wherein: The thickness of the base structure (112) is in the range between 10 μm and 20 μm.

18. The component carrier (100) according to claim 13, wherein: The plating structure (110) is configured as a double-layer plating.

19. The component carrier (100) according to claim 13, wherein: The thickness of the plated structure (110) is in the range of 30 μm to 50 μm.

20. The component carrier (100) according to any one of claims 1 to 5, comprising at least one of the following features: in, The conductive wiring structure (108) forms an antenna structure; wherein the component carrier comprises at least one component (116) surface mounted on and / or embedded in the component carrier (100); wherein the at least one conductive layer structure (104) comprises at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten; wherein the at least one electrically insulating layer structure (106) comprises at least one of the following: resin; FR-4; FR-5; cyanate; polyphenylene derivative; glass; prepreg; polyimide; polyamide; liquid crystal polymer; epoxy-based laminate; polytetrafluoroethylene; ceramic and metal oxide; wherein the component carrier (100) is formed as a plate; wherein the component carrier (100) is configured as one of a printed circuit board and a substrate; Therein, the component carrier (100) is configured as a laminated component carrier.

21. The component carrier (100) according to claim 20, wherein: The at least one component (116) is selected from the group consisting of: a heat transfer unit, a light-conducting element, a transmitter and / or a receiver and a further component carrier.

22. The component carrier (100) according to claim 20, wherein: The at least one component (116) is an electronic component.

23. The component carrier (100) according to claim 22, wherein: The electronic component is an active electronic component or a passive electronic component.

24. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a non-conductive inlay and / or a conductive inlay.

25. The component carrier (100) according to claim 20, wherein: The at least one component (116) is an energy harvesting unit, a signal processing component or an electromechanical transducer.

26. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a storage device, a power management component, a cryptographic component, or a magnetic element.

27. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a filter, an optoelectronic interface element, a voltage converter or an actuator.

28. The component carrier (100) according to claim 20, wherein: The at least one component (116) is an integrated circuit.

29. The component carrier (100) according to claim 20, wherein: The at least one component (116) is an electronic chip.

30. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a logic chip.

31. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a micro-electromechanical system.

32. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a microprocessor.

33. The component carrier (100) according to claim 20, wherein: The at least one component (116) is a capacitor, a resistor, an inductor, an accumulator, a switch, a camera, or an antenna.

34. The component carrier (100) according to claim 20, wherein: Any of the copper, aluminum, nickel, silver, gold, palladium and tungsten is coated with a superconducting material.

35. The component carrier (100) according to claim 34, wherein The superconducting material is graphene.

36. The component carrier (100) according to claim 20, wherein: The resin is a reinforced resin or a non-reinforced resin.

37. The component carrier (100) according to claim 20, wherein: The resin is an epoxy resin or a bismaleimide-triazine resin.

38. A method for manufacturing a component carrier (100), wherein: The component carrier (100) is one of the following: a printed circuit board, an organic interposer, an integrated circuit substrate, and a hybrid board combining different types of component carriers of the above types of component carriers (100), and the manufacturing method comprises: forming a stack (102), the stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); Forming a conductive wiring structure (108), the conductive wiring structure (108) being part of the at least one conductive layer structure (104), wherein a surface portion of the conductive wiring structure (108) related to the sidewall and / or a surface portion of the conductive wiring structure (108) opposite to the electrically insulating layer structure (106) has a roughness of less than 200 nm, and a surface portion of the conductive wiring structure (108) facing the electrically insulating layer structure (106) has a low roughness of less than 1 μm; The conductive wiring structure (108) is formed so that the passive intermodulation value of the signal propagating along the conductive wiring structure (108) is less than -153dBc.

39. The manufacturing method according to claim 38, wherein: The manufacturing method includes forming a conductive wiring structure (108) having a base structure (112) and having a plated structure (110), the plated structure (110) being disposed on the base structure (112).

40. The manufacturing method according to claim 39, wherein: The base structure (112) is arranged on the at least one electrically insulating layer structure (106).

41. The manufacturing method according to claim 39, comprising at least one of the following features: in, The manufacturing method comprises attaching a metal foil to the at least one electrically insulating layer structure (106) as the base structure (112) or as a preform of the base structure (112); The manufacturing method comprises plating a conductive material as the plated structure (110) or as a preform of the plated structure (110) on the base structure (112) or on a preform of the base structure (112).

42. The manufacturing method according to claim 39, wherein: The manufacturing method comprises laminating a metal foil to the at least one electrically insulating layer structure (106) as the base structure (112) or as a preform of the base structure (112).

43. The manufacturing method according to claim 39, wherein: The manufacturing method comprises electroplating a conductive material as the plated structure (110) or as a preform of the plated structure (110) on the base structure (112) or on a preform of the base structure (112).

44. The manufacturing method according to any one of claims 39 to 43, wherein: The manufacturing method comprises forming a plated structure (110) having a first plated layer (122) and a second plated layer (124), wherein the first plated layer (122) is located on the base structure (112), and the second plated layer (124) is located on the first plated layer (122), wherein the first plated layer (122) and the second plated layer (124) are formed in independent plating processes.

45. The manufacturing method according to claim 44, comprising at least one of the following features: in, The manufacturing method comprises: plating the first plating layer (122) on the base structure (112) before applying the resist (126), and plating the second plating layer (124) on only a portion of the first plating layer (122) after applying the resist (126); The manufacturing method comprises: forming the first plating layer (122) by rapid plating.

46. ​​The manufacturing method according to claim 45, wherein: The manufacturing method includes removing a portion of the first plating layer (122) and a portion of the base structure (112) together by etching after applying the resist (126).

47. The manufacturing method according to claim 46, wherein: The manufacturing method includes applying etching protection (113) to the second plating layer (124) before etching.

48. Method for using a component carrier (100) according to any one of claims 1 to 37 for high-frequency applications.

49. The method of use according to claim 48, comprising at least one of the following features: in, The component carrier (100) is used for wireless communication; The component carrier (100) is used for high-frequency applications above 1 GHz.

50. The method of use according to claim 48, wherein: The component carrier (100) is used for wireless communication according to 5G.

51. The method of use according to claim 48, wherein: The component carrier (100) is used for high frequency applications above 100 GHz.

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