A high-precision oscillator circuit

Abstract

The present invention provides a high-precision oscillator circuit, which includes a temperature compensation circuit and a clock generation circuit, wherein the temperature compensation circuit includes a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first bandgap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; the clock generation circuit includes a first comparator, a second comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate; the high-precision oscillator circuit of the present invention introduces the first comparator and the second comparator to reduce the change of the output frequency caused by the temperature change; in general, the structure is simple, easy to integrate, and the output voltage is stable.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits in SIM card technology, and in particular to a high-precision oscillator circuit. Background Art

[0002] The present invention relates to the technical field of integrated circuits in SIM technology, wherein the stability of an oscillator output clock is becoming increasingly important to the stability of system operation, and its performance is directly related to whether a SIM card can operate normally.

[0003] With the application of large-capacity and high-security SIM cards, the system has higher and higher requirements for the speed and stability of the clock. Oscillators are generally divided into quartz crystal oscillators, LC oscillators, and RC oscillators. Due to the advantages of simple structure, easy oscillation, small area, low power consumption, and easy integration, RC oscillators are widely used in the field of integrated circuits. However, the output frequency of the RC oscillator is easily affected by temperature and process deviations, and the accuracy will be relatively poor. Therefore, the design and research of high-precision and low-cost RC oscillator circuits are of great significance.

[0004] See also Figure 1 , is a commonly used RC oscillator circuit structure, and its working principle is as follows: in the RC oscillator circuit structure, the RC oscillator is a ring oscillator. Assume that the node N3 is subjected to a small interference, resulting in a positive jump. After a delay of T by the first inverter INV1 and the second capacitor C2, it is amplified into a larger negative jump signal N1, and then after a delay of T by the second inverter INV2 and the third capacitor C3, it is further amplified into a larger positive jump signal N2, and then after a delay of T by the third inverter INV3 and the first capacitor C1, it is further amplified into a larger negative jump signal N3, and after 3T, the N3 signal becomes a positive jump again, forming a positive feedback, generating self-excited oscillation, and the period is 6T.

[0005] However, the above RC oscillator circuit still has some shortcomings: first, the capacitors and devices in the inverter in the above circuit are easily affected by process deviations and temperature, making the output clock frequency unstable; moreover, IREF is generally generated by a bandgap reference voltage, which is easily affected by temperature and process deviations, resulting in unstable output clock frequency. Summary of the invention

[0006] In view of the deficiencies in the above-mentioned prior art, an object of the present invention is to provide a high-precision oscillator circuit, including a temperature compensation circuit and a clock generation circuit, which has the characteristics of easy integration and stable output voltage.

[0007] In order to achieve the above technical purpose, the technical solution adopted by the present invention is:

[0008] A high-precision oscillator circuit, the oscillator circuit comprising a temperature compensation circuit and a clock generation circuit; wherein the temperature compensation circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first bandgap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; one end of the second resistor is connected to one end of the first resistor, the other end of the first resistor and the drain end of the fifth PMOS transistor are connected to the negative input end of the first amplifier, the gate end of the fifth PMOS transistor, the gate end of the third PMOS transistor and the gate end of the fourth PMOS transistor are connected, the source end and substrate of the fifth PMOS transistor, the source end and substrate of the third PMOS transistor, the source end and substrate of the fourth PMOS transistor, the substrate of the first PMOS transistor, the substrate of the second NMOS transistor, the power supply end of the first amplifier and the voltage supply end are connected to the voltage supply end of the first amplifier. The first amplifier is connected to a source terminal VDD, a positive input terminal of the first amplifier is connected to a bandgap reference voltage source VREF, a drain terminal of the third PMOS transistor is connected to the source terminal of the first PMOS transistor, a drain terminal of the fourth PMOS transistor is connected to the source terminal of the second NMOS transistor, a gate terminal of the first PMOS transistor is connected to the gate terminal of the first NMOS transistor and serves as a first input terminal, a gate terminal of the second PMOS transistor is connected to the gate terminal of the second NMOS transistor and serves as a second input terminal, a drain terminal of the first PMOS transistor and one end of the first capacitor are connected to the drain terminal of the first NMOS transistor and serve as a first output terminal, a drain terminal of the second PMOS transistor and one end of the second capacitor are connected to the drain terminal of the second NMOS transistor and serve as a second output terminal, the other end of the second resistor, the other end of the first capacitor, the other end of the second capacitor, the source terminal and substrate of the first NMOS transistor, the source terminal and substrate of the second NMOS transistor, and a ground terminal of the first amplifier are connected to a ground terminal VSS;

[0009] The clock generating circuit comprises a first comparator, a second comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate; the positive input terminal of the first comparator and the positive input terminal of the second comparator are connected to a bandgap reference voltage VREF, the negative input terminal of the first comparator is connected to a second output terminal in the temperature compensation circuit, the negative input terminal of the second comparator is connected to a first output terminal in the temperature compensation circuit, the output terminal of the first comparator is connected to an input terminal of the first inverter, the output terminal of the second comparator is connected to an input terminal of the second inverter, the output terminal of the first inverter is connected to an input terminal of the first AND gate, the output terminal of the second inverter is connected to an input terminal of the second AND gate, the other input terminal of the first AND gate and the output terminal of the second AND gate are connected to an input terminal of the third AND gate, the other input terminal of the second AND gate and the output terminal of the first AND gate are connected to the fourth AND gate. An input end is connected to each other, the other input end of the third AND gate and the output end of the fourth AND gate are connected to the input end of the fourth inverter, the other input end of the fourth AND gate and the output end of the third AND gate are connected to the input end of the third inverter, the output end of the third inverter serves as the first input end, and the output end of the fourth inverter serves as the second input end, the power supply end of the first comparator, the power supply end of the second comparator, the power supply end of the first inverter, the power supply end of the second inverter, the power supply end of the third inverter, the power supply end of the fourth inverter, the power supply end of the first AND gate, the power supply end of the second AND gate, the power supply end of the third AND gate, and the power supply end of the fourth AND gate are connected to the power supply end VDD, and the ground end of the first comparator, the ground end of the second comparator, the ground end of the first inverter, the ground end of the second inverter, the ground end of the third inverter, the ground end of the fourth inverter, the ground end of the first AND gate, the ground end of the second AND gate, the ground end of the third AND gate, and the ground end of the fourth AND gate are connected to the ground end VSS.

[0010] Due to the adoption of the above structure, the present invention has the following advantages compared with the existing technical solutions:

[0011] First, in the high-precision oscillator circuit of the present invention, a first resistor and a second resistor are introduced, the first resistor has a positive temperature characteristic, and the second resistor has a negative temperature characteristic, so that the current flowing through the fifth PMOS transistor connected to the first resistor has a certain temperature coefficient, and at the same time, the current flowing through the third PMOS transistor has the same temperature coefficient, so as to compensate for the change caused by the temperature change of the first output terminal IN1 and the second output terminal IN2;

[0012] Secondly, in the high-precision oscillator circuit of the present invention, a first comparator and a second comparator are introduced to reduce the change of the output frequency caused by temperature change;

[0013] Moreover, in the high-precision oscillator circuit of the present invention, the first AND gate AND1, the second AND gate AND2, the third AND gate AND3 and the fourth AND gate AND4 are introduced, so that the duty cycle of the output clock is about 50%;

[0014] Finally, the high-precision oscillator circuit of the present invention has a simple structure, is easy to integrate, and has a stable output voltage.

[0015] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0017] Figure 1 It is a commonly used RC oscillator circuit structure;

[0018] Figure 2 This is a high-precision oscillator circuit in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] See also Figure 2 1 is a high-precision oscillator circuit in a specific embodiment of the present invention. The high-precision oscillator circuit in this specific embodiment includes a temperature compensation circuit 101 and a clock generation circuit 102 .

[0022] In the high-precision oscillator circuit, the temperature compensation circuit 101 includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first amplifier AMP1, a first bandgap reference voltage source VREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; one end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the first resistor R1. The first amplifier AMP1 is connected to the power supply terminal VDD, and the first amplifier AMP1 is connected to the power supply terminal VDD. The positive input terminal of the amplifier AMP1 is connected to the bandgap reference voltage source VREF, the drain terminal of the third PMOS transistor PM3 is connected to the source terminal of the first PMOS transistor PM1, the drain terminal of the fourth PMOS transistor PM4 is connected to the source terminal of the second NMOS transistor NM2, the gate terminal of the first PMOS transistor PM1 is connected to the gate terminal of the first NMOS transistor NM1 and serves as the first input terminal VOUT1, the gate terminal of the second PMOS transistor PM2 is connected to the gate terminal of the second NMOS transistor NM2 and serves as the second input terminal VOUT2, the first PMOS transistor A drain terminal of the first PMOS transistor PM1 and one end of the first capacitor C1 are connected to the drain terminal of the first NMOS transistor NM1 and serve as a first output terminal IN1; a drain terminal of the second PMOS transistor PM2 and one end of the second capacitor C2 are connected to the drain terminal of the second NMOS transistor NM2 and serve as a second output terminal IN2; the other end of the second resistor R2, the other end of the first capacitor C1, the other end of the second capacitor C2, the source terminal and substrate of the first NMOS transistor NM1, the source terminal and substrate of the second NMOS transistor NM2, and the ground terminal of the first amplifier AMP1 are connected to the ground terminal VSS.

[0023] In the high-precision oscillator circuit, the clock generating circuit 102 includes a first comparator COM1, a second comparator COM2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3 and a fourth AND gate AND4; the positive input terminal of the first comparator COM1 and the positive input terminal of the second comparator COM2 are connected to the bandgap reference voltage VREF, the negative input terminal of the first comparator COM1 is connected to the second output terminal IN2 in the temperature compensation circuit, and the negative input terminal of the second comparator COM2 is connected to the second output terminal IN2 in the temperature compensation circuit. The first output terminal IN1 of the first comparator COM1 is connected to the input terminal of the first inverter INV1, the output terminal of the second comparator COM2 is connected to the input terminal of the second inverter INV2, the output terminal of the first inverter INV1 is connected to an input terminal of the first AND gate AND1, the output terminal of the second inverter INV2 is connected to an input terminal of the second AND gate AND2, the other input terminal of the first AND gate AND1 and the output terminal of the second AND gate AND2 are connected to an input terminal of the third AND gate AND3, the other input terminal of the second AND gate AND2 and the output terminal of the first AND gate AND1 are connected to the fourth AND gate AND3. An input end of ND4 is connected, the other input end of the third AND gate AND3 and the output end of the fourth AND gate AND4 are connected to the input end of the fourth inverter INV4, the other input end of the fourth AND gate AND4 and the output end of the third AND gate AND3 are connected to the input end of the third inverter INV3, the output end of the third inverter INV3 serves as the first input end VOUT1, the output end of the fourth inverter INV4 serves as the second input end VOUT2, the power supply end of the first comparator COM1, the power supply end of the second comparator COM2, the power supply end of the first inverter INV1, the power supply end of the second inverter INV2, and the third inverter INV3 The power supply end of the first AND gate AND1, the power supply end of the second AND gate AND2, the power supply end of the third AND gate AND3, and the power supply end of the fourth AND gate AND4 are connected to the power supply end VDD, and the ground end of the first comparator COM1, the ground end of the second comparator COM2, the ground end of the first inverter INV1, the ground end of the second inverter INV2, the ground end of the third inverter INV3, the ground end of the fourth inverter INV4, the ground end of the first AND gate AND1, the ground end of the second AND gate AND2, the ground end of the third AND gate AND3, and the ground end of the fourth AND gate AND4 are connected to the ground end VSS.

[0024] See also Figure 2When the high-precision oscillator circuit is working, the bandgap reference voltage VREF in the temperature compensation circuit is a reference voltage that is independent of temperature, the first resistor R1 has a positive temperature characteristic, and the second resistor R2 has a negative temperature characteristic, so that the current flowing through the fifth PMOS transistor PM5 has a certain temperature coefficient. At the same time, the current flowing through the third PMOS transistor PM3 and the fifth PMOS transistor PM5 have the same temperature coefficient, compensating for the changes of the rising edge of the first output terminal IN1 and the second output terminal IN2 caused by temperature changes. The falling edge will be faster due to the strong pull-down of the first NMOS transistor NM1 and the second NMOS transistor NM2, so the falling edge will be less affected by temperature changes.

[0025] The first output terminal IN1 and the second output terminal IN2 in the temperature compensation circuit are compared with the bandgap reference voltage VREF in the temperature compensation circuit through the first comparator COM1 and the second comparator COM2 to generate the rising edge of the high-precision oscillator circuit. Since the rising edge voltages of the first output terminal IN1 and the second output terminal IN2 in the temperature compensation circuit are little affected by temperature, the rising edge of the output clock of the high-precision oscillator circuit is little affected by temperature; the falling edges of the first output terminal IN1 and the second output terminal IN2 in the temperature compensation circuit are relatively fast and are little affected by temperature. Therefore, the falling edge of the output clock of the high-precision oscillator circuit is also little affected by temperature.

[0026] Since the duty cycle of the clocks generated by the first comparator COM1 and the second comparator COM2 may be less than or greater than 50%, which is not conducive to system use, the first AND gate AND1, the second AND gate AND2, the third AND gate AND3 and the fourth AND gate AND4 in the clock generating circuit form a two-stage RS trigger, and the clocks generated by the first comparator COM1 and the second comparator COM2 are shaped into a clock with a duty cycle of about 50% for system use.

[0027] It can be seen from the above that the specific embodiment of the present invention effectively improves the stability of the clock output by the oscillator circuit through the speed compensation circuit 101 and the clock generation circuit 102.

[0028] It should be noted that the above embodiments are only schematic illustrations of the basic concept of the present invention, and the component circuits related to the present invention are not drawn according to the number, shape, device arrangement, and connection method of the component circuits in actual implementation. The type, number, connection method, device arrangement, and device parameters of each circuit in actual implementation can be changed at will.

[0029] The above-described embodiments are only preferred embodiments of the present invention and cannot limit the extension of the technical solution of the present invention. Any modification, equivalent change and obvious replacement of the known technology made by those skilled in the art on the basis of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-precision oscillator circuit, characterized in that: The oscillator circuit includes a temperature compensation circuit and a clock generation circuit; wherein, The temperature compensation circuit includes a first capacitor, a second capacitor, a first resistor, a second resistor, a first amplifier, a first bandgap reference voltage source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; one end of the second resistor is connected to one end of the first resistor, the other end of the first resistor and the drain end of the fifth PMOS transistor are connected to the negative input end of the first amplifier, the gate end of the fifth PMOS transistor, the gate end of the third PMOS transistor and the gate end of the fourth PMOS transistor are connected, the source end and substrate of the fifth PMOS transistor, the source end and substrate of the third PMOS transistor, the source end and substrate of the fourth PMOS transistor, the substrate of the first PMOS transistor, the substrate of the second NMOS transistor, and the power supply end of the first amplifier are connected to the power supply end VDD, the positive input end of the first amplifier is connected to the bandgap reference voltage VREF, the drain end of the third PMOS transistor is connected to the negative input end of the first amplifier, The source terminal of the first PMOS transistor is connected, the drain terminal of the fourth PMOS transistor is connected to the source terminal of the second NMOS transistor, the gate terminal of the first PMOS transistor is connected to the gate terminal of the first NMOS transistor and serves as a first input terminal, the gate terminal of the second PMOS transistor is connected to the gate terminal of the second NMOS transistor and serves as a second input terminal, the drain terminal of the first PMOS transistor and one end of the first capacitor are connected to the drain terminal of the first NMOS transistor and serve as a first output terminal, the drain terminal of the second PMOS transistor and one end of the second capacitor are connected to the drain terminal of the second NMOS transistor and serve as a second output terminal, the other end of the second resistor, the other end of the first capacitor, the other end of the second capacitor, the source terminal and substrate of the first NMOS transistor, the source terminal and substrate of the second NMOS transistor, and the ground terminal of the first amplifier are connected to the ground terminal VSS; the bandgap reference voltage VREF in the temperature compensation circuit is a reference voltage that is independent of temperature, the first resistor has a positive temperature characteristic, and the second resistor has a negative temperature characteristic; The clock generating circuit comprises a first comparator, a second comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate; the positive input terminal of the first comparator and the positive input terminal of the second comparator are connected to a bandgap reference voltage VREF, the negative input terminal of the first comparator is connected to a second output terminal in the temperature compensation circuit, the negative input terminal of the second comparator is connected to a first output terminal in the temperature compensation circuit, the output terminal of the first comparator is connected to an input terminal of the first inverter, the output terminal of the second comparator is connected to an input terminal of the second inverter, the output terminal of the first inverter is connected to an input terminal of the first AND gate, the output terminal of the second inverter is connected to an input terminal of the second AND gate, the other input terminal of the first AND gate and the output terminal of the second AND gate are connected to an input terminal of the third AND gate, the other input terminal of the second AND gate and the output terminal of the first AND gate are connected to the fourth AND gate. An input end is connected to each other, the other input end of the third AND gate and the output end of the fourth AND gate are connected to the input end of the fourth inverter, the other input end of the fourth AND gate and the output end of the third AND gate are connected to the input end of the third inverter, the output end of the third inverter serves as the first input end, and the output end of the fourth inverter serves as the second input end, the power supply end of the first comparator, the power supply end of the second comparator, the power supply end of the first inverter, the power supply end of the second inverter, the power supply end of the third inverter, the power supply end of the fourth inverter, the power supply end of the first AND gate, the power supply end of the second AND gate, the power supply end of the third AND gate, and the power supply end of the fourth AND gate are connected to the power supply end VDD, and the ground end of the first comparator, the ground end of the second comparator, the ground end of the first inverter, the ground end of the second inverter, the ground end of the third inverter, the ground end of the fourth inverter, the ground end of the first AND gate, the ground end of the second AND gate, the ground end of the third AND gate, and the ground end of the fourth AND gate are connected to the ground end VSS.

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