Display panel and manufacturing method thereof

Abstract

A display panel and a method for manufacturing the display panel are disclosed. The display panel includes a base substrate, a circuit layer located on the base substrate, and a display element layer located on the circuit layer. Among them, the circuit layer includes an active layer located on the base substrate and containing boron and fluorine, a control electrode located on the active layer, and a control electrode insulating layer located between the active layer and the control electrode. Among them, the active layer includes a core layer and a surface layer, and the concentration of boron in the core layer is greater than the concentration of fluorine; the surface layer is located on the core layer and the concentration of fluorine in the surface layer is greater than the concentration of boron.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0044117, filed on April 16, 2019, the entire content of which is incorporated herein by reference. Technical Field

[0003] Aspects of some exemplary embodiments of the present disclosure herein relate to a display panel and a method of manufacturing a display panel. Background Art

[0004] Recently, in order to promote portability and improve user convenience, display devices that can be folded or rolled up by using a bendable flexible display member are being developed.

[0005] Such a flexible display device may use a polymer film as a substrate, so that its shape can be freely deformed. When an organic material such as a polymer film is used as a substrate, there may be limitations regarding processing temperature, etc. during subsequent processes of forming a circuit layer, etc. on the substrate, in order to minimize or reduce damage to the substrate. For example, compared with the case where a high - temperature semiconductor process is performed, the case where a transistor is formed on the substrate may have a problem of performance degradation due to limitations in processing temperature.

[0006] The above information disclosed in this background section is only for enhancing the understanding of the background, and thus the information discussed in this background section does not necessarily constitute the prior art. Summary of the Invention

[0007] Aspects of some exemplary embodiments of the present disclosure herein relate to a display panel and a method of manufacturing a display panel, and for example, relate to a display panel having a circuit layer containing polysilicon and a method of manufacturing a display panel.

[0008] Aspects of some exemplary embodiments of the present disclosure may include a display panel, wherein the transistors included in the circuit layer have relatively improved performance and reliability.

[0009] Aspects of some exemplary embodiments of the present disclosure may further include a method of manufacturing a display panel that exhibits relatively improved reliability characteristics by controlling manufacturing steps of an active layer and a doping material.

[0010] According to some exemplary embodiments of the inventive concept, a display panel includes: a substrate, a circuit layer on the substrate, and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the substrate and containing boron and fluorine, a control electrode on the active layer, and a control electrode insulating layer between the active layer and the control electrode, wherein the active layer includes a core layer and a surface layer, the concentration of boron in the core layer is greater than the concentration of fluorine, the surface layer is on the core layer and the concentration of fluorine in the surface layer is greater than the concentration of boron.

[0011] According to some exemplary embodiments, the surface layer may include a first surface layer adjacent to the control electrode insulating layer and a second surface layer adjacent to the substrate.

[0012] According to some exemplary embodiments, the concentration of fluorine in each of the first surface layer and the second surface layer may be greater than the concentration of fluorine in the core layer.

[0013] According to some exemplary embodiments, the ratio of the thickness of the surface layer to the total thickness of the active layer may be 10% to 30%.

[0014] According to some exemplary embodiments, the substrate may be a polyimide substrate.

[0015] According to some exemplary embodiments, the active layer may include a channel region overlapping with the control electrode, and a first ion-doped region and a second ion-doped region respectively located on both sides of the channel region, wherein the concentration of boron in each of the first ion-doped region and the second ion-doped region is greater than the concentration of boron in the channel region.

[0016] According to some exemplary embodiments, the circuit layer may further include an input electrode connected to the first ion-doped region and an output electrode connected to the second ion-doped region.

[0017] According to some exemplary embodiments, the display element layer may include a first electrode electrically connected to the output electrode, a second electrode facing the first electrode, and a light-emitting layer between the first electrode and the second electrode.

[0018] According to some exemplary embodiments, the display element layer may include an organic electroluminescent element or a quantum dot light-emitting element.

[0019] According to some exemplary embodiments, the display panel may further include a buffer layer between the substrate and the active layer.

[0020] According to some exemplary embodiments of the inventive concept, a display panel including at least one folding region includes: a substrate, a circuit layer on the substrate, and a display element layer on the circuit layer and including light-emitting elements, wherein the circuit layer includes an active layer on the substrate and containing boron and fluorine, a control electrode on the active layer, and a control electrode insulating layer between the active layer and the control electrode, wherein the concentration of fluorine at a surface of the active layer adjacent to the control electrode insulating layer is greater than the concentration of fluorine in a core portion of the active layer.

[0021] According to some exemplary embodiments, the active layer may include a channel region overlapping with the control electrode and first and second ion-doped regions respectively located on both sides of the channel region, wherein the concentration of boron in each of the first and second ion-doped regions is greater than the concentration of boron in the channel region.

[0022] According to some exemplary embodiments, the substrate may include polyimide.

[0023] According to some exemplary embodiments of the inventive concept, in a method for manufacturing a display panel, the method includes forming a circuit layer and forming a display element layer, wherein forming the circuit layer includes: disposing a preliminary active layer containing amorphous silicon on a substrate, first doping the preliminary active layer with a first ion, second doping the first-doped preliminary active layer with a second ion different from the first ion, forming an active layer by providing a laser to the second-doped preliminary active layer, disposing a control electrode insulating layer on the active layer, forming a control electrode on the control electrode insulating layer, third doping the active layer with the first ion, and heat-treating the active layer.

[0024] According to some exemplary embodiments, the first ion may be a boron ion and the second ion may be a fluorine ion.

[0025] According to some exemplary embodiments, disposing the preliminary active layer may be depositing amorphous silicon.

[0026] According to some exemplary embodiments, forming the active layer by providing a laser may include forming polycrystalline silicon by providing a laser to amorphous silicon.

[0027] According to some exemplary embodiments, third doping the active layer may include using the control electrode as a mask to form an ion-doped region that does not overlap with the control electrode.

[0028] According to some exemplary embodiments, heat-treating the active layer may activate the active layer by providing heat of 250°C to 480°C.

[0029] According to some exemplary embodiments, the substrate may include polyimide. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate aspects of some exemplary embodiments of the inventive concept and, together with the specification, are used to explain aspects of some exemplary embodiments of the inventive concept. In the drawings:

[0031] Figure 1 is a perspective view of a display device according to some exemplary embodiments of the inventive concept;

[0032] Figure 2 shows Figure 1 a view of the folded state of the display device shown in;

[0033] Figure 3 is a perspective view of a display device according to some exemplary embodiments of the inventive concept;

[0034] Figure 4 shows Figure 3 a view of the folded state of the display device shown in;

[0035] Figure 5 is a cross-sectional view of a display device according to some exemplary embodiments of the inventive concept;

[0036] Figure 6 is a plan view of a display panel according to some exemplary embodiments of the inventive concept;

[0037] Figure 7 is an equivalent circuit diagram of a pixel included in a display panel according to some exemplary embodiments of the inventive concept;

[0038] Figure 8 is a cross-sectional view of a display panel according to some exemplary embodiments of the inventive concept;

[0039] Figure 9 shows Figure 8 a view of an enlarged view of region AA of;

[0040] Figure 10A schematically shows a bonding state at an interface between an active layer and a control electrode insulating layer in a display panel according to some exemplary embodiments of the inventive concept;

[0041] Figure 10B schematically shows a bonding state at an interface between an active layer and a control electrode insulating layer in a display panel;

[0042] Figure 11is a flowchart showing a method for manufacturing a display panel according to some exemplary embodiments of the inventive concept;

[0043] Figures 12A to 12F is a view showing a method for manufacturing a display panel according to some exemplary embodiments of the inventive concept;

[0044] Figure 13 is a graph showing the distribution of fluorine atoms;

[0045] Figure 14A is a graph showing the change in threshold voltage; and

[0046] Figure 14B is a graph showing the afterimage retention time. DETAILED DESCRIPTION

[0047] The inventive concept may be modified in many alternative forms, and thus, aspects of some exemplary embodiments will be shown in the drawings and described in more detail. However, it should be understood that the inventive concept is not intended to be limited to the specific forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the inventive concept.

[0048] In the present disclosure, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, it means that the element may be directly disposed on / directly connected to / directly coupled to the other element, or a third element may be positioned therebetween. Additionally, in the present disclosure, being "on" includes not only the case of being above but also the case of being below.

[0049] Meanwhile, in the present disclosure, "directly disposed" or "directly positioned" or "directly located" means that no layer, film, region, plate, etc. is added between a part of a layer, film, region, plate, etc. and other parts. For example, "directly disposed" may mean being disposed without another member (such as an adhesive member) between two layers or two members.

[0050] Like reference numerals denote like elements. Further, in the drawings, the thickness, ratio, and dimensions of elements are exaggerated for effective description of the technical content.

[0051] The term "and / or" includes all combinations of one or more of the related configurations that can be defined.

[0052] It will be understood that although terms such as "first", "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments of the inventive concept, a first element may be named a second element, and similarly, a second element may be named a first element. Unless the context clearly indicates otherwise, terms in the singular form may include the plural form.

[0053] In addition, terms such as "below", "under", "above", "on" etc. are used to describe the relationship of the configurations shown in the drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms defined in a general dictionary should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless they are clearly defined as such herein.

[0055] It should be understood that the terms "comprising" or "having" are intended to indicate the presence of the features, integers, steps, operations, elements, components, or combinations thereof set forth in the present disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0056] Hereinafter, a display panel according to some exemplary embodiments of the inventive concept and a method for manufacturing a display panel according to some exemplary embodiments of the inventive concept will be described in more detail with reference to the drawings.

[0057] Figure 1 is a perspective view of a display device according to some exemplary embodiments of the inventive concept. Figure 2 shows Figure 1 a folded state of the display device shown in Figure 3 is a perspective view of a display device according to some exemplary embodiments of the inventive concept, and Figure 4 shows Figure 3 a folded state of the display device shown in Figures 1 to 4 In

[0058] Reference Figure 1, according to some exemplary embodiments, the display device DD may have a rectangular shape having a long side extending in the direction of the first direction axis DR1 and a short side extending in the direction of the second direction axis DR2 that intersects the first direction axis DR1. However, embodiments of the inventive concept are not limited thereto. The display device DD may have various shapes on a plane, for example, a circular shape, a polygonal shape, etc. The display device DD may be a flexible display device.

[0059] In the display device DD according to some exemplary embodiments, a display surface DS on which an image IM is displayed may be parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2. A normal direction of the display surface DS (i.e., a thickness direction of the display device DD) is indicated by the direction of the third direction axis DR3. A front surface (or an upper surface) and a rear surface (or a lower surface) of each component are distinguished by the direction of the third direction axis DR3. However, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are relative concepts and may be converted into different directions. Hereinafter, the first to third directions are the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are given the same reference numerals as the corresponding direction axes.

[0060] According to some exemplary embodiments, the display device DD may include a folding region FA and a non-folding region NFA. Refer to Figure 1 and Figure 2 , the display device DD may include a folding region FA and a plurality of non-folding regions NFA. The folding region FA is located between the non-folding regions NFA, and the folding region FA and the non-folding regions NFA may be arranged adjacent to each other in the direction of the first direction axis DR1.

[0061] The folding region FA may be a portion that can be deformed into a folded shape with respect to a folding axis FX extending in the direction of the second direction axis DR2. The folding region FA may have a radius of curvature RD of 5 mm or less.

[0062] Figure 1 and Figure 2 illustrates an example of one folding region FA and two non-folding regions NFA. However, the number of the folding region FA and the non-folding regions NFA is not limited thereto. For example, the display device DD may include more than two non-folding regions NFA and a plurality of folding regions FA located between the non-folding regions NFA.

[0063] In a display device DD according to some exemplary embodiments, non-fold regions NFA may be arranged symmetrically with respect to a fold region FA. However, embodiments of the inventive concept are not limited thereto. The fold region FA is located between the non-fold regions NFA, but areas of two non-fold regions NFA facing each other with respect to the fold region FA may be different.

[0064] A display surface DS of the display device DD may include a display region DA and a non-display region NDA surrounding the display region DA. The display region DA displays an image, and the non-display region NDA may not display an image. The non-display region NDA surrounds the display region DA and may define an edge of the display device DD.

[0065] Reference Figure 2 , the display device DD may be a foldable display device that can be folded or unfolded. For example, the fold region FA may be bent with respect to a fold axis FX parallel to a second direction axis DR2 so that the display device DD is folded. The fold axis FX may be defined as a short axis parallel to a short side of the display device DD.

[0066] When the display device DD is folded, the non-fold regions NFA face each other, and the display device DD may be folded inward so that the display surface DS is not exposed to the outside. However, embodiments of the inventive concept are not limited thereto. Different from that shown in the figures, the display device DD may be folded outward so that the display surface DS is exposed to the outside.

[0067] In addition to the folding operation, Figure 3 the display device DD-a shown in Figure 1 may have a configuration substantially the same as the configuration of the display device DD shown in Figure 3 and Figure 4 . Therefore, hereinafter, the folding operation will be mainly described in the description of the display device DD-a shown in

[0068] Reference Figure 3 and Figure 4 , the display device DD-a may include a fold region FA-a and a plurality of non-fold regions NFA-a. The fold region FA-a is located between the non-fold regions NFA-a, and the fold region FA-a and the non-fold regions NFA-a may be arranged adjacent to each other on a second direction axis DR2.

[0069] The fold region FA-a may be bent with respect to a fold axis FX-a parallel to a first direction axis DR1 so that the display device DD-a is folded. The fold axis FX-a may be defined as a long axis parallel to a long side of the display device DD-a. Figure 1 The display device DD shown in Figure 3 may be folded with respect to a short axis, while the display device DD-a shown in Figure 4In the figure, the display device DD-a is shown as being folded inward such that the display surface DS is not exposed to the outside. However, embodiments of the inventive concept are not limited thereto. The display device DD-a is foldable with respect to the long axis and can be folded outward.

[0070] Hereinafter, in the description of a display panel according to some exemplary embodiments, a display panel included in a display device DD foldable with respect to the short axis will be described. However, the embodiments are not limited thereto. The content described below can be applied to a display panel included in a display device DD-a foldable with respect to the long axis.

[0071] In addition, in Figures 1 to 4 a foldable display device is shown and described. However, embodiments of the inventive concept are not limited thereto. According to some exemplary embodiments to be described in more detail later, the content of the display device and the display panel can also be applied to a curved display device, a rollable display device, a flat rigid display device, a curved rigid display device, etc.

[0072] Figure 5 is a cross-sectional view of a display device according to some exemplary embodiments of the inventive concept. Figure 5 may be a cross-sectional view corresponding to line I-I' of Figure 1 is a plan view of a display panel according to some exemplary embodiments of the inventive concept. Figure 6 is an equivalent circuit diagram of a pixel according to some exemplary embodiments of the present invention. Figure 7 is a cross-sectional view showing a display panel according to some exemplary embodiments of the inventive concept. Figure 8 is a cross-sectional view showing Figure 9 a part of Figure 8 is a cross-sectional view of a part of

[0073] According to some exemplary embodiments, the display device DD may include a display panel DP and an input sensing unit TP located on the display panel DP.

[0074] According to some exemplary embodiments, the display panel DP may include a substrate BS, a circuit layer DP-CL located on the substrate BS, a display element layer DP-EL located on the circuit layer DP-CL, and a packaging layer TFE covering the display element layer DP-EL.

[0075] The input sensing unit TP may be located on the packaging layer TFE of the display panel DP. The input sensing unit TP may be directly disposed on the packaging layer TFE of the display panel DP.

[0076] The input sensing unit TP senses an external input and converts the external input into a predetermined input signal, and may provide the input signal to the display panel DP. For example, in a display device DD according to some exemplary embodiments, the input sensing unit TP may be a touch sensing unit for sensing a touch. The input sensing unit TP may sense a direct touch of a user, an indirect touch of a user, a direct touch of an object, an indirect touch of an object, etc. At the same time, the input sensing unit TP may sense at least one of the position and intensity (pressure) of an externally applied touch. The input sensing unit TP according to some exemplary embodiments of the inventive concept may have various configurations or may be composed of various materials, but is not limited to any one embodiment. The input sensing unit TP may include a plurality of sensing electrodes for sensing an external input. The sensing electrodes may sense an external input in a capacitive manner. The display panel DP receives an input signal from the input sensing unit TP and may generate an image corresponding to the input signal.

[0077] The display panel DP may include a folding area FA and a non-folding area NFA. The display panel DP according to some exemplary embodiments may include at least one folding area FA.

[0078] Reference Figure 6 , the display panel DP includes a display area DP-DA and a non-display area DP-NDA. According to some exemplary embodiments, the non-display area DP-NDA may be defined along the edge of the display area DP-DA. The display area DP-DA and the non-display area DP-NDA of the display panel DP may respectively correspond to Figure 1 the display area DA and the non-display area NDA of the display device DD shown in etc.

[0079] The display panel DP may include a scan driver 100, a data driver 200, a plurality of scan lines SL, a plurality of emission control lines ECL, a plurality of data lines DL, a plurality of power lines PL, and a plurality of pixels PX (hereinafter, referred to as pixels). The pixels PX are located in the display area DP-DA. Each of the pixels PX includes a light-emitting element ED and a pixel circuit CC connected to the light-emitting element ED.

[0080] The scan driver 100 may include a scan driving unit and an emission control driving unit.

[0081] The scan driving unit generates a scan signal and sequentially outputs the generated scan signal to the scan lines SL. The emission control driving unit generates an emission control signal and outputs the generated emission control signal to the emission control lines ECL. At the same time, according to some exemplary embodiments, the scan driving unit and the emission control driving unit may not be divided in the scan driver 100, but may be formed as one circuit.

[0082] The scan driver 100 can be formed by the same process as the driving circuit of the pixel PX. For example, the scan driver 100 may include a plurality of thin film transistors formed through the step of forming a circuit layer in the method for manufacturing a display panel according to some exemplary embodiments described later. In addition, the scan driver 100 can be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline silicon oxide (LTPO) process.

[0083] The data driver 200 outputs a data signal to the data line DL. The data signal is an analog voltage corresponding to the gray value of the image data.

[0084] According to some exemplary embodiments of the inventive concept, the data driver 200 can be directly disposed on the display panel DP. However, the embodiments of the inventive concept are not limited thereto. In the display panel DP according to some exemplary embodiments, the data driver 200 is mounted on a printed circuit board, and the printed circuit board can be connected to a pad located at one end of the data line DL.

[0085] The scan line SL extends in the direction of the second direction axis DR2 and can be disposed in the direction of the first direction axis DR1 that intersects the second direction axis DR2. According to some exemplary embodiments of the inventive concept, the second direction axis DR2 and the first direction axis DR1 can be orthogonal, but the embodiments of the inventive concept are not limited thereto.

[0086] The emission control line ECL extends in a direction parallel to the second direction axis DR2 and can be disposed in a direction parallel to the first direction axis DR1. That is, the emission control lines ECL can be respectively arranged side by side with the corresponding scan lines among the scan lines SL.

[0087] The data line DL extends in the direction of the first direction axis DR1 and can be disposed in a direction parallel to the second direction axis DR2 that intersects the first direction axis DR1. The data line DL can provide a data signal to the corresponding pixel PX.

[0088] The power line PL extends in the direction of the first direction axis DR1 and is disposed in a direction parallel to the second direction axis DR2. The power line PL can provide a first power ELVDD to the corresponding pixel PX.

[0089] Each of the plurality of pixels PX is connected to the corresponding scan line among the scan lines SL, the corresponding emission control line among the emission control lines ECL, the corresponding data line among the data lines DL, and the corresponding power line among the power lines PL.

[0090] Figure 7 is an equivalent circuit diagram of a pixel according to some exemplary embodiments.

[0091] Figure 7 An exemplary pixel PX connected to the i-th scan line SLi and the i-th emission control line ECLi is shown. The pixel PX may include a light-emitting element ED and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC controls the amount of current flowing through the light-emitting element ED corresponding to a data signal.

[0092] In a display device DD according to some exemplary embodiments, the plurality of transistors T1 to T7 may be included in a circuit layer DP-CL of a display panel DP as shown in Figure 5 the display panel DP.

[0093] The light-emitting element ED may emit light with a predetermined luminance corresponding to the amount of current provided from the pixel circuit CC. To this end, the level of a first power supply ELVDD may be set to be higher than the level of a second power supply ELVSS.

[0094] Each of the plurality of transistors T1 to T7 may include an input electrode (or a source electrode, see “IE” in Figure 8 ), an output electrode (or a drain electrode, see “OE” in Figure 8 ), and a control electrode (or a gate electrode, see “GE” in Figure 8 ). In the present disclosure, for convenience, either the input electrode or the output electrode may be referred to as a first driving electrode, and the other of the input electrode and the output electrode may be referred to as a second driving electrode.

[0095] The first driving electrode of the first transistor T1 is connected to the first power supply ELVDD via the fifth transistor T5, and the second driving electrode of the first transistor T1 is connected to a first electrode of the light-emitting element ED (see “AE” in Figure 8 ). In the present disclosure, the first transistor T1 may be referred to as a driving transistor. The first transistor T1 controls the amount of current flowing through the light-emitting element ED corresponding to the voltage applied to the control electrode GE.

[0096] The second transistor T2 is connected between the data line DL and the first driving electrode of the first transistor T1. In addition, the control electrode GE of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the second transistor T2 is turned on, and the data line DL and the first driving electrode of the first transistor T1 are electrically connected.

[0097] The third transistor T3 is connected between the second driving electrode of the first transistor T1 and the control electrode GE of the first transistor T1. The control electrode GE of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal Si is supplied to the i-th scan line SLi, the third transistor T3 is turned on, and the second driving electrode of the first transistor T1 and the control electrode GE of the first transistor T1 are electrically connected. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0098] The fourth transistor T4 is connected between the node ND and the initialization power generation unit. In addition, the control electrode GE of the fourth transistor T4 is connected to the (i - 1)-th scan line SLi-1. When the (i - 1)-th scan signal Si-1 is supplied to the (i - 1)-th scan line SLi-1, the fourth transistor T4 is turned on, and an initialization voltage Vint is supplied to the node ND.

[0099] The fifth transistor T5 is connected between the power line PL and the first driving electrode of the first transistor T1. The control electrode GE of the fifth transistor T5 is connected to the i-th emission control line ECLi.

[0100] The sixth transistor T6 is connected between the second driving electrode of the first transistor T1 and the first electrode AE of the light-emitting element ED. In addition, the control electrode GE of the sixth transistor T6 is connected to the i-th emission control line ECLi.

[0101] The seventh transistor T7 is connected between the initialization power generation unit and the first electrode AE of the light-emitting element ED. In addition, the control electrode GE of the seventh transistor T7 is connected to the (i + 1)-th scan line SLi+1. When the (i + 1)-th scan signal Si+1 is supplied to the (i + 1)-th scan line SLi+1, the seventh transistor T7 is turned on, and an initialization voltage Vint is supplied to the first electrode AE of the light-emitting element ED.

[0102] In addition, Figure 7 The control electrode GE of the seventh transistor T7 connected to the (i + 1)-th scan line SLi+1 is shown, but the embodiment is not limited thereto. According to some exemplary embodiments of the present inventive concept, the control electrode GE of the seventh transistor T7 may be connected to the i-th scan line SLi or the (i - 1)-th scan line SLi-1.

[0103] Although Figure 7 PMOS is shown as a reference, the embodiment is not limited thereto. According to some exemplary embodiments, the pixel PX may be formed of NMOS. According to some exemplary embodiments of the present inventive concept, the pixel PX may be formed of a combination of NMOS and PMOS.

[0104] The capacitor CP is located between the power line PL and the node ND. The capacitor CP stores a voltage corresponding to a data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on according to the voltage stored in the capacitor CP, the amount of current flowing through the first transistor T1 can be determined.

[0105] Meanwhile, the equivalent circuit diagram of the pixel PX in the display panel DP is not limited to Figure 7 the configuration shown in. According to some exemplary embodiments of the inventive concept, the pixel PX may be implemented in various forms for emitting the light-emitting element ED.

[0106] Figure 8 is a cross-sectional view showing a part of a display panel according to some exemplary embodiments of the inventive concept. Figure 8 The part shown in may correspond to a cross-section of a part of the pixel. Figure 9 is Figure 8 an enlarged cross-sectional view of a part of. Figure 9 is a cross-sectional view showing more details of Figure 8 the region “AA” of.

[0107] According to some exemplary embodiments, the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-EL, and a packaging layer TFE. According to some exemplary embodiments, the base substrate BS, the circuit layer DP-CL, the display element layer DP-EL, and the packaging layer TFE may be sequentially stacked in a direction parallel to the third direction axis DR3. The display element layer DP-EL may include a pixel defining layer PDL and a light-emitting element ED.

[0108] The base substrate BS may be a member providing a base surface on which the display element layer DP-EL, the circuit layer DP-CL, etc. are located. The base substrate BS may be formed of a polymer material. For example, the base substrate BS may be a polyimide substrate. However, embodiments of the inventive concept are not limited thereto, and the base substrate BS may be an inorganic layer, an organic layer, or a composite material layer. The base substrate BS may be a flexible substrate.

[0109] According to some exemplary embodiments, the circuit layer DP-CL is located on the base substrate BS, and the circuit layer DP-CL may include a plurality of transistors T1 to T7 (see Figure 7 ). The plurality of transistors T1 to T7 (see Figure 7 ) may each include a control electrode GE, an input electrode IE, and an output electrode OE. For example, the circuit layer DP-CL may include a plurality of transistors T1 to T7 for driving the light-emitting element ED of the display element layer DP-EL. In Figure 8 and Figure 9 the cross-sectional views of, some of the plurality of transistors T1 to T7 (see Figure 7 ) ) are shown.

[0110] Reference Figure 8 , the circuit layer DP-CL may include transistors T1 and T2. Transistors T1 and T2 may each include a control electrode GE, an active layer ACL, an input electrode IE, and an output electrode OE. In addition, the circuit layer DP-CL may further include control electrode insulating layers GI1 and GI2, a buffer layer BFL, an interlayer insulating layer ILD, a via circuit insulating layer VIA, etc. The control electrode insulating layers GI1 and GI2 may include a first control electrode insulating layer GI1 located on a lower portion of the control electrode GE and a second control electrode insulating layer GI2 located on an upper portion of the control electrode GE.

[0111] In Figure 8 , an example of the first transistor T1 and the second transistor T2 included in the circuit layer DP-CL is shown. However, the configurations of the first transistor T1 and the second transistor T2 are not limited thereto. In Figure 8 , although the output electrode OE of the first transistor T1 is shown as being in direct contact with the first electrode AE of the light-emitting element ED, this figure shows the shape in cross-section, and thus is shown in this manner. In reality, as shown in Figure 7 , the first transistor T1 may be connected to the first electrode AE of the light-emitting element ED via a sixth transistor T6. However, embodiments of the inventive concept are not limited thereto. In a display panel DP according to some exemplary embodiments, the output electrode OE of the first transistor T1 may be in direct contact with the first electrode AE of the light-emitting element ED.

[0112] Reference Figure 8 and Figure 9 , the first transistor T1 and the second transistor T2 may each include an active layer ACL, a control electrode GE, an input electrode IE, and an output electrode OE.

[0113] In a display panel DP according to some exemplary embodiments, the active layer ACL may be a layer including polysilicon. The active layer ACL may include boron (B) and fluorine (F). That is, the active layer ACL may be a layer including polysilicon doped with boron and fluorine.

[0114] The active layer ACL may be patterned and disposed on a base substrate BS. The active layer ACL may include a core layer CRL that can be divided in a direction parallel to a third direction axis DR3 as a thickness direction, and surface layers FRL-T and FRL-B. The surface layers FRL-T and FRL-B may include a first surface layer FRL-T located on an upper portion of the core layer CRL based on the core layer CRL and a second surface layer FRL-B located on a lower portion of the core layer CRL.

[0115] In the core layer CRL, the concentration of boron can be greater than the concentration of fluorine. In the surface layers FRL-B and FRL-T, the concentration of fluorine can be greater than the concentration of boron. In addition, the concentration of boron included in the core layer CRL can be greater than the concentration of boron included in the surface layers FRL-B and FRL-T, and the concentration of fluorine included in the surface layers FRL-B and FRL-T can be greater than the concentration of fluorine included in the core layer CRL. That is, the surface of the active layer ACL can be a fluorine-rich region where fluorine atoms are enriched.

[0116] The thicknesses t F1 and t F2 of the surface layers FRL-B and FRL-T with respect to the total thickness t ACL of the active layer ACL can be 10% to 30%. At this time, the thicknesses of the surface layers FRL-B and FRL-T include the thickness t F1 of the first surface layer FRL-T and the thickness t F2 of the second surface layer FRL-B. That is, the surface layers FRL-B and FRL-T, which are fluorine-rich regions of the active layer ACL, are set to have a ratio of 10% to 30% of the entire thickness of the active layer ACL starting from the surface of the active layer ACL, thereby improving the surface characteristics of the active layer ACL. In addition, by allowing the thicknesses t F1 and t F2 of the surface layers FRL-B and FRL-T with a high fluorine concentration to have a ratio of 10% to 30% with respect to the total thickness t ACL of the active layer ACL, the active layer ACL can exhibit improved interface characteristics between the active layer ACL and the adjacent layer.

[0117] In addition, the active layer ACL can include a channel region INL-C and ion-doped regions INL-1 and INL-2. The active layer ACL can include a channel region INL-C that overlaps with the control electrode GE, and a first ion-doped region INL-1 and a second ion-doped region INL-2 that are respectively located on (e.g., opposite) both sides of the channel region INL-C.

[0118] The concentration of boron doped in each of the first ion-doped region INL-1 and the second ion-doped region INL-2 can be greater than the doping concentration of boron doped in the channel region INL-C.

[0119] Meanwhile, the circuit layer DP-CL includes an input electrode IE and an output electrode OE, and the input electrode IE can be connected to the first ion-doped region INL-1, while the output electrode OE can be connected to the second ion-doped region INL-2.

[0120] The control electrode GE can be positioned to be spaced apart from the active layer ACL, and the first control electrode insulating layer GI1 is interposed between the control electrode GE and the active layer ACL. The control electrode GE can be located on the active layer ACL. The control electrode GE of the first transistor T1 can be electrically connected to one electrode of the capacitor CP referred to Figure 7 as described. The control electrode GE of the first transistor T1 can be either of the two electrodes constituting the capacitor CP.

[0121] The control electrode GE can include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or at least one alloy thereof. The control electrode GE can have a single-layer structure or a multi-layer structure including different metal layers. For example, the control electrode GE can include molybdenum / aluminum / molybdenum in three layers, copper / titanium in two layers, etc. as the metal layers. At the same time, the control electrode GE can also include a metal oxide layer. The metal oxide layer can include indium tin oxide, indium zinc oxide, gallium zinc oxide, etc.

[0122] On the upper and lower portions of the control electrode GE, control electrode insulating layers GI1 and GI2 can be further formed. The control electrode insulating layers GI1 and GI2 can include an organic film and / or an inorganic film. The control electrode insulating layers GI1 and GI2 can include a plurality of inorganic films. The control electrode insulating layers GI1 and GI2 can include silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0123] The first control electrode insulating layer GI1 can cover the active layer ACL. In addition, the second control electrode insulating layer GI2 is located on the first control electrode insulating layer GI and can cover the control electrode GE.

[0124] At the same time, on the first control electrode insulating layer GI1, at least a part of the scan line SL (see Figure 7 ) and the emission control line ECL (see Figure 7 ) can be positioned.

[0125] On the second control electrode insulating layer GI2, the upper electrode UE can be positioned. The upper electrode UE can be connected to the other electrode of the capacitor CP referred to Figure 7 as described. The upper electrode UE can be either of the two electrodes constituting the capacitor CP.

[0126] On the second control electrode insulating layer GI2, an interlayer insulating layer ILD covering the upper electrode UE can be positioned. The interlayer insulating layer ILD can include an organic film and / or an inorganic film. The interlayer insulating layer ILD can include silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0127] On the interlayer insulating layer ILD, the data line DL (seeFigure 7 ) and at least a part of the power line PL (see Figure 7 ). On the interlayer insulating layer ILD, the input electrodes IE and the output electrodes OE of each of the transistors T1 and T2 may be positioned.

[0128] The input electrode IE and the output electrode OE may be connected to the corresponding active layers ACL respectively through vias penetrating through the control electrode insulating layers GI1 and GI2 and the interlayer insulating layer ILD. That is, the input electrode IE may be connected to the first ion-doped region INL-1, and the output electrode OE may be connected to the second ion-doped region INL-2.

[0129] The input electrode IE and the output electrode OE may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or at least one alloy thereof. The input electrode IE and the output electrode OE may have a single-layer structure or a multi-layer structure. In addition, the input electrode IE and the output electrode OE may include a metal oxide layer. The metal oxide layer may include indium tin oxide, indium zinc oxide, gallium zinc oxide, etc.

[0130] On the interlayer insulating layer ILD, a circuit insulating layer VIA covering the input electrode IE and the output electrode OE may be formed. The circuit insulating layer VIA may include an organic film and / or an inorganic film. The circuit insulating layer VIA may provide a flat surface.

[0131] The circuit layer DP-CL may include a buffer layer BFL as an inorganic film. The buffer layer BFL may prevent impurities from diffusing into the first transistor T1 and the second transistor T2. The buffer layer BFL may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. Meanwhile, depending on the material of the substrate BS and its processing conditions, the buffer layer BFL may be omitted.

[0132] The display element layer DP-EL may be formed on the circuit layer DP-CL. The display element layer DP-EL may include a light-emitting element ED. The display element layer DP-EL may include an organic electroluminescent element or a quantum dot light-emitting element.

[0133] Although not shown in the drawings, the display element layer DP-EL may include a plurality of light-emitting elements ED, and the plurality of light-emitting elements ED may emit light in different wavelength regions. However, the embodiments of the inventive concept are not limited thereto. The light-emitting elements ED spaced apart from each other may emit light in the same wavelength region, or at least one of them may emit light in a different wavelength region.

[0134] The light-emitting element ED may include a first electrode AE and a second electrode CE facing each other, and a light-emitting layer EML located between the first electrode AE and the second electrode CE. In addition, the light-emitting element ED may include a hole transport region HTR located between the first electrode AE and the light-emitting layer EML and an electron transport region ETR located between the light-emitting layer EML and the second electrode CE. The hole transport region HTR may include a hole injection layer adjacent to the first electrode AE and a hole transport layer located between the hole injection layer and the light-emitting layer EML, and the electron transport region ETR may include an electron injection layer adjacent to the second electrode CE and an electron transport layer located between the light-emitting layer EML and the electron injection layer.

[0135] The first electrode AE may be connected to the output electrode OE. The first electrode AE may be formed of a metal alloy or a conductive compound. The first electrode AE may be an anode. The first electrode AE may be a pixel electrode.

[0136] In the light-emitting element ED according to some exemplary embodiments, the first electrode AE may be a reflective electrode. However, the embodiments of the inventive concept are not limited thereto. For example, the first electrode AE may be a transmissive electrode or a semi-transmissive reflective electrode, etc. When the first electrode AE is a transmissive electrode or a semi-transmissive reflective electrode, the first electrode AE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). Alternatively, the first electrode AE may be a multilayer structure including a reflective film or a semi-transmissive reflective film both formed of the above exemplary materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode AE may be a multilayer metal film, or may have a structure of a metal film in which ITO / Ag / ITO is stacked.

[0137] The second electrode CE may be a common electrode or a cathode. The second electrode CE may be a transmissive electrode, a semi-transmissive reflective electrode, or a reflective electrode. When the second electrode CE is a transmissive electrode, the second electrode CE may be formed of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0138] When the second electrode CE is a semi-transmissive reflective electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). Alternatively, the second electrode CE may have a multilayer structure including a reflective film or a semi-transmissive reflective film formed of the above-exemplified materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0139] The light-emitting layer EML may have a single-layer structure having a single layer formed of a single material, a single-layer structure having a single layer formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials.

[0140] When the display panel DP according to some exemplary embodiments is an organic light-emitting display panel including an organic light-emitting element, the light-emitting layer EML may include an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a derivative, a dihydrophenanthrene derivative, or a triphenylene derivative. Specifically, the light-emitting layer EML may include an anthracene derivative or a pyrene derivative.

[0141] When the display panel DP according to some exemplary embodiments is a quantum dot light-emitting display panel including a quantum dot light-emitting element, the display panel DP may include a quantum dot material in the light-emitting layer EML. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, IV-VI group compounds, group IV elements, group IV compounds, and combinations thereof.

[0142] On the display element layer DP-EL, a packaging layer TFE may be positioned. The packaging layer TFE may be a single layer or a plurality of stacked layers. The packaging layer TFE may cover the light-emitting element ED. The packaging layer TFE may be directly disposed on the second electrode CE.

[0143] Figure 10A Schematically shows the interface between the active layer and the first control electrode insulating layer and its adjacent regions in the circuit layer included in the display panel according to some exemplary embodiments. Figure 10B Schematically shows the interface between the active layer and the first control electrode insulating layer and its adjacent regions in the exemplary display panel.

[0144] Figure 10A and Figure 10B The active layers ACL and ACL' shown in may include crystalline and aligned silicon (Si). Meanwhile, the first control electrode insulating layer GI1 may include silicon oxide (SiO x )

[0145] Reference Figure 10A Figure 10A The active layer ACL may include fluorine (F) in a region adjacent to the interface IF. The binding sites DB of the aligned silicon (Si) atoms exposed toward the interface IF side may bind to fluorine (F) atoms diffused into the active layer ACL or the first control electrode insulating layer GI1. Thus, according to some exemplary embodiments, the active layer ACL minimizes the exposure of the binding sites DB of the silicon (Si) atoms that are not bound at the interface IF, and has Si-F bonds in which silicon (Si) atoms and fluorine (F) atoms are coupled to have a high bond energy (for example, the bond energy of Si-F may be 576.4 KJ / mol), thereby exhibiting good reliability characteristics.

[0146]

[0146] That is, the exposure of the binding sites DB of the silicon (Si) atoms on the surface adjacent to the interface IF that are not bound to the active layer ACL is minimized to minimize the phenomenon that charges are trapped at the binding sites DB of the silicon (Si) atoms, thereby increasing the mobility of the charges. In addition, since the proportion of silicon (Si) atoms that form Si-F bonds by being adjacent to the surface of the active layer ACL adjacent to the interface IF increases, stable binding can be maintained even under severe processing conditions, so that the display panel according to some exemplary embodiments can exhibit relatively improved reliability characteristics.

[0147] In contrast, Figure 10B Figure 10B shows a part of an exemplary active layer ACL' and the first control electrode insulating layer GI1 adjacent thereto, and the binding sites DB' of the exposed silicon (Si) atoms that are not bound at the interface IF' between the active layer ACL' and the first control electrode insulating layer GI1 may be exposed. The exposed binding sites DB' may be part of the VC, where charges moving along the interface IF' are trapped. Meanwhile, in the exemplary display panel, the first control electrode insulating layer GI1 may include hydrogen (H) atoms. The hydrogen (H) atoms may bind to the binding sites DB' of the silicon (Si) atoms that are not bound at the interface IF' between the active layer ACL' and the first control electrode insulating layer GI1 to form Si-H bonds. However, since the Si-H bond has a relatively low bond energy compared to the Si-F bond (for example, the Si-H bond energy may be 293.3 KJ / mol), the Si-H bond is likely to break when subsequent processing is performed, so that the reliability of the active layer ACL' may deteriorate.

[0148] A display panel according to some exemplary embodiments includes transistors, each transistor including an active layer doped with fluorine, thereby exhibiting improved reliability. In a transistor according to some exemplary embodiments, the surface of the active layer may have fluorine atoms mainly distributed thereon, and the fluorine atoms may combine with silicon atoms of the active layer to form Si-F bonds. Accordingly, the dangling bonds of Si exposed at the surface of the active layer are reduced and the stability of the active layer is improved due to the strong bond energy between Si-F, such that the charge movement characteristics in the active layer can be improved. In addition, compared to a case where the dangling bonds of silicon are exposed or the dangling bonds of silicon combine with hydrogen atoms or the like, defects at the interface between the active layer and the control electrode insulating layer are reduced, thereby preventing mobile charges from being trapped at defect sites. Accordingly, the absolute value of the threshold voltage during driving of the transistor can be reduced, and the threshold voltage hysteresis corresponding to the difference between the forward and reverse threshold voltages can be reduced, and the afterimage retention time during operation of the display element layer can be reduced.

[0149] Hereinafter, with reference to Figure 11 and Figures 12A to 12F , a method of manufacturing a display panel according to some exemplary embodiments will be described. Figure 11 is a flowchart illustrating a method of manufacturing a display panel according to some exemplary embodiments of the present inventive concept. Figures 12A to 12F is a schematic diagram illustrating some of the steps of a method of manufacturing a display panel according to some exemplary embodiments.

[0150] A method of manufacturing a display panel according to some exemplary embodiments may include: forming a circuit layer (S10) and forming a display element layer (S20). In a method of manufacturing a display panel according to some exemplary embodiments, forming the circuit layer (S10) may include: disposing a preliminary active layer on a substrate (S100), performing a first doping on the preliminary active layer with a first ion (S200), performing a second doping on the preliminary active layer with a second ion (S300), forming an active layer by providing a laser to the preliminary active layer (S400), disposing a control electrode insulating layer on the active layer (S500), forming a control electrode (S600), performing a third doping on the active layer with a first ion (S700), and performing a heat treatment on the active layer (S800). After performing the heat treatment on the active layer (S800), forming the display element layer (S20) may be performed.

[0151] Figure 12AShows a preliminary active layer (S100) disposed on a substrate. The preliminary active layer P-ACL may be a layer including amorphous silicon. For example, the substrate BS may include polyimide. The preliminary active layer P-ACL may be disposed on the substrate BS using a deposition method. The preliminary active layer P-ACL may be formed using a method such as sputtering or chemical vapor deposition. Meanwhile, the preliminary active layer P-ACL may be disposed on a buffer layer BFL.

[0152] Figure 12B Is a view showing a first doping (S200) of the preliminary active layer with a first ion. In a method for manufacturing a display panel according to some exemplary embodiments, the first ion may be a boron (B) ion. The first doping DOP1 may be performed by implanting boron ions as the first ion into the preliminary active layer P-ACL including amorphous silicon.

[0153] Figure 12C Is a view showing a second doping (S300) of the preliminary active layer with a second ion. The second ion may be different from the first ion. In a method for manufacturing a display panel according to some exemplary embodiments, the second ion may be a fluorine (F) ion. The second doping DOP2 may be performed by implanting fluorine ions as the second ion into the preliminary active layer P-ACL in which the first doping DOP1 has been performed. The preliminary active layer P-ACL after the second doping DOP2 may include a core layer CRL-P and surface layers FRL-TP and FRL-BP. The surface layers FRL-TP and FRL-BP of the preliminary active layer P-ACL may include fluorine ions having a higher concentration than the core layer CRL-P.

[0154] Figure 12D Is a view showing the formation of an active layer (S400) by providing a laser to the preliminary active layer. The laser LR may be irradiated onto the preliminary active layer P-ACL (see Figure 12C ) that has been second-doped DOP2 with the second ion. The laser LR may anneal the amorphous silicon to crystallize it into polycrystalline silicon. That is, the preliminary active layer P-ACL including amorphous silicon (see Figure 12C ) may receive the laser LR to form an active layer ACL including polycrystalline silicon. The laser LR may be an excimer laser. For example, the laser LR may be an XeCl excimer laser (wavelength of 308 nm) or an XeF excimer laser (wavelength of 351 nm).

[0155] Meanwhile, with reference to Figure 12B and Figure 12CAfter the first doping DOP1 (S200) and the second doping DOP2 (S300) of the preliminary active layer P-ACL as described, a method for manufacturing a display panel according to some exemplary embodiments may provide a laser LR to the preliminary active layer P-ACL to activate the doped first and second ions with the laser LR. That is, in addition to the heat treatment (S800) described later, forming the active layer ACL (S400) by providing the laser LR to the preliminary active layer P-ACL may correspond to activating the doped active layer.

[0156] In the case of a method for manufacturing a display panel according to some exemplary embodiments, a laser LR with relatively high energy may be used to activate the doped preliminary active layer P-ACL, so that it is possible to reduce the temperature of the high-temperature process for activating the doped ions performed after the doping step, or reduce the steps or time of the high-temperature process, thereby minimizing damage to the substrate BS including polyimide and the like.

[0157] Furthermore, after doping the preliminary active layer P-ACL with ions, the preliminary active layer P-ACL may be annealed with the laser LR to increase the activation of the preliminary active layer P-ACL and allow the active layer ACL to recover from the damage caused during doping, so that the charge movement in the active layer ACL and the reliability of the active layer ACL can be improved. Therefore, the driving characteristics of the display panel manufactured by the method for manufacturing a display panel according to some exemplary embodiments can be relatively improved.

[0158] Figure 12E Illustrated are setting a control electrode insulating layer (S500) and forming a control electrode (S600) on the active layer in a method for manufacturing a display panel according to some exemplary embodiments. The control electrode insulating layer (refer to the first control electrode insulating layer GI1 described above) may be provided on the active layer ACL. The control electrode insulating layer (refer to the first control electrode insulating layer GI1 described above) may be provided to cover the active layer ACL.

[0159] On the control electrode insulating layer (refer to the first control electrode insulating layer GI1 described above), a control electrode GE may be formed. The control electrode GE may be patterned using a photolithography process and formed on the control electrode insulating layer (refer to the first control electrode insulating layer GI1 described above).

[0160] Figure 12FIt shows that the active layer is subjected to a third doping (S700) with a first ion. The method for manufacturing a display panel according to some exemplary embodiments may include subjecting the active layer ACL to a third doping DOP3 with boron ions as the first ion. In the third doping DOP3 (S700) of the active layer ACL with the first ion, the control electrode GE can be used as a mask. That is, the third doping DOP3 (S700) of the active layer ACL with the first ion may include using the control electrode GE as a mask to form ion-doped regions INL-1 and INL-2 that do not overlap with the control electrode GE.

[0161] The first ion may be mainly implanted into the region of the active layer ACL that does not overlap with the control electrode GE. After the third doping DOP3 (S700) of the active layer ACL with the first ion, the active layer ACL may include a channel region INL-C that overlaps with the control electrode GE and a first ion-doped region INL-1 and a second ion-doped region INL-2 that do not overlap with the control electrode GE, respectively.

[0162] After the third doping DOP3 (S700) of the active layer ACL with the first ion, heat treatment of the active layer ACL (S800) may be performed. Heat treatment of the active layer ACL (S800) may activate the active layer ACL implanted with boron ions and fluorine ions. Heat treatment of the active layer ACL (S800) may activate the active layer ACL by providing heat at 250 °C to 480 °C. In the case of a display panel according to some exemplary embodiments, an organic material such as polyimide is used as the substrate BS, and in this case, since there are limitations in the heat resistance of the organic material, the heat treatment temperature should be kept below 480 °C. However, since the activation of the doped ions increases under high-temperature conditions, the minimum heat treatment temperature may be 250 °C or higher.

[0163] Figure 13 It is a diagram showing the distribution of fluorine atoms in the active layer of a comparative example and an example. Figure 13 It shows the results of analyzing the active layer prepared by the processes of a comparative example and an example using secondary ion mass spectrometry (SIMS). Example A shows the relative distribution degree of fluorine atoms in the active layer prepared by the method for manufacturing a display panel according to some exemplary embodiments of the present inventive concept. Different from the method for manufacturing a display panel according to some exemplary embodiments, Comparative Example A shows the relative distribution degree of fluorine atoms in the active layer prepared by annealing a preliminary active layer with a laser and then performing doping by implanting fluorine ions.

[0164] In Figure 13In this case, "CT" corresponds to the core part of the active layer, and "IF-T" and "IF-B" correspond to the upper surface and the lower surface of the active layer, respectively. Figure 13 shows the relative concentration of fluoride ions in the thickness direction of the active layer. Meanwhile, in the present specification, the upper surface IF-T of the active layer is the surface of the active layer adjacent to the first control electrode insulating layer GI1 (see Figure 8 ), and the lower surface IF-B of the active layer is the surface of the active layer adjacent to the substrate BS (see Figure 8 ).

[0165] Referring to Figure 13 , in the case of Example A, it can be confirmed that the concentration of fluoride ions in the upper surface IF-T and the lower surface IF-B, which are the surfaces of the active layer, is relatively higher than the concentration of fluoride ions in the core part CT. It is determined that this is due to the fact that the active layer is formed by irradiating with a laser after doping with fluoride ions, so that the movement of the implanted fluoride ions is increased, allowing the fluoride ions to be mainly distributed on the surface of the active layer.

[0166] In contrast, Comparative Example A forms the active layer by irradiating amorphous silicon with a laser to crystallize the amorphous silicon into polycrystalline silicon and then implanting fluoride ions, so that the movement of the fluoride ions is less, thus showing a fluoride ion concentration similar to that in the entire active layer.

[0167] That is, in the case of an active layer manufactured by ion doping and then irradiating with a laser as in the method for manufacturing a display panel according to some exemplary embodiments, by using the laser light energy to increase the activation of the doped ions, allowing the ions to be mainly distributed on the surface of the active layer, the interface characteristics between the active layer and the adjacent layers can be improved. Therefore, the display panel manufactured by the method for manufacturing a display panel according to some exemplary embodiments can exhibit improved reliability characteristics.

[0168] Figure 14A is a graph showing the change in the threshold voltage in the comparative example and the example. Figure 14B is a graph showing the afterimage retention time in the comparative example and the example. Figure 14A and Figure 14B The change in the threshold voltage and the afterimage retention time shown in correspond to the evaluation items for evaluating the reliability of the display panel.

[0169] The change in the threshold voltage (△V th ) shows the difference between the forward threshold voltage and the reverse threshold voltage. Since the change in the threshold voltage (△V th ) is small, it can be seen that the threshold voltage hysteresis is improved. That is, since the change in the threshold voltage (△V th ) is small, it can be seen that the reliability of the display panel is improved.

[0170] The afterimage retention time indicates the retention time of the provided image after the light-emitting element is turned off, or the retention time of the emitted light. As the afterimage retention time is shortened, it can be seen that the afterimage effect is improved. That is, as the afterimage retention time is shortened, it can be seen that the reliability of the display panel is improved.

[0171] In Figure 14A and Figure 14B Comparative Example 1 is the result of the evaluation of a display panel manufactured by irradiating with a laser to form an active layer and then doping by implanting boron ions, and Comparative Example 2 is the result of the evaluation of a display panel manufactured with an active layer formed by doping boron ions and then irradiating with a laser. The Example is the result of the evaluation of a display panel manufactured by a method for manufacturing a display panel according to some exemplary embodiments. That is, the Example is the result of the evaluation of a display panel manufactured with an active layer formed by performing first doping with boron ions, second doping with fluorine ions, and then irradiating with a laser.

[0172] Referring to Figure 14A , the Example shows that the change in the threshold voltage is less than that of Comparative Example 1 and Comparative Example 2. That is, it can be seen that the display panel of the Example has improved threshold voltage hysteresis and improved reliability characteristics when compared with the display panels of each of Comparative Example 1 and Comparative Example 2.

[0173] Referring to Figure 14B , the Example shows that the afterimage retention time is shorter than that of Comparative Example 1 and Comparative Example 2. That is, it can be seen that the display panel of the Example has improved afterimage effect and improved reliability characteristics when compared with the display panels of each of Comparative Example 1 and Comparative Example 2.

[0174] The method for manufacturing a display panel according to some exemplary embodiments performs ion doping and then irradiates with a laser to form an active layer, so as to increase the activation of the doped active layer while minimizing the high-temperature process, thereby providing a display panel with improved electrical characteristics and high reliability. In addition, the method for manufacturing a display panel according to some exemplary embodiments performs ion doping and then irradiates with a laser to form an active layer, thereby increasing the activation of the active layer without a process at an ultra-high temperature (about 1000 °C or higher), and thus, it can be used to manufacture a flexible display panel using a substrate formed by including an organic material. In addition, the method for manufacturing a display panel according to some exemplary embodiments includes both boron ion doping and fluorine ion doping to increase the concentration of fluorine ions at the surface of the active layer, thereby improving the interface characteristics between the active layer and the layer adjacent to the active layer, to provide a display panel with good reliability characteristics.

[0175] Meanwhile, a display panel according to some exemplary embodiments (which is manufactured by a method for manufacturing a display panel according to some exemplary embodiments) may exhibit improved threshold voltage hysteresis and improved afterimage effects without deterioration of other electrical characteristics.

[0176] In addition, a display panel according to some exemplary embodiments includes a circuit layer having an active layer that has a high fluorine concentration in a surface adjacent to a control electrode insulating layer, thereby exhibiting good reliability characteristics.

[0177] Some exemplary embodiments of the inventive concept may include a display panel having relatively improved reliability characteristics and good electrical characteristics by including a fluorine-containing active layer in a surface layer.

[0178] Some exemplary embodiments of the inventive concept may also include a method for manufacturing a display panel having relatively improved reliability by performing doping before crystallizing amorphous silicon using a laser and further doping fluoride ions in a doping step.

[0179] Although the inventive concept has been described with reference to some exemplary embodiments of the inventive concept, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

[0180] Accordingly, the technical scope of the inventive concept is not intended to be limited to what is set forth in the detailed description of the specification, but is intended to be defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: a base substrate; a circuit layer located on the base substrate; and a display element layer located on the circuit layer, wherein the circuit layer includes: an active layer located on the base substrate and containing boron and fluorine; a control electrode located on the active layer; and a control electrode insulating layer located between the active layer and the control electrode, wherein the active layer includes: a core layer in which the concentration of boron is greater than the concentration of fluorine; and a surface layer located on the core layer, and the concentration of fluorine in the surface layer is greater than the concentration of boron.

2. The display panel according to claim 1, wherein, The surface layer includes a first surface layer adjacent to the control electrode insulating layer and a second surface layer adjacent to the base substrate.

3. The display panel according to claim 2, wherein, The concentration of fluorine in each of the first surface layer and the second surface layer is greater than the concentration of fluorine in the core layer.

4. The display panel according to claim 1, wherein, The ratio of the thickness of the surface layer to the total thickness of the active layer is 10% to 30%.

5. The display panel according to claim 1, wherein, The base substrate is a polyimide substrate.

6. The display panel according to claim 1, wherein, The active layer includes: a channel region overlapping with the control electrode; and a first ion-doped region and a second ion-doped region respectively located on both sides of the channel region, wherein the concentration of boron in each of the first ion-doped region and the second ion-doped region is greater than the concentration of boron in the channel region.

7. The display panel according to claim 6, wherein, The circuit layer further includes: an input electrode connected to the first ion-doped region; and an output electrode connected to the second ion-doped region.

8. The display panel according to claim 7, wherein, The display element layer includes: a first electrode electrically connected to the output electrode; a second electrode facing the first electrode; and a light-emitting layer located between the first electrode and the second electrode.

9. The display panel according to claim 1, wherein, The display element layer includes an organic electroluminescent element or a quantum dot light-emitting element.

10. The display panel according to claim 1, further comprising a buffer layer located between the base substrate and the active layer.

11. A display panel including at least one folding region, the display panel comprising: a base substrate; a circuit layer located on the base substrate; and a display element layer located on the circuit layer and including a light-emitting element, wherein the circuit layer includes: an active layer located on the base substrate and containing boron and fluorine; a control electrode located on the active layer; and a control electrode insulating layer located between the active layer and the control electrode, wherein the active layer includes a core layer and a surface layer on the core layer, the core layer contains both boron and fluorine, and the concentration of fluorine in the surface layer adjacent to the control electrode insulating layer is greater than the concentration of fluorine in the core layer.

12. The display panel according to claim 11, wherein, The active layer includes: a channel region overlapping with the control electrode; and a first ion-doped region and a second ion-doped region respectively located on both sides of the channel region, wherein the concentration of boron in each of the first ion-doped region and the second ion-doped region is greater than the concentration of boron in the channel region.

13. The display panel according to claim 11, wherein, The base substrate includes polyimide.

14. A method for manufacturing a display panel, the method comprising: Forming a circuit layer and forming a display element layer, Among them, forming the circuit layer includes: Providing a preliminary active layer containing amorphous silicon on a substrate; Doping the preliminary active layer with a first ion; Doping the doped preliminary active layer with a second ion different from the first ion; Forming an active layer by providing a laser to the doped preliminary active layer doped with the second ion; Providing a control electrode insulating layer on the active layer; Forming a control electrode on the control electrode insulating layer; Performing a third doping of the active layer with the first ion; and Performing a heat treatment on the active layer.

15. The method according to claim 14, wherein, The first ion is a boron ion, and the second ion is a fluorine ion.

16. The method according to claim 14, wherein, Providing the preliminary active layer includes depositing the amorphous silicon.

17. The method according to claim 14, wherein, Forming the active layer by providing the laser includes: forming polycrystalline silicon by providing the laser to the amorphous silicon.

18. The method according to claim 14, wherein, Doping the active layer includes: using the control electrode as a mask to form an ion doping region that does not overlap with the control electrode.

19. The method according to claim 14, wherein Performing a heat treatment on the active layer includes: activating the active layer by providing heat at 250°C to 480°C.

20. The method according to claim 14, wherein The substrate includes polyimide.

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